JP2010140554A - Method of reading nonvolatile semiconductor memory device - Google Patents

Method of reading nonvolatile semiconductor memory device Download PDF

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JP2010140554A
JP2010140554A JP2008315854A JP2008315854A JP2010140554A JP 2010140554 A JP2010140554 A JP 2010140554A JP 2008315854 A JP2008315854 A JP 2008315854A JP 2008315854 A JP2008315854 A JP 2008315854A JP 2010140554 A JP2010140554 A JP 2010140554A
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word line
voltage
level
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Takeshi Tanaka
豪 田中
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Samsung Electronics Co Ltd
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Priority to US12/654,062 priority patent/US8120953B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of reading nonvolatile semiconductor memory device, which accelerates reading by shortening a rise time of a word line voltage and has a sufficient margin for reading without increasing a layout area. <P>SOLUTION: In the method for reading the nonvolatile semiconductor storage device by supplying a voltage at a predetermined level to the word line, the voltage higher than the predetermined level is supplied to the word line to raise the word line voltage, and then the voltage at the predetermined level is supplied to the word line to set the word line voltage at the level for reading. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、特にマルチレベルセルに適用して有効な不揮発性半導体記憶装置の読出し方法に関する。   The present invention relates to a method for reading a nonvolatile semiconductor memory device that is particularly effective when applied to multilevel cells.

不揮発性半導体記憶装置の１つとして、多値情報を記憶できるマルチレベルセル（Ｍｕｌｔｉ−Ｌｅｖｅｌ Ｃｅｌｌ。以下、ＭＬＣと記す）がある。このＭＬＣを利用した場合、１回の読出し動作で、Ｎ−１回（ＮはＭＬＣにおけるしきい値の数で、Ｎ−１は通常３回）のワード線電圧のステップが必要となる。図５に従来のＭＬＣを利用した場合の読出し動作におけるワード線電圧のステップ状態を示す。ワード線電圧は、低レベルＬ、中レベルＭ、高レベルＨに３段階に制御されており、どの段階でＭＬＣに電流が流れるかにより２ビットデータの１つを取出すことができる。
特開平７−９８９８９号公報 As one of nonvolatile semiconductor memory devices, there is a multi-level cell (hereinafter referred to as MLC) that can store multilevel information. When this MLC is used, a word line voltage step is required N-1 times (N is the number of thresholds in MLC, and N-1 is usually 3 times) in one read operation. FIG. 5 shows the step state of the word line voltage in the read operation when the conventional MLC is used. The word line voltage is controlled in three stages of low level L, medium level M, and high level H, and one of 2-bit data can be taken out depending on which stage the current flows through the MLC.
Japanese Patent Laid-Open No. 7-98989

しかし、通常のメモリの場合、読出し時間は仕様で決まっているため、この時間内にワード線電圧のステップを行い、データを出力しなければならない場合、ワード線電圧の立上り時間が遅い場合には所望のワード線電圧レベルに至らないまま読出し動作を行うため、誤読出し、マージン確保が困難という問題点が発生する。また、容量増大に伴いワード線への負荷も大きくなるため、負荷による遅延のためセルアレイの近端と遠端でワード線電圧が異なり、充分なマージンがとれない問題点がある。   However, in the case of a normal memory, the read time is determined by the specification.Therefore, when the word line voltage must be stepped and data output within this time, the rise time of the word line voltage is slow. Since the read operation is performed without reaching the desired word line voltage level, there arises a problem that it is difficult to read erroneously and secure a margin. In addition, since the load on the word line increases as the capacity increases, the word line voltage differs between the near end and the far end of the cell array due to a delay due to the load, and there is a problem that a sufficient margin cannot be obtained.

これらの問題点を上述の図５を参照して説明すると、図中の実線はセルアレイの端（負荷：軽）、すなわちワード線ドライバから最も近いセルのゲートに印加されるワード線電圧、点線はセルアレイの中央部（負荷：重）、すなわちワード線ドライバから最も遠いセルのゲートに印加されるワード線電圧である（ただし、中央が最も負荷が重いかどうかは両側ドライブ・片側ドライブで異なる）。ワード線電圧の立上りが遅い場合、センスアンプでのセル電流検知時に、セルアレイ中央ではワード線電圧が所望のレベルまで到達しておらず、誤読出し、マージン確保が困難となる。   These problems will be described with reference to FIG. 5 described above. The solid line in the figure indicates the end of the cell array (load: light), that is, the word line voltage applied to the gate of the closest cell from the word line driver, and the dotted line indicates This is the word line voltage applied to the center of the cell array (load: heavy), that is, the gate of the cell farthest from the word line driver (however, whether the load is the heaviest at the center differs for both-side drive and single-side drive). When the rise of the word line voltage is slow, when the cell current is detected by the sense amplifier, the word line voltage does not reach a desired level in the center of the cell array, and it becomes difficult to read erroneously and secure a margin.

このとき、センス時間を遅らせ、所望のワード線電圧になるまで待ってからセンスすることで誤読出し、マージン不足を回避することが可能であるが、読出し動作自体の時間が遅くなる結果を招く。   At this time, it is possible to avoid erroneous reading and margin shortage by delaying the sensing time and waiting until the desired word line voltage is reached, but this results in the time of the reading operation itself being delayed.

また、特許文献１では、メインデコーダにて選択されるメインワード線に対し、サブデコーダを具備することでさらに分割し、メインワード線の負荷を軽減することでワード線電圧の立上りを早くすることで高速化を図っている。しかし、この方法では、サブデコーダを具備することでレイアウト面積の増大につながる。昨今の不揮発性メモリでは容量も大きくなっており、ワード線の増大に伴い同数のサブデコーダが必要になる。   Further, in Patent Document 1, the main word line selected by the main decoder is further divided by providing a sub-decoder, and the rise of the word line voltage is accelerated by reducing the load on the main word line. To speed up. However, in this method, the layout area is increased by providing the sub-decoder. The capacity of the recent nonvolatile memory is large, and the same number of sub-decoders are required as the number of word lines increases.

本発明は上記の点に鑑みなされたもので、その目的は、ワード線電圧の立上げ時間を速くして読出し動作の高速化を図ることができ、しかも充分なマージンを持って読出し動作が可能となり、レイアウト面積の増大を招くこともない不揮発性半導体記憶装置の読出し方法を提供することにある。   The present invention has been made in view of the above points, and an object of the present invention is to speed up the read operation by increasing the rise time of the word line voltage, and to perform the read operation with a sufficient margin. Accordingly, it is an object of the present invention to provide a method for reading a nonvolatile semiconductor memory device that does not increase the layout area.

本発明の第１の不揮発性半導体記憶装置の読出し方法は、ワード線に所定レベルの電圧を供給して読出しを行う不揮発性半導体記憶装置の読出し方法において、前記所定レベルより高い電圧をワード線に供給してワード線電圧を立上げた後、前記所定レベルの電圧をワード線に供給して、該レベルにワード線電圧を設定し、読出しを行うことを特徴とする。   According to a first non-volatile semiconductor memory device reading method of the present invention, a voltage higher than the predetermined level is applied to a word line. After supplying and raising the word line voltage, the voltage of the predetermined level is supplied to the word line, the word line voltage is set to the level, and reading is performed.

より具体的には、前記不揮発性半導体記憶装置は低レベル、中レベル、高レベルの電圧をワード線に供給して読出しを行うマルチレベルセルであり、低レベルの電圧をワード線に供給するときは、中レベルの電圧をワード線に供給してワード線電圧を立上げた後、低レベルの電圧をワード線に供給し、中レベルの電圧をワード線に供給するときは、高レベルの電圧をワード線に供給してワード線電圧を立上げた後、中レベルの電圧をワード線に供給し、高レベルの電圧をワード線に供給するときは、該高レベルより高い電圧をワード線に供給してワード線電圧を立上げた後、高レベルの電圧をワード線に供給する。   More specifically, the nonvolatile semiconductor memory device is a multi-level cell that performs reading by supplying low-level, medium-level, and high-level voltages to the word line, and when supplying low-level voltage to the word line. When a medium level voltage is supplied to the word line and the word line voltage is raised, a low level voltage is supplied to the word line, and a medium level voltage is supplied to the word line. Is supplied to the word line and the word line voltage is raised, then a medium level voltage is supplied to the word line, and when a high level voltage is supplied to the word line, a voltage higher than the high level is applied to the word line. After supplying and raising the word line voltage, a high level voltage is supplied to the word line.

本発明の第２の不揮発性半導体記憶装置の読出し方法は、複数のレベルの電圧をワード線に順次供給して読出しを行う不揮発性半導体記憶装置の読出し方法において、最初に、最も高いレベルの電圧をワード線に供給して読出し動作を行い、その後、ワード線電圧を放電させて１段低いレベルの電圧より下がったタイミングでその１段低いレベルの電圧をワード線に供給し、読出し動作を行うことを特徴とする。   According to the second non-volatile semiconductor memory device reading method of the present invention, in the non-volatile semiconductor memory device reading method in which reading is performed by sequentially supplying a plurality of levels of voltages to the word lines, Is supplied to the word line, and then the read operation is performed. Thereafter, the word line voltage is discharged, and the voltage lower by one step is supplied to the word line at the timing when the voltage is lowered by one step, and the read operation is performed. It is characterized by that.

より具体的には、前記不揮発性半導体記憶装置は低レベル、中レベル、高レベルの電圧をワード線に供給して読出しを行うマルチレベルセルであり、最初に、高レベルの電圧をワード線に供給して読出し動作を行い、次に、ワード線電圧を放電させてワード線電圧が中レベルの電圧より下がったタイミングで中レベルの電圧をワード線に供給し、読出し動作を行い、その後、ワード線電圧を放電させてワード線電圧が低レベルの電圧より下がったタイミングで低レベルの電圧をワード線に供給し、読出し動作を行う。また、ワード線電圧の放電は、ワード線に接続されたＮＭＯＳトランジスタにより行われる。   More specifically, the nonvolatile semiconductor memory device is a multi-level cell that performs reading by supplying low-level, medium-level, and high-level voltages to a word line. First, a high-level voltage is applied to the word line. Then, the read operation is performed. Next, the word line voltage is discharged, the medium level voltage is supplied to the word line at the timing when the word line voltage falls below the medium level voltage, and the read operation is performed. At the timing when the line voltage is discharged and the word line voltage falls below the low level voltage, a low level voltage is supplied to the word line to perform a read operation. The word line voltage is discharged by an NMOS transistor connected to the word line.

上記のような本発明によれば、所定レベルより高い電圧をワード線に供給してワード線電圧を立上げた後、所定レベルの電圧をワード線に供給して読出しを行うことにより、あるいは最初に最も高いレベルの電圧をワード線に供給して読出し動作を行い、その後その電圧から放電により電圧を下げて次のレベルでの読出し動作を行うことにより、ワード線電圧の立上げ時間を速くすることができ、読出し動作の高速化およびマージンの確保が可能となる。また、この方法は、電圧の切替え、放電手段だけを設ければよいので、サブデコーダを設ける場合のようにレイアウト面積の増大を招くことがない。   According to the present invention as described above, a voltage higher than a predetermined level is supplied to the word line to raise the word line voltage, and then a voltage of a predetermined level is supplied to the word line to perform reading, or first The voltage of the highest level is supplied to the word line to perform the read operation, and then the voltage is lowered from the voltage by discharging to perform the read operation at the next level, thereby speeding up the rise time of the word line voltage. Therefore, it is possible to speed up the reading operation and secure a margin. In addition, since this method only requires voltage switching and discharging means, the layout area is not increased as in the case of providing a sub-decoder.

以下、図面を参照して本発明による不揮発性半導体記憶装置の読出し方法の実施の形態を詳細に説明する。まず、第１実施形態について説明する。   Hereinafter, embodiments of a method for reading a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings. First, the first embodiment will be described.

本発明の第１実施形態は、低レベルＬ、中レベルＭ、高レベルＨの電圧をワード線に供給して読出しを行うマルチレベルセル（以下、ＭＬＣと記す）に適用した場合である。図１は、本発明の第１実施形態を説明するための波形図で、(ａ)はワード線電圧、(ｂ)はイコライズ、(ｃ)は出力データ、(ｄ)はワード線供給電圧を示す。(ａ)のワード線電圧波形において、実線はワード線ドライバから最も近いセルのゲートに印加されるワード線電圧、点線はワード線ドライバから最も遠いセルのゲートに印加されるワード線電圧である。   The first embodiment of the present invention is a case where the present invention is applied to a multi-level cell (hereinafter referred to as MLC) that performs reading by supplying low-level L, medium-level M, and high-level H voltages to a word line. FIG. 1 is a waveform diagram for explaining the first embodiment of the present invention. (A) is a word line voltage, (b) is equalized, (c) is output data, and (d) is a word line supply voltage. Show. In the word line voltage waveform of (a), the solid line is the word line voltage applied to the gate of the cell closest to the word line driver, and the dotted line is the word line voltage applied to the gate of the cell farthest from the word line driver.

ＭＬＣにおいては、低レベルＬ、中レベルＭ、高レベルＨの電圧をワード線に順次供給して読出しを行うが、図１に示すように、本発明の第1実施形態では、低レベルＬの電圧をワード線に供給して読出しを行うとき、中レベルＭの電圧を一旦ワード線に供給してワード線電圧を立上げた後、低レベルＬの電圧をワード線に供給して本来の電圧に戻し、読出しを行う。また、中レベルＭの電圧をワード線に供給して読出しを行うときは、高レベルＨの電圧を一旦ワード線に供給してワード線電圧を立上げた後、中レベルＭの電圧をワード線に供給して本来の電圧に戻し、読出しを行う。さらに、高レベルＨの電圧をワード線に供給して読出しを行うときは、該高レベルＨより高い第４レベルＺの電圧をワード線に供給してワード線電圧を一旦立上げた後、高レベルＨの電圧をワード線に供給して本来の電圧に戻し、読出しを行う。   In the MLC, low level L, medium level M, and high level H voltages are sequentially supplied to the word line for reading, but as shown in FIG. 1, in the first embodiment of the present invention, the low level L When reading is performed by supplying a voltage to the word line, a medium level M voltage is once supplied to the word line to raise the word line voltage, and then a low level L voltage is supplied to the word line to achieve the original voltage. Return to, and read. Further, when reading is performed by supplying a medium level M voltage to the word line, a high level H voltage is once supplied to the word line to raise the word line voltage, and then the medium level M voltage is applied to the word line. To return to the original voltage and read out. Further, when reading is performed by supplying a high level H voltage to the word line, a voltage of a fourth level Z higher than the high level H is supplied to the word line, the word line voltage is once raised, A voltage of level H is supplied to the word line to return to the original voltage, and reading is performed.

このように、本発明の第１実施形態では、所定レベルの電圧をワード線に供給して読出しを行うとき、一段高い電圧を一旦ワード線に供給してワード線電圧を立上げた後、前記所定レベルの電圧をワード線に供給して本来の電圧に戻し、読出しを行う。ここで、ワード線に関しては、立上げレベルが高い程、任意の時間における到達電圧が高い、あるいは任意の電圧における到達時間が速い。したがって、各レベルの読出し電圧より高い電圧でワード線電圧を一旦立上げれば、ワード線電圧の立上げ時間が速いことが以下の数１から分る。   As described above, according to the first embodiment of the present invention, when reading is performed by supplying a voltage of a predetermined level to the word line, a voltage higher by one step is temporarily supplied to the word line and then the word line voltage is raised. A voltage of a predetermined level is supplied to the word line to return to the original voltage, and reading is performed. Here, regarding the word line, the higher the rising level, the higher the reached voltage at an arbitrary time, or the faster the arrival time at an arbitrary voltage. Therefore, once the word line voltage is raised at a voltage higher than the read voltage at each level, it can be seen from the following formula 1 that the rise time of the word line voltage is fast.

Figure 2010140554
ここで、Ｖｏｕｔはワード線電圧、Ｅは一旦立上げるレベルの電圧、ＲＣはドライバとワード線に含まれる負荷である。
Figure 2010140554
 Here, Vout is a word line voltage, E is a voltage that is once raised, and RC is a load included in the driver and the word line.

そして、このようにして本発明の第１実施形態ではワード線電圧の立上げが速くなり、読出し電圧の確定が速くなり、セルアレイの近端と遠端における読出し電圧確定が速くなることでマージン確保が改善され、結果的に読出し動作の高速化が可能となる。また、この方法は、電圧の切替え手段だけを設ければよいので、サブデコーダを設ける場合のようにレイアウト面積の増大を招くことがない。   Thus, in the first embodiment of the present invention, the rise of the word line voltage is accelerated, the read voltage is quickly determined, and the read voltage is determined at the near end and the far end of the cell array, thereby ensuring a margin. As a result, the reading operation can be speeded up. In addition, since this method only needs to provide voltage switching means, the layout area does not increase as in the case where a sub-decoder is provided.

図２に、上記のような本発明の第１実施形態を実現するための回路構成図を示す。この図において、ＷＬはワード線で、複数のＭＬＣ１１のゲートに接続される。各ＭＬＣ１１のドレインは対応するそれぞれのビット線ＢＬに接続される。ワード線ＷＬは、デコード信号を入力とするワード線ドライバ１２により駆動される。ワード線ドライバ１２には、ワード線電圧切替え回路１３が接続される。   FIG. 2 is a circuit configuration diagram for realizing the first embodiment of the present invention as described above. In this figure, WL is a word line and is connected to the gates of a plurality of MLCs 11. The drain of each MLC 11 is connected to the corresponding bit line BL. The word line WL is driven by a word line driver 12 that receives a decode signal. A word line voltage switching circuit 13 is connected to the word line driver 12.

ワード線電圧切替え回路１３は、低レベルＬ、中レベルＭ、高レベルＨ、第４レベルＺの電圧源ＶＰＸと、この電圧源ＶＰＸの各レベルの電圧をワード線ドライバ１２に供給する第１ないし第４スイッチトランジスタ１４Ｌ，１４Ｍ，１４Ｈ，１４Ｚとを有する。第１スイッチトランジスタ１４Ｌは、第１スイッチ制御信号ＲＤＨＢＬにより制御されて低レベルＬの電圧をワード線ドライバ１２に供給する。第２スイッチトランジスタ１４Ｍは、第２スイッチ制御信号ＲＤＨＢＭにより制御されて中レベルＭの電圧をワード線ドライバ１２に供給する。第３スイッチトランジスタ１４Ｈは、第３スイッチ制御信号ＲＤＨＢＨにより制御されて高レベルＨの電圧をワード線ドライバ１２に供給する。第４スイッチトランジスタ１４Ｚは、第４スイッチ制御信号ＲＤＨＢＺにより制御されて第４レベルＺの電圧をワード線ドライバ１２に供給する。   The word line voltage switching circuit 13 includes a low-level L, medium-level M, high-level H, and fourth-level Z voltage source VPX, and first to first voltages supplied from the voltage source VPX to the word line driver 12. The fourth switch transistors 14L, 14M, 14H, and 14Z are included. The first switch transistor 14L is controlled by the first switch control signal RDHBL to supply a low level L voltage to the word line driver 12. The second switch transistor 14M supplies a medium level M voltage to the word line driver 12 under the control of the second switch control signal RDHBM. The third switch transistor 14H is controlled by the third switch control signal RDHBH and supplies a high level voltage to the word line driver 12. The fourth switch transistor 14Z is controlled by the fourth switch control signal RDHBZ and supplies the voltage of the fourth level Z to the word line driver 12.

したがって、低レベルＬの電圧をワード線ＷＬに供給して読出しを行うときは、第２スイッチ制御信号ＲＤＨＢＭにより第２スイッチトランジスタ１４Ｍを一旦オンして中レベルＭの電圧をワード線ドライバ１２さらにはワード線ＷＬに供給した後、第１スイッチ制御信号ＲＤＨＢＬにより第１スイッチトランジスタ１４Ｌをオンして低レベルＬの電圧をワード線ドライバ１２さらにはワード線ＷＬに供給することにより、第１実施形態の動作を実現できる。また、中レベルＭの電圧をワード線ＷＬに供給して読出しを行うときは、第３スイッチ制御信号ＲＤＨＢＨにより第３スイッチトランジスタ１４Ｈを一旦オンして高レベルＨの電圧をワード線ＷＬに供給した後、第２スイッチ制御信号ＲＤＨＢＭにより第２スイッチトランジスタ１４Ｍをオンして中レベルＭの電圧をワード線ＷＬに供給することにより、第１実施形態の動作を実現できる。さらに、高レベルＨの電圧をワード線ＷＬに供給して読出しを行うときは、第４スイッチ制御信号ＲＤＨＢＺにより第４スイッチトランジスタ１４Ｚを一旦オンして第４レベルＺの電圧をワード線ＷＬに供給した後、第３スイッチ制御信号ＲＤＨＢＨにより第３スイッチトランジスタ１４Ｈをオンして高レベルＨの電圧をワード線ＷＬに供給することにより、第１実施形態の動作を実現できる。   Accordingly, when reading is performed by supplying a low-level L voltage to the word line WL, the second switch transistor 14M is temporarily turned on by the second switch control signal RDHBM, and the medium-level M voltage is supplied to the word line driver 12 and further. After being supplied to the word line WL, the first switch transistor 14L is turned on by the first switch control signal RDHBL to supply a low level L voltage to the word line driver 12 and further to the word line WL. Operation can be realized. When reading is performed by supplying the medium level M voltage to the word line WL, the third switch transistor 14H is once turned on by the third switch control signal RDHBH to supply the high level H voltage to the word line WL. Thereafter, the second switch transistor 14M is turned on by the second switch control signal RDHBM to supply the medium level M voltage to the word line WL, thereby realizing the operation of the first embodiment. Further, when reading is performed by supplying a high level H voltage to the word line WL, the fourth switch transistor 14Z is once turned on by the fourth switch control signal RDHBZ and the fourth level Z voltage is supplied to the word line WL. Thereafter, the third switch transistor 14H is turned on by the third switch control signal RDHBH to supply a high level H voltage to the word line WL, whereby the operation of the first embodiment can be realized.

なお、低レベルＬ、中レベルＭ、高レベルＨの各電圧は既存の回路に存在しているので、これを使用するが、第４レベルＺの電圧は既存の回路に存在していないので、別途別電源を用意して発生させる。しかし、低レベルＬ、中レベルＭ、高レベルＨの電圧に関しても、別電源で発生させてもよい。   Since the low level L, medium level M, and high level H voltages exist in the existing circuit, they are used, but the fourth level Z voltage does not exist in the existing circuit. Prepare a separate power supply. However, the low level L, medium level M, and high level H voltages may be generated by separate power sources.

また、上記第１実施形態のようなワード線電圧の制御方法は、シングルレベルセル（ＳＬＣ）にも適用できる。   The word line voltage control method as in the first embodiment can also be applied to a single level cell (SLC).

次に、本発明の第２実施形態について説明する。本発明の第２実施形態は、低レベルＬ、中レベルＭ、高レベルＨの電圧をワード線に供給して読出しを行うＭＬＣに適用される。図３は、本発明の第２実施形態を説明するための波形図で、(ａ)はワード線電圧、(ｂ)はイコライズ、(ｃ)は出力データ、(ｄ)はワード線供給電圧、(ｅ)は放電タイミングを示す。(ａ)のワード線電圧波形において、実線はワード線ドライバから最も近いセルのゲートに印加されるワード線電圧、点線はワード線ドライバから最も遠いセルのゲートに印加されるワード線電圧である。   Next, a second embodiment of the present invention will be described. The second embodiment of the present invention is applied to an MLC that performs reading by supplying low-level L, medium-level M, and high-level H voltages to a word line. FIG. 3 is a waveform diagram for explaining the second embodiment of the present invention, where (a) is a word line voltage, (b) is equalized, (c) is output data, (d) is a word line supply voltage, (e) shows the discharge timing. In the word line voltage waveform of (a), the solid line is the word line voltage applied to the gate of the cell closest to the word line driver, and the dotted line is the word line voltage applied to the gate of the cell farthest from the word line driver.

ＭＬＣにおいては、低レベルＬ、中レベルＭ、高レベルＨの電圧をワード線に順次供給して読出しを行うが、図３に示すように、本発明の第２実施形態では、最初に、高レベルＨの電圧をワード線に供給して高レベルＨまでワード線の電圧を立上げ、高レベルＨの電圧がワード線に供給された状態で、高レベルＨでの読出し動作を最初に行う。次に、ワード線に接続されたワード線電圧放電用ＮＭＯＳトランジスタをオンさせてワード線電圧を放電させる。そして、ワード線電圧が中レベルＭの電圧より下がったタイミングでワード線電圧放電用ＮＭＯＳトランジスタをオフさせ、同時に中レベルＭの電圧をワード線に供給して中レベルＭの電圧がワード線に供給された状態で、中レベルＭでの読出し動作を行う。その後、ワード線に接続されたワード線電圧放電用ＮＭＯＳトランジスタを再度オンさせてワード線電圧を再度放電させる。そして、ワード線電圧が低レベルＬの電圧より下がったタイミングでワード線電圧放電用ＮＭＯＳトランジスタをオフさせ、同時に低レベルＬの電圧をワード線に供給して低レベルＬの電圧がワード線に供給された状態で、低レベルＬでの読出し動作を行う。   In the MLC, the low level L, medium level M, and high level H voltages are sequentially supplied to the word line to perform reading. However, as shown in FIG. A level H voltage is supplied to the word line, the voltage of the word line is raised to the high level H, and a read operation at the high level H is first performed in a state where the high level H voltage is supplied to the word line. Next, the word line voltage discharging NMOS transistor connected to the word line is turned on to discharge the word line voltage. Then, the word line voltage discharging NMOS transistor is turned off at the timing when the word line voltage falls below the medium level M voltage, and at the same time, the medium level M voltage is supplied to the word line and the medium level M voltage is supplied to the word line. In this state, the read operation at the medium level M is performed. Thereafter, the word line voltage discharging NMOS transistor connected to the word line is turned on again to discharge the word line voltage again. Then, the word line voltage discharging NMOS transistor is turned off at the timing when the word line voltage falls below the low level L voltage, and at the same time, the low level L voltage is supplied to the word line and the low level L voltage is supplied to the word line. In this state, a read operation at a low level L is performed.

ここで、ワード線に関しては、立上げレベルが高い程、任意の時間における到達電圧が高い、あるいは任意の電圧における到達時間が速い。したがって、低いレベルから順次ワード線電圧を増大させるよりは、最初に最も高い電圧をワード線に供給した方がワード線の立上げ時間が速いことが以下の数２から分る。   Here, regarding the word line, the higher the rising level, the higher the reached voltage at an arbitrary time, or the faster the arrival time at an arbitrary voltage. Therefore, it can be seen from the following formula 2 that the rise time of the word line is faster when the highest voltage is first supplied to the word line than when the word line voltage is increased sequentially from a low level.

Figure 2010140554
ここで、Ｖｏｕｔはワード線電圧、Ｅは一旦立上げるレベルの電圧、ＲＣはドライバとワード線に含まれる負荷である。また、放電用のＮＭＯＳトランジスタは、ドライバに含まれるＰＭＯＳトランジスタよりオン抵抗が低いため、数２におけるＲＣ分が小さくなる。すなわち、負荷が軽くなり、立上りよりさらに速い時間で放電を行える。
Figure 2010140554
 Here, Vout is a word line voltage, E is a voltage that is once raised, and RC is a load included in the driver and the word line. In addition, since the discharge NMOS transistor has a lower on-resistance than the PMOS transistor included in the driver, the RC component in Equation 2 is reduced. That is, the load becomes lighter, and discharge can be performed in a faster time than the rise.

したがって、最初に最も高いレベルの電圧をワード線に供給し、その後その電圧から放電により電圧を下げていく本発明の第２実施形態によれば、第１実施形態と同様に、読出し電圧の確定が速くなり、セルアレイの近端と遠端における読出し電圧確定が速くなることでマージン確保が改善され、結果的に読出し動作の高速化が可能となる。また、この方法も、電圧の切替え、放電手段だけを設ければよいので、サブデコーダを設ける場合のようにレイアウト面積の増大を招くことがない。   Therefore, according to the second embodiment of the present invention in which the highest level voltage is first supplied to the word line and then the voltage is lowered from the voltage by discharging, as in the first embodiment, the read voltage is determined. Since the read voltage is determined quickly at the near end and the far end of the cell array, the margin is improved, and as a result, the read operation can be speeded up. This method also requires only voltage switching and discharging means, so that the layout area is not increased as in the case of providing a sub-decoder.

図４に、本発明の第２実施形態を実現するための回路構成図を示す。この回路は、図２の回路と同様であるが、ワード線電圧切替え回路１３において、第４レベルＺの電圧源と、第４スイッチトランジスタ１４Ｚが省略されている。その一方で、ワード線ＷＬにはワード線電圧放電用ＮＭＯＳトランジスタ１５が接続されており、このＮＭＯＳトランジスタ１５はワード線放電制御信号ＤＣＧにより制御される。   FIG. 4 shows a circuit configuration diagram for realizing the second embodiment of the present invention. This circuit is the same as the circuit of FIG. 2 except that the voltage source of the fourth level Z and the fourth switch transistor 14Z are omitted in the word line voltage switching circuit 13. On the other hand, a word line voltage discharge NMOS transistor 15 is connected to the word line WL, and this NMOS transistor 15 is controlled by a word line discharge control signal DCG.

この回路においては、最初に、第３スイッチ制御信号ＲＤＨＢＨにより第３スイッチトランジスタ１４Ｈをオンさせて高レベルＨの電圧をワード線ドライバ１２さらにはワード線ＷＬに供給することにより、高レベルＨの電圧で読出し動作を行う。次に、ワード線放電制御信号ＤＣＧによりワード線電圧放電用ＮＭＯＳトランジスタ１５をオンさせてワード線電圧を放電させ、ワード線電圧が中レベルＭの電圧より下がったタイミングでワード線電圧放電用ＮＭＯＳトランジスタ１５をオフさせ、同時に第２スイッチ制御信号ＲＤＨＢＭにより第２スイッチトランジスタ１４Ｍをオンさせて中レベルＭの電圧をワード線ドライバ１２さらにはワード線ＷＬに供給することにより、中レベルＭの電圧で読出し動作を行う。その後、ワード線放電制御信号ＤＣＧによりワード線電圧放電用ＮＭＯＳトランジスタ１５を再度オンさせてワード線電圧を再度放電させ、ワード線電圧が低レベルＬの電圧より下がったタイミングでワード線電圧放電用ＮＭＯＳトランジスタ１５をオフさせ、同時に第１スイッチ制御信号ＲＤＨＢＬにより第１スイッチトランジスタ１４Ｌをオンさせて低レベルＬの電圧をワード線ドライバ１２さらにはワード線ＷＬに供給することにより、低レベルＬの電圧で読出し動作を行う。このようにして第２実施形態の動作を実現できる。   In this circuit, first, the third switch transistor 14H is turned on by the third switch control signal RDHBH, and a high level H voltage is supplied to the word line driver 12 and further to the word line WL. Read operation with. Next, the word line voltage discharge NMOS transistor 15 is turned on by the word line discharge control signal DCG to discharge the word line voltage, and at the timing when the word line voltage falls below the medium level M voltage, the word line voltage discharge NMOS transistor 15 is turned off, and at the same time, the second switch transistor 14M is turned on by the second switch control signal RDHBM to supply the medium level M voltage to the word line driver 12 and further to the word line WL. Perform the action. Thereafter, the word line voltage discharge NMOS transistor 15 is turned on again by the word line discharge control signal DCG to discharge the word line voltage again. At the timing when the word line voltage falls below the low level L, the word line voltage discharging NMOS transistor is discharged. The transistor 15 is turned off and at the same time the first switch transistor 14L is turned on by the first switch control signal RDHBL to supply a low level L voltage to the word line driver 12 and further to the word line WL. Perform a read operation. In this way, the operation of the second embodiment can be realized.

本発明の第１実施形態を説明するための波形図。The wave form diagram for demonstrating 1st Embodiment of this invention. 本発明の第１実施形態を実現するための回路構成図。The circuit block diagram for implement | achieving 1st Embodiment of this invention. 本発明の第２実施形態を説明するための波形図。The wave form diagram for demonstrating 2nd Embodiment of this invention. 本発明の第２実施形態を実現するための回路構成図。The circuit block diagram for implement | achieving 2nd Embodiment of this invention. 従来のＭＬＣを利用した場合の読出し動作におけるワード線電圧波形図。The word line voltage waveform figure in read-out operation at the time of using conventional MLC.

符号の説明Explanation of symbols

ＷＬ ワード線
ＢＬ ビット線
１１ ＭＬＣ
１２ ワード線ドライバ
１３ ワード線電圧切替え回路
１４Ｌ，１４Ｍ，１４Ｈ，１４Ｚ 第１ないし第４スイッチトランジスタ
１５ ワード線電圧放電用ＮＭＯSトランジスタ WL Word line BL Bit line 11 MLC
DESCRIPTION OF SYMBOLS 12 Word line driver 13 Word line voltage switching circuit 14L, 14M, 14H, 14Z 1st thru | or 4th switch transistor 15 NMOS transistor for word line voltage discharge

Claims (5)

ワード線に所定レベルの電圧を供給して読出しを行う不揮発性半導体記憶装置の読出し方法において、前記所定レベルより高い電圧をワード線に供給してワード線電圧を立上げた後、前記所定レベルの電圧をワード線に供給して、該レベルにワード線電圧を設定し、読出しを行うことを特徴とする不揮発性半導体記憶装置の読出し方法。   In a reading method of a nonvolatile semiconductor memory device that performs reading by supplying a voltage of a predetermined level to a word line, after the word line voltage is raised by supplying a voltage higher than the predetermined level to the word line, A reading method for a nonvolatile semiconductor memory device, comprising: supplying a voltage to a word line, setting the word line voltage to the level, and reading. 前記不揮発性半導体記憶装置は低レベル、中レベル、高レベルの電圧をワード線に供給して読出しを行うマルチレベルセルであり、低レベルの電圧をワード線に供給するときは、中レベルの電圧をワード線に供給してワード線電圧を立上げた後、低レベルの電圧をワード線に供給し、中レベルの電圧をワード線に供給するときは、高レベルの電圧をワード線に供給してワード線電圧を立上げた後、中レベルの電圧をワード線に供給し、高レベルの電圧をワード線に供給するときは、該高レベルより高い電圧をワード線に供給してワード線電圧を立上げた後、高レベルの電圧をワード線に供給することを特徴とする請求項１に記載の不揮発性半導体記憶装置の読出し方法。   The non-volatile semiconductor memory device is a multi-level cell that reads by reading a low-level, medium-level, and high-level voltage to the word line. When supplying a low-level voltage to the word line, the non-volatile semiconductor memory device After supplying the word line to the word line and raising the word line voltage, when supplying a low level voltage to the word line and supplying a medium level voltage to the word line, supply a high level voltage to the word line. After the word line voltage is raised, when a medium level voltage is supplied to the word line and a high level voltage is supplied to the word line, a voltage higher than the high level is supplied to the word line. 2. The method of reading data from a nonvolatile semiconductor memory device according to claim 1, wherein a high-level voltage is supplied to the word line after starting up. 複数のレベルの電圧をワード線に順次供給して読出しを行う不揮発性半導体記憶装置の読出し方法において、最初に、最も高いレベルの電圧をワード線に供給して読出し動作を行い、その後、ワード線電圧を放電させて１段低いレベルの電圧より下がったタイミングでその１段低いレベルの電圧をワード線に供給し、読出し動作を行うことを特徴とする不揮発性半導体記憶装置の読出し方法。   In a reading method of a nonvolatile semiconductor memory device in which reading is performed by sequentially supplying a plurality of levels of voltages to a word line, first, a reading operation is performed by supplying the highest level voltage to the word line, and then the word line A read method for a nonvolatile semiconductor memory device, wherein a read operation is performed by supplying a voltage of a level lower by one level to a word line at a timing when the voltage is discharged and lowered by a level lower than the voltage of a level lower by one level. 前記不揮発性半導体記憶装置は低レベル、中レベル、高レベルの電圧をワード線に供給して読出しを行うマルチレベルセルであり、最初に、高レベルの電圧をワード線に供給して読出し動作を行い、次に、ワード線電圧を放電させてワード線電圧が中レベルの電圧より下がったタイミングで中レベルの電圧をワード線に供給し、読出し動作を行い、その後、ワード線電圧を放電させてワード線電圧が低レベルの電圧より下がったタイミングで低レベルの電圧をワード線に供給し、読出し動作を行うことを特徴とする請求項３に記載の不揮発性半導体記憶装置の読出し方法。   The non-volatile semiconductor memory device is a multi-level cell that performs reading by supplying low-level, medium-level, and high-level voltages to a word line. First, a high-level voltage is supplied to the word line to perform a read operation. Next, discharge the word line voltage, supply the medium level voltage to the word line at the timing when the word line voltage falls below the medium level voltage, perform the read operation, and then discharge the word line voltage 4. The read method for a nonvolatile semiconductor memory device according to claim 3, wherein a read operation is performed by supplying a low level voltage to the word line at a timing when the word line voltage falls below the low level voltage. ワード線電圧の放電は、ワード線に接続されたＮＭＯＳトランジスタにより行われることを特徴とする請求項３または４に記載の不揮発性半導体記憶装置の読出し方法。   5. The method of reading data from a nonvolatile semiconductor memory device according to claim 3, wherein discharging of the word line voltage is performed by an NMOS transistor connected to the word line.
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