JP2010118445A - Thin-film transistor, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor such that the thickness of a gate insulating layer is easily made thick and semiconductor characteristics of a channel layer region are prevented from deteriorating caused by the influence of the gate insulating layer. <P>SOLUTION: A source electrode 5 and a drain electrode 6 are formed at an interval on a substrate 1, and a semiconductor layer 4 is formed of an oxide semiconductor layer on those source electrode 5, drain electrode 6, and substrate 1. On the semiconductor layer 4, an insulating layer 3 is formed of an organic insulating layer and on the insulating layer 3, a gate electrode 2 is formed to obtain the thin-film transistor 10 having a top gate structure. The organic insulating layer is formed after the oxide semiconductor layer is formed so as to prevent deterioration in semiconductor characteristics due to mixing of an organic substance in the organic insulating layer with the oxide semiconductor during the formation of the oxide semiconductor layer. The organic insulating layer is made thicker than the metal oxide insulating layer to improve electric endurance characteristics very easily. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor having a source electrode, a drain electrode, a gate electrode, a semiconductor layer, and an insulating layer interposed between the gate electrode and the semiconductor layer.

  2. Description of the Related Art In recent years, oxide transistors that can be manufactured at low cost by a low temperature process have been actively developed. As this oxide transistor, development using ZnO or InGaZnO as a channel layer is progressing, and transistor characteristics superior to those of a thin film transistor using amorphous silicon as a channel layer are also obtained (Nature, vol. 432). (2004), P. 488). For example, Japanese Unexamined Patent Publication No. 2000-150900 discloses a transistor using ZnO as a channel layer.

I. Currently, metal oxide insulators such as silicon oxide, aluminum oxide, tantalum oxide, hafnium oxide, and yttrium oxide are mainly used as gate insulating films of these thin film transistors. When these metal oxide insulators are used as a gate insulating film, the channel layer in contact with the gate insulating film is not altered, and the semiconductor characteristics of the channel layer are favorably maintained.

  When industrially forming a gate insulating film made of these metal oxide insulators, a sputtering method is often used. In particular, when a film substrate such as PET is used as the substrate, a sputter deposition method without heating is mainly used.

However, when a gate insulating film made of these metal oxide insulators is formed by a sputtering method, there is a problem that productivity is poor because the film forming speed is very slow. In addition, when a film is formed at a low temperature, it is often difficult to obtain sufficient withstand voltage characteristics and low leakage current, and it is difficult to apply to high-voltage driven devices such as QR-LPD.
II. In addition, an organic material such as PVP, polyimide, or acrylic resin is often used as the gate insulating film of the thin film transistor. These organic gate insulating films can be formed by a coating process such as spin coating or an inkjet method, and it is very easy to form a thick film on the order of microns.

  FIG. 2 is a schematic sectional view showing an example of a thin film transistor in which the gate insulating film is an organic gate insulating film. In this thin film transistor 10, a gate electrode 2 is formed on a substrate 1 by sputtering, and the above organic material is applied and dried thereon to form an insulating layer (organic gate insulating film) 3. Is formed by sputtering, and then the source electrode 5 and the drain electrode 6 are formed by sputtering.

However, in the thin film transistor 10, when the semiconductor layer 4 is formed on the insulating layer (organic gate insulating film) 3, the organic matter in the insulating layer 3 enters the semiconductor layer 4 as an impurity, and transistor characteristics are improved. There is a problem of significant deterioration.
JP 2000-150900 A Nature, vol. 432 (2004), p. 488

  An object of the present invention is to provide a thin film transistor in which it is easy to increase the thickness of a gate insulating layer, and deterioration of semiconductor characteristics of a channel layer due to the influence of the gate insulating layer is prevented.

  A thin film transistor of the present invention (Claim 1) is a thin film transistor having a source electrode and a drain electrode connected by a semiconductor layer on a substrate, and a gate electrode on the semiconductor layer with an insulating layer interposed therebetween, The semiconductor layer is an oxide semiconductor layer, and the insulating layer is an organic insulating layer.

  The thin film transistor according to claim 2 is the thin film transistor according to claim 1, wherein the oxide semiconductor layer is a ZnO semiconductor, an Al-doped ZnO semiconductor, an InGaZnO semiconductor, an InWO semiconductor, an InWSnO semiconductor, an InWSnO semiconductor, an InWSnZnO semiconductor, an InSnO semiconductor, an InZnO semiconductor, or It is characterized by comprising an InTiO semiconductor.

  The thin film transistor according to claim 3 is the thin film transistor according to claim 1 or 2, wherein the organic insulating layer is made of at least one of PVP, polyimide, epoxy resin, amorphous fluororesin, melamine resin, furan resin, xylene resin, polyamideimide, and silicon resin. It is characterized by becoming.

  A thin film transistor according to a fourth aspect is characterized in that, in any one of the first to third aspects, the substrate is made of at least one of PET, polyethylene naphthalate, polyimide, and PES.

  The thin film transistor according to claim 5 is characterized in that, in any one of claims 1 to 4, the thickness of the organic insulating layer is 100 nm to 2 μm.

  The thin film transistor according to claim 6 is the thin film transistor according to any one of claims 1 to 4, wherein the organic insulating layer includes a first organic insulating layer on the oxide semiconductor layer side and a second organic insulating layer on the gate electrode side. The first organic insulating layer is made of an amorphous fluororesin having a thickness of 5 nm to 200 nm, and the second organic insulating layer is an organic insulating material different from the amorphous fluororesin having a thickness of 100 nm to 2 μm. It is characterized by comprising.

  The thin film transistor manufacturing method of the present invention (invention 7) is the method of manufacturing a thin film transistor according to any one of claims 1 to 6, wherein the source electrode, the drain electrode, and the oxide semiconductor are formed on the substrate. A layer is formed, and then the organic insulating layer and the gate electrode are formed in this order over the oxide semiconductor layer.

  The method of manufacturing a thin film transistor according to claim 8 is the method of manufacturing a thin film transistor according to claim 7, wherein the source electrode and the drain electrode are formed on the substrate with a space therebetween, and then at least the source electrode and the drain electrode on the upper surface of the substrate The oxide semiconductor layer is formed so as to straddle the portion between the upper surface of the source electrode and the upper surface of the drain electrode, and then the organic insulating layer and the gate are formed on the oxide semiconductor layer. The electrodes are formed in this order.

  The method for manufacturing a thin film transistor according to claim 9 is the method according to claim 7, wherein the oxide semiconductor layer is formed on the substrate, and then the source electrode and the drain electrode are spaced apart on the oxide semiconductor layer. Next, the organic insulating layer is formed so as to straddle at least a portion between the source electrode and the drain electrode, an upper surface of the source electrode, and an upper surface of the drain electrode of the upper surface of the oxide semiconductor layer. A layer is formed, and then the gate electrode is formed on the organic insulating layer.

  A method for manufacturing a thin film transistor according to a tenth aspect is the method according to any one of the seventh to ninth aspects, wherein the oxide semiconductor layer is formed by a sputtering method.

  A thin film transistor manufacturing method according to an eleventh aspect is characterized in that, in any one of the seventh to tenth aspects, the organic insulating layer is formed by applying an organic insulating layer material-containing liquid and drying.

  In the thin film transistor and the method of manufacturing the same of the present invention, the thin film transistor has a top gate structure (that is, a source electrode and a drain electrode connected by a semiconductor layer on a substrate, and an insulating layer is interposed on the semiconductor layer). A structure having a gate electrode), and the semiconductor layer is an oxide semiconductor layer and the insulating layer is an organic insulating layer. Thereby, the improvement of the semiconductor characteristic of a semiconductor layer and the improvement of the withstand voltage characteristic of an insulating layer can be aimed at. In other words, according to the present invention, the organic insulating layer can be formed after the oxide semiconductor layer is formed over the substrate, so that organic substances in the organic insulating layer are mixed into the oxide semiconductor layer when the oxide semiconductor layer is formed. Thus, deterioration of the semiconductor characteristics is prevented. In addition, the organic insulating layer can be easily increased in thickness as compared with the metal oxide insulating layer, which can sufficiently improve the withstand voltage characteristics.

  In the present invention, when the oxide semiconductor layer is made of a ZnO semiconductor, an Al-doped ZnO semiconductor, an InGaZnO semiconductor, an InWO semiconductor, an InWSnO semiconductor, an InWSnO semiconductor, an InWSnZnO semiconductor, an InSnO semiconductor, an InZnO semiconductor, or an InTiO semiconductor, Good semiconductor characteristics such as degree. The oxide semiconductor layer may be formed by a sputtering method.

  In the present invention, when the organic insulating layer is made of at least one of PVP, polyimide, epoxy resin, amorphous fluorine resin, melamine resin, furan resin, xylene resin, polyamideimide, and silicon resin, higher withstand voltage characteristics and low leakage current Can be obtained.

  In the present invention, since the insulating layer is an organic insulating layer, and the organic insulating layer can be formed at a low temperature, the thin film transistor can be manufactured by a low temperature process. Accordingly, the substrate can be made of various polymer films such as PET, polyethylene naphthalate, polyimide, and PES. Accordingly, the thin film transistor can be a flexible device having flexibility.

The thickness of the organic insulating layer is preferably 100 nm to 2 μm. The thickness of the organic insulating layer means a thickness that is actually effective. Specifically, this corresponds to the distance between the gate electrode and the semiconductor layer.
The organic insulating layer includes a first organic insulating layer on the oxide semiconductor layer side and a second organic insulating layer on the gate electrode side. The first organic insulating layer is made of an amorphous fluororesin having a thickness of 5 nm to 200 nm. Thus, the second organic insulating layer may be made of an organic insulating material having a thickness of 100 nm to 2 μm and different from the amorphous fluororesin. In this case, the second organic insulating layer is preferably thicker than the first organic insulating layer. By using an amorphous fluororesin for the first organic insulating layer, introduction of impurities into the oxide semiconductor is favorably suppressed. Moreover, the withstand voltage performance of the whole organic insulating layer is improved by using the second organic insulating layer as an organic insulating material having a higher withstand voltage performance than the amorphous fluororesin.

  In the present invention, the source electrode and the drain electrode may be located on either the upper surface or the lower surface of the oxide semiconductor.

  That is, in the present invention, first, a source electrode and a drain electrode are formed on a substrate with a space therebetween, then, a portion between the source electrode and the drain electrode on the upper surface of the substrate, and the source electrode The oxide semiconductor layer may be formed so as to straddle the upper surface of the drain electrode and the upper surface of the drain electrode, and then the organic insulating layer and the gate electrode may be formed in this order on the oxide semiconductor layer.

  In addition, an oxide semiconductor layer is first formed over a substrate, and then a source electrode and a drain electrode are formed over the oxide semiconductor layer with a space therebetween, and then the source of the top surface of the oxide semiconductor layer is the source An organic insulating layer is formed so as to straddle a portion between the electrode and the drain electrode, an upper surface of the source electrode, and an upper surface of the drain electrode, and then a gate electrode is formed on the organic insulating layer. May be.

  The organic insulating layer may be formed by applying an organic insulating layer material-containing liquid and drying. Thereby, an organic insulating layer having a large thickness can be easily manufactured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic view showing an example of a thin film transistor of the present invention.

  The thin film transistor 10 has a source electrode 5 and a drain electrode 6 connected to each other by a semiconductor layer 4 on a substrate 1 and has a top gate structure having a gate electrode 2 on the semiconductor layer 4 with an insulating layer 3 interposed therebetween. is doing. The semiconductor layer 4 is made of an oxide semiconductor layer, and the insulating layer 3 is made of an organic insulating layer.

  In order to manufacture the thin film transistor 10, first, the source electrode 5 and the drain electrode 6 are formed on the substrate 1 with a space therebetween, and then the semiconductor layer 4 is formed on the source electrode 5, the drain electrode 6 and the substrate 1. . Next, the insulating layer 3 is formed on the semiconductor layer 4, and the gate electrode 2 is formed on the insulating layer 3.

  As the substrate 1, for example, glass such as alkali silicate glass, non-alkali glass, or quartz glass can be used. When the thin film transistor 10 is applied as a flexible device, the substrate 1 may be a plate substrate or a film substrate made of various synthetic resins such as PET, polyethylene naphthalate (PEN), polyimide, PES, and acrylic. Can also be used. The thickness of the substrate 1 is generally 0.05 to 10 mm, and preferably 0.2 to 5 mm.

As the source electrode 5 and the drain electrode 6, an AZO conductor, an ITO conductor, a metal film such as Al or Au, a conductive polymer film such as PEDOT-PSS, or the like is used. In the case of an AZO conductor, the atomic ratio Al / (Zn + Al) is preferably 0.01 to 30 atm%, particularly preferably 0.1 to 5 atm%. The specific resistance of the source electrode 5 and the drain electrode 6 is preferably 10 ⁻² Ω · cm or less, particularly preferably 10 ⁻³ Ω · cm or less. The specific resistance of the source electrode 5 and the drain electrode 6 can also be controlled by controlling the amount of oxygen introduced during film formation. The thicknesses of the source electrode 5 and the drain electrode 6 are, for example, about 5 to 200 nm. The distance between these electrodes 5 and 6 (channel length) is about 1 μm to 200 μm. The depth (channel width) of each electrode 5 and 6 depends on the required amount of current.

  The source electrode 5 and the drain electrode 6 can be formed on the substrate 1 by physical vapor deposition, for example, sputtering such as DC reactive sputtering or RF sputtering, pulse laser deposition, or the like.

The semiconductor layer 4 is made of an oxide semiconductor layer. The semiconductor layer 4 includes a ZnO semiconductor, an Al-doped ZnO semiconductor (AZO semiconductor), an InGaZnO semiconductor, an InWO semiconductor, an InWSnO semiconductor, an InWSnO semiconductor, an InWSnZnO semiconductor, an InSnO semiconductor, an InZnO semiconductor, an InTiO semiconductor, a Cu ₂ O semiconductor, A NiO semiconductor, an Al-doped Cu ₂ O semiconductor, or the like is used. In the case of an AZO semiconductor, the atomic ratio Al / (Zn + Al) is preferably 0.01 to 30 atm%, particularly preferably 0.1 to 5 atm%.

The specific resistance of the semiconductor layer 4 is preferably 10 ⁻¹ to 10 ⁷ Ω · cm, more preferably 1 to 10 ⁵ Ω · cm. When the specific resistance is within this range, the field effect mobility and the on / off ratio are sufficiently high. The thickness of the semiconductor layer 4 is, for example, about 10 nm to 100 nm.

  The semiconductor layer 4 can be formed on the substrate 1, the source electrode 5, and the drain electrode 6 by various physical vapor deposition methods as in the case of the source electrode 5 and the drain electrode 6.

  This insulating layer 3 is made of an organic insulating layer. As this insulating layer 3, PVP, polyimide, epoxy resin, amorphous fluororesin, melamine resin, furan resin, xylene resin, polyamideimide, silicon resin, or the like is preferably used.

The thickness of the insulating layer 3 depends on the device, but is preferably 10 nm to 2 μm, particularly preferably 100 nm to 2 μm, and more preferably 0.3 μm to 1.5 μm for QR-LPD. If it is less than 10 nm, the gate leakage current cannot be sufficiently suppressed. If it exceeds 2 μm, the gate voltage applied to the gate electrode 2 needs to be excessive. The specific resistance of the insulating layer 3 is preferably 1 × 10 ¹¹ Ω · cm or more, for example, 1 × 10 ¹¹ to 10 ¹⁵ Ω · cm, particularly preferably 1 × 10 ¹³ or more.

  The “thickness of the insulating layer 3” means an actually effective thickness. Specifically, this corresponds to the distance between the gate electrode and the semiconductor layer, or between the source / drain electrode and the gate electrode.

  The insulating layer 3 can be formed, for example, by applying a liquid containing an organic material for an organic insulating layer to the surface of the semiconductor layer 4, drying it, and baking it as necessary. This containing liquid is preferably an organic material-containing solution obtained by dissolving an organic material in a solvent. By increasing the coating thickness of the contained liquid, the insulating layer 3 having a large thickness can be easily manufactured.

  As a method for applying the liquid, spin coating, screen printing, jet printing, stamp printing, or the like can be used. The firing temperature is preferably 80 to 200 ° C., and the firing time is preferably about 30 minutes to 3 hours. Thus, when the firing temperature is low, a synthetic resin can be used as the substrate 1 as described above.

  When the insulating layer 3 is an amorphous fluororesin, the amorphous fluororesin includes a perfluorocyclopolymer having an oxygen atom as a constituent group. Specifically, Cytop manufactured by Asahi Glass Co., Ltd. is commercially available. The (CYTOP) series (for example, CTX-809, 803M, 805M, 807M, 809M, 811M, 813M) is preferably used. Further, Teflon (Teflon is a registered trademark) AF series (for example, Teflon AF1600, Teflon AF2400, Teflon AF1601S, etc.) manufactured by duPont can also be used.

  As a fluorine-based solvent for dissolving the amorphous fluororesin to obtain an amorphous fluororesin-containing solution, CT-Solv. Manufactured by Asahi Glass Co., Ltd. can be used. 100, CT-solv. 180, DuPont FLUORINERT, FC-75, etc. are suitable.

  In the present invention, since the insulating layer 3 is formed after the semiconductor layer 4 is formed in this way, organic substances in the insulating layer 3 are prevented from being mixed into the semiconductor layer 4 when the semiconductor layer 4 is formed. As a result, the semiconductor characteristics of the semiconductor layer 4 are maintained satisfactorily. On the other hand, when the semiconductor layer 4 is formed by sputtering or the like after the insulating layer 3 is formed as in the conventional example of FIG. 2, organic substances in the insulating layer 3 are mixed when the semiconductor layer 4 is formed. The semiconductor properties of the layer 4 are degraded.

As the gate electrode 2, a transparent conductive film such as ITO (indium tin oxide) or Al-doped ZnO, a metal film such as Al or Au, a conductive polymer film such as PEDOT-PSS, or the like is used. The specific resistance of the gate electrode 2 is, for example, about 8 × 10 ⁻⁵ to 1 × 10 ⁻² Ω · cm. The thickness of the gate electrode 2 is, for example, about 5 nm to 200 μm.

  The gate electrode 2 can be manufactured by various physical vapor deposition methods, similar to the source electrode 5 and the drain electrode 6 described above.

  The above embodiment is an example of the present invention, and the present invention is not limited to the above embodiment.

  For example, the insulating layer 3 may be composed of a first organic insulating layer on the semiconductor layer 4 side and a second organic insulating layer on the gate electrode 2 side. The first organic insulating layer may be made of an amorphous fluororesin having a thickness of 5 nm to 200 nm, and the second organic insulating layer may be made of an organic insulating material different from the amorphous fluororesin having a thickness of 100 nm to 2 μm. .

  Here, when the first organic insulating layer is an amorphous fluororesin, since the glass transition point (Tg) of the amorphous fluororesin is low, the first organic insulating layer can be formed on the semiconductor layer 4 at a low temperature, As a result, introduction of impurities into the semiconductor layer 4 is satisfactorily suppressed.

  In addition, since the glass transition point (Tg) of the amorphous fluororesin is low as described above, when the gate electrode is formed directly on the amorphous fluororesin, the surface of the amorphous fluororesin is uneven by heating, and the gate electrode is bent. In order to avoid cracking, it is necessary to set the heat treatment conditions in detail. On the other hand, by forming an organic insulating layer having higher heat resistance than the amorphous fluororesin on the first organic insulating layer made of amorphous fluororesin and forming a gate electrode thereon, the gate electrode can be easily formed. Can be formed.

  Furthermore, the withstand voltage performance of the entire insulating layer 3 can be improved by making the second organic insulating layer an organic insulating material having a higher withstand voltage performance than that of the amorphous fluororesin. If the thickness of the second organic insulating layer is made larger than that of the first organic insulating layer, the withstand voltage performance of the entire insulating layer 3 can be further improved.

  In FIG. 1, the source electrode 5 and the drain electrode 6 are disposed on the upper surface of the substrate 1, but the source electrode 5 and the drain electrode 6 may be disposed on the upper surface of the semiconductor layer 4.

  EXAMPLES Hereinafter, although this invention is demonstrated in detail using an Example, a comparative example, and a test example, this invention is not limited to an Example.

Test example 1
A laminate having the structure shown in FIG. 3 was produced under the following conditions. Table 1 shows the material of each layer of the laminate.

  As the substrate 11, 1737 alkali-free glass (length 50 mm × width 80 mm × thickness 1.0 mm) manufactured by Corning was used.

  An oxide semiconductor layer 12 made of a ZnO semiconductor having a thickness of 40 nm was formed on the substrate 11 by non-thermal sputtering. The sputtering conditions of the non-heat sputtering method were as follows.

Target: 75 mmφ metal zinc target Pressure during film formation: 0.5 Pa
Applied voltage: DC150W
Gas flow rate during film formation: Ar / O ₂ = 96 / 4.0 sccm
Deposition time: 10 minutes

Test example 2
A laminate having the structure shown in FIG. 4 was produced under the following conditions. Table 1 shows the material of each layer of the laminate.

  An amorphous fluorine-containing solution is spin-coated for 90 seconds at 1900 rpm on the same substrate 11 as in Test Example 1, and then baked at 120 ° C. for 1 hour to form an organic insulating layer made of an amorphous fluorine resin having a thickness of 0.54 μm. 13 was formed.

  As the amorphous fluorine-containing solution, an amorphous fluororesin (“Cytop CTX-807M” manufactured by Asahi Glass Co., Ltd.) and a solvent (“CT-Solv. 180” manufactured by Asahi Glass Co., Ltd.) are used at 80:20 (wt). %) Was used.

  An oxide semiconductor layer 12 made of a ZnO semiconductor having a thickness of 40 nm was formed on the organic insulating layer 13 under the same sputtering conditions as in Test Example 1.

Test example 3
A laminate having the structure shown in FIG. 4 was produced under the following conditions. Table 1 shows the material of each layer of the laminate.

  On the same glass substrate 11 as in Test Example 1, a polyimide resin (“Kemitite” manufactured by Kyocera Chemical Co., Ltd.) was spin-coated at 1900 rpm for 180 seconds, then baked at 200 ° C. for 1 hour, and a 0.78 μm thick organic An insulating layer 13 was formed. Next, an oxide semiconductor layer 12 made of a ZnO semiconductor was formed under the same conditions as in Test Example 1.

Test example 4
A laminate having the structure shown in FIG. 4 was produced under the following conditions. Table 1 shows the material of each layer of the laminate.

  An acrylic resin (“Acrylite” manufactured by Mitsubishi Rayon Co., Ltd.) is applied on the same glass substrate 11 as in Test Example 1 by screen printing, cured by irradiating UV light, and a 0.89 μm organic insulating layer 13 is formed. Formed. Next, an oxide semiconductor layer 12 made of a ZnO semiconductor was formed under the same conditions as in Test Example 1.

Test Examples 5-7
The laminated bodies of Test Examples 5 to 7 were manufactured in the same manner as Test Examples 2 to 4, respectively, except that the order of manufacturing the oxide semiconductor layer 12 and the organic insulating layer 13 was reversed. The structures and materials of the laminates of these test examples 5 to 7 are shown in FIG.

Test Examples 8-14
The laminated bodies of Test Examples 8 to 14 were manufactured in the same manner as Test Examples 1 to 7, respectively, except that the oxide semiconductor layer 12 was an InGaZnO semiconductor. Table 2 shows the materials of Test Examples 8 to 14.

  The oxide semiconductor layer 12 made of this InGaZnO semiconductor was formed under the following sputtering conditions by a non-thermal sputtering method.

Target: 75 mmφ InGaZnO sintered body target
(In: Ga: Zn = 1: 1: 1 (atm ratio))
Pressure during film formation: 0.5 Pa
Applied voltage: DC150W
Gas flow rate during film formation: Ar / O ₂ = 98 / 2.0 sccm
Deposition time: 5 minutes
Film thickness: 35nm

Test Examples 15-21
The laminated bodies of Test Examples 15 to 21 were manufactured in the same manner as Test Examples 1 to 7, respectively, except that the oxide semiconductor layer 12 was an InWO semiconductor. Table 3 shows the materials of Test Examples 15 to 21.

  Note that the oxide semiconductor layer 12 made of this InWO semiconductor was formed under the following sputtering conditions by a non-heated sputtering method.

Target: 75 mmφ InWZnO sintered body target
(W = 5wt%, Zn = 0.5wt%)
Pressure during film formation: 0.5 Pa
Applied voltage: DC150W
Gas flow rate during film formation: Ar / O ₂ = 94 / 6.0 sccm
Deposition time: 5 minutes
Film thickness: 30nm

<Measurement of sheet resistance>
About what made each sample of the said test examples 1-21 into the magnitude | size of 30 mm x 70 mm, sheet resistance was measured using Mitsubishi Chemical Corporation "Hirester-UP". The results are shown in Table 1.

  The resistivity of the sample having the structure shown in FIG. 3 (Test Examples 1, 8, and 15) is considered to be the original resistivity of the oxide semiconductor layer.

  It is confirmed that the samples having the structure shown in FIG. 4 (Test Examples 2 to 4, 9 to 11, and 16 to 18) have a lower resistivity than the samples having the structure shown in FIG. 3 (Test Examples 1, 8, and 15). It was done. In particular, when the samples in which the organic insulating layer 13 is a polyimide resin and an acrylic resin are compared, the samples having the structure shown in FIG. 4 (Test Examples 3, 4, 10, 11, 17, and 18) have the structure shown in FIG. The resistivity was significantly smaller than that of the samples (Test Examples 1, 8, and 15).

  On the other hand, the samples having the structure of FIG. 5 (Test Examples 5 to 7, 12 to 14, and 19 to 21) have a resistivity higher than those of the samples having the structure of FIG. 3 (Test Examples 1, 8, and 15). It was confirmed that the difference was very small.

Comparative Example 1
A thin film transistor having the structure of FIG. 2 was produced by the following procedure.

  After forming the gate electrode 2 made of ITO on the substrate 1 by the non-heat sputtering method, an insulating layer 3 made of amorphous fluororesin and a semiconductor layer 4 made of ZnO are formed in this order, and on the semiconductor layer 4 A source electrode 5 and a drain electrode 6 made of ITO were formed by a non-heated sputtering method to obtain a thin film transistor.

  The film formation conditions for the insulating layer 3 and the semiconductor layer 4 were the same as the film formation conditions for the organic insulating layer 13 and the oxide semiconductor layer 12 of Test Example 2.

  The sputtering conditions for the gate electrode 2, the source electrode 5, and the drain electrode 6 were as follows.

Target: 75 mmφ ITO target (In: Sn (mass ratio) = 90: 10)
Pressure during film formation: 0.5 Pa
Applied voltage: DC150W
Gas flow rate during film _{formation: Ar / O 2 = 99 /} 1.0sccm
Deposition time: 3 minutes
Film thickness: 40nm

  When forming the source electrode 5 and the drain electrode 6, a shadow mask was used, the channel length (the distance between the source electrode and the drain electrode) was set to 0.1 mm, and the channel width (the depth of the source electrode and the drain electrode) was set to 6.4 mm. .

Comparative Examples 2 and 3
A thin film transistor was fabricated in the same manner as in Comparative Example 1 except that the insulating layer 3 was made of polyimide resin (Comparative Example 2) and acrylic resin (Comparative Example 3), respectively.

  In Comparative Examples 2 and 3, the film formation conditions of the insulating layer 3 were the same as the film formation conditions of the organic insulating layer 13 in Test Examples 3 and 4, respectively.

Example 1
A thin film transistor having the structure shown in FIG. 1 was prepared by the following procedure.

  After the ITO source electrode 5 and the drain electrode 6 are formed on the substrate 1 by a non-thermal sputtering method, a ZnO semiconductor layer 4 and an amorphous fluororesin insulating layer 3 are formed in this order, and this insulating layer A gate electrode 2 made of ITO was formed on the substrate 3 by a non-heat sputtering method to obtain a thin film transistor.

  The film formation conditions for the insulating layer 3 and the semiconductor layer 4 were the same as the film formation conditions for the organic insulating layer 13 and the oxide semiconductor layer 12 of Test Example 2.

  The sputtering conditions for the gate electrode 2, the source electrode 5, and the drain electrode 6 were the same as in Comparative Example 1.

Examples 2 and 3
A thin film transistor was fabricated in the same manner as in Example 1 except that the insulating layer 3 was made of polyimide resin (Example 2) and acrylic resin (Example 3), respectively.

  In Examples 2 and 3, the conditions for forming these insulating layers 3 were the same as the conditions for forming the organic insulating layer 13 in Test Examples 3 and 4, respectively.

Comparative Examples 4-6 and Examples 4-6
Thin film transistors of Comparative Examples 4 to 6 and Examples 4 to 6 were produced in the same manner as Comparative Examples 1 to 3 and Examples 1 to 3, respectively, except that the semiconductor layer 4 was an InGaZnO semiconductor.

  The deposition conditions for the InGaZnO semiconductor layer 4 were the same as the deposition conditions for the oxide semiconductor layer 12 of Test Example 9.

Comparative Examples 7-9 and Examples 7-9
Thin film transistors of Comparative Examples 7 to 9 and Examples 7 to 9 were produced in the same manner as Comparative Examples 1 to 3 and Examples 1 to 3, respectively, except that the semiconductor layer 4 was an InWO semiconductor.

  The deposition conditions for the InWO semiconductor layer 4 were the same as the deposition conditions for the oxide semiconductor layer 12 of Test Example 16.

  Tables 4 to 6 show an outline of the structures and materials of the thin film transistors of the examples and comparative examples.

<Measurement of transistor characteristics>
As transistor characteristics, the gate voltage dependence of the drain current when the drain voltage was 70V was measured. As a measuring apparatus, Agilent's semiconductor parameter analyzer “4155C” was used.

  The measurement results of Comparative Examples 1-3 and Examples 1-3, Comparative Examples 4-6, Examples 4-6, Comparative Examples 7-9, and Examples 7-9 are shown in FIGS.

  As is apparent from FIGS. 6 to 8, among the thin film transistors (Comparative Examples 1 to 9) having a bottom gate structure (the structure of FIG. 2), the insulating layer 3 is made of polyimide resin (Comparative Examples 2, 5, and 8) and acrylic resin. It was confirmed that those of (Comparative Examples 3, 6, 9) did not have transistor characteristics. That is, it was always turned on without modulation by the gate voltage.

  On the other hand, it was confirmed that the thin film transistors of all Examples (Examples 1 to 9) having a top gate structure (structure of FIG. 1) have good transistor characteristics. That is, the channel was modulated by the change in the gate voltage, and a clear change from the off state to the on state was confirmed.

It is typical sectional drawing of the thin-film transistor which concerns on embodiment. It is typical sectional drawing of the thin-film transistor of a prior art example. 3 is a schematic cross-sectional view of a sample of Test Example 1. FIG. It is typical sectional drawing of the sample of Test Examples 2-4. It is typical sectional drawing of the sample of Test Examples 5-7. It is a graph which shows the transistor characteristic of a thin-film transistor. It is a graph which shows the transistor characteristic of a thin-film transistor. It is a graph which shows the transistor characteristic of a thin-film transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate electrode 3 Insulating layer 4 Semiconductor layer 5 Source electrode 6 Drain electrode 10, 10A Thin film transistor

Claims (11)

A thin film transistor having a source electrode and a drain electrode connected by a semiconductor layer on a substrate, and having a gate electrode on the semiconductor layer through an insulating layer,
A thin film transistor, wherein the semiconductor layer is an oxide semiconductor layer, and the insulating layer is an organic insulating layer.   2. The oxide semiconductor layer according to claim 1, wherein the oxide semiconductor layer is made of a ZnO semiconductor, an Al-doped ZnO semiconductor, an InGaZnO semiconductor, an InWO semiconductor, an InWSnO semiconductor, an InWSnO semiconductor, an InWSnZnO semiconductor, an InSnO semiconductor, an InZnO semiconductor, or an InTiO semiconductor. A thin film transistor.   3. The thin film transistor according to claim 1, wherein the organic insulating layer is made of at least one of PVP, polyimide, epoxy resin, amorphous fluororesin, melamine resin, furan resin, xylene resin, polyamideimide, and silicon resin. .   4. The thin film transistor according to claim 1, wherein the substrate is made of at least one of PET, polyethylene naphthalate, polyimide, and PES.   5. The thin film transistor according to claim 1, wherein the organic insulating layer has a thickness of 100 nm to 2 μm. 5. The organic insulating layer according to claim 1, wherein the organic insulating layer includes a first organic insulating layer on the oxide semiconductor layer side and a second organic insulating layer on the gate electrode side,
The first organic insulating layer is made of an amorphous fluororesin having a thickness of 5 nm to 200 nm,
The thin film transistor, wherein the second organic insulating layer is made of an organic insulating material having a thickness of 100 nm to 2 μm and different from the amorphous fluororesin. A method for producing the thin film transistor according to claim 1, comprising:
A thin film transistor comprising: forming the source electrode, the drain electrode, and the oxide semiconductor layer on the substrate; and then forming the organic insulating layer and the gate electrode in this order on the oxide semiconductor layer. Manufacturing method. In claim 7, the source electrode and the drain electrode are formed on the substrate at an interval,
Next, the oxide semiconductor layer is formed so as to straddle at least a portion of the upper surface of the substrate between the source electrode and the drain electrode, the upper surface of the source electrode, and the upper surface of the drain electrode,
Next, the organic insulating layer and the gate electrode are formed in this order over the oxide semiconductor layer. The oxide semiconductor layer is formed over the substrate according to claim 7,
Next, the source electrode and the drain electrode are formed on the oxide semiconductor layer with a gap therebetween,
Next, the organic insulating layer is formed so as to straddle at least a portion of the upper surface of the oxide semiconductor layer between the source electrode and the drain electrode, the upper surface of the source electrode, and the upper surface of the drain electrode. ,
Next, the gate electrode is formed on the organic insulating layer.   10. The method for manufacturing a thin film transistor according to claim 7, wherein the oxide semiconductor layer is formed by a sputtering method.   11. The method of manufacturing a thin film transistor according to any one of claims 7 to 10, wherein the organic insulating layer is formed by applying an organic insulating layer material-containing liquid and drying.

Images