JP2010118087A - Method and device for inverting data in memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an efficiency of data transfer from deteriorating caused by large number of transitions in a signal level. <P>SOLUTION: A current word is compared with a preceding word of N bits, to identify the number of the bit transitions from a low level value to a high level value, or reversely from the high level value to the low level value. The current bits are inverted when the number of the transitions is more than N/2. A data mask pin not used usually during writing operation for sending the inverted bits is utilized not to make an extra bit go with a data bite for displaying the presence of the inversion. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to the technical field of writing and reading data.

  Digital data is stored in the memory device as 1 and 0, and these data are transferred to and from the memory device through conductive paths called “pins”. Data is written into the memory as a string of high and low level signals indicating 1 and 0. Each time a change occurs between a low level signal and a high level signal, the efficiency of the memory device decreases. However, since the data is somewhat random, there is no easy way to control the data to reduce the number of changes. This problem can be understood by considering writing to and from the memory device.

  FIG. 1 is a block diagram of a data source and a data receiver. The data source 100 communicates with the data receiver 102 via the bus 101, and the data is transferred in 8-bit blocks called “bytes”. Each byte is sent in parallel to the data receiver 102 as eight data signals on eight lines, where each signal line is either high or low depending on the data being transmitted. For example, when a data value of “1” is sent, the bus line is in a high level state. If the next signal sent is "0", the bus line must fall to a low state to display new data. If the next following signal is "1", the bus line must rise again to a high level value. These state changes are known as data transitions, and time and energy are required to accomplish this. Consider the following scenario showing 8 bytes of data written to the data receiving circuit 102.

  The total number of data transitions in 24-bit bytes 2, 3, and 4 in the above example is 20, ie 83% (this means that each line of the bus was in a low state when the original byte was sent. Please note that As a result, the data transfer system is disadvantageous in terms of time and power to operate.

Data Inversion Scheme The prior art provides a scheme known as “data inversion” to reduce the number of data transitions when writing to a memory device. In this data inversion method, the number of data transitions between one byte and the next byte is determined and analyzed. If the number of transitions is greater than 4, the byte data to be sent is inverted. By doing so, the number of transitions is made less than four. This scheme can set the maximum number of transitions that can occur per byte to 4 for a maximum of 50% transitions. The operation of the data inversion method will be described with reference to the following table.

  Examine the next byte to see how many transitions will occur if the byte is sent without flipping after the first byte is sent. Here, when the byte changes from all 0 to all 1, the number of transitions is 8. Since the number of 8 is larger than 4, the byte is inverted to be all 0s. When sending this byte, each line of the bus is already in a low level state, so there is no data transition. When examining the next byte, the actual byte sent (in this case the inverted byte) is compared with the next byte to determine the number of possible transitions. Without inversion, the number of transitions is 2, and since this number is less than 4, bytes are sent without inversion. When sent without inversion, the number of transitions is 8 when the next byte (01110111) is compared with the already sent byte. Therefore, the byte is inverted to (10001000) and sent without causing a transition. As a result of sending the same data using the inversion scheme, only two transitions of 24 bytes will occur, i.e. only 8.3% transitions. As a result of such an improvement, the data transfer operation becomes better and faster.

  The disadvantage of this data inversion method is that when reading data from the receiving circuit, not only the data but also the extra bit must be sent together with the data byte so that it can be used and stored correctly. These extra bits must be written separately to the bus, data transmission circuit and reception circuit, increasing the cost and complexity of the system.

  The present invention relates to a method for writing information to a synchronous memory device by examining the current word of N bits to be written, each bit having a high or low level value. The current word is compared with a previous word having N bits to identify the number of bit transitions from a low level value to a high level value or vice versa. If the number of transitions is greater than N / 2, the current bit is inverted. The present invention utilizes a data mask pin that is not normally used during a read operation to send an inverted bit so that an extra bit does not have to accompany the data byte to indicate the presence or absence of inversion. . The non-inverted data is written directly to the memory device, while the inverted data is first inverted again before writing to the storage location, so that the true data is stored in the memory device.

It is a block diagram of a data source and a data receiver. FIG. 6 is a diagram of one embodiment for writing data to a device. 1 shows a read circuit for a DRAM of the present invention. It is an example of a DIM generator. 6 is a flowchart illustrating the operation of the present invention during a burst read operation. FIG. 3 is a block diagram of the present invention for use with a microprocessor interface. It is a block diagram of another Example of the read-out block of this invention. 4 is another embodiment of the writing block of the present invention.

The present invention relates to a method and apparatus for reading and writing data. In the following description, numerous specific details are set forth in order to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known features have not been described in detail so as not to obscure the invention.
Currently, no efficient scheme is provided for inverting data in dynamic random access memory (DRAM) systems. One advantage of using DRAM in the system is the low cost of DRAM and the commercial nature of such memory devices. If a DRAM using a data inversion scheme requires extra pins for inversion information, the DRAM cannot be used in many applications where the geography is for a DRAM with only a few pins. Similarly, the expense of manufacturing and selling DRAM with extra pins makes the DRAM less commercially viable.

  The present invention takes advantage of current pins called data mask (DM) pins associated with DRAM data pins. The DM pin is generally used at the data input, but not at the data output. The present invention utilizes the DM pin at the data output end in order to generate a signal indicating whether or not to invert data when outputting data by DM.

  In the DRAM of the preferred embodiment of the present invention, there are 32 data bits DQ0 to DQ31, which are divided into four bytes (each byte is DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23 and DQ24 to DQ31). Is done. Each of the data bytes has an associated data mask pin DM0-DM3, which is used during a write operation to mask the data input signal when appropriate. When any of DM1 to DM3 becomes high level, the data input signal is masked at the same timing.

Write Operation A write operation to the DRAM must be accompanied by an indication of whether or not the incoming data is inverted. A data inversion mask (DIM) bit is included with the data to be written so that the DRAM can store true state data. FIG. 2 shows one implementation for doing this. With the DIM bit 202, the incoming data is added as an input signal 201 to the exclusive OR gate 203. If the DIM bit is high, the incoming data is inverted and is reinverted through the XOR gate 203 before storing it in the data array 204.

Read Operation FIG. 3 shows a DRAM read circuit according to the present invention. Each byte of data has an associated DM pin. For example, data bytes D [7: 0] are associated with DM0, bytes D [15: 8] are associated with DM1, bytes D [23:16] are associated with DM2, and bytes D [ 31:24] is related to DM3. During a read operation, data is provided directly from the array 300 to the data input pins and DIM generators, eg, generators 301.1 to 301.4. The DM generator determines whether data should be inverted to reduce data transitions during read operations. The output signal of the DIM generator is output to the DM pin associated with the data bit.

  FIG. 4 shows an example of a DIM generator. The last data register 401 stores the most recently sent byte (inverted or not inverted, as it was actually sent). New data register 402 stores the current data byte to be sent. The comparator 403 is supplied with the output signals of the registers 401 and 402. If the number of transitions is greater than 4, the comparator 403 outputs a high level signal to be output to the DM pin along with the data byte.

Burst operation Reading from the DRAM is often performed in a burst mode. FIG. 5 is a flow chart illustrating the operation of the present invention during a burst mode read operation. In block 500, burst reading starts. In block 510, the previous data register signal and the DM signal are set low. At block 520, the current data and the previous data are compared to determine the number of transitions that occur when sending the current data. At decision block 530, the number of transitions is checked to see if the number of transitions is greater than four. If yes, block 540 inverts data and DM is inverted. If the result at decision block 530 is NO, block 550 does not invert the data and maintains the previous DM value.

  After either block 540 or 550, a determination is made at decision block 560 as to whether the burst operation is complete. If yes, the process ends at block 570. If no, store the current data in the previous data register, get a new data byte, and the process returns to block 520.

Pin Advantages The present invention has the advantage of providing the ability to invert data for DRAM without requiring an excessively large number of pins, especially for read operations. Normally, by using a pin that is not used in a read operation, for example, a DM pin, the present invention enables byte reading using data inversion without using an additional pin for the read operation.

Termination As described above with reference to the burst read example, the bus was considered low when the burst read operation started. This is not necessary and the invention is not limited to such schemes or assumptions. Bus termination may be any of a number of methods described below.

  A. Low Pull—In one embodiment of the invention, the bus is gradually pulled low after reading. In this method, an NMOS transistor is coupled to the bus line, and the NMOS transistor gradually lowers the bus line to the ground level during a certain period. When using this scheme, it is assumed that all lines remain in a low state and the read operation begins, and the number of transitions for the first byte of data is determined based on this assumption.

  B. Pull to high level—In another embodiment, the bus can be pulled high by a PMOS termination scheme to pull all lines to a high state for a predetermined time after activation to the bus. The assumption in this scheme is that all lines are high at the start of the read operation, thus determining the number of first byte transitions for all high state.

  C. Termination at the midpoint level-In another embodiment, the bus line is pulled to an intermediate level state for a predetermined time. When using this scheme, there is no difference between pulling the bus line from an intermediate level state to a high level and to a low level, so the first byte in the read operation is sent in a non-inverted state. .

  D. Operation not terminated in an unlatched state-In this embodiment, the bus line is not terminated at all, and the first data byte is always sent unterminated. As a result, the efficiency for the first byte is lost. The reason is that for the first byte, the number of transitions can be 5 or more.

  E. Non-terminating operation in a latched state-this embodiment leaves the bus line in the same state as the most recent byte on the bus and latches to this value. For subsequent operations, the previous byte register contains the latched value, and the first byte is compared with this latched value to determine the number of transitions.

Processor Interface Logic Application Although the present invention has been described in the context of DRAM, the present invention has other uses. For example, this scheme can be used in conjunction with the microprocessor's interface logic so that a data inversion scheme can be used. FIG. 6 shows such an embodiment.

  DRAM 601 includes, for example, a first data bank 601A and a second data bank 601B, each bank having an output bus 602A and 602B with an associated DIM signal 603A and 603B (note that the DIM signal can be provided to the DM pin). . A DRAM output signal is supplied to the memory controller 604. The DRAM data output signals 602A and 602B are combined on a 16-bit bus 605 to the microprocessor 608. DIM signals 603A and 603B are combined as an input signal to XOR gate 606 to generate an output signal 607 to microprocessor 608.

Power Optimization FIG. 7A shows one embodiment of the read block of the present invention. In this embodiment, DC power optimization is performed when the I / O is open drain (ie, the bus is terminated to logic 1). Referring to FIG. 7A, read data 701 (8 bits) is coupled to flip-flop 702, comparator 703, and NOR gate 704. A load signal 705 is coupled to the enable input terminal of flip-flop 702. The output signal of the flip-flop 702 is coupled to the input terminal of the OR gate 706 together with the DC optimization signal 707. The DC optimization signal is logic “1”, and this signal is ORed into the data field before the comparator block 703. This OR operation ensures that the output power of the comparator block 703 is greater than half the value of logic “1” and saves DC power. Comparator 703 compares the current data field with the previous data field to see if the number of bits having different values is 5 or more. If so, the output (DIN) is a logic “1” and is provided to a NOR gate 704 for appropriate inversion of the data.

  When the bus is terminated to logic 0, the DC optimization signal can be a logic “0” so that more than half of the outputs are biased to “0”, which also saves power. .

  Reference is now made to FIG. 7B, which shows a block diagram of a write block. Write data 710 (for example, 32 bits) is given to the flip-flop 711, and a DIM signal 712 is given to the flip-flop 713. Both flip-flops are clocked by a clock signal 714 for writing. The output signals of these flip-flops are combined as an input signal to NOR gate 715 to generate data to be written to the memory array.

  Although the present invention has been described above in relation to data transmission, the present invention is equally applicable to digital signals including address signals or command signals.

  The data inversion method and apparatus in the memory device has been described above.

100 Data Source 102 Data Receiver 401 Final Data Register 402 New Data Register 403 Comparator 604 Memory Controller 608 Microprocessor

Claims (21)

Examining a current word to be written having N bits, each of which has a low or high level value;
Comparing the current word with a previous word having N bits and determining the number of transitions from the low level value in the previous word to the high level value in the current word;
Inverting the current word when the number of transitions is greater than or equal to N / 2;
Writing information to the synchronous memory device, the method comprising: writing the current word to the synchronous memory device.   The method of claim 1, further comprising sending a data inversion mask (DIM) bit with the current word to indicate that the current word has been inverted.   The method of claim 1, wherein the synchronous memory device comprises a DRAM.   The method of claim 1, wherein the word represents data.   The method of claim 1, wherein the word displays graphical data.   The method of claim 1, wherein the information displays one or more commands.   The method of claim 1, wherein the information displays address information. Examining a current word in a synchronous memory device to be read having N bits, each of which has a low or high level value;
Compare the current word with the previous word having N bits and determine the number of transitions from the bit having the low level value in the previous word to the bit having the high level value in the current word. A process of determining;
Inverting the current word when the number of transitions is greater than or equal to N / 2;
Reading the current word from the synchronous memory device; and reading information from the synchronous memory device.   9. The method of claim 8, further comprising sending a data inversion mask (DIM) bit with the current word to indicate that the current word has been inverted.   The method of claim 9, wherein the DIM bit is sent on an existing pin on the memory device.   The method of claim 10, wherein the existing pin is a data mask (DM) pin.   9. The method of claim 8, wherein all of the previous words are considered to have a low level value when the previous word is unknown.   9. The method of claim 8, wherein all of the previous words are considered to have a high level value when the previous word is unknown.   9. The method of claim 8, wherein the current word is not inverted when the previous word is unknown.   9. The method of claim 8, wherein the current word is latched in a later read operation and used as the previous word.   The method of claim 8, wherein the information includes data.   The method of claim 8, wherein the information includes graphical data.   The method of claim 8, wherein the information includes one or more commands.   The method of claim 8, wherein the information includes address information.   The method of claim 8, wherein the synchronous memory device comprises a DRAM.   9. The method of claim 8, wherein the system comprises biasing means for biasing the current word depending on whether to invert the current word and biasing the previous word to have one or more logical values. .

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