JP2010109782A - Communications device, communicating mobile terminal, and reader/writer for non-contact ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable modulated data to be accurately demodulated in the entire area of a packet even though a phenomenon that a result of load modulation does not appear on a phase or amplitude of a load modulation signal exists. <P>SOLUTION: An amplitude detection circuit (30) for detecting amplitude variations in the load modulation signal, and a phase detection circuit (31) for detecting phase variations in the load modulation signal are provided, and normality of a decode signal relating to each detection signal is sequentially determined based on the normal duty of an information bit. Then one decode signal is selected while normality relating to the previously designated one decode signal is selected. Selection control for switching the selection of the decode signal from the one to the other decode signal is performed when non-normality is detected, and error check and accumulation in a data buffer are performed relating to the decode signal acquired through selection control. Thus, the normality of the detection signal is sequentially determined from the normality of duty of the information bit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a communication device that receives a load modulation signal, and relates to a technique that is effective when applied to, for example, a reader / writer device that performs data communication with a non-contact IC card.

  A system using a non-contact IC card includes a non-contact IC card and a reader / writer that reads and writes data from and to the non-contact IC card. Inside this reader / writer, for example, an AC signal of 13.56 [MHz], for example, is generated by a carrier signal source, and this is boosted through a resonance circuit composed of a resistor, a capacitor, and a coil. Thereby, the alternating magnetic field according to the alternating current signal which flows into the coil of this resonance circuit is radiated from the coil to the space. On the other hand, inside the non-contact IC card, the voltage induced in the coil in accordance with the alternating magnetic field is rectified by an internal rectifier circuit, and this is used as driving power for the non-contact IC card, so that the batteryless Works with. Here, data communication from the non-contact IC card to the reader / writer is performed by a load modulation method. In this case, the internal circuit of the reader / writer and the internal circuit of the non-contact IC card are electrically connected by a coupling coefficient determined based on the physical shape and positional relationship of the coils provided in each. Can be considered.

  The load modulation method will be described based on such a premise. The contactless IC card is a resistance of an internal circuit resistor of the contactless IC card by turning on or off according to transmission data transmitted to the reader / writer. The value is switched as appropriate, thereby changing the current flowing in the internal circuit of the reader / writer that is electrically connected. The reader / writer detects a change in amplitude due to a change in current flowing in the internal circuit of the reader / writer, and demodulates received data based on the detection result.

  By the way, in recent years, in such a non-contact IC card system, in order to cope with a situation where a plurality of non-contact IC cards are used in a stacked manner, an anti-collision non-contact IC card has been used. . In this non-contact IC card compatible with anti-collision, the resonance frequency on the non-contact IC card side is different from the carrier frequency (13.56 [MHz]) used for data communication with the reader / writer (for example, 19 [MHz]). Is set to If the distance between the reader / writer and the non-contact IC card is gradually changed by separating the anti-collision non-contact IC card from the reader / writer, it is too far from the reader / writer and the driving power of the non-contact IC card is insufficient. Before reaching the point, there may be a failure point (also referred to as a null point) in which the reader / writer cannot obtain transmission data from the non-contact IC card. In this case, the reader / writer and the non-contact IC There was a problem that data communication between cards was interrupted.

  In order to deal with such a problem, in Patent Document 1, the reader / writer detects the phase change as well as the amplitude change, and the load modulation result does not appear in the amplitude of the load modulation signal but appears in the phase. Also, the data can be demodulated.

JP 2005-318385 A

  It has been clarified by the present inventor that further examination is required as to how to use the detection result of the amplitude change and the detection result of the phase change. For example, when each packet has a header, sync code, data part and CRC code, when the sync code of each packet is recognized by amplitude change, if there is a recognition error, switch to recognition by phase change and recognize the whole packet On the contrary, when the sync code is recognized by the phase change, if there is a recognition error, it is conceivable to switch to the recognition by the amplitude change and recognize the whole packet. However, if data communication is interrupted during reception of the data portion following the sync code, the data cannot be reliably demodulated. It is also conceivable that the recognition results based on both the phase and the amplitude are stored in the data buffer, and the data stored in either one of the data buffers is used according to the CRC check results for both. Each recognition result needs to be stored in a data buffer, which increases the circuit scale and power consumption. The situation is the same for the case where the result of the load modulation appears in the amplitude instead of appearing in the phase of the load modulation signal.

  An object of the present invention is to make it possible to accurately demodulate modulation data in the entire packet even when there is a phenomenon that the result of load modulation does not appear in the phase or amplitude of the load modulation signal. It is to provide.

  Another object of the present invention is to accurately demodulate modulated data over the entire area of the packet with a small circuit scale.

  Another object of the present invention is to realize accurate demodulation of modulation data over the entire area of the packet with low power consumption.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, an amplitude detection circuit for detecting a change in the amplitude of the load modulation signal and a phase detection circuit for detecting a phase change in the load modulation signal are provided, and the normality of the decoded signal with respect to each detection signal is set to the normal duty of the information bit. When the normality to one of the predetermined decode signals is detected, the one decode signal is selected. When the non-normality is detected, the decode signal is selected from the one. Selection control for switching to the other decode signal is performed, and an error check and accumulation in the data buffer are performed for the decode signal obtained through this selection control.

  According to this, since the normality of the detection signal is sequentially determined from the normality of the duty of the information bit, even if a phenomenon in which the load modulation result does not appear in one of the phase or amplitude of the load modulation signal occurs randomly, Modulation data can be accurately demodulated over the entire area. For the decoded signal obtained through this selection control, error checking and accumulation in the data buffer are performed at a later stage than the selection control of the decoding signal. It is not necessary to provide a CRC circuit and a data buffer separately, and it is not necessary to operate them in parallel.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, even if there is a phenomenon in which the result of load modulation does not appear in the phase or amplitude of the load modulation signal, it is possible to accurately demodulate the modulation data in the entire packet.

  In addition, it is possible to accurately demodulate the modulation data over the entire area of the packet with a small circuit scale.

  Furthermore, accurate demodulation of the modulation data over the entire area of the packet can be realized with low power consumption.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A communication apparatus according to the present invention detects an amplitude change of a load modulation signal received by an antenna (10) and outputs an amplitude detection signal (ADTCS), and the antenna receives the antenna. A phase detection circuit (31) that detects a phase change of the load modulation signal and outputs a phase detection signal (PDTCS), and generates a first decode signal by decoding the amplitude detection signal output from the amplitude detection circuit A first decoder (50); a second decoder (51) for decoding the phase detection signal output from the phase detection circuit to generate a second decode signal; and the normality of the amplitude detection signal and the phase detection signal. While the normality of the detection signal corresponding to one of the first decode signal or the second decode signal designated in advance is detected, the one decode signal is detected. Select, and a non when normality is detected selection control circuit for switching the selection of decoding signals from the one of the decoded signals to the other decode signals (52) of the detection signal. The selection control circuit sequentially determines the normality of the signal based on the normal duty of the information bit in each detection signal.

  According to this, since the normality of the detection signal is sequentially determined from the normality of the duty of the information bit, even if a phenomenon in which the load modulation result does not appear in one of the phase or amplitude of the load modulation signal occurs randomly, Modulation data can be accurately demodulated over the entire area. For the decoded signal obtained through this selection control, error checking and accumulation in the data buffer are performed at a later stage than the selection control of the decoding signal. It is not necessary to provide an error check circuit and a data buffer separately, and it is not necessary to operate them in parallel.

  [2] In the communication device according to item 1, the selection control circuit includes a first determination circuit (60) for determining normality of the amplitude detection signal and a second determination circuit (61) for determining normality of the phase detection signal. ), A first delay circuit (62) for delaying propagation of the first decode signal for a period corresponding to the determination operation by the first determination circuit, and a second decode signal for a period corresponding to the determination operation by the second determination circuit. The second delay circuit (63) for delaying propagation and the output of either the first delay circuit or the second delay circuit are selected, and the non-normality by the determination circuit corresponding to the delay circuit on the selection side is selected. And a selection circuit (64) for selecting the output of the non-selection-side delay circuit each time a determination result is obtained.

  [3] In the communication device according to item 2, each of the first determination circuit and the second determination circuit has a transmission line code when the duty in the time unit corresponding to the information bit transmission line encoding method is a normal duty. A signal is determined to be non-regular by a duty that is too small and too large that can be considered from the system. That is, duty determination is performed for every 1 tu (Time Unit) in the transmission path coding method.

  [4] In the communication device according to item 3, the transmission line encoding method is a Manchester encoding method. The ideal duty of the decoded signal waveform at 1 tu is 50% regardless of the logical value of the information bit.

  [5] In the communication device according to item 4, the duty that is too small and the duty that is too large are a high level period that is too short and a high level period that is too long.

  [6] In the communication device according to [4], the duty that is too small and the duty that is too large are a low level period that is too short and a low level period that is too long.

[7] In the communication device according to [5], each of the first determination circuit and the second determination circuit detects a clock signal whose period is 2 ⁿ times (n is an integer of 2 or more) corresponding to a time unit. A counter (81) for counting every high level period of the signal, a latch circuit (82) for latching the count value of the counter for each time unit, and comparing the count value latched in the latch circuit with threshold data And a comparison circuit (83) for determining the normality.

[8] In the communication device according to [6], each of the first determination circuit and the second determination circuit detects a clock signal whose period is 2 ⁿ times (n is an integer of 2 or more) corresponding to a time unit. A counter that counts every low level period of the signal, a latch circuit that latches the count value of the counter for each time unit, and compares the count value latched in the latch circuit with threshold data to determine the normality A comparison circuit.

  [9] The communication device according to [2], further including an error check for performing a packet unit error check using a reception data buffer for storing a decode signal output from the selection circuit and a decode signal output from the selection circuit A circuit, and a data processing circuit for processing data in the reception data buffer based on a check result by the error check circuit.

  [10] The communication device described in [9] is formed on one semiconductor chip or formed by mounting a plurality of semiconductor chips on one module substrate.

  [11] A communication portable terminal equipped with the communication device according to item 10.

  [12] A non-contact IC card reader / writer equipped with the communication device according to item 10.

  [13] In the communication device according to item 2, each of the first determination circuit and the second determination circuit includes a high period counter (92) for counting a high level period of a corresponding detection signal, and a corresponding detection signal. Corresponds to the counter for the low period (91) that counts the low-level period and the count value of the counter for the high period exceeds the threshold value or the count value of the counter for the low period exceeds the threshold value And a detection circuit (93, 94, 97) that outputs as a result of determination of the non-normality of the detection signal to be detected, and the detection signal is constant within a range of continuous time units according to the transmission code system of information bits. The counted value exceeds the period. This is different from the duty determination for each tu in Item 3 and is used to determine the irregularity of the detection signal based on the signal pulse that is too small and the signal pulse that is too large across the continuous plural tu, which is derived from the duty of the transmission line coding method. is there. Signal pulses that are too small and signals that are too large can be obtained by counting the pulse periods of the high and low level pulses of the detection signal.

  [14] In the communication device according to item 13, the transmission line encoding method is a Manchester encoding method, a CMI encoding method, or an RZ method.

  [15] A communication device according to the present invention having a different viewpoint from the duty determination described above includes an amplitude detection circuit (30) that detects an amplitude change of a load modulation signal received by an antenna (10) and outputs an amplitude detection signal; A phase detection circuit (31) that detects a phase change of the load modulation signal received by the antenna and outputs a phase detection signal, and generates a first decode signal by decoding the amplitude detection signal output from the amplitude detection circuit A first decoder (50), a second decoder (51) for decoding the phase detection signal output from the phase detection circuit to generate a second decode signal, and a packet sync for the first decode signal A first sync code check circuit (100A) for checking a code and a second sync code for checking a sync code of a packet with respect to the second decoded signal; A check circuit (100P), a first error check circuit (72A) for performing an error check on the first decoded signal using a packet error check code, and a packet error check code for the second decoded signal A second error check circuit (72P) that performs error check using the first reception data buffer (71A) that stores the first decode signal in units of packets, and a second error check circuit that stores the second decode signal in units of packets. 2 Received data buffer (71P) and the received data buffer data on the decoded signal side where no error is detected in the check result of the first error check circuit and the second error check circuit and no error is detected in the sync code check And a data processing circuit (13).

  According to this, even if there is a phenomenon in which the result of load modulation does not appear in the phase or amplitude of the load modulation signal, it is possible to accurately demodulate the modulation data in the entire packet.

  [16] In the communication device according to item 15, when an error is detected in the check result of the first sync code check circuit or the check result of the second sync code check circuit, A control circuit (101) for stopping the operation of the error check circuit and the data buffer is provided.

  According to this, the error check circuit and the data buffer are separately provided in the phase detection signal processing system and the amplitude detection signal processing system, but both do not always operate, so that the modulation data is accurately demodulated in the entire area of the packet. Can be achieved with low power consumption.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 2 illustrates a contactless IC card communication system to which the communication device according to the present invention is applied. Reference numeral 1 denotes a contactless IC card (CRD), and reference numeral 2 denotes a reader / writer of the contactless IC card 1. The reader / writer 2 has a non-contact communication semiconductor device (CFCLSI) 3 and a server interface (SRVIF) 4, and the server interface 4 is connected to a server (SRV) 5 through a network together with other reader / writers (not shown). The reader / writer 2 can read / write the non-contact IC card 1 by wireless communication, and is not particularly limited, but includes a loop antenna 10, a non-contact communication analog unit (CFCALG) 11, a non-contact communication logic unit (CFCLGC). 12, a central processing unit (CPU) 13, a memory (MRY) 14, an external interface (EXIF) 15, and a bus (BUS) 16. This wireless communication is so-called packet communication, and is performed by dividing data into a plurality of packets. One packet includes a preamble (PREAMBLE), a sync (SYNC) code, and subsequent data. The preamble is a kind of data provided for measuring transmission / reception timing in packet communication. The preamble is all [00h] in hexadecimal code. The sync code is a 2-byte code following the preamble and has a specific value such as “h′B24D”. The sync code (SYNC) is used as a timing reference to enable data detection after the sync code (SYNC). The data following the sync code includes data for controlling communication between the reader / writer 2 and the IC card 1, user data, and the like, and finally includes an error check code such as CRC (Cyclic Redundancy Check).

  The non-contact communication analog unit 11 includes a transmission analog unit 20 that transmits an RF signal through the loop antenna 10 and a reception analog unit 21 that receives an RF signal through the loop antenna 10. The reception analog unit 21 receives the load modulation signal transmitted from the IC card, and generates an amplitude detection signal ADTCS that detects an amplitude change with respect to the reception signal and a phase detection signal PDTCS that detects a phase change. The transmission analog unit 20 outputs from the loop antenna 10 an RF signal modulated by amplitude shift keying (ASK) so that the digital signal is represented by the difference in amplitude of the sine wave.

  The non-contact communication logic unit 12 includes a transmission logic unit (TXLGC) 22, a reception logic unit (RXLGC) 23, and a control logic unit (CONTLGC) 24. A transmission logic unit (TXLGC) 22 generates a modulation control signal MDLCS for performing ASK modulation in the transmission analog unit 20 based on transmission data received from the CPU 13. The reception logic unit 23 receives the amplitude detection signal ADTCS and the phase detection signal PDTCS and performs digital processing for demodulating the reception data. The control unit 24 controls the operations of the transmission logic unit 22 and the reception logic unit 23 and controls the CPU 13 to hold the flag indicating the result of the operation in an accessible manner.

  The CPU 13 sends a transmission command to the control unit 24 in accordance with a program held in the memory 14 and performs transmission control to send transmission data to the transmission logic unit 22. The received data and the like are taken in from 23 and necessary data processing is performed.

  The non-contact communication semiconductor device 3 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The server interface 4 is connected to the external interface of the non-contact communication semiconductor device 3.

  The reader / writer 2 emits a carrier signal (carrier wave) having a predetermined frequency from the loop antenna 10. In the non-contact IC card 1, when its own loop antenna 9 is within a range that causes electromagnetic induction with the loop antenna 10 of the reader / writer 2, a carrier signal is induced in the loop antenna 9. This induced voltage is used as a power source for operation of the non-contact IC card 1. Further, the carrier signal is load-modulated by data to be transmitted in the non-contact IC card 1 and received by the reader / writer 2 to enable data communication. At this time, depending on the distance between the reader / writer 2 and the non-contact IC card 1, there may be no amplitude difference component between the modulated portion by load modulation and the non-modulated portion from the received signal (RF signal) received by the reader / writer 2. is there. For example, as illustrated in FIG. 3, at the null point (NULL-POINT), the amplitude difference between the modulation portion and the non-modulation portion (no modulation) disappears, and a phase difference appears. In order to cope with this phenomenon, the transmission analog circuit unit 21 performs both amplitude detection and phase detection on the load modulation signal, and the reception logic unit 23 uses both the amplitude detection signal ADTCS and the phase detection signal PDTCS, The received data can be demodulated without interruption. Hereinafter, the configuration for that purpose will be described in detail.

  FIG. 1 shows a specific example of the reception analog unit 21 and the reception logic unit 23. The reception analog unit 21 detects an amplitude change of the load modulation signal received by the loop antenna 10 and outputs an amplitude detection signal ADTCS, and the phase of the load modulation signal received by the loop antenna 10. And a phase detection circuit (PDTC) 40 that detects a change and outputs a phase detection signal PDTCS. The amplitude detection circuit 30 is not particularly limited. For example, as shown in FIG. 4, a peak hold circuit (PH) 31 that holds the peak of the input load modulation signal LMDLS, and an output signal of the peak hold circuit 31 are amplified. Nonlinear amplifier (NLA) 32, envelope detection circuit (EDET) 33 that enables amplitude shift keying (ASK) envelope detection, and an A / D conversion circuit that shapes the output of envelope detection circuit 33 (ADC) 34. The phase detection circuit 40 is not particularly limited, but, as shown in FIG. 4, a waveform shaping circuit (MOD) 41 that performs waveform shaping of the input signal LMDLS, an output signal of the waveform shaping circuit 40, and a reference clock SCLK. A multiplication circuit (MIX) 42 for detecting a phase difference by comparison, and an A / D conversion circuit (ADC) 43 for shaping the output of the multiplication circuit 42 are included.

  The reception logic unit 23 decodes the amplitude detection signal ADTCS output from the amplitude detection circuit 30 to generate an amplitude side decode signal (first decode signal) ADECS, and the phase A phase-side decoder (second decoder) 51 that generates a phase-side decoded signal (second decoded signal) PDECS by shaping the phase detection signal PDTCS output from the detection circuit, and a selection control circuit (SLCONT) 52. .

  The selection control circuit 52 sequentially determines the normality of each of the amplitude detection signal ADTCS and the phase detection signal PDTCS, and the normality of the detection signal corresponding to one of the decode signals ADECS or the decode signal PDECS designated in advance. When one of the decode signals is detected, the one decode signal is selected, and when the non-normality of the detected signal is detected, the selection of the decode signal is switched from the one decode signal to the other decode signal and outputted. The normality with respect to the detection signal is sequentially determined based on the normal duty of the information bits in the detection signal.

  More specifically, the selection control circuit 52 includes an amplitude-side duty determination circuit (ADTM) 60, a phase-side duty determination circuit (PDTM) 61, an amplitude-side delay circuit (ADLY) 62, a phase-side delay circuit ( PDLY) 63 and a selection circuit (SLCT) 64. The amplitude-side duty determination circuit (ADTM) 60 determines the normality of the duty of the amplitude detection signal ADTCS, and when the non-normal is determined, sets the error signal ADERR to a high level. The phase-side duty determination circuit (PDTM) 61 determines the normality of the duty of the phase detection signal PDTCS, and when the non-normal is determined, sets the error signal PDERR to a high level. The delay circuit (ADLY) 62 delays propagation of the amplitude side decode signal ADECS for a period corresponding to the determination operation by the amplitude side duty determination circuit 60. The delay circuit (PDLY) 63 delays propagation of the phase side decode signal PDECS for a period corresponding to the determination operation by the phase side duty determination circuit 61. The selection circuit (SLCT) 64 selects either the output ADLDAT of the delay circuit 62 or the output PDLDAT of the delay circuit 63, and the determination result of the non-normality by the determination circuit corresponding to the selection-side delay circuit is obtained. Each time it is obtained, the output of the non-selected delay circuit is selected. For example, when the control unit 24 initially instructs the selector 64 to select the delayed output ADDDAT, the state is maintained until the non-normality is determined in the duty on the amplitude side by the error signal ADERR, and the non-normal is determined. Then, the selection is switched to the selection of the delay output PDLDAT, and thereafter, the selection state of the selection circuit is toggled whenever the duty non-normality with respect to the detection signal on the selection side is determined.

  The output of the selection circuit 64 is converted into parallel data in units of bytes by a serial / parallel conversion circuit (SPCNV) 70, and the converted data is stored in a data buffer (RXDBUF) 71, and the converted data is included in it. An error check is performed by a CRC check circuit (CRCCHK) 72 using the CRC code. The CRC check result CRCERR can be referred to by the CPU 13, and the data stored in the data buffer 71 is used for data processing of the CPU 13.

  FIG. 5 illustrates the configuration of the duty determination circuit 60 on the amplitude side. Here, the Manchester system will be described as an example of the transmission path modulation system. One time unit (Tu) is not particularly limited, but is, for example, 64 periods of the carrier clock CARCK. The duty determination circuit 60 includes an AND gate 80, a counter (COUNT) 81, a latch circuit (LAT) 82, and a comparison circuit (COMP) 83. The AND gate 80 receives the amplitude detection signal ADTCS and the carrier clock CARCK, and outputs the carrier clock CARCK during the high level period of the amplitude detection signal ADTCS. The counter 81 has a reset terminal reset, a clock terminal ck, and a count value output terminal Q. PLS_1tu is a reset signal whose pulse is changed every 1 Tu. PLS_1tu is generated based on the carrier clock CARCK. Thus, the counter 81 outputs the high level period of the amplitude detection signal ADTCS as the count value of the carrier clock CARCK (the high level period value of the amplitude detection signal ADTCS) VCOUNT. The count value of the counter 81 is latched in the latch circuit 82 every 1 Tu, and the comparison circuit 83 compares the high level period value of the latched amplitude detection signal ADTCS with the threshold value Dth. In the Manchester encoding method, as illustrated in FIG. 6, the normal duty of the signal at 1 Tu is 50%, the logical value 1 is the low level in the first half, the high level is the second half, and the reverse is the logical value 0. The threshold value Dth is set to the minimum value a and the maximum value b in consideration of errors such as waveform distortion caused by the detection operation. The comparison circuit 8 determines whether or not a <VCOUNT <b is satisfied, and if satisfied, sets the signal ADERR to a high level, and if not satisfied, sets the signal ADERR to a low level.

  The phase-side duty determination circuit 61 may be configured in the same manner as described above by supplying the phase detection signal PDTCS to the AND gate 80, although not particularly illustrated.

  FIG. 7 illustrates a timing chart of the duty non-normality determination operation for the detection signal ADTCS. Here, it is assumed that the detection signal ADTCS should be changed to 1, 0, 1, 0, but is fixed at a high level during the period from time t0 to t4. The count value VCOUNT is n at time t1, y at time t2, y at time t3, and n at time t5. Since VCOUNT = y at time t2 is outside the allowable range by the thresholds a and b, the error signal ADERR is set to low level at time t2. At time t5, VCOUNT = n, which is within the allowable range by the threshold values a and b, so that the error signal ADERR is inverted to high level at time t5.

  FIG. 8 illustrates the operation timing of the selection control circuit 52. TRN is a modulation waveform on the transmission side, and a portion where the waveform is distorted due to the influence of a null point or the like in the detection signals ADTCTS and PDTCS (portion where the duty is non-normal) is shown by a one-dot chain line. The delay circuits 62 and 63 are constituted by, for example, a shift register, and output decode signals ADLDAT and PDLDAT with a delay of 1 Tu. Therefore, the portions of the decode signals ALDDAT and PDLDAT corresponding to the duty non-normal portions of the detection signals ADTCTS and PDTCS are clearly indicated by hatching portions that are delayed by 1 Tu.

  First, the selection circuit 64 selects and outputs the phase side data PDLDAT (SLDAT). At time t1, it is detected that the duty of the phase side detection signal PDTCS is irregular, and the error signal PDERR is changed to a low level. In response to this, the selection circuit 64 switches the output data SLDAT from the phase side data PDLDAT to the amplitude side data ADLDAT. Next, at time t5, it is detected that the duty of the amplitude side detection signal ADTCS is irregular, and the error signal ADERR is changed to a low level. In response to this, the selection circuit 64 switches the output data SLDAT from the amplitude side data ADDDAT to the phase side data PDLDAT.

  As a result, the normality of the detection signals PDTCS and ADTCS is sequentially determined from the normality of the duty of the information bit of 1 Tu, so that a phenomenon in which the load modulation result does not appear in one of the phase or amplitude of the load modulation signal occurs randomly. However, the modulation data can be accurately demodulated over the entire area of the packet by the data SLDAT. For the decoded signal obtained through this selection control, error checking by the error check circuit 72 and accumulation in the data buffer 71 are performed after the selection control of the decoding signal, so that both phase change and amplitude change are decoded. It is not necessary to provide an error check circuit and a data buffer separately for each of the signals PDECS and ADECS, and it is not necessary to operate them in parallel. It is possible to accurately demodulate the modulation data over the entire area of the packet with a small circuit scale and with low power consumption.

  In the description of the first embodiment, each of the duty determination circuits 60 and 61 considers the transmission line code method when the duty in the time unit (Tu) corresponding to the information bit transmission line code method is a normal duty. The signal is determined to be non-regular due to a too small duty and a too large duty, for example, the transmission line coding method is a Manchester coding method, and the too small duty and too large duty are too short high level period and long Detected as too high level period. The present invention is not limited to this, and the duty that is too small and the duty that is too large may be detected as a low level period that is too short and a low level period that is too long. For example, the inverted signal of the detection signal ADTCS may be supplied to the AND gate 80.

<< Embodiment 2 >>
FIG. 9 shows another example of the duty detection circuit. Here, the phase-side duty detection circuit 90 is shown. The duty detection circuit 90 includes a high period side counter (COUNT_H) 92, a low period side counter (COUNT_L) 91, a high period side comparator (COMP_H) 93, a low period side comparator (COMP_L) 94, an AND gate 95, 96 and 97, and inverters 98 and 99. The high period side counter 92 counts the high level period of the phase side detection signal PDECS. The low period side counter 91 counts the low level period of the phase side detection signal PDECS. ck is a clock input terminal that receives the outputs of the corresponding AND gates 95 and 96, reset is a reset terminal, and Q is an output terminal of count values VCOUNT_L and VCOUNT_H. The comparator 93 on the high period side detects that the count value VCOUNT_H of the high counter 92 exceeds the threshold value Dth, and sets the signal PDERR_H to the low level. The comparator 94 on the low period side detects a state where the count value VCOUNT_L of the counter 91 exceeds the threshold value Dth and sets the signal PDERR_L to the low level. The signal PDERR is a logical product signal of the signals PDERR_H and PDERR_L, and indicates a low level state when the count value VCOUNT_L of the counter 91 exceeds the threshold value Dth or the count value VCOUNT_H of the counter 92 exceeds the threshold value Dth. The low level means non-normality of the corresponding detection signal PDECS.

  The threshold value Dth is a count value exceeding a period in which the detection signal is constant within a range of continuous time units corresponding to the transmission coding method of information bits. For example, in the case of the Manchester system, a continuous high level period or a low level period in a plurality of time units is normally a period of 1 Tu, and even if an error is taken into consideration, it does not become 1.5 Tu. Considering this, Dth = z. The duty detection circuit 90 determines the non-normality of the detection signal based on a too short high level period (too long low level period) and a too long high level period, which are derived from the duty of the Manchester encoding method and span a plurality of consecutive Tu. The high level period that is too short (low level period that is too long) is obtained by counting the pulse period of the low level pulse, and the high level period that is too long is obtained by counting the high level pulse period of the detection signal. be able to.

  Although not specifically shown, the amplitude-side duty detection circuit 61 is also configured in the same manner as in FIG.

  FIG. 10 shows the operation timing of the duty detection circuit 90 when non-normality occurs in which the high level period of the phase detection signal PDECS is too long. When the count value VCOUNT_H of the counter 92 that counts the high level period of the phase detection signal PDECS exceeds the threshold value Dth = z, the detection signal PDERR_H is inverted to the low level. Thus, the toggle operation of the output SLDAT by the selection circuit 64 due to the change of the signal PDERR is the same as in the above example.

  FIG. 11 shows the operation timing of the duty detection circuit 90 when non-normality occurs when the low level period of the phase detection signal PDECS is too long. When the count value VCOUNT_L of the counter 91 that counts the low level period of the phase detection signal PDECS exceeds the threshold value Dth = z, the detection signal PDERR_L is inverted to the low level. The output SLDAT of the selection circuit 64 according to the change of the logical product signal PDERR of the signals PDERR_H and PDERR_L in FIGS. 9 and 10 is switched to toggle like the above example.

  In the second embodiment, the case of the Manchester code system has been described as the transmission path code system, but the present invention is not limited to this, and the CMI code system or the RZ system may be used.

<< Embodiment 3 >>
FIG. 12 shows another example of the reception analog unit 21 and the reception logic unit 23. The first difference from FIG. 1 is that serial / parallel conversion circuits (ASPCONV, PSPCONV) 70A, 70P, data buffers (ARXDBUF, PRXDBUF) 71A, 71P, CRC check circuit (on the amplitude detection side and the phase detection side, respectively) ACRCCHK, PCRCCHK) 72A, 72P and sync code check circuits (ASYNCCHK, PSYNCCHK) 100A, 100P are provided separately, and the check result by the CRC check circuits 72A, 72P and the check result by the sync code check circuits 100A, 100P are controlled by the control circuit 101. Is stored in the flag register (FLGREG) 102 and can be referred to by the CPU 13. The sync code check circuits (ASYNCCHK, PSYNCCHK) 100A, 100P determine whether or not the sync code located at the head of each packet is a predetermined value, and the determination result is set in the flag register 102. ASCERR and PSCERR are determination result signals by the sync code check circuits (ASYNCCHK and PSYNCCHK) 100A and 100P. ACCERR and PCCERR are determination result signals by CRC check circuits (ACRCCHK and PCRCCHK) 72A and 72P.

  The CPU 13 uses data in the reception data buffer on the decode signal side in which there is no error in the CRC check and no error is detected in the sync code check. Thereby, even if there is a phenomenon in which the result of load modulation does not appear in the phase or amplitude of the load modulation signal, the modulation data can be accurately demodulated over the entire area of the packet.

  A second difference from FIG. 1 is that when an error is detected in the check result of the sync code check circuit 100A or the sync code check circuit 100P, the control circuit 101 detects an error in the packet. The operation of the certain amplitude detection side CRC check circuit 72A and the data buffer 71A or the phase detection side CRC check circuit 72P and the data buffer 71P is stopped. According to this, the error check circuit and the data buffer are separately provided in the phase detection signal processing system and the amplitude detection signal processing system, but both do not always operate, so that the modulation data is accurately demodulated in the entire area of the packet. Can be achieved with low power consumption.

<< Embodiment 4 >>
FIG. 13 illustrates a case where the present invention is applied to a mobile phone (MBLPN) 110 having an NFC system. The present invention is not limited to the application to the reader light 2 of the IC card of FIG. The non-contact communication semiconductor device 2 is connected to a host controller (HSTCNT) 111 and a secure module (SCRMDL) 112. The host controller (HSTCNT) 111 is connected to an operation unit (OPRTN) 113, a display unit (DSP) 114, and a mobile communication unit (MBLCOM) 115 for a mobile phone. The secure module 112 is used for authentication processing and the like. The host controller 111 performs overall control. According to this, in the case where the mobile phone 110 receives a load modulation signal transmitted from another mobile phone of the same type, it is possible to realize reception incapability due to a null point or the like with a small circuit scale and reduced power consumption. it can.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the value of the threshold value Dth is not limited to the above description and can be changed as appropriate. The type of circuit block mounted on the non-contact communication semiconductor device is not limited to FIG. 2 and can be changed as appropriate.

FIG. 1 is a block diagram showing a specific example of the reception analog unit 21 and the reception logic unit 23 in the present invention. FIG. 2 is a block diagram illustrating a contactless IC card communication system to which the communication device according to the present invention is applied. FIG. 3 is an explanatory diagram illustrating the state of the null point where the amplitude difference between the modulation part and the non-modulation part disappears and the phase difference appears. FIG. 4 is a block diagram showing a specific example of an amplitude detection circuit and a phase detection circuit. FIG. 5 is a block diagram illustrating the configuration of the amplitude-side duty determination circuit. FIG. 6 is an explanatory diagram showing information bits and waveforms in 1 Tu in the Manchester encoding method. FIG. 7 is a timing chart of the duty non-normality determination operation for the detection signal ADTCS. FIG. 8 shows the operation timing of the selection control circuit 52. FIG. 9 is a block diagram showing another example of the duty detection circuit. FIG. 10 is an operation timing chart of the duty detection circuit 90 when non-normality is generated in which the high level period of the phase detection signal PDECS is too long. FIG. 11 is an operation timing chart of the duty detection circuit 90 when non-normality is generated in which the low level period of the phase detection signal PDECS is too long. FIG. 12 is a block diagram illustrating another example of the reception analog unit and the reception logic unit. FIG. 13 is a system block diagram when the present invention is applied to a mobile phone equipped with an NFC system.

Explanation of symbols

1 Non-contact IC card (CRD)
2 Reader / Writer for Contactless IC Card 1 3 Contactless Communication Semiconductor Device (CFCLSI)
4 Server interface (SRVIF)
5 Server (SRV)
10 Loop antenna 11 Non-contact communication analog part (CFCALG)
12 Non-contact communication logic part (CFCLGC)
13 Central processing unit (CPU)
14 Memory (MRY)
15 External interface (EXIF)
16 Bus (BUS)
20 Transmission analog part 21 Reception analog part 22 Transmission logic part (TXLGC)
23 Reception logic block (RXLGC)
24 Control Logic (CONTLGC)
ADTCS Amplitude detection signal 30 Amplitude detection circuit (ADTC)
PDTCS Phase detection signal 40 Phase detection circuit (PDTC)
31 Peak hold circuit (PH)
32 Nonlinear Amplifier (NLA)
33 Envelope detection circuit (EDET)
34 A / D conversion circuit (ADC)
41 Waveform shaping circuit (MOD)
42 Multiplication circuit (MIX)
43 A / D conversion circuit (ADC)
ADECS Amplitude side decode signal (first decode signal)
50 Amplitude side decoder (first decoder)
PDTCS Phase side decode signal (second decode signal)
51 Phase decoder (second decoder)
52 Selection control circuit (SLCONT)
60 Amplitude duty determination circuit (ADTM)
61 Phase-side duty determination circuit (PDTM)
62 Amplitude side delay circuit (ADLY)
63 Phase-side delay circuit (PDLY)
64 selection circuit (SLCT)
70 Syria-Parallel Conversion Circuit (SPCNV)
71 Data buffer (RXDBUF)
72 CRC check circuit (CRCCHK)
CARCK Carrier clock 80 AND gate 81 Counter (COUNT)
82 Latch circuit (LAT)
83 Comparison circuit (COMP)
90 Phase side duty detection circuit 92 High period side counter (COUNT_H)
91 Low period counter (COUNT_L)
93 High period comparator (COMP_H)
94 Low period side comparator (COMP_L)
95, 96, 97 AND gate 98, 99 Inverter 70A, 70P Serial / parallel conversion circuit (ASPCONV, PSPCONV)
71A, 71P Data buffer (ARXDBUF, PRXDBUF)
72A, 72P CRC check circuit (ACRCCHK, PCRCCHK)
100A, 100P Sync code check circuit (ASYNCCHK, PSYNCCHK)
101 Control circuit 102 Flag register (FLGREG)
110 Mobile phone (MBLPN)
111 Host controller (HSTCNT)
112 Secure Module (SCRMDL)

Claims (16)

An amplitude detection circuit that detects an amplitude change of the load modulation signal received by the antenna and outputs an amplitude detection signal; and
A phase detection circuit that detects a phase change of a load modulation signal received by an antenna and outputs a phase detection signal;
A first decoder for decoding the amplitude detection signal output from the amplitude detection circuit and generating a first decode signal;
A second decoder for decoding the phase detection signal output from the phase detection circuit to generate a second decoded signal;
While the normality of each of the amplitude detection signal and the phase detection signal is sequentially determined, and the normality of the detection signal corresponding to one of the first decode signal and the second decode signal designated in advance is detected A selection control circuit that selects the one decode signal and switches the selection of the decode signal from the one decode signal to the other decode signal when the non-normality of the detection signal is detected;
The said selection control circuit is a communication apparatus which determines the normality of a signal sequentially based on the normal duty of the information bit in each detection signal. The selection control circuit includes a first determination circuit that determines normality of the amplitude detection signal;
A second determination circuit for determining normality of the phase detection signal;
A first delay circuit for delaying propagation of the first decode signal for a period corresponding to a determination operation by the first determination circuit;
A second delay circuit for delaying propagation of the second decode signal by a period corresponding to a determination operation by the second determination circuit;
Each time an output of either the first delay circuit or the second delay circuit is selected and a non-normality determination result is obtained by the determination circuit corresponding to the selection-side delay circuit, the non-selection-side delay circuit The communication device according to claim 1, further comprising: a selection circuit that selects the output of.   Each of the first determination circuit and the second determination circuit has an excessively small duty and an excessively large duty that can be considered from the transmission line coding method when the duty in the time unit corresponding to the transmission line coding method of information bits is a normal duty. The communication device according to claim 2, wherein the signal is determined as non-regular by   The communication apparatus according to claim 3, wherein the transmission path encoding method is a Manchester encoding method.   5. The communication device according to claim 4, wherein the duty that is too small and the duty that is too large are a high level period that is too short and a high level period that is too long.   The communication apparatus according to claim 4, wherein the duty that is too small and the duty that is too large are a low level period that is too short and a low level period that is too long. Each of the first determination circuit and the second determination circuit includes a counter that counts a clock signal corresponding to a time unit having a cycle of 2 ⁿ times (n is an integer of 2 or more) for each high level period of the detection signal. ,
A latch circuit that latches the count value of the counter for each time unit;
The communication apparatus according to claim 5, further comprising a comparison circuit that compares the count value latched by the latch circuit with threshold data to determine the normality. Each of the first determination circuit and the second determination circuit includes a counter that counts a clock signal corresponding to a time unit that is 2 ⁿ times the period (n is an integer of 2 or more) for each low level period of the detection signal. ,
A latch circuit that latches the count value of the counter for each time unit;
The communication device according to claim 6, further comprising: a comparison circuit that compares the count value latched by the latch circuit with threshold data to determine the normality.   Based on a reception data buffer for accumulating a decode signal output from the selection circuit, an error check circuit for performing an error check on a packet basis using the decode signal output from the selection circuit, and a check result by the error check circuit The communication device according to claim 2, further comprising: a data processing circuit that processes data in the reception data buffer.   The communication device according to claim 9, wherein the communication device is formed on a single semiconductor chip, or formed by mounting a plurality of semiconductor chips on a single module substrate.   A communication portable terminal equipped with the communication device according to claim 10.   A reader / writer for a non-contact IC card equipped with the communication device according to claim 10. Each of the first determination circuit and the second determination circuit includes a high period counter for counting a high level period of a corresponding detection signal, a low period counter for counting a low level period of a corresponding detection signal, A detection circuit that outputs a state in which the count value of the counter for the high period exceeds a threshold value or a state in which the count value of the counter for the low period exceeds the threshold value as a determination result of the non-normality of the corresponding detection signal; Have
The communication apparatus according to claim 2, wherein the threshold value is a count value exceeding a period in which the detection signal is constant in a range of continuous time units according to a transmission code scheme of information bits.   The communication apparatus according to claim 13, wherein the transmission path code method is a Manchester code method, a CMI code method, or an RZ method. An amplitude detection circuit that detects an amplitude change of the load modulation signal received by the antenna and outputs an amplitude detection signal; and
A phase detection circuit that detects a phase change of a load modulation signal received by an antenna and outputs a phase detection signal;
A first decoder for decoding the amplitude detection signal output from the amplitude detection circuit and generating a first decode signal;
A second decoder for decoding the phase detection signal output from the phase detection circuit to generate a second decoded signal;
A first sync code check circuit for checking a sync code of a packet with respect to the first decoded signal;
A second sync code check circuit for checking a sync code of a packet with respect to the second decoded signal;
A first error check circuit that performs an error check on the first decoded signal using an error check code of a packet;
A second error check circuit that performs an error check on the second decode signal using an error check code of a packet;
A first received data buffer for storing the first decoded signal in units of packets;
A second received data buffer for storing the second decoded signal in units of packets;
A data processing circuit that uses data in the received data buffer on the decoding signal side in which no error is detected in the check results of the first error check circuit and the second error check circuit and no error is detected in the sync code check. apparatus.   When an error is detected in the check result of the first sync code check circuit or the check result of the second sync code check circuit, the operation of the error check circuit and data buffer on the side where the error is detected for the packet is stopped. The communication apparatus according to claim 15, further comprising a control circuit.

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