JP2010108385A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device which enables constant high-speed writing from a host and reduces a frequency of rewriting of a flash memory. <P>SOLUTION: The storage device has: a RAM whose storage area is divided into a plurality of blocks (n blocks); a flash memory which is divided into a plurality of sets (m sets); an internal bus consisting of a first bus, which enables writing of data to the RAM from the outside, and m second buses which each independently enable writing of data to the flash memory, which is divided into the m sets, from the RAM; and an internal controller part which simultaneously conducts a first operation and a second operation by time division, the first operation executing writing to the RAM by using the first bus, and the second operation writing the stored data in the RAM which cover one to m blocks, to the flash memory, in chronological data writing order, so as to ensure the storage area for the first operation, by using the second buses in accordance with the data volume of the stored data concerned. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a storage device, and relates to a technique that is configured using a batch erasing nonvolatile memory (hereinafter referred to as a flash memory) and is effective when used for a storage device that can be replaced with, for example, a hard disk drive memory.

As a replacement product of a hard disk drive (hereinafter referred to as HDD), there is, for example, Japanese Patent Application Laid-Open No. 2006-252535 as a storage device in which SSD (Solid State Drive) using a flash memory as a storage medium is commercialized.
JP 2006-252535 A

  In a storage device using a flash memory, the writing speed at the time of storing data is the upper limit of the writing speed to the flash memory. The writing speed to the flash memory is slower than the writing speed to the HDD, and apparently the same speed as that of the HDD can be achieved by making the writing to the flash memory multi-stage (pipeline operation or interleave operation). There is a configuration limit. In addition, such multi-stage is advantageous for high speed as described above, but also when rewriting a part of data, it is necessary to rewrite data to an unnecessary part corresponding to the data amount by the multi-stage. As a result, the flash memory is rewritten more frequently, leading to a reduction in life.

  By interposing a semiconductor random access memory (hereinafter simply referred to as RAM) capable of high-speed writing as a buffer memory as in the above-mentioned Patent Document 1, the speed is increased and the flash memory is rewritten as compared with the one using only the flash memory. The number of times can be reduced. However, while data in the RAM is transferred to the flash memory, new data cannot be received as a storage device, and the data input from the host must be temporarily interrupted, resulting in poor usability.

  One object of the present invention is to provide a storage device that enables constant high-speed writing from a host and reduction of the rewrite frequency of a flash memory. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. The storage device includes a RAM, a flash memory, a controller unit that performs memory access to the RAM and the flash memory, and an internal bus. The RAM is divided into n blocks each having a plurality of storage areas. The flash memory is divided into a plurality of m sets. The internal bus is capable of independently writing data to the first bus in which data can be written to the RAM from the outside, and to the flash memory divided into the m sets from the RAM. Second buses. In order to secure a storage area for the first operation for externally writing to the RAM using the first bus and the first operation for the RAM, the controller unit uses the oldest data at the time of writing among the stored data in the RAM. Thus, the second operation of writing data of 1 to m blocks to the flash memory using the second bus corresponding to the data amount of the stored data is simultaneously performed in a time division manner.

  By the simultaneous operation of the first operation and the second operation in a time-sharing manner, constant high-speed writing from the host is enabled, and data is independently written from the RAM to the flash memory divided into the m groups. With the m second buses enabled, the writing speed to the flash memory can be increased and the rewriting frequency can be reduced.

  FIG. 1 shows a schematic configuration diagram of an embodiment of a storage device according to the present invention. The storage device of this embodiment is directed to an SSD (Solid State Drive) using a flash memory as a storage medium as a replacement product for an HDD. The storage device includes a controller unit CONT, a high-speed memory RAM, a flash memory FLSH, and internal buses BUS and IBUS1 to IBUSm. The high-speed memory RAM is composed of, for example, a synchronous dynamic random access memory (hereinafter referred to as SDRAM). This high-speed memory RAM has a storage capacity divided into n blocks of blocks BLK1 to BLKn. These blocks BLK1 to BLKn are not particularly limited, but have a storage capacity of 128 KB (kilobytes).

  The flash memory FLSH includes flash memories FLSH1 to FLSHm divided into m groups. Between the high-speed memory RAM and the flash memories FLSH1 to FLSHm divided into m groups, data transfer is performed by m second buses IBUS1 to IBUSm constituting a part of the internal bus. These second buses IBUS1 to IBUSm can be used independently. For example, any one of IBUS1 to IBUSm can be used alone, or each of IBUS1 to IBUSm can be variably combined and used simultaneously. In addition, a first bus BUS is provided which constitutes another part of the internal bus that enables data to be written from the external host HOST to the RAM.

  The controller unit CONT can perform the first operation and the second operation simultaneously in a time division manner. The first operation is an operation of writing data from the external host HOST to the high-speed memory RAM using the first bus BUS. The second operation is the oldest data at the time of writing among the stored data stored in the high-speed memory RAM in order to secure a storage area for the first operation with respect to the high-speed memory RAM. In this operation, 1 to m blocks are written into the flash memory using the second bus corresponding to the amount of data. Corresponding to each of the buses BUS and IBUS1 to IBUSm, control lines C and C1 to Cm for transmitting control signals used for operations using the buses are provided.

  A high-speed memory RAM such as the SDRAM is sufficiently faster than the data writing speed in the HDD and the data writing speed in the flash memory. By utilizing this fact, a time required for data writing from the host is allocated, and writing to and reading from the high-speed memory RAM using the first bus is enabled. As a result, the controller unit uses the time allotted in a time-sharing manner to perform a constant read operation on condition that a constant write operation by the host HOST or stored data corresponding to the high-speed RAM is stored. Operation is ensured.

  In this embodiment, the storage capacity as the storage medium is determined by the storage capacity of the flash memory FLSH, and the storage device of this embodiment has a large storage capacity comparable to the HDD so as to be able to replace or be compatible with the HDD. Is set. The storage capacity of the high-speed memory RAM is made smaller than the storage capacity of the flash memory FLSH. Therefore, when the storage area of the high-speed memory RAM becomes full, no further writing can be performed. In order to maintain the first operation constantly, the controller unit saves the stored data stored in the high-speed memory RAM in the flash memory FLSH in the order of the oldest data at the time of writing. A second operation for securing a storage area for writing new data from the host HOST is performed.

  In the second operation, the remaining time used by the first operation is allocated to the memory accessible time for the high-speed memory RAM. Thus, the first operation and the second operation are performed on the high-speed memory RAM in a time-sharing manner, so that external memory access and data saving to the flash memory are simultaneously performed on the high-speed RAM. be able to. As a premise of the second operation, the flash memory FLSH needs to be in an erased state. Therefore, in the flash memory FLSH, an erase operation is performed when there is write data at the save destination. Therefore, it is convenient for the flash memory FLSH to determine the erase unit size corresponding to the block size of the high-speed memory RAM. Even if the erase unit size is 1 / integer of the block size, an integral multiple may be erased simultaneously.

  In the second operation, for example, when the number of blocks in the writable storage area of the high-speed memory RAM becomes the minimum value, the storage data of the block including the oldest storage data at the time of writing is stored in the flash memory regardless of the first operation. Retreat to FLSH. At this time, when a continuous series of data exists across a plurality of blocks, a plurality of blocks are simultaneously saved. In other words, since there are m second buses such as IBUS1 to IBUSm, the maximum m blocks are simultaneously transferred to the flash memory FLSH. When the continuous data to be saved is small and within one block, for example, one block is saved in the flash memory FLSH using one bus IBUS1. This configuration is useful for reducing the number of rewrites in the flash memory FLSH.

  For example, even if the number of blocks in the writable storage area of the high-speed memory RAM is equal to or greater than the minimum value, the second operation is performed when the amount of data requested for writing in the first operation is larger than the minimum value. Correspondingly, the second operation is performed. In this case, since it is necessary to secure a storage area for writing a large amount of data in a single time, when the continuous series of data exists across a plurality of blocks, a plurality of blocks are saved at the same time, and there is a remainder on the data bus. In some cases, the next oldest stored data is saved together. That is, the save data is selected so as to save the maximum m pieces of data.

  For example, when m = 4 and 1 block BLK is 256 sectors (128 KB), it is possible to transfer 1 to 4 blocks of an arbitrary amount of continuous logical address data at a time. For example, if the continuous logical address save data is for 256 sectors, one block is transferred, and if the continuous logical address save data is for 512 sectors, two blocks are transferred at the same time as the transfer for the one block. Forwarded to In the configuration in which the internal bus between the high-speed memory RAM and the flash memory FLSH is fixedly used, data is saved according to the transfer amount of the internal bus. Therefore, when the internal buses IBUS1 to IBUS4 are provided, data is saved in units of the four blocks, and even when data for the one block may be saved, data for four blocks is saved. As a result, the number of rewrites in the flash memory FLSH increases. However, in the configuration in which each bus can be used independently according to the saved data amount as in this embodiment, the number of rewrites in the flash memory FLSH is reduced. it can.

  The independent use of the second bus can simultaneously store discontinuous logical address data in the flash memory FLSH in the high-speed memory RAM. For example, a serial number is assigned to all sectors in the hard disk, and one block with LBA (Logical Blook Addressing) 0x0000, which is an address system for designating a sector by the serial number, and one block with LBA 0x0500 as the top address Thus, a total of four blocks, one block having LBA0x0A00 as the head address and one block having LBA0x0F00 as the head address, can be simultaneously saved in the flash memory FLSH. There are 7 combinations of such discontinuous logical address data by combining 1 block with 2 blocks and 2 blocks with 1 block, 1 block with 1 block, and 3 blocks with 1 block. Exists. That is, (1, 1, 1, 1), (1, 1, 2), (1, 2, 1), (2, 1, 1), (1, 3), (3, 1). Numbers 1 to 3 in parentheses represent the number of blocks.

  FIG. 2 shows a schematic configuration diagram of another embodiment of the storage device according to the present invention. The high-speed memory RAM of this embodiment is provided with p sets, each of which includes blocks BLK1 to BLKm. In this case, n in FIG. 1 has a relationship of n = m × p. These sets of blocks BLK1 to BLKm are not particularly limited, but each has a storage capacity of 256 sectors (128 KB) as described above.

  In this configuration, the second operation in units of blocks can be performed in addition to the second operation in units of blocks as in the embodiment of FIG. That is, when the amount of saved data is large, the controller unit only specifies one set of the p sets without specifying the combination of the block BLK and the corresponding bus, and when m = 4. The four consecutive blocks and the four buses IBUS1 to IBUS4 can be automatically selected.

  The controller unit processes 1 to p groups of segmenting operations for the high-speed memory RAM. The operation mode of each section is transfer / standby / storage, and has a mechanism (scheduling) for securing one or more sections for writing data from the host HOST. In order to perform each operation without delay, for example, when the first set performs data transfer to the flash memory FLSH among the 1 to p sets of the high-speed memory RAM, the second set waits for transfer to the flash memory FLSH. Among them, a model in which the third set is storing data from the host HOST can be considered. Therefore, 3 is the minimum configuration value in the above-described p set.

  FIG. 3 is a schematic block diagram showing an embodiment of the storage device according to the present invention. The storage device of this embodiment is not particularly limited as an SSD (Solid State Drive) using a flash memory (FLSH) as a storage medium, but is a binary or multi-level (4-level) flash memory having a storage capacity of 1024 Mbits. Are installed in a single package to have a storage capacity that can replace the HDD.

  These many non-volatile memories (FLSH) are not particularly limited, but are divided into four groups and are connected to the internal buses IBUS1 to IBUS4 as the second bus through the non-volatile memories I / F (interfaces), respectively. . The internal bus BUS as the first bus is connected to a controller unit having an interface I / F such as ATA or SCSI. The controller section includes a controller such as a one-chip microcomputer as indicated by a CPU and an interface I / F such as ATA (AT Attachment) or SCSI (Small Computer System Interface). Therefore, the controller unit exchanges data between the driver provided in the nonvolatile memory interface I / F and the nonvolatile memory (FLSH), that is, writes and reads data.

  The controller unit has a multiplexer MPX in an interface unit with a volatile memory (RAM), and by switching the multiplexer MPX, access from the host HOST and data saving in the volatile memory (RAM) are performed. Access to the network is enabled in a time-sharing manner.

  Since the data read from the flash memory FLSH can be performed faster than the write operation, even if there is no logical address data in the volatile memory (RAM), the read from the volatile memory (RAM) is possible. Similar to the operation, the data can be read from the flash memory FLSH to the host HOST through the interface I / F such as ATA or SCSI and the data line (first bus). Therefore, although omitted in the embodiments of FIGS. 1 and 2, a signal path for reading data from the flash memory FLSH to the host HOST is provided in the controller unit CONT. The table TBL provided in the controller unit CONT stores logical addresses and the like used for scheduling data saving in the volatile memory (high-speed memory) RAM.

  In this embodiment, the package is further provided with a power detection circuit and a capacitor CP and a switch SW for securing an operating voltage when the power is shut off, although not particularly limited. The capacitor CP supplies a voltage to the nonvolatile memory, the controller unit, the volatile memory, and the power detection circuit by the accumulated charge even when the power supply is unexpectedly shut down on the system side, so that the nonvolatile memory is interrupted. It operates so as to maintain the operating voltage until the normal end state is included. In order to secure an operating voltage such that the above interruption processing is performed, a plurality of ceramic capacitors or electric double layer capacitors are arranged in parallel so as to have a capacitance value of about several hundred μF to several tens of mF, for example. .

  The power supply detection circuit receives the power supply voltage Vcc from the host side such as a microcomputer and detects the power-on and power-off. This detection signal is supplied to one input of the gate circuit G. A control signal through a control line is supplied to the other input of the gate circuit G. The gate circuit G is composed of a logic circuit such as a NAND gate circuit, for example. The gate circuit G has a switch SW corresponding to a signal from a controller corresponding to power-on or power-off or a control signal supplied from a control line. Control and so on.

  The switch SW is switched by the output signal of the gate circuit G, and the capacitor CP performs an operation of supplying the held voltage as an operating voltage of the internal circuit of the storage device SSD from the charging operation by the power source Vcc. The power supply detection circuit also has a function of preventing the operating voltage formed by the capacitor CP from flowing back to the system side so that the holding voltage of the capacitor CP can be used effectively. is there. In the simplest configuration, the power supply voltage Vcc from the system side is charged to the capacitor CP through the switch SW as the power supply voltage of the storage device SSD through a unidirectional element such as a diode, and the control unit, nonvolatile memory ( Flash memory FLSH), volatile memory (high-speed memory RAM), interface circuit I / F, and power supply detection circuit.

  The storage device SSD has, for example, the same outer size (70.0 × 100.0 × 9.5 mm) as that of a 2.5-inch hard disk drive device or the same outer size (101. 6 × 146.0 × 25.4 mm), and the connector pin connected to the interface circuit INF is the same as the 2.5 inch hard disk drive device or the 3.5 inch hard disk drive device. It is done. Thus, the storage device SSD of this embodiment is an HDD (Hard Disk Drive) compatible storage device.

  In the storage device SSD of this embodiment, the handling during the operation when the power cut-off is detected by the power detection circuit can be selected to wait until the normal operation is completed or to interrupt the operation. This is determined based on the processing contents during operation, the amount of data written from the volatile memory to the nonvolatile memory by the memory controller unit (required time), and whether or not to continue when the power is turned on again.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the volatile memory, for example, the high-speed memory RAM may be a static RAM in addition to the SDRAM as described above. The flash memory may be a NOR flash memory in addition to the NAND flash memory. The controller unit may be anything as long as it enables simultaneous access to the high-speed memory RAM from a plurality of buses by the time division.

  It is configured using a flash memory and can be widely used for a storage device that can be replaced with a hard disk drive memory, for example.

1 is a schematic configuration diagram of an embodiment of a storage device according to the present invention. It is a schematic block diagram of other one Example of the memory | storage device based on this invention. 1 is a schematic block diagram of an embodiment of a storage device according to the present invention.

Explanation of symbols

  CONT: Controller unit, RAM: High speed memory (volatile memory), BLK1 to BLKn: Block, FLSH (FLSH1 to m) ... Flash memory (nonvolatile memory), BUS ... First bus (internal bus), IBUS1 to IBUSm ... Second bus (internal bus), HOST ... Host, CPU ... 1 chip microcomputer, TBL ... Table, SW ... Switch, CP ... Capacitor, G ... Gate circuit,

Claims (5)

Semiconductor random access memory,
Batch erase nonvolatile memory,
A controller unit for performing memory access including a first operation and a second operation on the semiconductor random access memory and the batch erase nonvolatile memory;
An internal bus,
The semiconductor random access memory is divided into n blocks each having a plurality of storage areas.
The batch erase nonvolatile memory is divided into a plurality of m sets,
The internal bus
A first bus capable of writing data to the semiconductor random access memory from the outside;
And m second buses capable of independently writing data from the semiconductor random access memory to the batch erasable nonvolatile memory divided into the m groups,
The controller part
The first operation and the second operation can be performed simultaneously in a time-sharing manner,
The first operation is to write data to the semiconductor random access memory from the outside using the first bus.
The second operation is the oldest data at the time of writing in the storage data of the semiconductor random access memory in order to secure a storage area for the first operation for the semiconductor random access memory. Write 1 to m blocks to the batch erase nonvolatile memory using the second bus corresponding to the amount of data.
Storage device In claim 1,
The batch erasing type nonvolatile memory enables a batch erasing operation for each storage area corresponding to a block unit of the semiconductor random access memory.
Storage device. In claim 1,
The second operation includes an operation of writing the maximum m blocks to the batch erasable nonvolatile memory in the old plural order when writing the stored data using the second bus.
Storage device. In claim 1 or 2,
The n blocks of the semiconductor random access memory are divided into a plurality of p sets, and each of the m blocks is assigned to each set.
The second operation includes an operation of writing to the batch erase nonvolatile memory in the block erase nonvolatile memory in units of m blocks using the second bus.
Storage device In claims 1 to 4,
The controller unit further includes an HDD compatible interface unit for inputting / outputting data to / from the host,
The semiconductor random access memory, the batch erase nonvolatile memory, the controller unit and the internal bus are mounted in a package having an external size and a connector pin corresponding to a general-purpose small hard disk drive device.
Storage device.

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