JP2010087035A - Apparatus for manufacturing three-dimensional semiconductor device and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing apparatus and a method for manufacturing the same reducing manufacturing cost of a three-dimensional semiconductor device. <P>SOLUTION: An integrated circuit chip bonding apparatus 1 manufactures a three-dimensional semiconductor device by stacking a plurality of memory chips 41 with copper terminals on an upper and lower faces on a base board 40 with copper terminals on an upper face and bonding the copper terminals to each other. The integrated circuit chip bonding apparatus 1 includes: a hydrogen plasma cleaner section 2 for exposing the base board 40 and the memory chips 41 in a hydrogen plasma atmosphere to remove oxide films formed on the copper terminals; and a chip mounting section 30 sequentially stacking integrated circuit chips of the memory chips 41, from which the oxide films of the copper terminals have been removed, on the base board 40, from which the oxide films of the copper terminals have been removed, and pressing and bonding the copper terminals formed on mutually opposed surfaces to each other in a non-oxygen atmosphere. The base board 40 and the memory chips 41 are thereby transferred from the hydrogen plasma cleaner section 2 to the chip mounting section 30 in a non-oxygen atmosphere. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a manufacturing apparatus and a manufacturing method of a three-dimensional semiconductor device configured by stacking a plurality of integrated circuit chips in a plurality of stages.

  With the recent increase in operation speed of integrated circuit devices, three-dimensional mounting technology for integrated circuit chips has attracted attention. Compared to the two-dimensional mounting, the three-dimensional mounting has a significant effect on increasing the operation speed of the integrated circuit device because the signal wiring length is drastically shortened and the propagation delay time thereof is greatly shortened. On the other hand, for the purpose of shortening the signal propagation delay time, the resistance of the wiring material, for example, the transition from aluminum wiring to copper wiring is progressing inside and outside the integrated circuit chip. Along with this, the material of terminals (bumps) formed on the integrated circuit chip has also shifted from solder to copper.

  Patent Document 1 discloses an example of a three-dimensional semiconductor device configured by stacking a plurality of memory integrated circuit chips. The terminals of the memory integrated circuit chip constituting the three-dimensional semiconductor device disclosed in Patent Document 1 are formed by through electrodes that penetrate the upper and lower surfaces of the chip, and the upper and lower portions of the through electrodes are copper bumps. The copper bump electrode is plated with nickel and gold.

The nickel and gold plating on the copper electrode is performed to prevent copper oxidation. That is, since copper is easy to oxidize, an oxide film (natural oxide film) is easily formed on the surface even in air at normal temperature. When the natural oxide film is formed, the electrical resistance increases and the bondability between the copper terminals decreases. Therefore, the copper terminal is often covered with a metal that is difficult to oxidize, such as gold, and is easy to join.
JP 2008-16720 A

  However, if nickel or gold plating or the like is applied to the terminals of the memory integrated circuit chip, an extra plating step is required, and the use of a noble metal such as gold increases the manufacturing cost. Therefore, when a three-dimensional semiconductor device is manufactured by the method disclosed in Patent Document 1, there is a problem that the manufacturing cost increases.

  SUMMARY OF THE INVENTION The present invention provides a three-dimensional semiconductor device manufacturing apparatus and a manufacturing method thereof that can reduce the manufacturing cost of the three-dimensional semiconductor device.

  According to the present invention, a plurality of integrated circuit chips having terminals formed of copper on both the upper surface and the lower surface are stacked on a base substrate having terminals formed of copper on at least the upper surface thereof, and the surfaces facing each other are laminated. It is a manufacturing apparatus of a three-dimensional semiconductor device that manufactures a three-dimensional semiconductor device configured by joining the formed terminals. The three-dimensional semiconductor device manufacturing apparatus exposes each of a base substrate and an integrated circuit chip to a hydrogen plasma atmosphere, and removes an oxide film formed on a copper terminal of each of the base substrate and the integrated circuit chip. And a substrate substrate having a terminal from which an oxide film has been removed by the hydrogen plasma cleaner section, or an integrated circuit chip having a terminal from which the oxide film has been removed by the hydrogen plasma cleaner section is laminated on the substrate substrate. The other one of the integrated circuit chips having the terminal from which the oxide film has been removed by the hydrogen plasma cleaner unit is placed on the upper surface of the three-dimensional semiconductor device that is being bonded and formed on the surfaces facing each other. In addition, a chip mount part that joins the terminals together in a non-oxygen atmosphere and a hydrogen plasma cleaner part. The base substrate and the integrated circuit chip having a terminal oxide film is removed, respectively, and a transport unit for transporting the hydrogen plasma cleaner unit in a non-oxygen atmosphere to the chip mounting part, characterized in that it comprises a.

  According to the apparatus for manufacturing a three-dimensional semiconductor device of the present invention, even if an oxide film is formed on a terminal of an integrated circuit chip used for manufacturing the three-dimensional semiconductor device, the oxide film is a hydrogen plasma cleaner section. Removed. Further, the integrated circuit chip having the terminal from which the oxide film has been removed is transported to the chip mount section under a non-oxygen atmosphere, and the chip mount section includes a plurality of integrated circuit chip oxide films under a non-oxygen atmosphere. A three-dimensional semiconductor device is manufactured by bonding copper terminals that are not present together.

  Accordingly, when a three-dimensional semiconductor device is manufactured by the three-dimensional semiconductor device manufacturing apparatus of the present invention, the terminals of the integrated circuit chip used for manufacturing the three-dimensional semiconductor device are plated with nickel, gold, or the like. There is no need. Therefore, no precious metal such as gold is required as the material, and the plating process is not required.

  According to the present invention, the manufacturing cost of the three-dimensional semiconductor device is reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

  FIG. 1 is a diagram showing an example of the configuration of an integrated circuit chip bonding apparatus according to an embodiment of the present invention as an arrangement view from the top surface, and FIG. 2 is manufactured by the integrated circuit chip bonding apparatus according to the present embodiment. It is the figure which showed the example of the cross-section of a laminated memory integrated circuit device.

  The integrated circuit chip bonding apparatus 1 shown in FIG. 1 is an apparatus that manufactures a three-dimensional semiconductor device by stacking a plurality of integrated circuit chips on a base substrate and bonding terminals formed on each of them. Here, before describing the integrated circuit chip bonding apparatus 1 in detail, the configuration of the stacked memory integrated circuit apparatus 4 which is an example of a three-dimensional semiconductor device will be described with reference to FIG.

  As shown in FIG. 2A, in the stacked memory integrated circuit device 4, a plurality of memory chips 41 and interface chips 43 each having a memory integrated circuit are stacked on an interposer 42 constituting a base substrate, and mutual terminals are provided. Are joined together. Here, the memory chip 41 and the interface chip 43 are both bare chips cut out from the Si wafer.

  As shown in FIG. 2B, in the memory chip 41, a memory integrated circuit (not shown) is formed on the surface layer portion of the Si substrate 410, and a plurality of input / output signal lines and power supply lines of the memory integrated circuit are respectively connected to through electrodes. 411. The through electrode 411 is configured by filling a via hole penetrating from the upper surface to the lower surface of the Si substrate with a metal having good conductivity such as Cu. Here, a Cu bump 412 is formed on the upper surface of the through electrode 411 on the upper surface of the memory chip 41, and a Cu bump 413 is formed on the lower surface of the memory chip 41 on the lower surface of the through electrode 411.

  Such Cu bumps 412 and 413 function as bonding terminals, and are bonded to Cu bumps 413 and 412 of other memory chips 41, Cu bumps 424 formed on the interposer 42, or the like.

  FIG. 2C is an enlarged view of the through electrode 411 and its peripheral portion of the memory chip 41. The through electrode 411 is electrically connected to the Cu bumps 412 and 413, and is electrically insulated from the Si substrate of the Si substrate 410 by insulating films 414, 415, and 416 made of silicon oxide, silicon nitride, or the like. ing.

  As shown in FIG. 2D, the interposer 42 is constituted by an insulating substrate 420 such as polyimide in which a via hole 421 is formed, and the via hole 421 is filled with a metal having good conductivity such as Cu. Further, Cu wirings 422 connected to the metal in the respective via holes 421 are formed on the upper surface of the interposer 42, and Cu bumps 423 are formed at the positions of the via holes 421 on the lower surface thereof. Further, a Cu bump 424 is formed on the Cu wiring 422 at a position where the Cu bump 413 of the memory chip 41 is joined.

  The interposer 42 is also referred to as a rearrangement board, and has a function of converting the signal line of the memory chip 41 into a signal line for connecting to an external system via an interface chip 43 bonded to the lower surface thereof. Accordingly, solder bumps 44 for external system connection are formed on the lower surface of the interposer 42, and signal lines converted for external system connection by the interface chip 43 are connected to the solder bumps 44 via the Cu wiring 422.

  Further, as shown in FIG. 2A, the gaps between the plurality of memory chips 41 stacked and bonded on the interposer 42 are filled with an underfill material 45 made of insulating resin or the like. Covered by the molding material 46. As described above, the stacked memory integrated circuit device 4 is finally assembled as a three-dimensional semiconductor device in the form of a BGA (Ball Grid Array) package.

  Next, referring to FIG. 1 and referring to FIG. 3 and subsequent drawings, an example of the configuration of the integrated circuit chip bonding apparatus 1 for manufacturing the stacked memory integrated circuit device 4 shown in FIG. Details of the components will be described.

  As shown in FIG. 1, an integrated circuit chip bonding apparatus 1 according to an embodiment of the present invention includes a hydrogen plasma cleaner unit 2 and a chip mount unit 3. Here, the hydrogen plasma cleaner unit 2 is formed on the memory chip 41 used when manufacturing the stacked memory integrated circuit device 4 and Cu terminals (Cu bumps 412, 413, 423, 424, etc.) on the base substrate 40. An apparatus for removing a natural oxide film. The chip mount unit 3 is a device that sequentially stacks the memory chips 41 on the base substrate 40 and is provided on each of the upper and lower surfaces and joins Cu terminals that are in contact with each other.

  In the present embodiment, the base substrate 40 is a substrate in which a plurality of interposers 42 (four interposers 42 in FIG. 1) are connected in a plane, and the wafer 5 is a wafer protection sheet 51. Is attached and is diced into a plurality of memory chips 41. Note that the wafer 5 to which the wafer protection sheet 51 is attached is held by a protection ring (not shown) for convenience of transportation.

  In FIG. 1, the hydrogen plasma cleaner unit 2 includes a substrate substrate supply unit 21a, a substrate substrate cleaning plasma chamber 22a, a wafer supply unit 21b, and a wafer cleaning plasma chamber 22b. Here, the substrate cleaning plasma chamber 22a and the wafer cleaning plasma chamber 22b are vacuum chambers in which hydrogen plasma is generated, as will be described in detail with reference to FIG.

  The base substrate supply unit 21a is a carry-in port for carrying the base substrate 40 accommodated in a magazine or the like into the base substrate cleaning plasma chamber 22a, and includes a magazine loader, a load lock chamber (not shown), and the like. The load lock chamber is a sealed chamber having at least two loading / unloading gates, and a transfer device is usually provided therein.

  In such a base substrate supply unit 21a, when the base substrate 40 set in the magazine loader is taken into the load lock chamber, the base substrate 40 is further transferred into the base substrate cleaning plasma chamber 22a via the transfer device in the load lock chamber. It is conveyed to.

  In the transfer operation of the base substrate 40, when the base substrate 40 is taken into the load lock chamber, the magazine loader side (atmosphere side) gate of the load lock chamber is opened, and the gate to the base substrate cleaning plasma chamber 22a is opened. Is closed. When the base substrate 40 is transferred to the base substrate cleaning plasma chamber 22a, the gate on the atmosphere side is closed and the gate between the base substrate cleaning plasma chamber 22a is opened.

  Similar to the base substrate supply unit 21a, the wafer supply unit 21b is a carry-in port for carrying the wafer 5 to which the wafer protection sheet 51 is stuck into the wafer cleaning plasma chamber 22b, and is a wafer loader or a similar load lock chamber ( (Not shown). Further, by the same operation, the wafer 5 set in the wafer loader is transferred to the wafer cleaning plasma chamber 22b.

  FIG. 3 is a diagram showing an example of a schematic configuration of the plasma chamber 22 in the integrated circuit chip bonding apparatus 1 according to the present embodiment. Here, the plasma chamber 22 is a general term for the substrate cleaning plasma chamber 22a and the wafer cleaning plasma chamber 22b. In FIG. 3, the plasma chamber 22 is described taking the wafer cleaning plasma chamber 22b as an example.

As shown in FIG. 3, the inside of the plasma chamber 22 is supplied with hydrogen gas from a hydrogen gas supply port 222, while the exhaust port 223 is evacuated by a vacuum pump (not shown) or the like. For example, it is maintained at about 10 Pa. Further, a high-frequency voltage such as a microwave supplied from a high-frequency power source 226 is applied between the upper electrode 224 and the lower electrode 225, and hydrogen ion (H ⁺ ) plasma is generated inside the plasma chamber 22. .

As a result, the wafer 5 placed above the lower electrode 225, that is, the memory chip 41, is exposed to the generated hydrogen ion (H ⁺ ) plasma. Therefore, the Cu bumps 412 and 413 of the memory chip 41 are exposed to hydrogen ion (H ⁺ ) plasma. Here, when a natural oxide film is formed on the Cu bumps 412 and 413, hydrogen ion (H ⁺ ) plasma exerts a reducing action on the natural oxide film, so that copper oxide (CuO) is converted into intrinsic copper ( Change to Cu).

Therefore, the natural oxide film formed on the Cu bumps 412 and 413 is removed by placing the memory chip 41 in the plasma chamber 22 and exposing it to hydrogen ion (H ⁺ ) plasma for a predetermined time (for example, 20 seconds). Is done.

  As described above, when the natural oxide film formed on the Cu bumps 412 and 413 of the memory chip 41 is removed, the memory chip 41, that is, the wafer 5 is attached to the wafer protection sheet 51. Then, it is taken out from the inside of the plasma chamber 22 (wafer cleaning plasma chamber 22b) by a transfer robot in a load lock chamber (not shown) provided on the chip mount portion 3 side, and is carried out to the chip mount portion 3.

  Similarly, the natural oxide films on the Cu bumps 423 and 424 of the base substrate 40 (interposer 42) are removed by the base substrate cleaning plasma chamber 22a. The base substrate 40 from which the natural oxide film of the Cu bumps 423 and 424 has been removed is accommodated in a tray by a transfer device in a load lock chamber (not shown) provided on the chip mount unit 3 side. Then, it is taken out from the inside of the plasma chamber 22 (base substrate cleaning plasma chamber 22 a) and carried out to the chip mount unit 3.

  Next, the configuration and function of the chip mount unit 3 will be described again with reference to FIG. As shown in FIG. 1, the chip mount unit 3 includes a base substrate transfer unit 31a, a wafer transfer unit 31b, a mount stage 32, a wafer stage 33, a collet 34 including a travel track 341 and a collet support 342, a mounted substrate recovery unit. 35a, a used wafer collecting unit 35b, and the like.

  The base substrate transport unit 31 a is configured by a transport device including a suction hand, a conveyor, and the like. The base substrate 40 is appropriately taken out from the base substrate cleaning plasma chamber 22 a, transported, and placed on the mount stage 32.

  Similarly, the wafer transfer unit 31b is configured to include a transfer robot having a hand that holds the protective ring holding the wafer 5, receives the wafer 5 unloaded from the wafer cleaning plasma chamber 22b, and transfers the wafer 5 to the wafer stage 33. Place on top.

  Next, as shown in FIGS. 1 and 4, a traveling track 341 is provided above the mount stage 32 and the wafer stage 33 so as to straddle both. Here, FIG. 4 is a side view showing an example of a moving mechanism of the collet 34 including the traveling track 341.

  The collet support 342 includes an arm 343 that hangs down, and the collet 34 is attached to the lower end of the arm 343. The arm 343 appropriately expands or contracts to move the collet 34 in the vertical direction. The collet support 342 is attached to the travel track 341 and travels freely on the travel track 341 while supporting the collet 34. In FIG. 4, the vertical direction is the Z axis, and the direction of the traveling track 341 is the Y axis.

  Although not shown, each of the wafer stage 33 and the mount stage 32 has a moving mechanism that freely moves in a direction intersecting the traveling track 341 (X-axis direction in FIG. 1).

  In addition, the chip mount unit 3 includes a control device (not shown) that controls these moving mechanisms in conjunction with each other, and is controlled by the control device so that any horizontal surface on the wafer stage 33 or the mount stage 32 can be obtained. The collet 34 can be positioned at a position. Further, the control device can determine the height position of the collet 34 by appropriately extending or contracting the arm 343.

  The collet 34 is provided with a suction portion by vacuum suction or the like at the lower end thereof. Therefore, when the collet 34 adsorbs the memory chip 41 to the adsorbing portion, the control device first moves the collet 34 and the wafer stage 33 appropriately in the Y direction or the X direction, thereby moving the collet 34, It is positioned directly above the suction target memory chip 41. Then, by extending the arm 343, the collet 34 is lowered to a position where the suction portion contacts the memory chip 41, and the memory chip 41 is sucked. Thereafter, the arm 343 is contracted to raise the collet 34.

  The wafer stage 33 has a chip push-up mechanism (not shown) for facilitating peeling of the memory chip 41 from the wafer protection sheet 51. The chip push-up mechanism pushes up the sucked memory chip 41 from the lower part of the wafer protection sheet 51 in synchronization with the collet 34 sucking the memory chip 41 and assists the peeling operation.

  When the collet 34 attracts the memory chip 41 and rises, the control device again moves the collet support 342 and the wafer stage 33 in the Y direction or the X direction as appropriate, and the collet 34 is mounted on the mount stage 32. It is positioned at a predetermined position above the placed base substrate 40.

  Then, the control device extends the arm 343 to lower the collet 34 to a position where the memory chip 41 adsorbing the tip of the collet 34 contacts the base substrate 40. At this time, the control device performs detailed alignment based on an image acquired from an imaging device (not shown) such as a camera attached to the collet support 342 or the collet 34, and Cu bumps 413 on the lower surface of the memory chip. The position is adjusted so that the Cu bumps 424 on the upper surface of the base substrate 40 (interposer 42) are in contact with each other.

  The collet 34 further includes a spring mechanism (not shown) that is driven by a control device via an electromagnetic coil or the like, and generates a pressing force that pushes the suction portion outward (downward in FIG. 4) by the spring mechanism. To do.

  Therefore, when the control device detects that the memory chip 41 is in contact with the base substrate 40, it drives the spring mechanism to press the memory chip 41 from above, and the Cu bump 413 on the bottom surface of the memory chip 41 and the base The Cu bumps 424 on the upper surface of the substrate 40 (interposer 42) are bonded by pressure.

  Although the memory chip 41 is bonded to the base substrate 40 here, the bonded memory chip 41 may be stacked on the base substrate 40 in some cases. In that case, the control device detects that the memory chip 41 adsorbed by the collet 34 contacts the stacked memory chip 41, drives the spring mechanism, and removes the adsorbed memory chip 41 from above. The pressed Cu bumps 413 on the lower surface of the memory chip 41 and the Cu bumps 412 on the upper surface of the stacked memory chips 41 are bonded by pressure bonding.

  FIG. 5 is a diagram illustrating a state in which two layers of memory chips 41 are bonded and stacked on the base substrate 40 placed on the mount stage 32, and a new memory chip 41 is further bonded thereon. is there. Here, FIG. 5A shows a state in which the collet 34 sucks the memory chip 41 being transported, and FIG. 5B shows a state in which a new layer is formed on the two-layer memory chip 41 on the base substrate 40. A memory chip 41 is placed, and a pressing force by a spring mechanism or the like is applied to the memory chip 41, so that Cu bumps 413 and 412 that are in contact with each other are joined.

  Here, the region where the substrate transfer unit 31a, the wafer transfer unit 31b, the mount stage 32, the wafer stage 33, and the collet 34 (including the traveling track 341 and the collet support 342) shown in FIG. It is assumed that it is covered with a housing for blocking the atmosphere. And the inside of the housing | casing is satisfy | filled with inert gas, such as nitrogen supplied from the inert gas supply part which is not shown in figure, and the pressure a little higher than atmospheric pressure shall be maintained. That is, the inside of the housing is kept in a non-oxygen atmosphere.

  Accordingly, the base substrate 40 and the memory chip 41 are taken out from the plasma chamber 22 and the process until the memory chip 41 is stacked on the base substrate 40 is performed in a non-oxygen atmosphere. That is, since the natural oxide film formed on the Cu bumps 423, 424, 412, and 413 on the base substrate 40 and the memory chip 41 is removed by the plasma chamber 22, the Cu bumps 423, 424, 412, and 413 are thereafter removed. Intact copper (Cu) is exposed until they are joined together. Therefore, the Cu bumps 423, 424, 412, and 413 can be bonded to each other with a pressing force that is not so large, that is, with a pressing force that is generated by the spring mechanism of the collet 34.

  When the Cu bumps 423, 424, 412, and 413 are pressed together, a heater is embedded in the mount stage 32 and the collet 34, and the Cu bumps 423, 424, 412, and 413 are heated and then pressed. Also good. In that case, it is possible to obtain a more stable bond between the Cu bumps 424, 412 and 413, to reduce the pressing force, and to shorten the time for applying the pressing force, as compared with the pressure bonding at room temperature. .

  FIG. 6 is a diagram showing an example of the configuration of a mounted substrate in which a predetermined number of memory chips 41 are stacked on the base substrate 40 by the chip mount unit 3. In the example shown in FIG. 6, six stages of memory chips 41 are stacked on a base substrate 40 constituted by four interposers 42. A structure in which a predetermined number of memory chips 41 are stacked on the base substrate 40 in a predetermined number of stages is hereinafter referred to as a mounted substrate.

  The control device of the chip mount unit 3 manages the number and the total number of the memory chips 41 stacked on the base substrate 40 by the collet 34, and completes stacking of the memory chips 41 on the base substrate 40, that is, manufacture of the mounted substrate. Completion is detected, and a notification to that effect is sent to the mounted substrate collection unit 35a (see FIG. 1).

  The mounted substrate collecting unit 35a is constituted by a transfer robot or the like, and when receiving a notification of the completion of manufacturing of the mounted substrate from the control device, collects the mounted substrate from the mount stage 32 and removes it from the chip mount unit 3. Carry out.

  Similarly, the used wafer collection unit 35b (see FIG. 1) is configured by a transfer robot or the like, and receives a notification from the control device notifying that there are no usable memory chips 41 on the wafer protection sheet 51. When this occurs, the wafer protection sheet 51 is recovered from the wafer stage 33 and carried out of the chip mount unit 3.

  Note that the memory chip 41 that can be used normally operates normally both electrically and functionally by inspection using a predetermined inspection apparatus performed before the wafer 5 is diced. This is what has been confirmed. Therefore, the memory chip 41 that has not been confirmed to operate normally by the inspection device is a defective product and is not used.

  The mounted substrate carried out of the chip mount unit 3 is a semi-finished product in the process of manufacturing the stacked memory integrated circuit device 4. After that, the mounted substrate is molded by the molding material 46 around the stacked portion of the memory chip 41 by another manufacturing apparatus, and then cut in units of the interposer 42. Further, the interface chip 43 is bonded to the lower surface of the interposer 42 and the solder bumps 44 are formed to complete the stacked memory integrated circuit device 4.

  As described above, when the integrated circuit chip bonding apparatus 1 described in this embodiment is used for manufacturing the stacked memory integrated circuit device 4, the base substrate 40 and the memory chip 41 are bonded, or the memory chips 41 are bonded to each other. In this case, since it is not necessary to apply gold or nickel plating to the junction terminals, the manufacturing cost of the stacked memory integrated circuit device 4 can be reduced.

(Modification 1 of embodiment)
Subsequently, a modification of the present embodiment will be described with reference to FIG. FIG. 7 is a diagram showing an example of the configuration of an integrated circuit chip bonding apparatus according to a modification of the present embodiment. In the integrated circuit chip bonding apparatus 1 described with reference to FIG. 1, the memory chip 41 necessary for manufacturing the stacked memory integrated circuit apparatus 4 is in a form in which the wafer 5 affixed to the wafer protection sheet 51 is diced. Has been supplied. On the other hand, in the modification of this embodiment, the memory chip 41 after dicing is supplied to the integrated circuit chip bonding apparatus 1 ′ in a form accommodated in the tray 6.

  The tray 6 is a container for the memory chips 41 provided with a plurality of sections, and the memory chips 41 are laid flat one by one in each section. At this time, the memory chip 41 that has been confirmed to operate normally by the inspection apparatus is accommodated in the tray 6.

  The tray 6 in which the memory chip 41 is accommodated is carried into the tray cleaning plasma chamber 22b ′ via the tray supply unit 21b ′, and the natural oxidation formed on the Cu bumps 412 and 413 of the memory chip 41 therein. The film is removed. The memory chip 41 from which the natural oxide film of the Cu bumps 412 and 413 has been removed is conveyed to the chip mount unit 3 ′ while being accommodated in the tray 6.

  In the chip mount portion 3 ′, since the memory chip 41 is placed flat on the tray 6, it can be easily sucked and transported by the collet 34. Therefore, the operation of the chip mount portion 3 ′ in which the memory chip 41 is stacked on the base substrate 40 by the collet 34 is almost the same as the operation of the chip mount portion 3 described in FIG. 1. Therefore, description of the operation of the chip mount unit 3 is omitted.

  When a predetermined number of memory chips 41 are stacked on the base substrate 40 by the collet 34, the mounted substrate recovery unit 35a uses the base substrate 40 on which the predetermined number of memory chips 41 are stacked as a mounted substrate to integrate the integrated circuit. It is carried out of the chip bonding apparatus 1 ′. Similarly, the used tray collection unit 35b 'appropriately carries the empty tray 6 out of the integrated circuit chip bonding apparatus 1'.

  In addition, some embodiment variations are possible.

(Modification 2 of embodiment)
In the integrated circuit chip bonding apparatus 1 described so far, the base substrate 40 is configured by connecting a plurality of interposers 42. However, in the modification of this embodiment, the base substrate 40 is a single interposer. 42.

  In this case, the base substrate 40, that is, the interposer 42, is carried into the plasma chamber 22 while being accommodated in a tray similar to the tray 6 shown in FIG. 7, and natural oxidation of the Cu bumps 423 and 424 of the interposer 42 is performed. The film is removed. Then, the tray containing the interposer 42 is carried out of the plasma chamber 22 and placed on the mount stage 32. Thereafter, in the same manner as described with reference to FIG. 1, a predetermined number of memory chips 41 are stacked on the interposer 42, and the interposer 42 in which the predetermined number of memory chips 41 are stacked is accommodated in a tray. Then, it is carried out from the integrated circuit chip bonding apparatus.

  In the modified example-2 of this embodiment, the memory chip 41 may be one in which the wafer 5 is diced and pasted on the wafer protection sheet 51 as shown in FIG. It may be accommodated in the tray 6 as in Example-1.

(Modification 3 of embodiment)
The interposer 42 may be manufactured using an insulating film formed on a silicon wafer. In this case, the silicon substrate on which the interposer 42 is formed corresponds to the base substrate 40 in FIG.

  Therefore, in this case, a silicon wafer is carried into the integrated circuit chip bonding apparatus 1 instead of the base substrate 40. Therefore, the base substrate cleaning plasma chamber 22a shown in FIG. The configuration is the same as 22b. Or you may make it share the wafer cleaning plasma chamber 22b with the wafer in which the interposer 42 was formed, and the wafer in which the memory chip 41 was formed.

  In the modified example-3 of this embodiment, the memory chip 41 may be one in which the wafer 5 is diced and pasted on the wafer protection sheet 51 as shown in FIG. It may be accommodated in the tray 6 as in Example-1.

  Also in the modified examples 1, 2, and 3 of the embodiment as described above, when the interposer 42 and the memory chip 41 are joined or the memory chips 41 are joined together, the joining terminals are plated with gold or nickel. Therefore, the manufacturing cost of the stacked memory integrated circuit device 4 can be reduced.

(Modification 4 of embodiment)
In the above-described embodiment and its modifications, the memory chip 41 is formed by forming Cu bumps on a silicon bare chip. However, the memory chip 41 and the interposer 42 may be a CSP (Chip Size Package) or the like. A flip chip or the like in which a silicon bare chip is housed in a predetermined package according to a technique and a Cu terminal is provided in the package may be used. In this case, the interposer 42 and the memory chip 41 are both carried into the integrated circuit chip bonding apparatus in a form accommodated in the tray, and the memory chip 41 is stacked on the interposer 42.

  Also in the modification of this embodiment, it is not necessary to apply gold or nickel plating to the junction terminals, so that the manufacturing cost of the stacked memory integrated circuit device 4 can be reduced.

(Modification 5 of embodiment)
In the above-described embodiment and its modification, the three-dimensional integrated circuit device is the stacked memory integrated circuit device 4 as shown in FIG. 2, but the substrate substrate 40 (interposer) is not limited thereto. 42) The integrated circuit chip stacked thereon may be a logic integrated circuit, an analog integrated circuit, or a combination thereof. In particular, in the case of a flip chip or the like in which an integrated circuit chip is packaged as in Modification 4 above, the integrated circuit chip to be stacked is a logic integrated circuit, a memory integrated circuit, an analog integrated circuit, or a combination thereof. It is thought that there are many things that have been made.

(Modification 6 of embodiment)
In the embodiment described above and the modification thereof, it is assumed that the terminals of the base substrate 40 (interposer 42) and the integrated circuit chip (memory chip 41) stacked thereon are bumps formed of copper (Cu). However, some or all of the bumps of the base substrate 40 and the integrated circuit chip may be formed of solder, aluminum, or the like. In that case, in the integrated circuit chip bonding apparatus according to the embodiment, bonding of “Cu bump” and “solder bump”, bonding of “Cu bump” and “Al bump”, or the like is performed.

(Modification 7 of Embodiment)
In the embodiment described above and its modification, the base substrate transport unit 31a, the wafer transport unit 31b, the mount stage 32, the wafer stage 33, and the collet 34 (the travel track 341 and the collet support 342 shown in FIG. The region in which the housing is disposed is covered with a housing and the housing is filled with an inert gas such as nitrogen, but it is not always necessary to fill the entire housing with an inert gas.

  For example, an outlet for ejecting an inert gas supplied from an inert gas supply unit (not shown) is provided in the vicinity of the mount stage 32, the wafer stage 33, and the like, and the inert gas ejected from the outlet is mounted on the mount stage 32 and the wafer stage. By spraying on 33 or the like, a local non-oxygen atmosphere may be formed in the vicinity thereof.

  In this case, when the base substrate 40 or the memory chip 41 is transported, the base substrate 40 and the memory chip 41 are exposed to oxygen-containing air. The amount of oxidation of the 41 Cu bump is slight.

1 is a diagram showing an example of the configuration of an integrated circuit chip bonding apparatus according to an embodiment of the present invention as a layout from the top. The figure which showed the example of the cross-section of the laminated memory integrated circuit device manufactured with the integrated circuit chip bonding apparatus which concerns on this embodiment. The figure which showed the example of schematic structure of the plasma chamber in the integrated circuit chip bonding apparatus which concerns on this embodiment. The figure which showed the example of the movement mechanism of the collet containing a driving | running | working track | truck by the side view. The figure which showed a mode that two layers of memory chips were joined and laminated | stacked on the base substrate mounted on the mount stage, and a new memory chip was joined on it. The figure which showed the example of the structure of the mounted board | substrate by which the predetermined number of memory chips were laminated | stacked on the base substrate by the chip mount part. The figure which showed the example of the structure of the integrated circuit chip bonding apparatus which concerns on the modification of this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Integrated circuit chip bonding apparatus 2 Hydrogen plasma cleaner part 3 Chip mount part 4 Stacked memory integrated circuit apparatus 5 Wafer 6 Tray 21a Base substrate supply part 21b Wafer supply part 22 Plasma chamber 22a Base substrate cleaning plasma chamber 22b Wafer cleaning plasma chamber 31a Base Substrate transfer unit 31b Wafer transfer unit 32 Mount stage 33 Wafer stage 34 Collet 35a Mounted substrate recovery unit 35b Used wafer recovery unit 40 Base substrate 41 Memory chip 42 Interposer 43 Interface chip 44 Solder bump 45 Underfill material 46 Mold material 51 Wafer protection Sheet 222 Hydrogen gas supply port 223 Exhaust port 224 Upper electrode 225 Lower electrode 226 High frequency power source 333 Wafer Stage 33
341 Traveling track 342 Collet support 343 Arm 410 Si substrate 411 Through electrode 412, 412 Cu bump 413 Cu bump 414 Insulating film 420 Insulating substrate 421 Via hole 422 Cu wiring 423,424 Cu bump

Claims (8)

A plurality of integrated circuit chips having terminals formed of copper on both the upper surface and the lower surface thereof are stacked on a base substrate having terminals formed of copper on at least the upper surface, and formed on surfaces facing each other. A three-dimensional semiconductor device manufacturing apparatus for manufacturing a three-dimensional semiconductor device configured by joining terminals together,
A hydrogen plasma cleaner unit that exposes each of the base substrate and the integrated circuit chip to a hydrogen plasma atmosphere and removes an oxide film formed on a copper terminal of each of the base substrate and the integrated circuit chip;
The base substrate having a terminal from which an oxide film has been removed by the hydrogen plasma cleaner section, or at least one integrated circuit chip having a terminal from which the oxide film has been removed by the hydrogen plasma cleaner section is stacked on the base substrate. The other one of the integrated circuit chips having a terminal from which an oxide film has been removed by the hydrogen plasma cleaner is placed on the upper surface of a three-dimensional semiconductor device that is being manufactured, and formed on surfaces facing each other. A chip mount part for joining the terminals by pressure bonding in a non-oxygen atmosphere;
An apparatus for manufacturing a three-dimensional semiconductor device, comprising: 3. The substrate according to claim 1, wherein the base substrate and the integrated circuit chip each having a terminal from which an oxide film has been removed by the hydrogen plasma cleaner are transported to the chip mount in a non-oxygen atmosphere. -Dimensional semiconductor device manufacturing equipment. The three-dimensional semiconductor device manufacturing apparatus according to claim 1, wherein the integrated circuit chip is a silicon bare chip. The three-dimensional semiconductor device manufacturing apparatus according to claim 1, wherein the integrated circuit chip is a packaged integrated circuit chip in which a silicon bare chip is housed in a predetermined package. A plurality of integrated circuit chips having terminals formed of copper on both the upper surface and the lower surface thereof are stacked on a base substrate having terminals formed of copper on at least the upper surface, and formed on surfaces facing each other. A manufacturing method of a three-dimensional semiconductor device for manufacturing a three-dimensional semiconductor device configured by joining terminals together,
A hydrogen plasma cleaning step of exposing each of the base substrate and the integrated circuit chip to a hydrogen plasma atmosphere and removing an oxide film formed on a copper terminal of each of the base substrate and the integrated circuit chip;
The base substrate having the terminal from which the oxide film has been removed by the hydrogen plasma cleaning process, or at least one integrated circuit chip having the terminal from which the oxide film has been removed by the hydrogen plasma cleaning process is stacked on the base substrate. The other one of the integrated circuit chips having a terminal from which an oxide film has been removed by the hydrogen plasma cleaning process is placed on the upper surface of a three-dimensional semiconductor device that is in the process of manufacturing, and formed on surfaces facing each other. A chip mounting process in which the terminals are bonded by pressure bonding in a non-oxygen atmosphere;
Having 6. The base substrate and the integrated circuit chip, each having a terminal from which an oxide film has been removed in the hydrogen plasma cleaner process, are transported in a non-oxygen atmosphere and supplied to the chip mount unit. A manufacturing method of the three-dimensional semiconductor device described in 1. The method for manufacturing a three-dimensional semiconductor device according to claim 5, wherein the integrated circuit chip is a silicon bare chip. The method for manufacturing a three-dimensional semiconductor device according to claim 5, wherein the integrated circuit chip is a packaged integrated circuit chip in which a silicon bare chip is housed in a predetermined package.

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