JP2010079536A - Memory access control circuit and memory access control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve latency when a plurality of requests are issued simultaneously and to reduce overhead due to handshake during memory access. <P>SOLUTION: A request control unit accepts all read requests from an image processing unit and registers information thereof in a request management table. If a preceding write request for the same bank address has been already registered in a table when a read request is accepted, the read request is queued. If a write request has not been registered, the read request is issued to an SDRAM controller. A subsequent read request with a different bank address is prevented from being rejected by a memory access control unit and remaining in the image processing unit. For a plurality of write requests, a request control unit stores write data in a write data buffer, combines them into one write request, and issues the one write request to the SDRAM controller. In this way, bus occupancy can be reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory access control technique for a block that performs image processing and the like.

  In a system equipped with a functional block (image processing macro) for performing image processing or the like, a configuration in which a plurality of image processing macros share one SDRAM (Synchronous Dynamic Random Access Memory) 1104 via the SDRAM controller 1105 is often adopted. Is done.

FIG. 11 is a diagram illustrating a configuration example of a system including an image processing macro.
The image processing macro 1101 includes an image processing unit 1102 that is a core part that executes image processing, and a memory access control unit 1103 that controls memory access to image data stored in the SDRAM 1104. A plurality of image processing macros 1101 can be mounted such as B,..., #X.

The SDRAM 1104 is connected via the SDRAM controller 1105 to the image bus 1109 to which the memory access control unit 1103 of each image processing macro 1101 is connected.
The SDRAM controller 1105 executes handshake control with the corresponding image processing macro 1101 in response to requests from a plurality of image processing macros 1101, and performs memory access based on each request to the SDRAM 1104 while arbitrating each request. Execute.

  The SDRAM controller 1105 is also connected to a system bus 710 to which functional units such as a CPU macro 1106, a card interface macro 1107, and a peripheral macro 1108 are connected, and a control program communicated between these portions and the SDRAM 1104 It also performs arbitration for control data.

  Here, in the image processing macro 1101, a plurality of write requests or read requests are often issued from the image processing unit 1102 to the SDRAM 1104 at the same timing in order to realize parallel processing or the like for a plurality of pixel data. .

  In this case, a plurality of requests for the same address on the SDRAM 1104 cannot change the order of requests in order to maintain data consistency. For this reason, the request must wait for the RAM access of the request preceding it to be completed.

  On the other hand, a request that accesses an address different from the preceding request does not destroy the data consistency, and therefore the request does not need to wait for the RAM access of the preceding request to be completed.

Conventionally, as shown in, for example, Patent Document 1 below, a technique for performing overtaking control of a request using the above-described characteristics is known. With this conventional technique, latency of RAM access (processing delay from request issuance to response) ) Can be improved.
Japanese Patent Laid-Open No. 5-120113

In a conventional memory access control method in a system equipped with an image processing macro 1101 as shown in FIG. 11, the memory access control unit 1103 in the image processing macro 1101 performs a write request and a read issued by the image processing unit 1102. The access destination addresses of the requests are compared. If they match, the read request is waited. If they do not match, the write request being executed is overtaken in advance and the read request is issued to the SDRAM 1104.

As an example, as shown in FIG. 12, consider a case where a plurality of requests are issued in the following order from the image processing unit 1102 to each destination RAM area indicated by A to D on the SDRAM 1104.

1) A write request is issued to area A.
2) A read request is issued to area A.
3) A read request is issued to the D area.
4) A write request is issued to area B.
5) A read request is issued to area B.

The memory access control unit 1103 holds information indicating that the write request to the A area indicated in 1) above is incomplete, so that a read request to the A area that is the same access destination indicated in 2) above is stored. Will not accept.

As a result, a read request or the like that does not need to wait for the B area and D area, which are different access destinations, cannot be issued to the SDRAM 1104.
As described above, in the prior art, when the comparison result between the address of the write request issued by the image processing unit 1102 and the read request indicates that the current read request matches, the memory access control unit 1103 determines that the current read request is the SDRAM 1104 by the preceding write request. The subsequent request issued from the image processing unit 1102 must wait for the completion of processing of the preceding request even if it is not an access to the same address as the matching address. However, there is a problem that there is a limit in improving the latency of RAM access.

  Conventionally, even if the order of requests can be changed, handshake control is generated between the memory access control unit 1103 and the SDRAM controller 1105 every time a request is issued. It was difficult to reduce the problem.

  The first problem is to improve the latency when multiple requests are issued simultaneously. A second problem is to reduce overhead due to handshaking during memory access.

  In the following aspect, for example, at least one data processing device (image processing macro 1101) including a data processing unit (image processing unit 1102) that performs image processing and a memory access control unit (101), a memory element (SDRAM 1104), Data including a memory device including a memory controller (SDRAM controller 1105) that arbitrates read request information (110) or write request information (109) issued from the memory access control unit and controls access to the memory element A processing system is assumed.

  In the memory access control unit, a request management table unit (103), a read request output determination & latch unit (202), a write request reception determination & latch unit (201), and a table entry invalidation unit (204) are shown below. )including.

The request management table unit stores read request information or write request information requested from the data processing unit.
When the read request output determination & latch unit requests read request information from the data processing unit, it requests valid write request information indicating the same destination memory area as the destination memory area indicated by the read request information. When registered in the management table part, the read request information is accepted and registered in the request management table part in an unissued state, and the same destination memory area as the destination memory area indicated by the read request information is indicated When valid write request information is not registered in the request management table section, the read request information is issued to the memory controller in the memory device, and the read request information is registered in the request management table section.

  When the write request acceptance determination & latch unit requests write request information from the data processing unit, it requests valid read request information indicating the same destination memory area as the destination memory area indicated by the write request information. If it is not registered in the management table part, the write request information is registered in the request management table part.

  The table entry invalidation unit reads a memory write completion signal (RAM write completion signal 111) indicating the completion of a write access from the memory controller in the memory device to the memory device based on the write request information or a read access to the memory device based on the read request information. The read data reception signal (112) indicating completion of the read data is received, the read request information or the write request information registered in the request management table corresponding to the read data reception signal is invalidated or deleted, and the invalidation or When the deleted table entry is write request information, the table entry of the unissued read request information having the same destination memory area as the write request information is searched from the request management table section, and the searched table entry Issuing an instruction of the corresponding read request information to the read request output determination and latch unit.

  In the configuration of the above-described aspect, the write data buffer (104) for buffering the write data corresponding to the write request information and the write request information delivered from the write request acceptance determination & latch unit are held and held in the write data buffer. When the write data exceeds a predetermined amount, the held one or more pieces of write request information are collected and issued as one piece of write request information to the memory controller in the memory device, and in the write data buffer. A write request output determination unit that outputs the held write data to the memory controller, and the write request reception determination & latch unit receives the write request information when requested by the data processing unit. Information Is held in the request output determination unit may be configured so as to hold the write data corresponding to the write request information output from the data processing unit to the write data buffer.

  At this time, the write request output determination unit further collects one or more pieces of write request information held when the number of valid table entries registered in the request management table exceeds a predetermined amount. It can be configured to issue the request information to the memory controller in the memory device and to output the write data held in the write data buffer to the memory controller.

By changing the order of requests, it is possible to reduce the waiting time for accessing the memory of requests and improve the efficiency of memory access.
Also, by reducing the number of write requests executed to the memory, the bus occupancy rate due to memory handshake can be reduced. Therefore, it greatly contributes to the performance improvement during memory access.

Hereinafter, the best embodiment will be described in detail with reference to the drawings.
1 and 2 are system configuration diagrams of the present embodiment. This system is based on the system configuration shown in FIG. In FIG. 1, the same reference numerals as those in FIG. 11 realize the same operation as in FIG. In FIG. 1, the image bus 1109 shown in FIG. 11 is omitted. The memory access control unit 101 shown in FIG. 1 corresponds to the memory access control unit 1103 shown in FIG.

  In FIG. 1, a memory access control unit 1103 includes a request control unit 102 that processes a request from the image processing unit 1102, a request management table 103 that manages a request that requires waiting, and a write data buffer 104 that holds write data 107. Have

  FIG. 2 is a more detailed configuration diagram of FIG. The request control unit 102 in FIG. 2 determines whether or not to accept the write request 109 from the image processing unit 1102 and latches the write request reception determination and latch unit 201 for latching, and the write request 109 from the image processing unit 1102. A read request output determination & latch unit 202 for determining whether or not to accept and a write request 109 from the image processing unit 1102 are collected and issued to the SDRAM 1104 (actually the SDRAM controller 1105). A write request output determination unit 203 to perform, and a table entry that receives the RAM write completion signal 111 or the read data reception signal 112 from the SDRAM controller 1105 and invalidates the corresponding table entry in the request management table 103 And a Enabling portion 204.

FIG. 3 is a diagram showing an outline of the operation of this embodiment in the same case as the case of FIG. 12 in the description of the problems of the prior art. That is, consider a case where a plurality of requests are issued in the following order from the image processing unit 1102 to each destination RAM area indicated by A to D on the SDRAM 1104.

1) A write request is issued to area A.
2) A read request is issued to area A.
3) A read request is issued to the D area.
4) A write request is issued to area B.
5) A read request is issued to area B.

   In the present embodiment, when a write request 109 to the A area indicated by 1) above is issued to the SDRAM 1104, the access state is first held in the request management table 103. When the read request 110 shown in 2) above is issued for the same area A, the read request output determination & latch unit 202 in the request control unit 102 sends the read request 110 from the image processing unit 1102. Once accepted, by detecting that the access information to the A area of the write request 109 is held in the request management table 103, the read request 110 shown in 2) above is registered in the request management table 103. Wait for an unissued state. Then, the read request output determination & latch unit 202 and the write request reception determination & latch unit 201 perform the read request 110 or the above described 3) to 5) for different destination RAM areas D and B from the image processing unit 1102. The write request 109 or the like is accepted, and the read request 110 shown in 2) above is overtaken and issued to the SDRAM 1104.

  In this way, in this embodiment, the memory access control unit 101 accepts all the read requests 110 from the image processing unit 1102 and waits as necessary, thereby allowing the read request 110 to be waited for. Subsequently, since the read request 110 addressed to another destination RAM area requested to be issued by the image processing unit 1102 is issued after being accepted, the subsequent read request 110 is sent to the memory access control unit. It is possible to prevent the acceptance from being rejected in 101 and stay in the image processing unit 1102. The subsequent read request 110 addressed to the same destination RAM area as the preceding write request 109 can be controlled to be issued to the SDRAM 1104 in the order of requests in order to maintain data consistency.

FIG. 4 is a diagram illustrating a data configuration example of the request management table 103 for realizing the above-described operation.
In the valid field 401, a value for determining whether or not the management data of the table entry including the valid field 401 is valid is registered.

In the serial number field 402, a serial number indicating the order of issuing requests corresponding to the table entry including the serial number is registered.
In the destination RAM area field 403, bank address information indicating an access bank on the SDRAM 1104 of a request corresponding to the table entry including the address is registered.

  In the read / write distinction field 404, a value indicating the distinction between whether the request corresponding to the table entry including the read / write distinction field 404 is the read request 110 or the write request 109 is registered.

A plurality of table entries having the above-described configuration can be registered in the request management table 103.
Detailed operations of the present embodiment using the request management table 103 having the above data configuration example will be sequentially described below.

First, FIG. 5 is an operation flowchart showing an operation of the control executed by the read request output determination & latch unit 202 of FIG.
First, it is determined whether or not the read request 110 has been received from the image processing unit 1102 and waits (repetition processing in step S501).

  Here, when the read request 110 is received, the determination in step S501 is YES, and each of the read request address 106 corresponding to the received read request 110 and the request management table 103 is accessed. Based on the bank RAM write completion signal wait request presence / absence signal 205, the content of the destination RAM area field 403 is the same as the bank address accessed by the received read request 110, and the value of the valid field 401 is 1 (= valid). Whether or not a table entry in which the value of the read / write distinction field 404 indicates write is registered in the request management table 103, that is, a write request addressed to the same bank address that is incomplete and waiting for the RAM write completion signal 111 109 climbs Whether it is is determined (step S502).

  If the write request 109 addressed to the same bank address has not been registered (NO in step S502), the received read request 110 is issued to the SDRAM 1104 (step S503).

  The issued read request 110 is registered in an empty entry in the request management table 103 or an entry in which the value of the valid field 401 is 0 (= invalid). In this case, the valid field 401 has the value 1, the serial number has the maximum value in the table indicating the latest, the destination RAM area field 403 has the bank address indicated by the read request address 106, and the read / write distinction field 404 has the Each value indicating a lead is registered (step S504).

  If the write request 109 that has not been completed and is addressed to the same bank address is registered (NO in step S502), the read request output determination & latch unit 202 accepts the received read request 110 for the time being. Is held in an unissued state (step S505).

  Then, the accepted read request 110 is registered in an empty entry in the request management table 103 or an entry whose value of the valid field 401 is 0 (= invalid). In this case, the valid field 401 has the value 1, the serial number has the maximum value in the table indicating the latest, the destination RAM area field 403 has the bank address indicated by the read request address 106, and the read / write distinction field 404 has the Each value indicating a lead is registered (step S506).

After the process of step S504 or S506, the process returns to a state of waiting for reception of another read request 110 (step S504 or S506 → step S501).
Next, FIG. 6 is an operation flowchart showing the control executed by the write request acceptance determination & latch unit 201 of FIG.

First, it is determined whether or not the write request 109 has been received from the image processing unit 1102 and waits (repetition processing in step S601).
Here, when the write request 109 is received, the determination in step S601 becomes YES, and then each bank obtained by accessing the write request address 105 corresponding to the received write request 109 and the request management table 103 is obtained. Based on the read data reception wait request presence / absence signal 204, the contents of the destination RAM area field 403 are the same as the bank address accessed by the received write request 109 and the value of the valid field 401 is 1 (= valid). Whether or not a table entry in which the value of the write distinction field 404 indicates a read is registered in the request management table 103, that is, a read request 110 addressed to the same bank address that is incomplete and waiting for the read data reception signal 112 Registered Dolphin whether it is determined (step S602).

  If the read request 110 addressed to the same bank address is not registered (the determination in step S602 is NO), the received write request 109 is temporarily stored in the write request output determination unit 203 (step S603).

At the same time, the write data 107 received together with the received write request 109 is buffered in a rubber (step S604).
The received write request 109 is registered in an empty entry in the request management table 103 or an entry in which the value of the valid field 401 is 0 (= invalid). In this case, the valid field 401 has the value 1, the serial number has the maximum value in the table indicating the latest, the destination RAM area field 403 has the bank address indicated by the write request address 105, and the read / write distinction field 404 has the Each value indicating the write is registered (step S605).

  If the read request 110 that has not been completed and is addressed to the same bank address is registered (the determination in step S602 is NO), the write request acceptance determination & latch unit 201 has received the image processing unit 1102 The write request 109 is made to wait (step S606).

After the process of step S605 or S606, the process returns to the state of waiting for reception of another write request 109 (step S605 or S606 → step S601).
7 shows that the table entry invalidation unit 204 in the memory access control unit 101 completes the write access operation corresponding to the write request 109 issued to the SDRAM 1104 from the SDRAM controller 1105 (see FIG. 1). 5 is an operation flowchart showing a control operation when a RAM write completion signal 111 indicating a read data reception signal 112 indicating completion of a read access operation corresponding to a read request 110 issued to the SDRAM 1104 is received.

  First, it is determined whether or not the RAM write completion signal 111 has been received (step S701). If the RAM write completion signal 111 has not been received and the determination in step S701 is NO, it is next determined whether or not the read data reception signal 112 has been received (step S702). If the read data reception signal 112 is not received and the determination in step S702 is NO, the process returns to step S701 again.

  When the RAM write completion signal 111 is received in the reception standby state and the determination in step S701 is YES, the request management table 103 corresponding to the write access to one or more destination RAM areas indicated by the RAM write completion signal 111 is displayed. One or more deletion target table entries are searched (step S703). Specifically, the value of the valid field 401 is 1 (= valid), one bank address indicated by the RAM write completion signal 111 is registered in the destination RAM area field 403, and writing is performed in the read / write distinction field 404. The table entry in which the indicated value is registered is searched.

  As will be described later, the write request output determination unit 203 accumulates a plurality of write data 107 corresponding to the plurality of write requests 109 from the image processing unit 1102 in the write data buffer 104 to a predetermined amount, and the plurality of write requests 109. Are compiled into one write request 109 and issued to the SDRAM 1104. Therefore, the RAM write completion signal 111 may indicate the completion of write access to the plurality of destination RAM areas corresponding to the plurality of write requests 109. In step S703, one or more deletion target table entries registered in the request management table 103 corresponding to the one or more write accesses are searched, and one of them is selected.

  Next, the value of the valid field 401 of one retrieved table entry is set to 0 (= invalid) (step S704). As a result, the table entry is released and other requests can be registered.

Subsequently, the value of the valid field 401 is 1, the value of the destination RAM area field 403 is the same as the value of the destination RAM area field 403 of the deleted table entry, and the value of the read / write distinction field 404 indicates read. If the value of the serial number field 402 is the smallest (= the oldest), it is searched whether or not the table entry of the read request 110 waiting for the target write request 109 is registered in the request management table 103 (step) S705).

  If the corresponding table entry exists and the determination in step S705 is YES, the table entry invalidation unit 204 issues an instruction to issue an unissued read request 110 corresponding to the table entry, as a read request output determination & latch unit. 202 (step S706). As a result, the read request output determination & latch unit 202 issues the read request 110 to the SDRAM 1104.

  After the process of step S706 or when the determination in step S705 is NO, the process returns to the process of step S703, and another process corresponding to the write access to one or more destination RAM areas indicated by the received RAM write completion signal 111 is performed. A deletion target table entry is retrieved from the request management table 103.

  If the deletion target table entry corresponding to the received RAM write completion signal 111 is not retrieved from the request management table 103 by the repeated processing from step S703 to S706, and the determination in step S703 is NO, the processing in step S701 is performed. The process returns to a state of waiting for reception of another RAM write completion signal 111 or read data reception signal 112.

  On the other hand, when the read data reception signal 112 is received and the determination in step S702 is YES in the standby state by the repeated processing of step S701 and step S702, the request corresponding to the read access to the destination RAM area indicated by the read data reception signal 112 A deletion target table entry on the management table 103 is searched. Specifically, the value of the valid field 401 is 1 (= valid), the bank address indicated by the read data reception signal 112 is registered in the destination RAM area field 403, and the read / write distinction field 404 indicates read. The table entry in which is registered is searched. Then, the value of the valid field 401 of the retrieved table entry is set to 0 (= invalid) (step S707). As a result, the table entry is released and other requests can be registered.

FIG. 8 is a diagram showing a state transition example of the request management table 103 based on the operation flowcharts of FIGS.
Assume that a write request 109 has been issued to the A area that is the destination RAM area on the SDRAM 1104. In this case, in the request management table 103, as shown in FIG. 8A, the value of the valid field 401 is 1, the value of the serial number field 402 is 1, the value of the destination RAM area field 403 is the A area, read / A table entry in which the value of the write distinction field 404 is write (W) is registered. The state of this entry is a state where a request has been issued but has not been completed.

  In this state, when the read request 110 addressed to the A area is received, the incomplete write request 109 addressed to the same A area is registered in the request management table 103, so the determination in step S502 of FIG. Thus, after the read request 110 is accepted in an unissued state (step S505 in FIG. 5), the value of the valid field 401 is 1 in the request management table 103, as shown in FIG. A table entry in which the value of the field 402 is 2, the value of the destination RAM area field 403 is the A area, and the value of the read / write distinction field 404 is read (R) is registered (step S506 in FIG. 5).

  Subsequently, when the read request 110 addressed to the area B is received, as shown in FIG. 8A, since the request addressed to the same area B is not registered in the request management table 103, the steps in FIG. The determination in S502 is NO, and the read request 110 is issued to the SDRAM 1104 in advance of the read request 110 addressed to the unissued A area (step S503 in FIG. 5). As shown in FIG. 8B, the value of the valid field 401 is 1, the value of the serial number field 402 is 3, the value of the destination RAM area field 403 is B area, and the value of the read / write distinction field 404 is read (R ) Is registered (step S504 in FIG. 5).

  Thereafter, when the write access of the issued write request 109 addressed to the area A is completed and the memory access control unit 101 receives the RAM write completion signal 111 from the SDRAM controller 1105, the request management in the state of FIG. The value of the valid field 401 of the table entry whose destination RAM area is the A area on the table 103 is reduced to 0, and the entry is invalidated (step S704 in FIG. 7). Subsequently, the table entry of the read request 110 addressed to the same area A is searched on the request management table 103 in the state of FIG. 8B, and the read request 110 corresponding to the entry is issued to the SDRAM 1104 (FIG. 8). 7 step S706). As a result, the request management table 103 transitions to the state of FIG.

  As described above, waiting is performed for the subsequent read request 110 addressed to the area A where the preceding incomplete write request 109 exists, while the subsequent read request 110 addressed to the area B is the read request. Issued to SDRAM 1104 overtaking 110.

  Next, in this embodiment, since the latency of the read request 110 is long, the write request output determination unit 203 has a plurality of write requests 109 corresponding to the plurality of write requests 109 so that the read request 110 can easily obtain the access right of the SDRAM 1104. A set of write data 107 is buffered in the write data buffer 104, and after the amount of data has been stipulated, a write request 109 is issued to the SDRAM 1104 in one to control the number of write accesses.

  Conventionally, as shown in FIG. 9A, for each write request 109 (write 1, write 2, and write 3 in the figure) issued from the image processing unit (image core) 1102, issuance to the SDRAM 1104 is performed. It was done. As a result, as shown in the figure, for each write request 109, handshake control for establishing communication on arbitration between the memory access control unit 1103 (see FIG. 11) and the SDRAM controller 1105. And each request was issued. For this reason, handshake control is required for each write request 109 issued from the image processing unit 1102, and the image bus 1109 (see FIG. 11) is exclusively used each time, and other image processing macros 1101 cannot communicate with the SDRAM controller 1105. The period was long.

  In the present embodiment, as shown in FIG. 9B, the write request output determination unit 203 has a plurality of write requests 109 issued from the image processing unit (image core) 1102 (in the figure, write 1 and write 2). , Write 3) corresponding to the write 3) is stored in the write data buffer 104, and the buffer amount reaches a specified amount or valid in the request management table 103 (the value of the valid field 401 is 1). When the number of requests held reaches the limit number, the write requests 109 are combined into one write request 109, which is issued to the SDRAM 1104 and stored in the write data buffer 104. The write data 107 is output to the image bus 1109 (see FIG. 11).As a result, since the handshake process exchanged between the write request output determination unit 203 and the SDRAM controller 1105 is only once as shown in FIG. 9B, the image bus 1109 is exclusively used for a period of time. As a result, the latency of the write request 109 is improved.

FIG. 10 is an operation flowchart illustrating a control process of the write request output determination unit 203 of FIG. 2 for realizing the above-described control of the write request 109.
First, it is determined whether or not the buffer amount of the write data buffer 104 has reached a specified amount (step S1001).

  If this determination is NO, the number of requests held for which the value of the valid field 401 in the request management table 103 is 1 (= valid) based on the table full detection signal 206 from the request management table 103 is further limited. It is determined whether or not the number has been reached (step S1002).

If this determination is also NO, processing returns to step S1001 and the same processing as described above is repeated.
When the buffer amount of the write data buffer 104 reaches the specified amount and the determination in step S1001 is YES, or the number of valid requests held in the request management table 103 reaches the limit number and the determination in step S1002 is YES. In this case, the write request output determination unit 203 collects the stored write requests 109 into one write request 109 and issues it to the SDRAM 1104 (step S1003).

  Then, the write request output determination unit 203 issues a data output instruction 207 to the write data buffer 104, and outputs the write data 107 staying there to the image bus 1109 (see FIG. 11).

Thereafter, the process returns to step S1001 to return to the monitoring state of the buffer amount and the request amount.
In the embodiment described above, the bank addresses on the SDRAM 1104 designated by the read request address 106 or the write request address 105 are compared with each other in the address unit other than the bank address in the determination of request waiting or overtaking issuance. A comparison may be made.

  Further, when a write request 109 addressed to a certain destination RAM area remains in the write data buffer 104, a subsequent read request 110 addressed to the same destination RAM area is requested from the image processing unit 1102 to the memory access control unit 101. In this case, the memory access control unit 101 returns the write data 107 retained in the write data buffer 104 in the memory access control unit 101 to the image processing unit 1102 without waiting for the read request 110. Such control may be implemented.

  Further, the write request 109 compiled by the write request output determination unit 203 is generally a request for different destination RAM areas, but the write request 109 is continuously issued to the same destination RAM area (bank address). A configuration in which they are buffered may be employed.

In addition, when a write request 109 is requested from the image processing unit 1102, the write request acceptance determination & latch unit 201 receives a previous uncompleted read request addressed to the same destination RAM area as the destination RAM area specified by the write request. If it exists in the request management table 103, the image processing unit 1102 is controlled to wait for the write request 109 (step S606 in FIG. 6), but the write request 109 is first received in an unissued state. Control such as buffering the write data 107 corresponding to the write data 107 in the write data buffer 104 may be performed. In this case, for example, the write request output determination unit 203 performs control to output only the write data 107 for which an issue instruction has been issued from the write data buffer 104 when issuing the write request 109 as a single request. To do.

  An embodiment of a system in which a data processing apparatus other than the image processing macro 1101 that performs image processing accesses the SDRAM 1104 may be applied.

It is a system configuration figure of this embodiment. It is a more detailed system configuration diagram of the present embodiment. It is a figure which shows the operation | movement outline | summary of this embodiment. 4 is a diagram illustrating an example of a data configuration of a request management table 103. FIG. 5 is an operation flowchart showing an operation of control executed by a read request output determination & latch unit 202. 5 is an operation flowchart showing an operation of control executed by a write request acceptance determination & latch unit 201. 5 is an operation flowchart showing a control operation when receiving a RAM write completion signal 111 or a read data reception signal 112. It is a figure which shows the example of a state transition of the request management table 103 in this embodiment. It is explanatory drawing of buffering control of the write data. 5 is an operation flowchart illustrating a control process of a write request output determination unit 203. It is a figure showing an example of composition of a system carrying an image processing macro. It is explanatory drawing of the problem of a prior art.

Explanation of symbols

101 Memory access control unit 102 Request control unit 103 Request management table 104 Write data buffer 105 Write request address 106 Read request address 107 Write data 108 Read data 109 Write request 110 Read request 111 RAM write completion signal 112 Read data reception signal 201 Write request Acceptance determination & latch unit 202 Read request output determination & latch unit 203 Write request output determination unit 204 Read data reception wait request presence / absence signal of each bank 205 RAM write completion signal wait request presence / absence signal of each bank 206 Table full detection signal 207 Data output Instruction 208 Table entry invalidation section 401 Valid field 402 Serial number field 403 Destination RAM area field 404 Read / write distinction field 1101 Image processing macro 1102 Image processing unit 1103 Memory access control unit 1104 SDRAM 1104
1105 SDRAM controller 1106 CPU macro 1107 Card interface macro 1108 Peripheral macro 1109 Image bus 1110 System bus

Claims (7)

Control at least one data processing device including a data processing unit and a memory access control unit, and read access information or write request information issued from the memory device and the memory access control unit to control access to the memory device In a data processing system including a memory device including a memory controller,
In the memory access control unit,
A request management table unit for storing the read request information or the write request information requested from the data processing unit;
When the read request information is requested from the data processing unit, valid write request information indicating the same destination memory area as the destination memory area indicated by the read request information is registered in the request management table unit. Valid read request information in which the read request information is received and registered in the request management table portion in an unissued state, and the same destination memory area as the destination memory area indicated by the read request information is indicated Is not registered in the request management table part, the read request information is issued to the memory controller in the memory device, and the read request information is registered in the request management table part. & Latch part,
When the write request information is requested from the data processing unit, valid read request information indicating the same destination memory area as the destination memory area indicated by the write request information is registered in the request management table unit. A write request reception determination & latch unit for registering the write request information in the request management table unit,
A memory write completion signal indicating completion of write access to the memory device by the write request information from a memory controller in the memory device or a read data reception signal indicating completion of read access to the memory device by the read request information; The read request information or the write request information registered in the request management table unit corresponding to the read data reception signal is invalidated or deleted, and the invalidated or deleted table entry is the write request information. If the request management table part is searched for a table entry of unissued read request information having the same destination memory area as the write request information, an issue instruction of the read request information corresponding to the retrieved table entry is retrieved. And table entry invalidation unit which performs relative to the read request output determining & latch unit,
A memory access control circuit comprising: A write data buffer for buffering write data corresponding to the write request information;
The write request acceptance determination & latch unit holds the write request information, and when the write data held in the write data buffer exceeds a predetermined amount, the held one or more writes Write request output judgment that collects request information and issues it as one write request information to the memory controller in the memory device and outputs the write data held in the write data buffer to the memory controller And
Further including
The write request acceptance determination & latch unit holds the write request information in the write request output determination unit when the write request information is requested from the data processing unit, and corresponds to the write request information. Holding the write data output from the data processing unit in the write data buffer;
The memory access control circuit according to claim 1. The write request output determination unit further collects the held one or more write request information when the number of valid table entries registered in the request management table exceeds a predetermined amount. Issuing to the memory controller in the memory device as request information, and outputting the write data held in the write data buffer to the memory controller,
The memory access control circuit according to claim 1, wherein the memory access control circuit is a memory access control circuit. The data processing unit executes image processing;
The memory access control circuit according to claim 1, wherein the memory access control circuit is a memory access control circuit. Control at least one data processing device including a data processing unit and a memory access control unit, and read access information or write request information issued from the memory device and the memory access control unit to control access to the memory device A memory access control method in a data processing system including a memory device including a memory controller,
When the read request information is requested from the data processing unit, valid write request information indicating the same destination memory area as the destination memory area indicated by the read request information is registered in the request management table unit. If the read request information is received and registered in the request management table section in an unissued state, valid write request information indicating the same destination memory area as the destination memory area indicated by the read request information is present. When not registered in the request management table unit, the read request information is issued to the memory controller in the memory device, and the read request information is registered in the request management table unit. A latch step;
When the write request information is requested from the data processing unit, valid read request information indicating the same destination memory area as the destination memory area indicated by the write request information is registered in the request management table unit. If not, a write request acceptance determination & latch step for registering the write request information in the request management table unit;
A memory write completion signal indicating completion of write access to the memory device by the write request information from a memory controller in the memory device or a read data reception signal indicating completion of read access to the memory device by the read request information; The read request information or the write request information registered in the request management table unit corresponding to the read data reception signal is invalidated or deleted, and the invalidated or deleted table entry is the write request information. If the request management table part is searched for a table entry of unissued read request information having the same destination memory area as the write request information, an issue instruction of the read request information corresponding to the retrieved table entry is retrieved. And table entries invalidated step of performing,
A read request information issuing step for issuing the read request information instructed to issue;
A memory access control method comprising: The write request acceptance determination & latch step includes a valid read request in which the same destination memory area as the destination memory area indicated by the write request information is indicated when the write request information is requested from the data processing unit. When the information is not registered in the request management table unit, the write request information is held, the write data output from the data processing unit corresponding to the write request information is held in the write data buffer,
When the write data held in the write data buffer exceeds a predetermined amount, one or more write request information held by the write request acceptance determination & latch step is collected as one write request information. A write request output determination step for issuing to the memory controller in the memory device and outputting the write data held in the write data buffer to the memory controller;
6. The memory access control method according to claim 5, wherein: The write request output determination step further includes one or more write requests held by the write request reception determination & latch step when the number of valid table entries registered in the request management table exceeds a predetermined amount. The request information is collected and issued as one write request information to the memory controller in the memory device, and the write data held in the write data buffer is output to the memory controller.
The memory access control circuit according to claim 5, wherein the memory access control circuit is a memory access control circuit.

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