JP2010057032A - Digital broadcast receiver, digital broadcast receiving method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital broadcast receiver which reduces circuit scale and manufacturing costs. <P>SOLUTION: A digital broadcast receiver includes: a first tuner for receiving a first transport stream including video data of a first program; a second tuner for receiving a second transport stream including video data of a second program; a demultiplexer 14 shared by the first and second tuners 11 and 12, for extracting video data from the first and second transport streams received by the first and second tuners 11 and 12; and a processing order determining circuit 13 for sequentially determining the first or second transport stream to be processed by the demultiplexer circuit 14 in accordance with the first and second transport streams received by the first and second tuners 11 and 12. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a digital broadcast receiving apparatus, a digital broadcast receiving method for receiving a digital broadcast transferred from a terrestrial digital broadcast, a BS / CS broadcast satellite, a communication satellite or the like, and a program for causing a computer to execute the digital broadcast. The present invention relates to a digital broadcast receiving apparatus, a digital broadcast receiving method, and a program for causing a computer to execute the same.

  In digital broadcasting, the number of channels that can be selected is increased compared to conventional analog broadcasting due to the realization of multi-channel broadcasting. A user selects a program by operating a button on a remote controller of the digital broadcast receiving apparatus. However, as the number of channels increases, this program selection takes time, and the operation tends to be complicated. Therefore, a function of enabling a viewer to quickly select a program to be viewed by displaying a plurality of programs currently being received by the receiving apparatus on the same screen and selecting a program to be viewed from among them. Realization is required.

  For example, Patent Literature discloses an apparatus having a function of displaying a plurality of programs on the same screen (paragraphs 0013 to 0021). FIG. 13 is a block diagram showing a configuration of the apparatus disclosed in Patent Document 1. As shown in FIG. This apparatus includes tuners 111, 112, and 113 and transport decoders 114, 115, and 116 that decode TS packets received by the tuner.

  The received MPEG-2 (Moving Picture Expert Group-2) transport stream (hereinafter also referred to as TS packet) is input to tuners 111, 112, and 113 for each channel. The TS packet input to the tuner 111 is input to the transport decoder 114. The transport decoder 114 extracts a video stream, an audio stream, broadcast data, program arrangement information, and the like designated for each program from the received TS packet.

  The video stream received by the tuner 111 is decoded into a video signal by the video decoder 108 and stored in the memory 124 for each frame. The audio stream received by the tuner 111 is decoded into an audio signal by the audio decoder 119 and output as sound from the speaker 121.

  When two programs are received simultaneously, TS packets of other programs are received from the tuner 112 simultaneously with the tuner 111. Similarly, the TS packet received by the tuner 112 is stored in the memory 123 via the transport decoder 115 and the video decoder 109. The video signal of the channel received by the tuner 111 and the video signal received by the tuner 112 are combined by the combining processor 122 and displayed on the display unit 125. As the audio data, the sound of one of the programs is selected by the user's operation and output from the speaker 121.

  The data broadcast is a broadcast program repeatedly transmitted from a broadcast station by the DSM-CC data carousel method defined in ISO / IED 13818-6, and is received by the tuner 113. In this program broadcast, a data stream is extracted by the transport decoder 116 and sent to the control unit 118. The data stream includes text information, script information, image information, and video / audio information.

  These data are interpreted and executed by the control unit 118, and character, graphic, and image information are generated by the graphic generation unit 120 and displayed on the display unit 125 through the synthesis processor 122. The audio information is output from the speaker 121 through a sound generation unit (not shown).

  FIG. 14 shows the structure of software that operates in the control unit disclosed in Patent Document 1. The data broadcast browser is an application that runs on the OS. From the application, the graphic generation unit is controlled via the graphic library 141 and the graphic driver 142, and characters, graphics, images, and the like are stored in the graphic buffer included in the synthesis processor 122. Delineate.

  Further, the compositing processor 122 is controlled through the window control middleware and the screen compositing unit driver, and the compositing process of the video, the still image, and the character / figure sent from the video decoders 108 and 109 through the memories 123 and 124 is controlled. .

The operation of the data broadcasting browser is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-104518.
JP 2003-101900 A JP 2004-104518 A

  However, in the apparatus described in Patent Document 1, in order to simultaneously display a plurality of received programs, it is necessary to prepare as many demultiplexers as the number of tuners for extracting data from received TS packets. Therefore, the conventional digital broadcast receiving apparatus has a problem that the circuit scale and cost are large.

  One aspect of the receiving apparatus according to the present invention is a first tuner that receives a first transport stream including video data of a first program, and a second tuner that receives a second transport stream including video data of a second program. A demultiplexer for extracting the video data from the first and second transport streams shared by the first and second tuners and received by the first and second tuners, respectively; A processing order determining circuit for sequentially determining the first or second transport stream to be processed by the demultiplexer according to the first and second transport streams received by the first and second tuners; , Provided.

  In this way, by providing a processing order determination circuit that sequentially determines the first or second transport stream to be processed by the demultiplexer, two or more first tuners and second tuners can share one demultiplexer. it can.

  According to one aspect of the digital broadcast receiving apparatus according to the present invention, the circuit scale and manufacturing cost can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing an example of the overall configuration of a digital broadcast receiving apparatus according to the first embodiment of the present invention. The two-way digital receiver receives a first tuner 11 that receives a first transport stream packet (hereinafter referred to as a TS packet) including data of a first program, and a second TS packet that includes data of a second program. A demultiplexer circuit 14 for extracting data from the first and second TS packets shared by the second tuner 12 and the first and second tuners 11, 12 and received by the first and second tuners 11, 12; In accordance with the first and second TS packets received by the first and second tuners 11 and 12, a processing order determining circuit 13 that sequentially determines the first or second TS packet processed by the demultiplexer circuit 14 is provided.

  In the description, the TS packet received by the first tuner 11 is referred to as a first TS packet, and the TS packet received by the second tuner 12 is illustrated as a second TS packet.

  The first tuner 11 and the second tuner 12 receive digital broadcasts distributed from terrestrial digital broadcast satellites, BS / CS broadcast satellites, and communication satellites. The first tuner 11 and the second tuner 12 sequentially receive TS packets including video data of a program of an arbitrary channel selected by a user or the like from a plurality of channels. TS packets received by the tuners 11 and 12 are held in a temporary buffer described later.

  The demultiplexer circuit 14 performs processing such as analysis, separation, and synchronization of the TS packet input from the processing order determination circuit 13. The demultiplexer circuit 14 outputs the first TS packet received by the first tuner 11 to the first video decoder 15, and outputs the second TS packet received by the second tuner 12 to the second video decoder 16.

  The processing order determination circuit 13 is arranged between the tuners 11 and 12 and the demultiplexer circuit 14 and determines the processing order of the first TS packet and the second TS packet held in the temporary buffer. The processing order determination circuit 13 outputs the first TS packet or the second TS packet to the demultiplexer circuit 14 according to this order. In the present embodiment, since one demultiplexer circuit 14 needs to process the first TS packet and the second TS packet received from the two tuners 11 and 12, the processing order determination circuit 13 sequentially determines the processing order. Thus, the first TS packet or the second TS packet is output to the demultiplexer circuit 14. The demultiplexer circuit 14 is supplied with TS packets from the processing order determination circuit 13 in accordance with the processing order determined by the processing order determination circuit 13.

  The first video decoder 15 and the second video decoder 16 decode the video data extracted by the demultiplexer circuit 14 into a video signal. The first video decoder 15 and the second video decoder 16 correspond to the first tuner 11 and the second tuner 12, respectively. The first video decoder 15 decodes the video data included in the first TS packet into a video signal and outputs it to the image synthesis circuit. The second video decoder 16 decodes the video data included in the second TS packet into a video signal and outputs it to the image synthesis circuit.

  The video data decoded by the first video decoder 15 and the second video decoder 16 are combined so that a plurality of contents can be displayed on one screen by an image combining circuit and displayed on a monitor. For example, the image synthesis circuit synthesizes the video signal received by the first tuner 11 and the video signal received by the second tuner 12 and displays them on one screen.

  The audio data decoded by the audio decoder 17 is D / A (Digital To Analog) converted and output to a speaker. When the received video signal or audio signal is recorded, the demultiplexer circuit 14 sends the TS packet data to the record buffer, so that a storage device (HDD (Hard Disk Drive), DVD (Digital Versatile Disc) is used. Etc.).

  Here, in addition to program data, a program reference clock PCR indicating a clock on the transmission side is inserted into the TS packet sent from the transmission side. The digital broadcast receiving apparatus refers to the program reference clock PCR to synchronize the internal clock with the clock on the transmission side. This is because if the number of frames transmitted from the transmission side is different from the number of frames per time processed on the reception side, data deficiency will occur. Therefore, the digital broadcast receiving apparatus is provided with a first system time clock (STC) 18 and a second system time clock (STC) 19 to synchronize the clock on the transmitting side and the clock on the receiving apparatus side.

  The first system time clock (STC) 18 is supplied to the first video decoder 15 and the audio decoder 17 by controlling the pulse width modulation circuit (PWM) 24 with reference to the program reference clock PCR included in the first TS packet. The first clock 22 is synchronized with the program reference clock PCR of the first program. Similarly, the second system time clock (STC) 19 refers to the program reference clock PCR included in the second TS packet and controls the pulse width modulation circuit (PWM) 24 to thereby control the second video decoder 16 and the audio decoder 17. Is synchronized with the program reference clock PCR of the second program.

  Two pulse width modulation circuits 24 and two oscillators 25 are provided so as to correspond to the first tuner 11 and the second tuner 12, respectively. The pulse width modulation circuit 24 provided for the first tuner 11 generates a control signal whose duty ratio is adjusted by the first system time clock 18 and outputs the control signal to the oscillator 25 provided for the first tuner. As a result, the first clock 22 is generated from the oscillator 25. Similarly, the pulse width modulation circuit 24 provided for the second tuner 12 generates a control signal whose duty ratio is adjusted by the second system time clock 19 and outputs the control signal to the oscillator 25 provided for the second tuner. To do. As a result, the second clock 23 is generated from the oscillator 25. In the drawing, the two pulse width modulation circuits 24 and the oscillator 25 are omitted.

  The first counter 20 and the second counter 21 count the number of clocks of the first clock 22 and the second clock 23, respectively, and output them to the processing order determination circuit 13. The count values counted by the first counter 20 and the second counter 21 are used when the processing order determination circuit 13 determines processing packets as will be described later.

  FIG. 2 is a block diagram showing a configuration of a processing order determination circuit included in the digital broadcast receiving apparatus according to the first embodiment of the present invention. The processing order determination circuit 13 includes a first buffer 26, a second buffer 27, and a processing packet determination circuit 28. TS packets input from the first tuner 11 and the second tuner 12 are stored in a temporary buffer prepared for each tuner. The first TS packets received by the first tuner 11 are sequentially stored in the first buffer 26, and the second TS packets received by the second tuner 12 are sequentially stored in the second buffer 27. At this time, the processing order determination circuit 13 imprints the count values of the first counter 20 and the second counter 21 connected to the tuners 11 and 12 as time stamps in the TS packet.

  The processing order determination circuit 13 imprints the count value of the first counter 20 on the first TS packet received from the first tuner 11 as the first time stamp, and then stores the first TS packet in the first buffer 26. . Similarly, the processing order determination circuit 13 imprints the count value of the second counter 21 as the second time stamp in the second TS packet, and stores the second TS packet in the second buffer 27.

  The reason why TS packets input from the first tuner 11 and the second tuner 12 are not held together in one buffer is to simplify the management of the memory. For example, when viewing of the program B is stopped while simultaneously viewing the program A and the program B, the TS packet data of the program B is unnecessary data, so the memory used for holding the TS packet of the program B It is sufficient to release the area, but in the situation where TS packets of program A and TS packets of program B are distributed and mixed, it is complicated to release only the memory area holding the TS packet of program B. Memory management is required.

  On the other hand, by preparing the first buffer 26 for the program A and the second buffer 27 separately for the program B, the memory can be easily released without requiring the complicated memory management function described above. be able to.

  The processing packet determination circuit 28 is configured to determine a TS packet to be processed by the subsequent demultiplexer circuit 14 based on the first TS packet and the second TS packet stored in the first buffer 26 and the second buffer 27. Yes.

  Next, the processing packet determination method of the processing packet determination circuit 28 will be described. TS packets input from the first tuner 11 and the second tuner 12 may have different bit rates between the first tuner 11 and the second tuner 12. In such a case, it is necessary to preferentially process the TS packet with the higher bit rate out of the first TS packet and the second TS packet. In other words, it is necessary to preferentially process the shorter transfer interval per TS packet.

  If processing of TS packets with a short transfer interval is postponed after processing of TS packets with a long transfer interval is delayed, processing of the TS packets with a short transfer interval is awaited by the demultiplexer circuit 14, so that each decoder sends the intention of the transmission side to each decoder. This is because there is a possibility that data will not be sent at the intervals and the image and sound will be disturbed.

  Therefore, in order to supply data to each decoder at the intended interval on the transmission side, the processing packet determination circuit 28 adjusts the order of the TS packets so that TS packets with a short transfer interval are preferentially output to the demultiplexer circuit 14. is doing. Specifically, the processing packet determination circuit 28 calculates the transfer rate per packet of the first TS packet received by the first tuner and the transfer rate per packet of the second TS packet received by the second tuner. Based on the ratio, TS packets to be processed by the demultiplexer circuit 14 are determined. The specific procedure will be described below.

  FIG. 3 is a flowchart showing a procedure until a processing packet is determined. FIG. 4 shows the transfer intervals of the first TS packet and the second TS packet used when determining the processing packet.

As shown in FIG. 3, first, sampling is performed to obtain the transfer interval between the first TS packet and the second TS packet. Here, the transfer interval of the first TS packet and the second TS packet indicates a time interval from the start of reception of the previous TS packet to the start of reception of the next TS packet. The processing packet determination circuit 28 refers to the time stamp added to the received TS packet, and acquires the count values of the first counter 20 and the second counter 21 when sampling is started (step S1). This count value is the count value of the first counter 20 and the second counter 21 stamped in the TS packet. The obtained count values of the first counter 20 and the second counter 21 at the start of sampling are set as a first start count value V _1START and a second start count value V _2START , respectively.

The first tuner 11 and the second tuner 12 sequentially receive TS packets during this sampling period T _S. Each time a TS packet is received, the processing packet determination circuit 28 refers to the time stamp imprinted on the TS packet, and determines the time stamp of the received TS packet and the time stamp of the next received TS packet. To obtain the TS packet transfer interval (step S2).

The process of acquiring the transfer interval is repeated until a preset number of transfer intervals can be acquired (step S3). Here, for the sake of explanation, the number of transfer intervals for sampling is assumed to be three. As shown in FIG. 4, the transfer intervals of the first TS packets received by the first tuner 11 are set as transfer intervals P ₁₁ , P ₁₂ , and P ₁₃ in time series order. Similarly, the transfer intervals of the second TS packets received by the second tuner 12 are set as transfer intervals P ₂₁ , P ₂₂ , and P _{23 in} chronological order.

Returning to FIG. 3, the average value of the transfer intervals of the acquired first TS packet and second TS packet is calculated (step S4). Referring to FIG. 4 as an example, P _1AVE that is the average transfer interval of the first TS packets is (P ₁₁ + P ₁₂ + P ₁₃ ) / 3, and P _2AVE is (P ₂₁ + P ₂₂ + P ₂₃ ) / 3. .

Next, when the preset sampling period T _S expires, the count values of the first counter 20 and the second counter 21 are acquired (step S5). Here, the count values at the end of the sampling are set as a first end count value V _1END and a second end count value V _2END , respectively (FIG. 4).

Here, the processing packet determination circuit 28 determines the packet processing order by comparing P _1AVE and P _2AVE obtained in step S4, but cannot compare them as they are. This is because the frequency of the first counter 20 and the second counter 21 used for time stamping may be different. For example, when the average transfer interval acquired in step S4 is P _1AVE = 10 and P _2AVE = 15, if P _1AVE and P _2AVE are simply compared, the transfer interval per 1 TS packet is shorter for the first TS packet. Conceivable.

However, as shown in FIG. 5, the ratio of the frequency _{C 2} frequencies _{C 1} and the second counter 21 of the first counter 20 is 1: At 2, P _{1AVE_2} representing the P _1AVE count value of the second counter 21 , P _{1AVE_2} = 20. In practice, the second TS packet has a shorter transfer interval than the first TS packet.

Therefore, in order to compare the P _1AVE and P _2AVE, the obtained P _1AVE and P _2AVE, it must be expressed in terms of the common clock frequency to be a reference. In addition, what expressed _P1AVE with the count value of the 2nd counter 21 is set as transfer interval _{P1AVE_2,} and what expressed _P2AVE with the count value of the 1st counter 20 is shown as transfer interval _{P2AVE_1} .

As shown in FIG. 5, the sampling period T _S is common to both the first tuner 11 and the second tuner 12, and the frequency C ₁ of the first clock and the frequency C ₂ of the second clock are used as shown in Equation 1. Can show.

(Expression 1) T _S = (V _1END −V _{1 START} ) / C ₁ = (V _2END −V _{2 START} ) / C ₂
Here, _assuming that the ratio of the frequency of the first clock and the second clock is R _C1toC2 , R _C1toC2 can be expressed as Equation 2.

(Equation _{2) R C1toC2 = C 1 /} C 2 = (V 1END -V 1START) / (V 2END -V 2START)
R _C1toC2 is obtained by _substituting the first start clock V _1END , the first end clock V _1START , the second start clock V _2END , and the second end clock V _2START acquired in Steps S1 and S5 into Equation 2, respectively. be able to.

Returning to FIG. 3, in step S6, the first start clock V _1END , the first end clock V _1START , the second start clock V _2END , and the second end clock V _2START acquired in steps S1 and S5 are added to the above equation 2. R _C1toC2 is calculated by substituting.

Next, using R _C1toC2 obtained in step S6, among the average transfer intervals obtained in step S4, the average transfer interval counted by the counter having the lower frequency is changed to the value counted by the counter having the higher frequency. Convert.

R _C1toC2 ≧ 1, that is, when the first clock frequency C1 is greater than the frequency C2 of the second clock, using equation 3, and calculates the P _{2AVE_1} expressing the P _2AVE by the count value of the first counter 20 .

(Formula 3) P _{2AVE_1} = P _2AVE × R _C1toC2
Here, P _{2AVE_1} indicates an average value of the transfer intervals of the second TS packets received by the second tuner obtained when the time stamp is _imprinted using the first counter instead of the second counter.

For R _C1toC2 <1, that is, when the frequency C2 of the second clock is larger than the frequency C1 of the first clock, using Equation 4, the P _{1AVE_2} expressing the P _1AVE count value of the second counter 21 calculate.

(Formula 4) P _{1AVE_2} = P _1AVE / R _C1toC2
Thereby, it is possible to compare average transfer intervals expressed by a common frequency.

In step S6 shown in FIG. 3, a TS packet to be processed by the demultiplexer circuit 14 is determined based on the TS packet transfer interval calculated in step S5. Subsequently, in step S6, described average transfer interval P _1AVE (P _{1AVE_2)} and method for determining the processed packet corresponding to the average transfer interval P _2AVE of the 2TS packet (P _{2AVE_1)} of the 1TS packet. For the sake of explanation in the following, the P _1AVE or P _{1AVE_2,} simply indicated as P _1AVE, simply referred as P _2AVE the P _2AVE or P _{2AVE_1.}

FIG. 6 is a conceptual diagram showing a procedure in which the processing packet determination circuit 28 determines a processing packet based on P _{1AVE and} P _2AVE expressed by a common counter frequency. The upper part shows the first TS packet and the second TS packet that have arrived, and the lower part shows the processing packet determined by the processing packet determination circuit 28. The numbers in the figure are count values expressed by a common counter frequency. Diagonal lines and dots indicate that each TS packet has reached the count value. In Figure 6, P _1AVE of the 1TS packet is 3, P _2AVE of the 2TS packet is 4.

  The processing packet determination circuit 28 is configured so that the first TS packet and the second TS packet that are sequentially received from the left side to the right side of the paper surface are arranged as shown in the lower part of the paper surface and output to the subsequent demultiplexer circuit 14. Has been.

  Specifically, after the first TS packet having the count value 3 that has reached first is processed, the second TS packet having the count value 4 that has arrived next is processed. Then, the first TS packet having the count value 6 that has arrived thereafter is processed. In addition, when the first TS packet and the second TS packet arrive at the same time as in the count value 12, the first TS packet with a small transfer interval is preferentially processed, and then the second TS packet that has reached the count value 12 Process.

In order to cause the computer to execute the process of assigning the first TS packet and the second TS packet that have arrived in this way as processing packets, the addition average transfer interval P _{1AVE_ADD} and the addition average transfer interval P _{2AVE_ADD} for each of the first TS packet and the second TS packet. Is calculated.

FIG. 7 shows P _{1AVE_ADD} and P _{2AVE_ADD in} parentheses. Here, the addition average transfer interval P _{AVE_ADD} is a value obtained by adding P _AVE every time a TS packet is processed. P _{1AVE_ADD} of the first TS packet is a value obtained by adding the value of P _1AVE every time one first TS packet is processed. Similarly, the addition average transfer interval P _{2AVE_ADD} of the second TS packet is a value obtained by adding the value of P _2AVE of the second TS packet every time one second TS packet is processed.

In detail according to FIG. 7, the first 1TS packet count value 3 are processed, it is added to P _1AVE = 3 to P _{1AVE_ADD,} P _{1AVE_ADD} is 3 at the next count value 4 for the count value 3 . Similarly, when the first 1TS packet count value 6 is processed, the P _{1AVE_ADD} = 3 which has been held by the count value 6, that P _1AVE is added, P _{1AVE_ADD} count value 7 is 6. The processing packet is determined by comparing the values of P _{1AVE_ADD} of the first TS packet and P _{2AVE_ADD} of the second TS packet added in this way.

Specifically, a processing packet is determined according to procedures 1 and 2. In (Step 1) First, to compare the magnitude of P _{2AVE_ADD} of P _{1AVE_ADD} and the 2TS packets of the 1TS packet, determines that the packet to be next processed the TS packets of smaller value. (Step 2) In addition, if P _{1AVE_ADD} and P _{2AVE_ADD} of the 2TS packet of the 1TS packet are equal, determines the packet to be processed next by the magnitude comparison of P _1AVE and P _2AVE. The processing packet determination circuit 28 determines that a packet having a smaller value as a result of the size comparison is a packet to be processed next.

When the TS packets determined by the (Step 1) or (Step 2) is treated, processed packet determination circuit 28 adds the average transfer interval of the processed TS packets P _{AVE_ADD.} If processed packet is a first 1TS packet, it adds the P _1AVE of the 1TS packet P _{1AVE_ADD} of the 1TS packet. Similarly Accordingly, TS packets have been processed if the first 2TS packet, adds the P _2AVE of the 2TS packet P _{2AVE_ADD} of the 2TS packet. Then, P _{1AVE_ADD} and P _{2AVE_ADD} are compared again, and the processing packet determination by this size comparison and the process of adding the average transfer interval after the processing packet determination are repeated. Procedures 1 and 2 will be described using specific examples with reference to FIGS.

FIG. 8 is a diagram showing a procedure for determining a processing packet when P _1AVE <P _2AVE . FIG. 9 is a diagram showing a procedure for determining a processing packet when P _1AVE > P _2AVE . is a diagram showing a determination procedure of processing packet when the average transfer interval P _1AVE = average transfer interval P _2AVE.

As shown in FIG. 8, by the procedure 1 (first round), it compares the P _{1AVE_ADD} of the 1TS packet, the P _{2AVE_ADD} of the 2TS packet. P _{1AVE_ADD} and P _{2AVE_ADD} of the 2TS packet of the 1TS packet, since both are 0, the procedure 2 compares the P _1AVE and P _2AVE. Since there with _{P 1AVE = 3, P 2AVE =} 4, towards the P _1AVE of the 1TS packet is smaller P _2AVE of the 2TS packet. Therefore, the processing packet determination circuit 28 causes the demultiplexer circuit 14 to process the first TS packet received by the first tuner 11. Then, P _1AVE = _ADD is added to P _{1AVE_ADD} = 0, and the first round is completed.

The (second round) Step 1 compares the P _{1AVE_ADD} of the 1TS packet, the P _{2AVE_ADD} of the 2TS packet. Here, P _{1AVE_ADD} = 3 of the 1TS packet, since a P _{2AVE_ADD} = 0 of the 2TS packet, towards the P _{2AVE_ADD} of the 2TS packet is smaller than P _{1AVE_ADD} of the 1TS packet. Therefore, the second TS packet received by the second tuner 12 is processed. Then, P _2AVE of the processed second TS packet is added to P _{2AVE_ADD} . Thereafter, the same processing as described above is repeated.

FIG. 9 is a diagram showing a procedure for determining a processing packet when P _1AVE > P _2AVE .

(First round): the step 1 is compared with P _{1AVE_ADD} of the 1TS packet, the P _{2AVE_ADD} of the 2TS packet. P _{1AVE_ADD} and P _{2AVE_ADD} of the 2TS packet of the 1TS packet, since both are 0, the procedure 2 compares the P _1AVE and P _2AVE. Since P _1AVE = 5 and P _2AVE = 2, the second TS packet is processed. Then, the P _{2AVE_ADD} of the 2TS packet, adds the P _2AVE of the 2TS packet.

(Second round): by the procedure 1 compares the P _{1AVE_ADD} of the 1TS packet, the P _{2AVE_ADD} of the 2TS packet. Since P _{1AVE_ADD} = 0 of the first TS packet and P _{2AVE_ADD} = 2 of the second TS packet, the first TS packet is processed. Then, by adding the P _1AVE of the 1TS packet ends the second round to the P _{1AVE_ADD} of the 1TS packet. Thereafter, procedure 1 or procedure 2 is repeated in the same procedure.

FIG. 10 is a diagram illustrating a procedure for determining a processing packet when P _1AVE of the first TS packet and P _2AVE of the second TS packet are 1: 1. According to the procedure 1, P _{1AVE_ADD} of the first TS packet is compared with P _{2AVE_ADD} of the second TS packet. P _{1AVE_ADD} and P _{2AVE_ADD} of the 2TS packet of the 1TS packet, since both are 0, the procedure 2 compares the P _1AVE and P _2AVE. Here, in the case of FIG. 10, since P _1AVE and P _2AVE are equal, either the first TS packet or the second TS packet may be selected as a packet to be processed. In such a case, the determination process cycle is repeated so that the first TS packet and the second TS packet are alternately processed thereafter.

  As described above, according to the digital broadcast receiving apparatus according to the first embodiment, the processing order determination circuit 13 is provided, and the TS packet to be processed is determined, whereby the demultiplexer circuit 14 is replaced with the two first tuners 11, It can be shared by the second tuner 12. As a result, there is no need to provide a demultiplexer circuit 14 for each tuner as in the conventional case, so that the circuit scale can be reduced as compared with the conventional case, and the cost can be reduced.

Also, as shown in FIGS. 8 to 10, by comparing P _{1AVE_ADD} and P _{2AVE_ADD} , TS packets with a short transfer interval can be preferentially processed by a simpler procedure.

In the first embodiment, the procedure for determining the TS packet to be processed by comparing P _{1AVE_ADD} and P _{2AVE_ADD} for each packet is described. However, the present embodiment is not limited to this. Based on the first TS packet and the second TS packet, the processing order can be determined by an arbitrary method. For example, the TS packet to be processed is not limited to each packet, and the TS packet to be processed next may be selected for any number of packets.

[Second Embodiment]
Next, a digital broadcast receiving apparatus according to the second embodiment of the present invention will be described. FIG. 11 is a block diagram showing a configuration example of a digital broadcast receiving apparatus according to the second embodiment of the present invention. A feature of the second embodiment is that three tuners that receive TS packets are shared, and one tuner is shared by the three tuners. In addition, since it has the structure substantially the same as 1st Embodiment about another structure, about the structure substantially the same as 1st Embodiment, the description shall be abbreviate | omitted by attaching | subjecting the same code | symbol.

  The digital broadcast receiving apparatus includes a third tuner 91 in addition to the first tuner 11 and the second tuner 12. The third TS packet received by the third tuner 91 is sent to the third video decoder 92 via the demultiplexer circuit 14. The third system time clock 93 receives the program reference clock PCR included in the third TS packet, generates a third clock 95 synchronized with the program reference clock PCR, and outputs it to the third video decoder 92. The number of clocks of the third clock 95 is counted by the third counter 94, and this count value is inserted into the third TS packet by the processing order determination circuit 13.

Next, the operation of the digital broadcast receiving apparatus configured as described above will be described. Note that the process until calculating the average transfer interval expressed by the same frequency is the same as that of the first embodiment shown in FIG. Similarly, in the second embodiment, the order of packet processing is determined by comparing the magnitude relationships of P _1AVE , P _2AVE , P _3AVE or P _{1AVE_ADD} , P _{2AVE_ADD} , P _{3AVE_ADD} expressed by the same counter frequency. .

In the first embodiment, there are two patterns where P _1AVE and P _2AVE have different values, and P _1AVE and P _2AVE are the same. In the second embodiment, the following three patterns are considered. It is done.
(Pattern 1) When all three P _1AVE , P _2AVE , and P _3AVE have the same value (Pattern 2) When P _1AVE , P _2AVE , and P _3AVE have different values (Pattern 3) P _1AVE , P _2AVE , two of the P _3AVE less if the same value, will be described packet processing-order determining process in three patterns. When all of P _1AVE , P _2AVE , and P _3AVE have the same value as in pattern 1, TS packets received by the first tuner 11, the second tuner 12, and the third tuner 91 are respectively Process each packet in a predetermined order. Which tuner's TS packet is used for processing can be arbitrarily set. For example, if it is set to process packets in the order of the first tuner 11, the second tuner 12, and the third tuner 91, the packets may be processed according to this setting.

Next, as shown in pattern 2, the case where the average transfer intervals P _1AVE , P _2AVE , and P _3AVE are different from each other will be specifically described with reference to FIG.

The (first round) Step 1 compares P _{1AVE_ADD} of the 1TS packet, the P _{2AVE_ADD} and P _{3AVE_ADD} of the 3TS packet of the 2TS packet. Since P _{1AVE_ADD} , P _{2AVE_ADD} , and P _{3AVE_ADD} are all 0, P _1AVE , P _2AVE , and P _3AVE are compared in the procedure 2. Since _{P 1AVE = 1, P 2AVE =} 2, P 3AVE = 3, P 1AVE of the 1TS packet is the smallest. Thus processing the first 1TS packet of the first tuner 11, adds the P _1AVE of the 1TS packet P _{1AVE_ADD} of the 1TS packet.

(Second round): by the procedure 1, compares P _{1AVE_ADD} of the 1TS packet, the P _{2AVE_ADD} and P _{3AVE_ADD} of the 3TS packet of the 2TS packet. In this case, since the P _{2AVE_ADD} and P _{3AVE_ADD} it is the same, compared with the P _{1AVE_ADD} may only P _{2AVE_ADD.} Comparing the P _{1AVE_ADD} and P _{2AVE_ADD,} the smaller P _{2AVE_ADD} of the 2TS packet. Therefore, the packet processing of the second tuner 12 and the third tuner 91 has priority over the first tuner 11.

Further, a second 2TS packet first 3TS packet, since P _{2AVE_ADD} and P _{3AVE_ADD} is equal, the procedure 2 is determined by the magnitude comparison of P _2AVE and P _3AVE. Since P _2AVE = 2 and P _3AVE = 3, the second TS packet is smaller. Thus processes TS packets of the second tuner 12, adds the P _2AVE to P _{2AVE_ADD.}

  As described above, even in the case of the pattern 2, the procedures 1 and 2 described in the first embodiment are simply applied as they are, and no new basic policy or process is generated.

Next, the case where two of P _1AVE , P _2AVE , and P _3AVE have the same value as shown in pattern 3 will be described. Specifically, it is assumed that P _1AVE = P _2AVE = 2 and P _3AVE = 3, and the packet processing is set in the order of the second TS packet after the first TS packet.

In this case, first collectively P _1AVE and P _2AVE of a 2TS packet of the 1TS packet is defined as the average transfer interval P _4AVE. By defining in this way it can be treated as a magnitude comparison between P _4AVE and P _3AVE. In addition, about the subsequent procedure, since it should just process according to the procedure 1 and procedure 2, the description is abbreviate | omitted.

  Further, the processing order of the first TS packet and the second TS packet may be processed in the order of the second TS packet following the first TS packet set in advance as described above.

  As described above, according to the second embodiment, even when the demultiplexer is shared by three tuners, the processing order is determined by comparing the transfer intervals as in the first embodiment. Can do. Thus, according to the present invention, one demultiplexer circuit can process TS packets input from three tuners. The number of tuners sharing the demultiplexer is not limited to this, and may be three or more. Thus, as the number of tuners sharing the demultiplexer circuit 14 is increased, the effect of reducing the circuit area and reducing the cost is increased as compared with the conventional case.

  It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

It is a block diagram which shows the example of whole structure of the digital broadcast receiver which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the process order determination circuit which the digital broadcast receiver which concerns on the 1st Embodiment of this invention has. It is a flowchart which shows the procedure until it determines the packet processing order in the digital broadcast receiver which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the procedure until it determines the packet processing order in the digital broadcast receiver which concerns on the 1st Embodiment of this invention. It is a figure which shows the relationship between the frequency of a 1st counter and a 2nd counter. It is a conceptual diagram which shows the procedure which determines a process packet based on the average transfer interval represented by the common counter frequency in the digital broadcast receiver which concerns on the 1st Embodiment of this invention. It is a conceptual diagram which shows the procedure which determines a process packet based on the average transfer interval represented by the common counter frequency in the digital broadcast receiver which concerns on the 1st Embodiment of this invention. In the digital broadcast receiving apparatus according to a first embodiment of the present invention and shows the procedure for determining the processing packet when the P _1AVE <P _2AVE. In the digital broadcasting receiver according to the first embodiment of the present invention and shows the procedure for determining the processing packet when the P _1AVE> P _2AVE. In the digital broadcast receiving apparatus according to a first embodiment of the present invention and shows the procedure for determining the processing packet when the P _1AVE = P _2AVE. It is a block diagram which shows the whole structure of the digital broadcast receiver which concerns on the 2nd Embodiment of this invention. It is a figure which shows the procedure which determines the process packet in the digital broadcast receiver which concerns on the 2nd Embodiment of this invention. 1 is a diagram illustrating a configuration of an apparatus disclosed in Patent Document 1. FIG. FIG. 3 is a diagram illustrating a structure of software that operates in a control unit disclosed in Patent Document 1.

Explanation of symbols

11 1st tuner 12 2nd tuner 91 3rd tuner 13 processing order decision circuit 14 demultiplexer circuit 15 1st video decoder 16 2nd video decoder 17 audio decoder 18 1st system time clock 19 2nd system time clock 20 1st counter 21 Second counter 22 First clock generation circuit 23 Second clock generation circuit 24 Pulse width modulation circuit 25 Oscillator 26 First buffer 27 Second buffer 28 Processing packet determination circuit 91 Third tuner 92 Third video decoder 93 Third system time Clock 94 Third counter 95 Third clock generation circuit 107 Transport decoder 108 Video decoder 109 Video decoder 110 Antenna 111 Tuner 123 Memory 124 Memory 121 Speaker 114 G Nsu port decoder 120 graphic generator 122 Synthesis processor 125 display unit 117 the video decoder 118 the video memory 118 controller 119 audio decoder 120 speaker

Claims (12)

A first tuner for receiving a first transport stream;
A second tuner for receiving a second transport stream;
A demultiplexer circuit for extracting data from the first and second transport streams shared by the first and second tuners and received by the first and second tuners, respectively;
Digital broadcast reception comprising: a processing order determining circuit that determines a processing order of the packets to be processed by the demultiplexer circuit based on a transfer interval of packets included in the first and second transport streams apparatus. The digital broadcast receiving apparatus according to claim 1, wherein the transfer interval is an average transfer interval. A first clock generating circuit for generating a first clock; a second clock generating circuit for generating a second clock; a first counter for counting the number of clocks of the first clock; and a first counter for counting the number of clocks of the second clock. 2 counters,
The processing order determination circuit adds the count value of the first counter to the received first transport stream, adds the count value of the second counter to the received second transport stream, and 3. The transfer interval according to claim 1, wherein the transfer interval is calculated based on a count value of the first counter added to one transport stream and a count value of the second counter added to the second transport stream. Digital broadcast receiver. The processing order determining circuit uses the ratio of the frequency of the first clock and the second clock to transfer the packet included in the first transport stream and the packet included in the second transport stream. The digital broadcast receiving apparatus according to claim 3, wherein a ratio of the transfer intervals is calculated, and a processing order of the packets is determined based on the ratio. The processing order determination circuit is configured to add an average transfer interval obtained by adding the average transfer intervals of the determined first transport stream every time the processing order is determined, and to determine the determined second transport stream. Each of the addition average intervals obtained by adding the average intervals is calculated,
5. The processing order of the packets is determined by comparing the addition average transfer interval of the first transport stream with the addition average transfer interval of the second transport stream. The digital broadcast receiver described in 1. A first storage unit for storing the first transport stream received by the first tuner;
A second storage unit for storing the second transport stream received by the second tuner;
The processing order determination circuit inputs the packets included in the first and second transport streams stored in the first and second storage units, and determines the processing order of the packets. 6. The digital broadcast receiver according to any one of items 5 to 5. Receiving a first transport stream and a second transport stream;
The first and second transport streams included in the first and second transport streams to be subjected to extraction processing based on the transfer intervals of packets included in the received first transport stream and second transport stream, respectively. Determine the order of packet processing,
A digital broadcast receiving method for executing the extraction processing according to the processing order. The digital broadcast receiving method according to claim 7, wherein the transfer interval is an average transfer interval. A first count value obtained by counting the number of clocks of the first clock is added to the received first transport stream, and a second count value obtained by counting the number of clocks of the second clock is added to the received second transport stream. Add
The digital broadcast according to claim 7 or 8, wherein the transfer interval is calculated based on the first count value added to the first transport stream and the second count value added to the second transport stream. Reception method. A ratio of the transfer interval of the first transport stream and the transfer interval of the second transport stream is calculated using a ratio of the frequencies of the first clock and the second clock, and the processing is performed based on the ratio The digital broadcast receiving method according to any one of claims 7 to 9, wherein the order is determined. Each time the processing order is determined,
When the determined packet is the first transport stream, the average transport interval of the first transport stream is calculated by adding the average transport interval of the packets included in the first transport stream. ,
When the determined packet is the second transport stream, an average transfer interval of the second transport stream is calculated by adding the average transfer interval of the packets included in the second transport stream. ,
The digital broadcasting according to any one of claims 8 to 10, wherein the processing order is determined based on the addition average transfer interval of the first transport stream and the addition average transfer interval of the second transport stream. Reception method.   A program for causing a computer to execute the digital broadcast receiving method according to any one of claims 7 to 11.

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