JP2010055386A - Electric circuit and function restriction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric circuit and a function restriction method that eliminate an unnecessary increase in the number of chip pads, the need to revise a mask for each combination of function restrictions, and the risk that a user or third party will remove function restrictions. <P>SOLUTION: The electric circuit includes a function restriction key storage memory 5 for storing key data for applying an optional combination of function restrictions to a plurality of prepared functions, a function restriction control circuit 4 for outputting a notification indicating memory areas of the functions to be restricted according to the key data read from the function restriction key storage memory, and a processing unit 3 for, in response to the notification, reading data on the plurality of functions and storing it in a functional block memory 9 after applying predetermined processing to the data on the functions to be restricted. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  This application relates to an electric circuit and a function limiting method, and more particularly to an electric circuit and a function limiting method capable of selectively limiting a plurality of functions.

  2. Description of the Related Art Conventionally, for example, various terminal devices such as cable television STBs (set-top boxes) are prepared in advance with a plurality of functions, and the functions are limited in any combination according to the user or specifications. It has been broken. At this time, the function to be restricted needs to be set without being tampered with or deciphered by the user or a third party.

FIG. 1 is a block diagram showing an example of a conventional electric circuit.
As shown in FIG. 1, an electric circuit (chip) 100 includes a CPU 101, a decoding circuit / function restriction control circuit 102, selectors 103-1 to 103-n, functional blocks 104-1 to 104-n, and a pad 105. .

  Here, the functional blocks 104-1 to 104-n may be either hardware or software, and may be blocks such as a JPEG decoder, an audio decoder, an enlargement / reduction function, or various scrambling release functions, for example. is there. The CPU 101 has a boot memory (Boot ROM) 111.

  In the electric circuit shown in FIG. 1, for example, among a plurality of pads (Pad) 105 provided around the chip 100, a predetermined number of pads 105a are connected to the power supply line Vcc or the ground line GND to set a function restriction. To do. Here, the connection of the pad 105a to the power supply line Vcc or the ground line GND is performed as a bonding option, for example.

  That is, by connecting the pad 105a to the power supply line Vcc or the ground line GND, any combination of function restrictions is set for the decode circuit / function restriction control circuit 102. For example, during booting by reading data from the boot memory 111, the selectors 103-1 to 103-n are controlled by a control signal from the decode circuit / function restriction control circuit 102, and the corresponding function blocks 104-1 to 104-1 are executed. The function limitation of 104-n is performed.

  As a result, the functions of the function blocks 104-1 to 104-n in the chip 100 are limited in any combination without the function or the third party being tampered with or decoded.

FIG. 2 is a block diagram showing another example of a conventional electric circuit.
As shown in FIG. 2, the electric circuit 200 includes a CPU 201, a decoding circuit / function restriction control circuit 202, selectors 203-1 to 203-n, function blocks 204-1 to 204-n, and a function restriction setting mask ROM 205. Prepare.

  The electric circuit shown in FIG. 2 sets arbitrary combinations of function restrictions for the decoding circuit / function restriction control circuit 202 by, for example, writing predetermined data in advance in the function restriction setting mask ROM 205. For example, during booting by reading data from the boot memory 211, the selectors 203-1 to 203-n are controlled by the control signal from the decoding circuit / function restriction control circuit 202, and the corresponding functional blocks 204-1 to 204-1 are executed. The function is limited to 204-n.

  As a result, the functions of the functional blocks 204-1 to 204-n in the chip 200 are limited in any combination without the function or the third party being altered or deciphered by the user or a third party.

  It should be noted that the above-described function restrictions prepared in advance and in any combination depending on the user or specifications are widely applied not only to terminal devices such as cable television STBs but also to various electric circuits. It can be done.

  By the way, conventionally, in order to prevent unauthorized use of an electronic system such as a cellular phone, it has been proposed to provide an auxiliary memory in addition to the main memory and control by programming at least one specific code in the auxiliary memory. ing. Here, the auxiliary memory is a memory that can be permanently locked outside the array space of the main memory.

Special Table 2002-514840 Publication

  As described above, conventionally, as an electric circuit for preparing a plurality of functions in advance and restricting functions in an arbitrary combination, a predetermined number of pads are clipped as a bonding option, or a function is provided in a built-in mask ROM. It was known to write data for restriction.

  That is, in the example of the conventional electric circuit shown in FIG. 1, a predetermined number of pads 105a are connected to the power supply line Vcc or the ground line GND by a bonding option to limit the function in an arbitrary combination.

  However, in the electric circuit of FIG. 1, since pads corresponding to the number of functional blocks subject to function restriction are required, the number of pads increases and the cost increases.

  In another example of the conventional electric circuit shown in FIG. 2, the function restriction is performed in an arbitrary combination by writing predetermined data in advance in the function restriction setting mask ROM 205. However, for example, when function restriction is performed without setting from the outside (including those by firmware installed in the CPU 201), a mask revision is required for each combination of function restrictions.

  In view of the above-described problems, this application does not increase the number of pads on the chip more than necessary, and does not require revision of the mask for each combination of function restrictions. An object is to provide an electric circuit and a function restriction method without risk of release.

  According to the first embodiment, an electric circuit including a function restriction key storage memory, a function restriction control circuit, and an arithmetic processing device is provided.

  The function-restricted key storage memory stores key data to be subjected to function restriction in an arbitrary combination among a plurality of functions prepared in advance. Further, the function restriction control circuit outputs a notification indicating the memory area of the function to which the function restriction is applied according to the key data read from the function restriction key storage memory.

  Further, the arithmetic processing unit receives a notification from the function restriction control circuit, reads data of a plurality of functions, performs predetermined processing on the data of the function to which the function restriction is applied, and stores it in the function block memory.

  According to the second embodiment, there is provided a function limiting method for an electric circuit that limits the function in any combination among a plurality of functions prepared in advance.

  First, key data to be subjected to function restriction in an arbitrary combination is stored in advance in a function restriction key storage memory. Further, at the time of booting the electric circuit, the arithmetic processing unit is notified of the memory area of the function to be subjected to the function restriction according to the key data read from the function restriction key storage memory.

  Then, a predetermined process is performed on the memory area of the function to which the function is restricted, and the result is stored in the function block memory.

  According to each embodiment, it is not necessary to increase the number of pads on the chip more than necessary, and it is not necessary to update the mask for each combination of function restrictions. It is possible to provide an electric circuit and a function limiting method that are free of any problems.

Hereinafter, embodiments of an electric circuit and a function limiting method will be described in detail with reference to the accompanying drawings.
FIG. 3 is a block diagram showing an embodiment of an electric circuit.

  As shown in FIG. 3, the electric circuit 1 of this embodiment includes a CPU (arithmetic processing unit) 3, a function restriction control circuit 4, a function restriction key storage OTP (One Time Programmable) ROM 5, a write control circuit 6, and a system. A bus 7, a boot ROM 8 and a function block memory 9 are provided.

  The electric circuit shown in FIG. 3 includes, for example, an arbitrary bit string data (key data) table corresponding to a combination of function restrictions in software functions 0 to m (m = 0,..., N) stored in the external memory 2. Create in advance. Although not shown, it goes without saying that hardware or software functions can be provided inside the electric circuit 1 in addition to the functions of the software stored in the external memory 2.

  Functions 0 to m stored in the external memory 2 indicate software. For example, JPEG, JPEG200, MPEG, MPEG2, MPEG4, MPEG4-AVC (H.264), MPEG1-Layer1,2,3, MPEG2-Layer1,2 , 3, or various MPEG2 / AAC decoders. The external memory 2 is configured by a memory such as a NOR flash memory, a NAND flash memory, an SDR-SDRAM, a DDR-SDRAM, or a DDR2-SDRAM, for example.

Here, the function restriction combination and key data correspondence table is created in advance, for example, as shown in Table 1 below. Table 1 shows an example in which m = 2 and the key data is 3 bits.

  Specifically, in Table 1, for example, when all functions 0 to 2 are restricted and cannot be used, the key data is “111”, and functions 0 and 1 can be used without being restricted. When the function 2 is restricted and cannot be used, the key data is set to “001”.

  According to the electric circuit of this embodiment, key data of an arbitrary length corresponding to the combination of restriction of each function is written in the function restriction key storage OTPROM 5, and the key data function restriction control circuit 4 reads out and notifies the CPU 3 of the key data. By doing so, the function is limited.

  That is, the CPU 3 sequentially reads data (software) from the external memory 2 and writes it in the designated memory area of the function block memory 9. Here, in the present embodiment, the functional block memory 9 is configured as a built-in tightly coupled memory (TCM) provided in the electric circuit 1.

  Thus, the use of the tightly coupled memory 9 provided in the electric circuit 1 as the function block memory is preferable, for example, when the target function (software) has a small capacity or is frequently used.

  When read processing from the address area of the external memory 2 corresponding to the function to which the function is restricted occurs, a fixed value is written in the memory area of the corresponding function block memory 9 or the area is written. Write by skipping. Thereby, the function of the external memory 2 to which the function restriction is applied is restricted and cannot be used.

  As described above, according to the electric circuit of the present embodiment, it is possible to limit the functions of a desired combination from the outside by using only the pads necessary for writing the key data to the function-limiting key storage OTPROM 5.

  Here, since the CPU 3 is configured such that it cannot access the function-restricted key storage OTPROM 5, the function-restricted control circuit 4, and the write-controlled circuit 6, the decryption of key data or the function of the user or a third party is prevented. It is difficult to remove restrictions.

  Since the external memory 2 for storing software of each function is binary data, it is difficult for a user or a third party to tamper or decode the data itself. The function restriction key storage memory 5 may be a memory other than the OTPROM, for example, a UV-EPROM capable of erasing data by ultraviolet irradiation.

FIG. 4 is a flowchart showing an example of key data writing processing in the electric circuit shown in FIG.
When the key data writing process is started, first, in step ST11, the OTPROM writing control terminal is validated and the process proceeds to step ST12 to cancel the external reset.

  Further, the process proceeds to step ST13, and key data having an arbitrary bit length corresponding to the combination of software whose function is to be restricted is input. Here, for the key data, for example, a correspondence table between the combination of function restrictions and the key data as shown in Table 1 is created in advance, and the key data corresponding to the required combination of function restrictions is input.

  As a result, the write control circuit 6 sets the function restriction key storage OTPROM 5 to the write state, and writes the input key data to the function restriction key storage OTPROM 5. That is, in step ST14, data writing to the function-restricted key storage OTPROM 5 is completed, and the key data writing process is terminated.

  Thus, when the key data is input to the write control circuit 6 with the OTPROM write control terminal enabled, the write control circuit 6 validates the write control signal supplied to the function-restricted key storage OTPROM 5 and receives the key data. Write to the function-restricted key storage OTPROM 5.

  Here, the OTPROM write control terminal is made effective, for example, by applying a voltage higher than the power supply voltage during operation to a predetermined pad. In addition, the function-restricted key storage OTPROM 5 is designed such that once data is written, the data at the location where the data is written cannot be erased again.

  FIG. 5 is a flowchart showing an example of function restriction processing in the electric circuit shown in FIG. 3, and FIG. 6 is a diagram showing an example of mapping of internal memory in the electric circuit shown in FIG.

  When the function restriction process is started, first, in step ST21, the external reset is canceled, and the process proceeds to step ST22 and step ST23. Here, step ST22 (ST22 and ST25 to ST27) is a process of the CPU 3, and steps ST23 and ST24 are a process of the function restriction control circuit 4.

  In step ST22, the CPU 4 starts boot processing in accordance with the instruction stored in the boot ROM 8 and proceeds to step ST25, and the function restriction control circuit 4 performs steps ST23 and ST24.

  In step ST23, the function restriction control circuit 4 accesses the function restriction key storage OTPROM 5 in which the function restriction key data is stored, and proceeds to step ST24. In step ST24, the function restriction control circuit 4 outputs a notification (a) corresponding to the key data read from the function restriction key storage OTPROM 5 to the CPU 3.

  Here, the notification (a) from the function restriction control circuit 4 to the CPU 4 relates to, for example, an address area corresponding to the function to which the function restriction is applied from the memory map information of FIG.

  Further, the process proceeds to step ST25, and when software is read from the memory space where the function is restricted, all fixed values (for example, all “0”) are read, or the corresponding memory space is skipped.

  Normally, data is read from the external memory 2 and written into a designated memory area of the function block memory 9.

  When a read process from the address area corresponding to the function to which the function is restricted occurs, a fixed value is written into the write target memory area in the function block memory 9, or the area is skipped for writing. . The external memory 2 is composed of, for example, a flash memory.

  Specifically, for example, when the key data in Table 1 is “001” (function 2 is OFF), the notification (a) from the function restriction control circuit 4 to the CPU 3 is the address information of “0x00006000h” and “0x00007fffh”. It becomes.

  In the case of fixed value writing, when the CPU 3 starts to read the memory area 2 (“0x00006000h” to “0x00007fffh”) in FIG. The read value is an arbitrary fixed value (for example, “0”).

  Alternatively, in the case of area skip, when the start of the start address “0x0006000” is reached during the boot process, the CPU 3 skips the function 2 memory area and reads from the start address “0x00008000h” of the function 3 memory area. Do.

  The data read from the memory 2 is written into the corresponding function block memory 9. For example, all the memory areas corresponding to the memory area of the function 3 have arbitrary fixed values (for example, all “0”). ]) Will be written.

  Further, after performing the process of step ST26 described above, the process proceeds to step ST27 to determine whether or not the boot process is completed. If the boot process is not completed, the process returns to step ST25 and the boot process is performed. The same process is repeated until completion. If it is determined in step ST27 that the boot process has been completed, the process proceeds to the next process.

FIG. 7 is a block diagram showing another embodiment of the electric circuit.
As is clear from the comparison between FIG. 7 and FIG. 3 described above, in the embodiment shown in FIG. 7, the functional block memory 9 configured as the tightly coupled memory in the embodiment of FIG. It is configured as a memory 9 ′ such as a provided DRAM.

  As described above, the memory 9 ′ provided outside the electric circuit 1 is used as the function block memory when, for example, the capacity of the target function (software) is large or the frequency of use is low. There is no need to increase the circuit scale of the circuit 1.

  Even when the functional block memory is configured as a memory 9 ′ such as a DRAM provided outside the electric circuit 1, for example, in the data stored in the memory 9 ′, all the data subject to function restriction are arbitrarily fixed. The value (for example, all “0”) or skipped, there is no risk of releasing the function restriction by the user or a third party.

  As described above, according to each embodiment, it is not necessary to increase the number of pads on the chip more than necessary, and it is not necessary to perform mask revision for each combination of function restrictions. It is possible to provide an electric circuit and a function restriction method without risk of function restriction release.

The following supplementary notes are further disclosed regarding the embodiment including the above examples.
(Appendix 1)
A function-restricted key storage memory for storing key data to be subjected to function restriction in an arbitrary combination among a plurality of functions prepared in advance;
A function restriction control circuit that outputs a notification indicating a memory area of a function to which the function restriction is applied according to the key data read from the function restriction key storage memory;
An arithmetic processing unit that receives the notification, reads the data of the plurality of functions, performs predetermined processing on the data of the function to which the function restriction is applied, and stores the data in a function block memory; Electrical circuit to do.

(Appendix 2)
In the electrical circuit described in Appendix 1,
The arithmetic processing unit, according to the information of the memory area of the function to be subjected to the function restriction included in the notification, all the data read from the memory area of the function to perform the function restriction to an arbitrary fixed value, or An electric circuit characterized by skipping and reading a memory area of a function for performing function restriction.

(Appendix 3)
In the electrical circuit according to any one of appendices 1 and 2,
The electric circuit, wherein the function restriction key storage memory is an OTPROM.

(Appendix 4)
In the electrical circuit according to any one of appendices 1 to 3,
The processing according to the notification is performed when the electrical circuit is booted.

(Appendix 5)
In the electric circuit according to any one of appendices 1 to 4,
The plurality of functions prepared in advance are software stored as data in a nonvolatile memory provided outside the electrical circuit.

(Appendix 6)
In the electric circuit according to any one of appendices 1 to 5,
The electric circuit according to claim 1, wherein the functional block memory is a tightly coupled memory provided in the electric circuit.

(Appendix 7)
A function limiting method of an electric circuit that applies a function limitation in an arbitrary combination among a plurality of functions prepared in advance,
Store key data to be subjected to function restriction in any combination in advance in a function restriction key storage memory,
When the electrical circuit is booted, according to the key data read from the function restriction key storage memory, the memory area of the function to be subjected to the function restriction is notified to the arithmetic processing unit,
A function restriction method comprising: performing a predetermined process on a memory area of a function to which the function restriction is applied and storing the memory area in a function block memory.

(Appendix 8)
In the function restriction method described in appendix 7,
The predetermined processing for the memory area of the function that performs the function restriction may be performed by setting all of the data read from the memory area of the function that performs the function restriction to an arbitrary fixed value, or the memory area of the function that performs the function restriction. A function restriction method characterized by skipping and reading.

It is a block diagram which shows an example of the conventional electric circuit. It is a block diagram which shows the other example of the conventional electric circuit. It is a block diagram which shows one Example of an electric circuit. It is a flowchart which shows an example of the key data writing process in the electric circuit shown in FIG. It is a flowchart which shows an example of the function restriction | limiting process in the electric circuit shown in FIG. It is a figure which shows an example of the mapping of the internal memory in the electric circuit shown in FIG. It is a block diagram which shows the other Example of an electric circuit.

Explanation of symbols

1,100,200 Electric circuit (chip)
2 External memory 3, 101, 201 CPU (arithmetic processing unit)
4 Function restriction control circuit 5 OTPROM for function restriction key storage
6 Write Control Circuit 7 System Bus 8, 111, 211 Boot ROM
9, 9 'function block memory 102, 202 decode circuit / function restriction control circuit 103-1 to 103-n, 203-1 to 203-n, selector 104-1 to 104-n, 204-1 to 204-n Function block 105, 105a Pad 205 Function restriction system setting mask ROM

Claims (4)

A function-restricted key storage memory for storing key data to be subjected to function restriction in an arbitrary combination among a plurality of functions prepared in advance;
A function restriction control circuit that outputs a notification indicating a memory area of a function to which the function restriction is applied according to the key data read from the function restriction key storage memory;
An arithmetic processing unit that receives the notification, reads the data of the plurality of functions, performs predetermined processing on the data of the function to which the function restriction is applied, and stores the data in a function block memory; Electrical circuit to do. The electrical circuit according to claim 1,
The arithmetic processing unit, according to the information of the memory area of the function to be subjected to the function restriction included in the notification, all the data read from the memory area of the function to perform the function restriction to an arbitrary fixed value, or An electric circuit characterized by skipping and reading a memory area of a function for performing function restriction. The electric circuit according to any one of claims 1 and 2,
The electric circuit, wherein the function restriction key storage memory is an OTPROM. A function limiting method of an electric circuit that applies a function limitation in an arbitrary combination among a plurality of functions prepared in advance,
Store key data to be subjected to function restriction in any combination in advance in a function restriction key storage memory,
When the electrical circuit is booted, according to the key data read from the function restriction key storage memory, the memory area of the function to be subjected to the function restriction is notified to the arithmetic processing unit,
A function restriction method comprising: performing a predetermined process on a memory area of a function to which the function restriction is applied and storing the memory area in a function block memory.

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