JP2010049700A - Task processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve efficient task execution control in multitask processing. <P>SOLUTION: A task processing apparatus includes a CPU 210, a save circuit, and a task control circuit 210. The task control circuit 210 includes a task selection circuit and status storage parts associated with respective tasks. When executing a prescribed system call instruction, the CPU notifies the task control circuit about the execution. When being notified about the execution of the system call instruction, the task control circuit selects a task to be next executed, in accordance with an output from the task selection circuit. When an interrupt circuit 400 receives a high speed interrupt request signal, the task control circuit 210 executes an interrupt operation instruction designated by the interrupt circuit 400 to control the status transition of tasks. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an OS (Operating System) function, and more particularly to interrupt processing.

  Advanced functions are being demanded not only for OSs for general-purpose devices such as personal computers but also for OSs for dedicated devices such as mobile phones. In particular, an OS capable of executing a plurality of tasks with a single CPU (Central Processing Unit) (hereinafter, this type of OS is also referred to as a “multitask OS”) is installed in many electronic devices. It has become to.

  The multitask OS divides the processing time of the CPU into unit times (time slices) and assigns time slices to a plurality of tasks in order. Each task can use the CPU only when a time slice is given from the OS. One task is executed in each time slice. Since time slices are very short from the user's point of view, it looks as if multiple tasks are being executed simultaneously. According to such a processing method, when the task A reaches an input standby state and does not require the CPU processing capability for the time being, the processing capability of the CPU can be effectively utilized by giving another task B the execution right. The execution right here is synonymous with the right to use the CPU.

  Switching the task execution right by the multitasking OS is called “task switch”. A task switch occurs when a time slice elapses or when a task executes a predetermined instruction. When the task switch execution timing is reached, the multitask OS saves the context information of the task being executed in a TCB (Task Control Block). The context information is data related to the execution state of a task or data stored in a CPU register at the time of task execution. The TCB is an area secured in the memory for holding task-specific information. After saving the context information of the task being executed to the TCB, the multitask OS selects the next task to which the execution right is assigned, reads the context information from the TCB of the task, and loads it into the CPU register. In this way, each task advances its own processing little by little in units of time slices.

  The multitask OS has an advantage that a plurality of tasks can be efficiently executed, but has a disadvantage that an overhead of saving / loading context information is newly generated. Usually, the merit of the multitasking OS more than compensates for the overhead associated with task switching.

JP 11-272480 A JP 2001-75820 A

Naohisa Mori, Yoshimi Sakamaki, Hiroshi Shigematsu, “Hardware implementation of a read-time operating system for embedded control system”, Tokyo Metropolitan Industrial Technology Research Institute research report, Japan, 2005 August 4, 2014 (manuscript acceptance), 8, p. 55-58

  In recent years, a real-time OS (hereinafter referred to as “RTOS (Real-Time Operating System)”) that strictly requires processing to be completed within a predetermined time has become widespread mainly in embedded systems (Enbeded Systems). is there. In such an RTOS with strict time requirements, the overhead at the time of task switching may greatly affect the performance of the entire system.

  Further, the RTOS must immediately cope with various external factors that occur irregularly, such as completion of DMA (Direct Memory Access) transfer, reception of a communication packet, or depression of a keyboard. Normally, when an interrupt request signal indicating the occurrence of an external factor is received, the RTOS activates a special task and executes “interrupt processing”. In order to improve the performance of the RTOS, it is particularly important to suppress overhead when dealing with such external factors.

  The present invention has been completed on the basis of the above-mentioned problem recognition by the present inventor, and its object is to provide a technique for performing and controlling tasks more efficiently in multitask processing, and in particular, The object is to provide a technique for realizing high-speed interrupt processing.

One embodiment of the present invention is a task processing device.
This device includes a processing register, an execution control circuit that loads data from the memory to the processing register and executes a task according to the data in the processing register, a state register that holds state data for each task, and a task execution state. A task switching circuit to be controlled; a task selection circuit for selecting a task according to a predetermined selection condition; and an interrupt circuit for processing an interrupt request signal from the outside.
When the first task executes the system call instruction, the execution control circuit notifies the task switching circuit to that effect. The task selection circuit selects a task to be executed from among tasks in a READY state indicating a state waiting for execution.
The task switching circuit selects the second task to be executed next by the output from the task selection circuit when the system call instruction is executed, saves the data in the processing register in a predetermined storage area, and The state control data is changed, the data saved in the storage area for the selected second task is loaded into the processing register, and the state data is changed from the READY state to the RUN state. Allow task execution. After transmitting the system call signal, the execution control circuit executes the second task on the condition that this execution is permitted.
On the other hand, when the interrupt circuit receives an interrupt request signal from the outside, the interrupt circuit transmits an interrupt operation command associated with the interrupt request signal to the task switching circuit. The task switching circuit responds to the interrupt request signal by changing the setting of the task status data in accordance with the interrupt operation instruction.

  The data loaded into the processing register may be an instruction and an operand, an instruction having no operand, or simple data such as a program counter or a stack pointer. According to such a processing method, since the state of the task is managed by the state register, the task switching circuit can execute the task switch based on the output from the task selection circuit. When an interrupt request signal is received from the outside, the task switching circuit changes the status register data according to the interrupt operation instruction associated with the interrupt request signal. It will be possible to respond at high speed at the hardware level.

  It should be noted that any combination of the above-described components, and the present invention expressed by a method, system, recording medium, and computer program are also effective as an aspect of the present invention.

  According to the present invention, more efficient task execution control is realized in multitask processing.

It is a state transition diagram of a task. It is a conceptual diagram of general RTOS. It is a circuit diagram of a general CPU on which software RTOS is executed. It is a conceptual diagram of RTOS in a basic example. It is a circuit diagram of a task processing device in a basic example. FIG. 6 is a circuit diagram of the CPU in FIG. 5. It is a circuit diagram which shows the mechanism in which the execution control circuit 152 stops a CPU clock. It is a time chart which shows the relationship of the various signals at the time of interruption request signal generation | occurrence | production. It is a time chart which shows the relationship of the various signals at the time of system call execution. It is a schematic diagram for demonstrating the stop timing of the CPU clock in a pipeline process. It is a circuit diagram which shows the relationship between a state memory | storage part and a task switching circuit. It is a figure which shows the task ready list utilized at the time of RUN-task selection by general RTOS. It is a circuit diagram of an execution selection circuit. It is a figure which shows the wait semaphore list utilized in the semaphore process by general RTOS. It is a circuit diagram of a semaphore selection circuit. It is a state transition diagram of the task switching circuit in the basic example. FIG. 6 is a circuit diagram of a task processing device that does not include a task control circuit in the task processing device of FIG. 5. FIG. 6 is a circuit diagram of a task processing device that does not include a save circuit among the task processing devices of FIG. 5. It is a time chart of the interruption process by general software OS. It is a circuit diagram of a task processing device in an improved example. It is a circuit diagram of an interrupt circuit. It is a data structure figure of a memory | storage part. It is a data structure of an interrupt operation instruction. It is a sequence diagram which shows the process of a high-speed interruption process. It is a state transition diagram of a task switching circuit in an improved example. It is a time chart which shows the process of the high-speed interruption process by the task processing apparatus of an improved example.

The task processing apparatus 100 according to the present embodiment realizes task scheduling of the multitask OS by an electronic circuit, and further improves the processing efficiency as the multitask OS by implementing an interrupt processing algorithm as hardware logic. Yes.
First, a task processing apparatus 100 that implements task scheduling of a multitask OS by an electronic circuit in this embodiment will be described as a “basic example”. After that, a method for realizing higher speed by implementing an interrupt processing algorithm will be described as an “improved example”. Hereinafter, when referring to "this embodiment", in principle, both "basic example" and "improved example" are shown.
{Basic example}

The task processing apparatus 100 shown in the present embodiment realizes a task scheduling function of a multitask OS by an electronic circuit. Before explaining the details of the task processing apparatus 100, first, the task state transition will be explained with reference to FIG. Here, description will be made on task state transition in a general multitask OS, but the same applies to task state transition by the task processing apparatus 100. The system call executed in the task processing apparatus 100 will also be outlined. A general multitask OS design concept will be described with reference to FIGS. 2 and 3, and a processing method of the task processing apparatus 100 in the basic example will be described in detail with reference to FIGS. Further, the characteristics of the task processing apparatus 100 will be described as appropriate for processing related to semaphores, mutexes, events, and the like, as compared with general techniques.
[Task state transition]

FIG. 1 is a task state transition diagram.
In multitask processing, each task has a “state”. Each task transits between a plurality of states described later, and is always in one of the states. The trigger for the state transition is “execution of system call” and “detection of interrupt request signal”. A system call is a special instruction among instructions executed by each task. An interrupt request signal is a signal generated when predetermined data is received from a peripheral device, such as a keyboard press, mouse click, or communication data reception. Of course, the state transition also occurs when the time slice allocated to each task is consumed.

  Tasks are roughly classified into two types: “general tasks” and “special tasks”. A general task is a normal task that is executed in response to a system call. The special task is a task that is executed when the interrupt request signal is detected. This is a so-called interrupt handler. First, after describing each task state, various system call instructions will be described.

(1) STOP state (resting state)
Indicates that the task is in a dormant state. Both general and special tasks can be in the STOP state. Hereinafter, a task in the STOP state is referred to as “STOP-task”.
1-1. General Task When another system executes a system call instructing activation of another task (hereinafter referred to as “activation system call”), the general task in the STOP state transitions to the READY state described later.
1-2. Special tasks Special tasks are usually in the STOP state. When an interrupt request signal is detected by a task switching circuit 210 described later, the special task transits from a STOP state to a RUN state described later. At this time, the task in the RUN state is switched to the READY state instead.

(2) RUN state (execution state)
Indicates that the task is running. That is, the task is assigned a time slice and has acquired the right to use the CPU. Both general and special tasks can be in the RUN state. Hereinafter, a task in the RUN state is referred to as “RUN-task”. Of the plurality of tasks, only one task can be in the RUN state at any one time, and two tasks cannot be in the RUN state at the same time.
2-1. General Task A general task in the RUN state transitions from the RUN state to the READY state or a WAIT state described later when a predetermined system call is executed. A general task in the RUN state also transitions to the READY state when the time slice is consumed. In any case, instead of the general task that was in the RUN state, the general task that is in the READY state transitions to the RUN state. When an interrupt request signal is detected, the RUN-task transitions to the READY state. At this time, the special task in the STOP state transitions to the RUN state.
When the RUN-task executes a system call that terminates itself (hereinafter referred to as “end system call”), the RUN-task transitions to the STOP state.
2-2. Special task The special task that has transitioned from the STOP state to the RUN state by the interrupt request signal returns to the STOP state when its own processing is completed. The states that the special task can take are only the STOP state and the RUN state.

(3) READY state (executable state)
Indicates that the task is ready to run. A task in the READY state can transition to the RUN state at any time if an execution right is given from the OS. Only general tasks can be in the READY state. Hereinafter, a task in the READY state is referred to as “READY-task”.
When a general task in the RUN state transitions to a state other than the RUN state due to the execution of a system call, or when a special task in the RUN state finishes its processing and transitions to the STOP state, the READY-task is switched. Transition to the RUN state. The general task changes from the READY state only to the RUN state. When there are a plurality of tasks in the READY state, one of the READY-tasks transitions to the RUN state based on the task priority that is part of the context information. When there are a plurality of READY-tasks having the same task priority, the task having the oldest transition to the READY state transitions to the RUN state.

(4) WAIT state (standby state)
The task is waiting for a predetermined WAIT cancellation condition to be satisfied. When the WAIT cancellation condition is satisfied, the task in the WAIT state transitions to the READY state. Only general tasks can be in the WAIT state. Hereinafter, a task in the WAIT state is referred to as “WAIT-task”. The WAIT cancellation condition will be described in detail later.

In summary, each task can proceed with its own processing using the CPU only when it is in the RUN state. The RTOS switches RUN-tasks as appropriate while managing the states of a plurality of tasks. As a result, a processing mode in which the CPU always executes one of the tasks is realized.
[System Call]

Next, let me add a note about system calls. System calls are roughly classified into three types: “activation system”, “WAIT system”, and “SET system”.
(1) Activation system call A system call related to a transition between the STOP state and the READY state.
1-1. Activation system call This is a system call in which task A, which is a RUN-task, activates another general task B. At this time, the general task B in the STOP state transitions to the READY state.
1-2. End system call The task that executed this system call ends its own processing and transitions from the RUN state to the STOP state. The end system call may be an instruction for one task to end another task.
(2) WAIT system call A system call related to a transition between the RUN state and the WAIT state.
2-1. Wait semaphore system call This system call requests acquisition of a semaphore (described later).
2-2. Wait mutex system call This system call requests acquisition of a mutex (described later).
2-3. Wait event system call A system call that waits for the establishment of an event (described later). In addition to the event ID, a standby flag pattern (described later) and a flag condition (described later) are executed as variables.
In any case, various WAIT cancellation conditions are set by the WAIT system call. If the WAIT cancellation condition is already satisfied when the WAIT system call is executed, the RUN-task that executed the system call transitions to the READY state. On the other hand, when the WAIT cancellation condition is not satisfied, the RUN-task transits to a WAIT state that waits for the WAIT cancellation condition to be satisfied.
(3) SET system call A system call related to a transition between the WAIT state and the READY state. Execution of a SET system call triggers the establishment of a WAIT cancellation condition.
3-1. Release semaphore system call (or “signaling semaphore system call”)
A system call that releases a semaphore.
3-2. Release mutex system call This system call releases a mutex.
3-3. Set event system call (or “set flag system call”)
This is a system call for setting a current flag pattern (described later) of an event.
3-4. Clear flag system call This system call clears the current flag pattern to zero.
In the basic example, the above nine types of system calls will be described, but it goes without saying that various other system calls can be implemented.
For example, a “release wait system call” for unconditionally transitioning a WAIT-task to the READY state or a “wake-up task system call” for transitioning a task in the WAIT state to the READY state by a sleep command may be implemented. .
[General RTOS design concept]

FIG. 2 is a conceptual diagram of a general RTOS.
This RTOS is a multitasking OS. A general RTOS is realized as software. A case where the RUN-task is switched from task A to task B will be described as an example. Since task A occupies the CPU, the RTOS interrupts the CPU and picks up the right to use the CPU from task A. After that, the context information of task A is saved in the TCB. The RTOS selects task B as the next RUN-task and loads the context information from the task B TCB into the CPU registers. When the loading is completed, the RTOS passes the right to use the CPU to task B. In this way, the RTOS executes task switching from task A to task B by temporarily acquiring the right to use the CPU. The same applies to the execution of special tasks. Also in this case, the task switch is realized by saving the context information of the RUN-task to the TCB and then passing the right to use the CPU to the special task.
Since the RTOS is realized as software, it requires the right to use the CPU in order to execute its own processing. In other words, RTOS and tasks are competing for CPU usage. Hereinafter, the RTOS realized by software in this way is referred to as “software RTOS”.

FIG. 3 is a circuit diagram of a general CPU on which software RTOS is executed.
The CPU 84 includes an execution control circuit 90 that comprehensively controls memory access, instruction execution, and the like, a processing register 92 that stores various data such as task context information, and an arithmetic circuit 94 that executes arithmetic operations. The processing register 92 is a set of a plurality of types of registers, and is roughly divided into a special register 88 and a general-purpose register 86. The special register 88 is a register that holds a program counter, a stack pointer, a flag, and the like. The general-purpose register 86 is a register that holds work data, and includes a total of 16 registers R0 to R15. The special register 88 has two sides for the user and the system, but the general-purpose register 86 has only one side. Hereinafter, the data stored in the processing register 92 is referred to as “processing data”.

  The execution control circuit 90 causes the arithmetic circuit 94 to output processing data of a desired register among the processing registers 92 in response to a control signal (CTRL) for the output selector 98. The arithmetic circuit 94 performs an operation according to processing data, that is, an instruction or a variable. The calculation result is output to the input selector 96. The execution control circuit 90 inputs an operation result to a desired register among the processing registers 92 by a control signal (CTRL) for the input selector 96.

  Further, the execution control circuit 90 reads data from the memory via the CPU data bus, and loads it appropriately into the processing register 92 via the input selector 96. The execution control circuit 90 also records processing data in the memory as appropriate via the CPU data bus. The execution control circuit 90 executes the task while updating the program counter of the special register 88.

When a task switch occurs, the execution control circuit 90 saves the processing data in the TCB, which is an area on the memory. Assume that task A executes a system call and a task switch from task A to task B occurs. Since the RTOS acquires the right to use the CPU when the system call is executed, the CPU 84 temporarily operates in accordance with the RTOS program. The processing process is as follows.
<Save context information of task A>

1. The execution control circuit 90 switches the special register 88 from the user to the system. The system special register 88 is loaded with processing data for RTOS processing.
2. The execution control circuit 90 saves the data in the general-purpose register 86 in a stack (not shown).
3. The execution control circuit 90 loads processing data for RTOS into the general-purpose register 86 from a storage medium (not shown), for example, another register. At this stage, the processing data in the processing register 92 is completely replaced with processing data for RTOS.
4). The RTOS detects the task A TCB from the memory and writes the processing data saved in the stack to the TCB. Also, the processing data of the user special register 88 is written to the TCB as part of the context information. In this way, the processing data of task A is saved in the TCB. The RTOS records in the TCB of the task A that the state transition of the task A from “RUN” to “READY (or WAIT)”.
<Load context information of task B>

1. The RTOS detects the task B TCB from the memory and writes the TCB context information to the stack and the user special register 88. The RTOS records in the TCB of the task B that the task B has made a state transition from “READY” to “RUN”.
2. The RTOS saves RTOS processing data from the general-purpose register 86 to a recording medium (not shown).
3. The execution control circuit 90 loads the stack context information into the general-purpose register 86. The execution control circuit 90 switches the special register 88 from system use to user use. In this way, the processing data of task B is loaded into the processing register 92.

  The task switch is realized through the above processing steps. Normally, the general-purpose register 86 has a one-sided structure, and therefore a stack is used to switch between task processing data and RTOS processing data. If the general-purpose register 86 is also made two-sided, it is not necessary to save and load through the stack, so that higher-speed task switching is possible.

In the basic example, a save register 110 is further provided for each task, thereby realizing a faster task switch. The task switch using the save register 110 will be described in detail with reference to FIG. In the case of the CPU 84 and the general software RTOS described in relation to FIG. 3, it can be seen that frequent access to the TCB occurs during task switching. In the above example, description has been made on the premise that the task is switched from the task A to the task B, but actually, it is necessary for the RTOS to execute many instructions in order to select the task B to be executed next. Also at this time, the RTOS frequently accesses the memory. The task processing apparatus 100 in the basic example realizes a higher-speed task switch because a task control circuit 200 described later executes task selection processing exclusively.
[RTOS hardware implementation by the task processing device 100]

FIG. 4 is a conceptual diagram of RTOS in the basic example.
Unlike a general software RTOS, the RTOS in the basic example is mainly realized as hardware separate from the CPU. Hereinafter, RTOS realized by hardware is referred to as “hardware RTOS”. The RTOS in the basic example is mainly hardware that is separate from the CPU, and therefore requires substantially no CPU usage right to execute its own processing. In other words, RTOS and tasks have little competition for CPU usage. In the case of the general software RTOS shown in FIG. 2, the CPU is not only a task execution circuit but also an RTOS execution circuit. On the other hand, in the case of the hardware RTOS in the basic example, the CPU is clarified as a task execution circuit, and the task scheduling function can be realized centering on a save circuit 120 and a task control circuit 200 described later.

FIG. 5 is a circuit diagram of the task processing apparatus 100 in the basic example.
The task processing device 100 includes a save circuit 120 and a task control circuit 200 in addition to the CPU 150. The CPU 150 is a task execution subject, and the save circuit 120 and the task control circuit 200 are circuits that play the role of the RTOS shown in FIG. The task scheduling process is led by the task control circuit 200.

  The CPU 150 includes an execution control circuit 152, a processing register 154, and an arithmetic circuit 160. The CPU 150 may be a general CPU described with reference to FIG. However, the CPU 150 in the basic example is slightly different from the CPU 84 shown in FIG. A specific circuit configuration will be described in detail with reference to FIG.

  The task control circuit 200 includes a task switching circuit 210, a semaphore table 212, an event table 214, a task selection circuit 230, and a state storage unit 220. The semaphore table 212 and the event table 214 will be described in detail with reference to FIG. The state storage unit 220 is a unit associated with each task. Hereinafter, the state storage unit 220 corresponding to the task A is expressed as “state storage unit 220_A”. Each state storage unit 220 holds task state data. The state data is information indicating task attributes such as task priority and state among context information. Specific data contents will be described later with reference to FIG. From each state storage unit 220, all state data of all tasks is constantly output to the task selection circuit 230. The task selection circuit 230 is a circuit that performs various task selection such as selection of a RUN-task based on the state data of each task. The task selection circuit 230 will also be described in detail with reference to FIG. When task switching circuit 210 detects a system call signal (SC) received from execution control circuit 152 or an interrupt request signal (INTR) from an external device, task switching circuit 210 executes a task switch.

  The execution control circuit 152 transmits a system call signal (SC) to the task switching circuit 210 when the system call is executed. When the task switching circuit 210 receives an interrupt request signal (INTR) from an interrupt controller (not shown), the task switching circuit 210 asserts a stop request signal (HR) to the execution control circuit 152. The execution control circuit 152 asserts a stop completion signal (HC) to the task switching circuit 210 when the operation of the CPU 150 is stopped. With these three types of signals, the CPU 150 and the task control circuit 200 are linked to each other.

  The save circuit 120 includes a load selection circuit 112 and a plurality of save registers 110. The save register 110 is also a unit associated with each task, and is a register for saving the processing data of the processing register 154. Therefore, the save register 110 has a data capacity equal to or greater than that of the processing register 154. Hereinafter, the save register 110 corresponding to the task A is expressed as “save register 110_A”. When instructed by the task switching circuit 210, the load selection circuit 112 loads data in any of the save registers 110 (hereinafter, data held by the save register 110 is referred to as “saved data”) into the processing register 154. To do.

  Each save register 110 always outputs each save data to the load selection circuit 112. When the task switching circuit 210 inputs a task selection signal (TS) designating a task ID to the load selection circuit 112, the load selection circuit 112 outputs the saved data of the save register 110 corresponding to the designated task to the processing register 154. . Further, when the task switching circuit 210 inputs a write signal (WT) to the processing register 154, the saved data is actually loaded into the processing register 154.

On the other hand, all the processing data in the processing register 154 is always output to the all save register 110. When the task switching circuit 210 asserts a write signal (WT) to a desired save register 110, the processing data is saved in the save register 110. Here, the number of bits that can be transmitted at one time by the bus connecting the processing register 154 and each save register 110 is set so that the processing data can be transferred in parallel. Therefore, the task switching circuit 210 can write the processing data to the save register 110 at a stretch by transmitting a write signal to the save register 110 once. The number of bits of the bus connecting the save register 110 and the load selection circuit 112, and the load selection circuit 112 and the CPU 150 are set in the same manner.
The task switch execution method for each of the system call and the interrupt request signal will be described below.
[1] System call execution

  When the execution control circuit 152 of the CPU 150 executes the system call, the execution control circuit 152 stops the clock of the CPU 150 (hereinafter referred to as “CPU clock (CLK)”). A specific stopping method will be described later in detail with reference to FIG. The execution control circuit 152 transmits a system call signal (SC) indicating the execution of the system call to the task switching circuit 210 of the task control circuit 200. When CLK is completely stopped, the execution control circuit 152 asserts a stop completion signal (HC) to the task switching circuit 210.

Nine signal lines are connected between the CPU 150 and the task switching circuit 210 for system call signal transmission. Nine signal lines correspond to the nine types of system calls described above. The execution control circuit 152 transmits a digital pulse through one of the system call signal lines according to the type of the system call that has been executed. The task switching circuit 210 can immediately detect the type of the system call executed according to which of the nine system call signal lines the digital pulse is detected from. The task switching circuit 210 selects necessary data from the output data of the task selection circuit 230 according to the type of the system call, and executes the process instructed by the system call. This process is executed on condition that HC is asserted. The relationship between the task switching circuit 210 and the task selection circuit 230 will be described in detail with reference to FIG. The system call parameters and return values are written to a predetermined general-purpose register 158 in the processing register 154. The task switching circuit 210 can read parameters and write return values to the general-purpose register 158. Here, it is assumed that task A, which is a RUN-task, executes a wait semaphore system call. Therefore, first, it is necessary to save the processing data of task A.
<Save context information of task A>

  The execution control circuit 152 inputs an SC signal indicating a wait semaphore system call to the task switching circuit 210. The execution control circuit 152 stops CLK and asserts HC when the stop is completed. The task switching circuit 210 outputs a semaphore ID of a semaphore to be waited for to a semaphore selection circuit 234, which will be described later, among various selection circuits built in the task selection circuit 230, and then selects a task B to be executed next select. The task switching circuit 210 writes predetermined data to the state storage unit 220_A. For example, the state of task A is changed from “RUN” to “READY” or “WAIT”. More specifically, the task switching circuit 210 outputs “WAIT” as data indicating the task state among the state data to the entire state storage unit 220 and then inputs a write signal (WT_A) only to the state storage unit 220_A. To do. In this way, the state of task A is changed.

Next, the task switching circuit 210 outputs a write signal (WT) to the save register 110_A. Since the processing data of the processing register 154 is always output to each save register 110, it is saved in the save register 110_A of the task A by this write signal (WT).
<Load context information of task B>

The task switching circuit 210 outputs a task selection signal (TS_B) designating the task B to the load selection circuit 112 when the change of the state data of the task A and the saving of the processing data are completed. As a result, the save data of the save register 110_B is output to the processing register 154. When the task switching circuit 210 outputs a write signal (WT) to the processing register 154, the saved data of task B is loaded into the processing register 154. Further, the task switching circuit 210 writes predetermined data in the state storage unit 220 of task B. For example, the state of task B is changed from “READY” to “RUN”. When the above processing is completed, the execution control circuit 152 restarts the CPU clock. The CPU 150 starts executing the task B by the resumed CPU clock. Further details of the processing method will be described later with reference to FIG.
[2] Generation of interrupt request signal

  The task switching circuit 210 detects an interrupt request signal (INTR) from a peripheral device. More specifically, the interrupt request signal (INTR) is transmitted to the task switching circuit 210 from an interrupt controller (not shown). A parameter indicating the level of the interrupt request signal (INTR) is recorded in a register built in the interrupt controller. The task switching circuit 210 asserts a stop request signal (HR) to the execution control circuit 152, and the execution control circuit 152 stops the CPU clock. As in the case of system call execution, the task switching circuit 210 saves the processing data of the RUN-task in the save register 110. Next, the task switching circuit 210 starts a special task. There is one type of special task that is activated regardless of the parameters of the interrupt request signal. The special task reads the INTR parameter from the built-in register of the interrupt controller, and executes processing according to the parameter. The processing executed by the special task may be execution of a set event system call or a set semaphore system call, or activation of a general task. Depending on the parameters, the special task may end without executing any special processing. What processing is executed according to the parameters of INTR depends on the implementation of the special task. When the execution of the special task is completed, the next RUN-task is selected from the READY-tasks.

  The task switching circuit 210 causes the CPU 150 to load the processing data of the save register 110 corresponding to the special task. The time required for switching from the general task to the special task can be estimated in advance by the operation clock of the task control circuit 200. When the operation clock of the task switching circuit 210 elapses after the HR is asserted to the execution control circuit 152, the task switching circuit 210 negates HR to cancel the stop of the CPU clock. The execution control circuit 152 restarts the CPU clock when HR is negated. At this time, the task switching circuit 210 completes the task switch from the general task to the special task. Details of the processing method will be described later with reference to FIG.

In either case,
(A) Saving / loading of processing data (B) The core processing of task switching such as task state transition and RUN-task selection is realized by hardware. Regarding (A) and (B), the need to access the TCB on the memory is eliminated, which contributes to the speedup of the task switch. In realizing the task processing apparatus 100, the CPU 150 need only have a function of stopping and restarting the CPU clock. Note that the realization of all of these functions by hardware does not limit the scope of the present invention. For example, those skilled in the art will understand that the main functions of (A) or (B) may be implemented by hardware, and some RTOS functions may be implemented by software to assist the hardware functions. It is a place.

FIG. 6 is a circuit diagram of the CPU 150 of FIG.
Unlike the CPU 84 in FIG. 3, the processing register 154 includes only one surface for both the special register 156 and the general-purpose register 158. An input bus from the load selection circuit 112, an output bus to the save register 110, and a signal line for a write signal (WT) from the task switching circuit 210 are added to the processing register 154, respectively. The execution control circuit 152 inputs data of a desired register among the processing registers 92 to the arithmetic circuit 160 by a control signal (CTRL) for the output selector 164. The calculation result is input to the input selector 162. The execution control circuit 152 inputs a calculation result to a desired register among the processing registers 154 by a control signal (CTRL) to the input selector 162. The execution control circuit 152 executes the task while updating the program counter of the special register 156.

  The processing data is saved in the save register 110 instead of the TCB on the memory. The processing data is always output from the processing register 154 to each save register 110. The task switching circuit 210 controls which save data is actually saved in which save register 110 as described above.

  The save data is loaded into the processing register 154 from the save register 110 instead of the TCB on the memory. The task switching circuit 210 controls which save register 110 processing data is actually loaded at which timing as described above.

  The bus connecting the processing register 154 and the load selection circuit 112, and the processing register 154 and the save register 110 is a bus having the number of bits that can transfer the processing data in parallel at one time. Therefore, reading and writing can be performed at once by the write signal (WT) from the task switching circuit 210. The general software RTOS needs to temporarily occupy the processing register 154 at the time of task switching. On the other hand, the hardware RTOS in the basic example does not need to load special processing data for task switch processing into the processing register 154. When switching from task A to task B, the task B processing data is simply loaded after saving the task A processing data, so two processing registers 154 are prepared for the system and the user, or stacks are prepared. There is no need to perform data exchange processing via

FIG. 7 is a circuit diagram showing a mechanism by which the execution control circuit 152 stops the CPU clock.
The inputs of the second AND gate 174 are the original clock (CLK0) and the output of the first AND gate 172, and the latter is negative logic. The output of the first AND gate 172 is a stop completion signal (HC). Since the stop completion signal (HC) is normally 0, the second AND gate 174 outputs the input original clock (CLK0) as it is as the CPU clock (CLK). The CPU 150 operates in response to the CPU clock output from the second AND gate 174. When the output of the first AND gate 172 is “1”, in other words, when the stop completion signal (HC) = 1, the output of the second AND gate 174 is fixed to zero and the CPU clock (CLK) stops.

  The inputs of the first AND gate 172 are the output of the OR gate 176 and the CPU busy signal (CBUSY), the latter being negative logic. CBUSY is a signal output from a known state machine that generates an internal cycle of the CPU 150, and is a signal that is “1” when the CPU 150 is in a stoppable state. For example, when the arithmetic circuit 94 completes the last instruction of a single instruction being executed or a plurality of locked instructions, the CPU can be stopped, or the supply of the CPU clock has already been stopped. "0" when

The inputs of the OR gate 176 are an output (SC_DETECT) of the instruction decoder 170 and a stop request signal (HR) from the task switching circuit 210. The instruction decoder 170 includes a latch circuit that holds SC_DETECT. The instruction decoder 170 receives the data (FD) fetched from the CPU 150 and outputs SC_DETECT = 1 when the FD is a system call instruction. Even if the FD subsequently changes due to the built-in latch circuit, the instruction decoder 170 continues to output SC_DETECT = 1. The instruction decoder 170 also receives a write signal (WT) for the processing register 154 of the task switching circuit 210. When WT changes from 0 to 1, loading of the saved data into the processing register 154 is executed as described above. This WT is a pulse signal that returns from 1 to 0 after a predetermined time. When WT changes from 1 to 0, the latch circuit of instruction decoder 170 is reset and instruction decoder 170 negates SC_DETECT. The relationship between SC_DETECT and the write signal (WT) will be described in detail with reference to FIG. The instruction decoder 170 in the basic example is a device provided exclusively for the execution control circuit 152 in order to determine whether or not the execution target instruction is a system call. As a modification, the instruction decoder 170 may be shared with a CPU decoder in charge of the decoding stage of the CPU 150. In this case, the instruction decoder 170 can be realized by adding a function of outputting SC_DETECT = 1 to the CPU decoder when the decoded data is a system call instruction.
When the interrupt request signal (INTR) is generated, the task switching circuit 210 asserts a stop request signal (HR) to the execution control circuit 152. That is, the output of the OR gate 176 becomes “1” when a system call is executed or a stop request signal (HR) is asserted.

  In summary, when a system call is executed or an interrupt request signal is generated and the CPU busy signal becomes “0”, the output of the first AND gate 172 becomes “1”, and the second AND 174 outputs the CPU clock. Will not be output.

FIG. 8A is a time chart showing the relationship between various signals when an interrupt request signal is generated.
In the figure, first, at time t ₀ , the task switching circuit 210 detects an external interrupt request signal (INTR). The task switching circuit 210 asserts a stop request signal (HR) to the execution control circuit 152 in order to execute a special task. Input timing _{t 1} is almost simultaneous with the detection timing _{t 0.} At time _{t 1,} the state machine of the CPU150 is "in the task execution" is a CBUSY = 1. Since HR = 1, the OR gate 176 outputs “1”, but the CPU 150 does not stop because CBUSY = 1. Therefore, even if HR = 1 is input, the CPU clock (CLK) is output in synchronization with the original clock (CLK0) for a while.

As time elapses, it changes CBUSY = 0 at time _{t 2.} Since HR = 1 already, the first AND gate 172 outputs HC = 1, and the CPU clock output from the second AND gate 174 is fixed to 0. On the other hand, the task switching circuit 210 starts task switching from a general task to a special task when HC is asserted. As will be described in detail later, the time required for the task switch is several times as the operation clock of the task control circuit 200. The task control circuit 200 negates the stop request signal (HR) on condition that the operation clock of the task control circuit 200 has changed a predetermined number of times after HC is asserted (time t ₃ ). Since HR = 0, the execution control circuit 152 restarts the CPU clock (CLK). When the CPU 150 resumes the processing, the CPU 150 changes CBUSY from 0 to 1 (time t ₄ ). Thus, the period from time t ₂ the CPU clock is stopped at time t _3, so that the task switch to a special task is performed from the general task.
As another processing method, HR may be negated on the condition that the task control circuit 200 has completed the task switch instead of being conditional on the operation clock of the task control circuit 200 changing a predetermined number of times. Good. Then, the execution control circuit 152 may negate HC on the condition that HR is negated. When HC = 0, the execution control circuit 152 restarts the CPU clock (CLK). In this way, the execution of the task may be resumed.

FIG. 8B is a time chart showing the relationship between various signals when a system call is executed.
In the figure, first, at time t ₀ , the instruction decoder 170 detects a system call and changes SC_DETECT from 0 to 1. At time t ₀ , the state machine of the CPU 150 is “task executing” and CBUSY = 1. Since SC_DETECT = 1, the OR gate 176 outputs “1”, but the CPU 150 does not stop because CBUSY = 1. Therefore, even if SC_DETECT = 1 is output, the CPU clock (CLK) is output in synchronization with the original clock (CLK0) for a while.

As time elapses, it changes CBUSY = 0 at time _{t 1.} Since SC_DETECT = 1 and CBUSY = 1, HC is negated and the CPU clock is stopped. When HC = 0 is input, task switching circuit 210 starts task switch processing and outputs a write signal (WT) to CPU 150. The saved data is loaded into the processing register 154 at time t ₂ when WT changes from 0 to 1. Write signal (WT), since the pulse signal, the WT = 0 to time _{t 3} after a predetermined time. SC_DETECT latched in the instruction decoder 170 is reset by detecting the falling edge of WT: 1 → 0 (time t ₄ ). At this time, CBUSY changes from 0 to 1. Since CBUSY = 1, HC = 0 and the CPU clock is restarted. Between time t ₁ at which the CPU clock is stopped at time t _4, so that the task switch is performed.
As another processing method, instead of being conditional on the detection of the fall of WT: 1 → 0, the task control circuit 200 completes the task switch and negates HR. HC may be negated. SC_DETECT is reset on condition that HC = 0. The execution control circuit 152 restarts the CPU clock (CLK), and CBUSY changes from 0 to 1.

  In any case, the CPU 150 does not need to recognize that the RUN-task switching has been performed while the CPU clock is stopped. Since the task switching circuit 210 performs task switching while the CPU clock is stopped and the CPU 150 is frozen, the processing of the CPU 150 and the processing of the task control circuit 200 are sequentially separated.

FIG. 9 is a schematic diagram for explaining the stop timing of the CPU clock in the pipeline processing.
The CPU 150 executes a task by executing a plurality of instructions while sequentially reading them from the memory to the processing register 154. The instruction which is the execution unit of this task is decomposed into the following four phases.
1. F (fetch): fetches an instruction from the memory.
2. D (decode): interprets an instruction.
3. E (execution): execute an instruction.
4). WB (write back): The execution result is written in the memory.

  When a certain task sequentially executes instruction 1 to instruction 5, F from instruction 2 may be executed after executing from instruction F to WB. However, for more efficient execution, execution of instruction 2 is often initiated during execution of instruction 1. Such a processing method is called pipeline processing. For example, when the instruction 1 reaches the phase D, the F phase of the instruction 2 is started. When the instruction 1 reaches the phase E, the D phase of the instruction 2 and the F phase of the instruction 3 are executed. Thus, by increasing the number of instructions executed per unit time, the execution time for each task can be reduced.

  Furthermore, each phase may be subdivided into two phases. For example, the F phase is separated into two phases F1: F2. When instruction 1 reaches the phase of F2, the phase of F1 of instruction 2 is started. When the instruction 1 reaches the phase D1, the F2 phase of the instruction 2 and the F1 phase of the instruction 3 are executed. By subdividing the phases, the calculation resources of the CPU 150 can be used more efficiently. In FIG. 9, the CPU clock stop timing when a system call occurs in the pipeline processing in which each phase is divided into two phases will be described.

  In the figure, instruction 1 starts processing at the timing of CPU clock “0”. Decoding of the instruction 1 is completed at the timing of the CPU clock “4”. Assume that instruction 1 is a system call. The instruction decoder 170 changes SC_DETECT from 0 to 1. Next, the condition for SC_DETECT to return from 1 to 0 is that the write signal (WT) from the task switching circuit 210 to the processing register 154 changes from 1 to 0. Even if SC_DETECT = 1, since instructions 2 to 5 are already being executed or have been started, CBUSY = 1 remains. Therefore, the second AND gate 174 continues to output the CPU clock. However, when SC_DETECT = 1, the execution control circuit 152 temporarily stops updating the program counter so that a new instruction is not fetched. Therefore, the instruction 6 and later are not fetched from the memory.

Although the instruction 1 is completely executed at the timing of the CPU clock “8”, since the instructions 2 to 5 are being executed, the CPU busy signal remains “1”. When the timing of the CPU clock “12” is reached, execution of the instruction 5 is completed. At this time, the CPU busy signal becomes “0”. After that, the supply of the CPU clock is stopped according to the process related to FIG. The task switching circuit 210 saves the processing data at the stage where the instructions up to the instruction 5 are completed in the save register 110. According to such a stopping method, the task can be switched without wasting the execution result of the instruction after the system call is executed. When the task switch is completed, the CPU busy signal is set to “1” again, and the processing of the instruction decoder 170 is resumed. Thus, the CPU clock is supplied again.
As another processing method, the CPU busy signal may be set to “0” and the supply of the CPU clock may be stopped when the execution of the system call instruction is completed. In this case, another instruction that has been executed simultaneously with the system call instruction is stopped during execution. The intermediate processing result of the interrupted instruction is recorded in the processing register 154 and then saved in the save register 110. The next time this task becomes a RUN-task, the continuation of the suspended instruction is executed. For example, when an instruction is interrupted at the stage where the fetch is completed, the instruction and operand read from the memory are saved in the save register 110. When the task is resumed, the data in the save register 110 is loaded into the processing register 154, and the subsequent processing is executed from the decode stage.

FIG. 10 is a circuit diagram showing the relationship between the state storage unit 220 and the task switching circuit 210.
The state storage unit 220 includes a state register 250 and a timer 252. The state storage unit 220 holds task state data. The timer 252 is a timer that starts when the task transitions to the READY state or the WAIT state. The time that has elapsed since the task transitioned to the READY state is referred to as “READY elapsed time”, and the time that has elapsed since the task transitioned to the WAIT state is referred to as “WAIT elapsed time”. The timer 252 always outputs the value as a TIM signal. When a task is switched to a READY state or a WAIT state at the time of task switching, the task switching circuit 210 drives the timer 252 of the task to start time measurement.

The state storage unit 220 is a set of registers shown below.
(A) Task ID register 254: Holds a task ID. An ID signal indicating a task ID is constantly output from the task ID register 254 to the task selection circuit 230. Hereinafter, the ID signal output from the task ID register 254 of the task A to the task selection circuit 230 is referred to as “ID_A signal”. The same applies to other signals output from the state storage unit 220.
(B) Task priority order register 256: Holds task priority order. The task priority order register 256 always outputs a PR signal indicating the task priority order. “0” is the highest priority, and a larger value indicates a lower task priority.
(C) Task status register 258: indicates a task status. Any one of STOP, READY, RUN, WAIT, and IDLE is always output as the ST signal. Note that IDLE is a state before the task is initialized.
(D) Task activation address register 260: indicates the TCB address of the task in the memory. The output is an AD signal.
(E) Wait reason register 262: When the task is in the WAIT state, it indicates the reason for waiting as part of the WAIT cancellation condition. The reason for waiting is one of “waiting for semaphore”, “waiting for event”, and “waiting for mutex”. The output is a WR signal.
(F) Semaphore ID register 264: Holds the semaphore ID of the semaphore to be waited (hereinafter simply referred to as “waiting semaphore”) when the task is in the WAIT state because of waiting for semaphore The output is a SID signal.
(G) Mutex ID register 265: Holds the mutex ID of the mutex to be waited (hereinafter simply referred to as “waiting mutex”) when the task is in the WAIT state because of waiting for the mutex. The output is a MID signal.
(H) Event ID register 266: Holds an event ID of an event to be waited (hereinafter simply referred to as “waiting event”) when the task is in the WAIT state because of waiting for an event. The output is an EID signal.
(I) Wait flag register 268: Holds a wait flag pattern when the task is in the WAIT state because of waiting for an event. The output is the FL signal.
(J) Flag condition register 270: Holds a flag condition when the task is in the WAIT state because of waiting for an event. The output is an FLC signal. The standby flag pattern and flag conditions will be described later.
(K) Flag initialization register 272: Holds data indicating the presence or absence of a standby flag pattern. The output is the FLI signal.
(L) Timeout counter 274: In a WAIT system call, a timeout value is specified as a variable. The timeout counter 274 holds a timeout value. The task switching circuit 210 periodically decrements the timeout value of each timeout counter 274. The output is a TO signal. Instead of the task switching circuit 210 decrementing the timeout value, the timeout counter 274 itself may autonomously decrement its own timeout value periodically.

The task selection circuit 230 selects a task based on various signals output from each state storage unit 220. The task selection circuit 230 includes the following circuits.
(A) Execution selection circuit 232: When the task is switched, the next RUN-task is selected. The execution selection circuit 232 always selects one of the tasks as a RUN-task based on the state data constantly output from the state storage unit 220. There are four types of input signals of the execution selection circuit 232: ID, ST, PR, and TIM. The output is the task ID of the next RUN-task. A detailed circuit configuration will be described in detail with reference to FIG.
(B) Semaphore selection circuit 234: Selects a task to transition from the WAIT state to the READY state by executing a release semaphore system call. A semaphore ID of a semaphore released by a release semaphore system call (hereinafter simply “release semaphore”) is input from the task switching circuit 210. There are six types of input signals from the state storage unit 220: ID, ST, WR, PR, SID, and TIM. The output signal is a task ID of a task that makes a transition from the WAIT state to the READY state. If there is no corresponding task, a predetermined value such as -1 is output. A more specific circuit configuration will be described in detail with reference to FIG.
(C) Event selection circuit 236: Selects a task that transitions from the WAIT state to the READY state by executing the set event system call. An event ID of an event (hereinafter simply referred to as “setting event”) set by the set event system call is input from the task switching circuit 210. There are six types of input signals from the state storage unit 220: ID, ST, WR, EID, FL, and FLC. The output signal outputs the task ID of the task that transitions from the WAIT state to the READY state, and the FL and FLC of the task.
(D) Timeout detection circuit 238: Among the tasks in the WAIT state, a task for which the timeout value of the timeout counter 274 has become zero is detected. The timeout detection circuit 238 is driven every time the timeout value is updated. There are three types of input signals to the timeout detection circuit 238: ID, ST, and TO. The output signal is the task ID of the corresponding task. If there is no corresponding task, a predetermined value such as -1 is output.
(E) Mutex circuit 240: Selects a task that transitions from the WAIT state to the READY state by executing the release mutex system call. The mutex ID of the mutex released by the release mutex system call (hereinafter simply referred to as “release mutex”) is input from the task switching circuit 210. There are six types of input signals from the state storage unit 220: ID, ST, WR, PR, SID, and TIM. The output signal is a task ID of a task that makes a transition from the WAIT state to the READY state. If there is no corresponding task, a predetermined value such as -1 is output.
(F) Search circuit 242: When a task ID is input from the task switching circuit 210, all state data of the task is output.

In the following, regarding the task switch, RUN-task selection, semaphore, event, mutex, and timeout will be described in comparison with a general technique, particularly focusing on the processing of the task selection circuit 230.
[RUN-task selection]
[1] Selection of RUN-task by general software RTOS

FIG. 11 is a diagram showing a task ready list used when selecting a RUN-task by a general RTOS.
The task ready list is formed on a memory and is a list in which TCBs of each READY-task are linked by pointers. The priority level pointer 280 is provided for each task priority level and points to the head address of the TCB of the task having the corresponding task priority level. In the case of the task ready list shown in the figure, the priority priority pointer 280 of the task priority “0” addresses the TCB of the task A, and the priority priority pointer 280 of the task priority “1” addresses the TCB of the task B. ing. The TCB of task A further addresses the TCB of task D. The general software RTOS selects the next RUN-task while scanning the task ready list. At this time, RTOS
A. RUN--Transitions the task from RUN to READY.
B. The next RUN-task is selected, and the task state of the task is changed from READY to RUN.
A two-stage process is performed. Each processing by the software RTOS is disassembled as follows.
<RUN-task state transition>

Here, RUN-task is described as task J.
A1. The RTOS holds the task ID of the RUN-task in the memory. Based on this task ID, the TCB address of task J is acquired.
A2. Access TCB and obtain task priority of task J. It is assumed that the task priority is “0”.
A3. A priority order pointer 280 corresponding to the task priority order of task J is acquired from the task ready list shown in FIG.
A4. The TCB indicated by the acquired priority order pointer 280 is detected. Here, the TCB of task A is detected.
A5. Traces the pointer of the task A TCB and detects the last TCB. In the figure, task F is the last.
A6: The task F TCB pointer is set to address the task J TCB. In this way, the TCB of task J is added to the task ready list.
A7. “READY” is set in the TCB of task J. Further, the processing data is copied to the register storage area of the TCB.
<READY-task state transition>

B1. The RTOS detects which TCB the priority level pointer 280 of the task priority level “0” indicates. If there is no TCB, it is detected whether the priority order pointer 280 of the task priority “1” indicates any TCB. One task is specified while lowering the task priority until a TCB is found. In the case of the figure, task A is specified.
B2. Remove task A from the task ready list. Specifically, the priority order pointer 280 of the task order “0” is rewritten so as to address not the task A but the task D TCB. Also, NULL is set so that the pointer of task A does not address task D. Thus, the TCB for task A is removed from the task ready list.
B3. “RUN” is set in the TCB of task A. Further, the processing data saved in the TCB register storage area of task A is loaded into the processing register.

A general software RTOS performs task switching by such a task ready list. That is, the policy for RTOS to select a RUN-task from a plurality of READY-tasks is as follows.
1. READY-task (first condition).
2. READY-task having the highest task priority (second condition).
3. When there are a plurality of tasks with the highest task priority, the task that has entered the READY state is the oldest task (third condition).
These three conditions are collectively referred to as “RUN task selection conditions”. The execution selection circuit 232 of the task processing apparatus 100 implements such a task scheduling function of RTOS by hardware.
[2] RUN-task selection by hardware RTOS in basic example

FIG. 12 is a circuit diagram of the execution selection circuit 232.
Here, a description will be given assuming that a RUN-task is selected from eight tasks of task 0 to task 7. The execution selection circuit 232 includes four first comparison circuits 290 (290a to 290d), two second comparison circuits 292 (292a and 292b), and one third comparison circuit 294. Further, eight determination circuits 296 (296a to 296h) are also included.
The determination circuit 296 receives the ST signal indicating the task state, and outputs a CID signal indicating “1” if READY and “0” if not READY. The determination circuit 296 performs determination based on the first condition among the RUN task selection conditions. The first comparison circuit 290 receives the IDs of the two tasks, PR, TIM, and the CID signal from the determination circuit 296 as inputs.

Description will be made by paying attention to the first comparison circuit 290a. The first comparison circuit 290a compares the task 0 and the task 1, and selects a more suitable task based on the RUN task selection condition described above.
First determination: First, the CID signals output from the determination circuit 296a and the determination circuit 296b are compared. If either one is “1”, in other words, if only one of the tasks is in the READY state, the first comparison circuit 290a outputs the ID, PR, and TIM of the task. If both are “0”, that is, if no task is in the READY state, the first comparison circuit 290a outputs ID = PR = TIM = NULL. This indicates that no task has been selected. If both are “1”, that is, if any task is in the READY state, the next second determination is executed.
Second determination: The PR signal of task 0 and the PR signal of task 1 are compared, and a task having a higher task priority is selected. For example, if the task priority of task 0 is “1” and the task priority of task 1 is “2”, the ID, PR, and TIM of task 0 are output. According to the second determination, a task having a higher task priority is selected as a RUN-task candidate. If the task priorities of task 0 and task 1 are the same, the next third determination is executed.
Third determination: The task 0 TIM signal is compared with the task 1 TIM signal, and the task having the longer READY elapsed time is selected. If the READY elapsed time is the same, task 0 is selected. Since the determination can be made simply by comparing the magnitudes of the elapsed times, TCB order management like a task ready list becomes unnecessary.

  In this way, task 0 and task 1, task 2 and task 3, task 4 and task 5, task 6 and task 7 are respectively compared according to the RUN task selection condition. The second comparison circuit 292 further narrows down RUN-task candidates based on the outputs from the two first comparison circuits 290. The second comparison circuit 292a executes task selection based on the outputs of the first comparison circuit 290a and the first comparison circuit 290b. For this reason, the second comparison circuit 292a outputs the ID, PR, and TIM of the task that best meets the RUN task selection condition among the tasks 0 to 3. The same applies to the third comparison circuit 294, and the third comparison circuit 294 outputs the task ID of one of the tasks 0 to 7.

According to such a processing method, the RUN task selection condition can be realized by hardware. The general software RTOS selects the RUN-task while accessing the task ready list. However, the execution selection circuit 232 in the basic example selects the RUN-task based on the state data constantly output from the state storage unit 220. is doing. The processing of the execution selection circuit 232 is summarized as follows.
<RUN-task state transition>

Here, RUN-task is described as task J.
A1. The task switching circuit 210 sets “READY” in the task status register 258 of task J.
A2. The task switching circuit 210 sets the timer 252 for task J and starts measuring the elapsed READY time.
Thus, task J makes a state transition from RUN to READY. The processing data is saved in the save register 110 of the task J as described above. Since the bus connecting the processing register 154 and the save register 110 can transmit processing data in parallel, the processing of A1 and A2 can be executed in one clock time.
<READY-task state transition>

B1. The task switching circuit 210 specifies a RUN-task from the task ID output by the execution selection circuit 232 when the state transition of the task J is completed. “RUN” is set in the task status register 258 of this task.
Thus, the specified task makes a state transition from READY to RUN. The processing data of the identified task is loaded from the save register 110 to the processing register 154. Since the bus connecting the save register 110 and the processing register 154 is also the number of bits that can transmit processing data in parallel, the processing of B1 can be executed in one clock time.

The software RTOS consumes a large amount of CPU clock time due to access to a task ready list or the like at the time of task switching. On the other hand, the task control circuit 200 in the basic example can complete the task switch in a short time. Since the state storage unit 220 always outputs the state data to the execution selection circuit 232, the execution selection circuit 232 always outputs the task ID of any task. The RUN-task selection process is not started after the task switch occurs, but the selection of the RUN-task by the output of the execution selection circuit 232 when the task switch occurs also contributes to the speedup of the task switch. is doing. Here, although it has been described that there are eight tasks, it is possible to cope with more tasks by increasing the number of stages of the comparison circuit.
[Semaphore processing]

FIG. 13 is a diagram showing a wait semaphore list used in semaphore processing by a general RTOS.
Before describing the wait semaphore list, a brief description of semaphores will be given. In the semaphore table 212, a semaphore ID and a semaphore counter are recorded in association with each other. The semaphore counter is set to a finite number as an initial value. For example, it is assumed that semaphore ID = 4 and semaphore counter = 3 are set. When any task executes a wait semaphore system call with the semaphore with semaphore ID = 4 as a waiting semaphore, the task switching circuit 210 decrements the semaphore counter of the waiting semaphore. The semaphore counter is decremented every time acquisition is requested by a wait semaphore event call. A task that has executed a wait semaphore system call with a semaphore whose semaphore counter is 0 as a standby semaphore makes a transition to the WAIT state.

On the other hand, when any task executes a release semaphore system call with the semaphore with semaphore ID = 4 as a release semaphore, the task switching circuit 210 increments the semaphore counter in the semaphore table 212. Summary,
When semaphore counter> 0: The task that executed the wait semaphore system call transits from RUN to READY. At this time, the semaphore counter is decremented.
When semaphore counter = 0: The task that has executed the wait semaphore system call transitions from RUN to WAIT. The semaphore counter is not decremented.
In order for the task that executed the wait semaphore system call to transition from the WAIT state to the READY state, another task needs to execute the release semaphore system call.
[1] Semaphore processing by general software RTOS

A general software RTOS manages a TCB of a task in a WAIT state because of waiting for a semaphore (hereinafter, particularly referred to as “semaphore waiting task”) by a wait semaphore list. The wait semaphore list is a list having the same shape as the task ready list of FIG. 11, and is formed on the memory. The TCB of each semaphore waiting task is linked by a pointer. The priority order pointer 280 indicates the head address of the TCB of the semaphore waiting task with the corresponding task priority order.
When a general software RTOS executes a release semaphore system call, it scans this wait semaphore list and selects a semaphore waiting task to be changed from the WAIT state to the READY state. The RTOS processing at the time of executing the wait semaphore system call and the release semaphore system call is as follows.
<Execution of wait semaphore system call>

Here, RUN-task is described as task J.
A1. The RTOS holds the task ID of the RUN-task in the memory. Based on this task ID, the TCB address of task J is acquired.
A2. The semaphore counter of the waiting semaphore specified in the wait semaphore system call is detected. Hereinafter, the process branches according to the value of the semaphore counter.
(When semaphore counter> 0)
A3. The RTOS decrements the semaphore counter of the standby semaphore.
A4. “READY” is set in the TCB of task J. In this case, the TCB of task J is added to the task ready list.
(When semaphore counter = 0)
A3. Access TCB and obtain task priority of task J. It is assumed that the task priority is “0”.
A4. A priority pointer corresponding to the task priority of task J is acquired from the wait semaphore list.
A5. The TCB indicated by the acquired priority order pointer is detected. Here, the TCB of task A is detected.
A6. Traces the pointer of the task A TCB and detects the last TCB. In the figure, task F is the last.
A7: The task F TCB pointer is set to address the task J TCB. Thus, the TCB of task J is added to the wait semaphore list.
A8. “WAIT” is set in the TCB of task J. A semaphore ID of the standby semaphore is also set.
<Execution of release semaphore system call>

B1. The RTOS searches for a semaphore waiting task having the release semaphore as a waiting semaphore while following the tasks with the task priority “0” in order. If not, the task with the task priority “1” is set as a search target. Processing branches depending on whether or not a semaphore waiting task whose release semaphore is a waiting semaphore is detected.
(When detected)
B2. A description will be given assuming that the detected task is task E. “READY” is set in the TCB of task E. Also, the semaphore ID of the standby semaphore is cleared.
B3. The task E TCB is removed from the wait semaphore list.
B4. The state of the task that has released the semaphore is changed from RUN to READY. The TCB for this task is added to the task ready list.
(When not detected)
B2. Increment the semaphore counter.
B3. The state of the task that has released the semaphore is changed from RUN to READY. The TCB for this task is added to the task ready list.

A general software RTOS performs semaphore-related processing by managing such a wait semaphore list. When releasing a semaphore, the policy for RTOS to select a READY-task from a plurality of WAIT-tasks is as follows.
1. WAIT-task (first condition).
2. Of the WAIT-tasks, the task must be a release semaphore as a standby semaphore (second condition)
3. When there are a plurality of such tasks, the task has the highest task priority (third condition).
4). When there are a plurality of tasks having the highest task priority, the task that has entered the WAIT state is the oldest task (fourth condition).
These four conditions are collectively referred to as “semaphore standby release conditions”. The semaphore selection circuit 234 of the task processing device 100 realizes such a task scheduling function of RTOS by hardware.
[2] Semaphore processing by hardware RTOS in basic example

FIG. 14 is a circuit diagram of the semaphore selection circuit 234.
Here, description will be made on the premise of eight tasks of task 0 to task 7. The semaphore selection circuit 234 includes four first comparison circuits 300 (300a to 300d), two second comparison circuits 302 (302a and 302b), and one third comparison circuit 304. Also, eight determination circuits 306 (306a to 306h) are included.
The determination circuit 306 is a circuit that receives the ST, WR, and SID signals from the state storage unit 220 and the signal indicating the semaphore ID from the task switching circuit 210 as inputs. The semaphore ID input here is the semaphore ID of the released semaphore. The determination circuit 306 outputs a CID signal indicating “1” if the task is a semaphore waiting task with the released semaphore as a standby semaphore, and “0” otherwise. The determination circuit 306 is a circuit that outputs a determination result regarding the first condition and the second condition among the semaphore standby cancellation conditions. The first comparison circuit 300 receives the IDs of the two tasks, PR, TIM, and the CID signal from the determination circuit 306 as inputs.

The first comparison circuit 300 is a circuit that performs determination on the third condition and the fourth condition among the semaphore standby cancellation conditions. The same applies to the second comparison circuit 302 and the third comparison circuit 304. As is apparent, the second condition and the third condition of the RUN task selection condition are the same as the third condition and the fourth condition of the semaphore standby cancellation condition. Each comparison circuit of the execution selection circuit 232 is a circuit that compares task state data (PR, TIM). On the other hand, each comparison circuit of the semaphore selection circuit 234 is also a circuit that compares task status data (PR, TIM). Therefore, the first comparison circuit 290 of the execution selection circuit 232 and the first comparison circuit 300 of the semaphore selection circuit 234 are circuits that incorporate the same logic and can be shared. Each task is subjected to the determination process of the first comparison circuit 300 after the determination circuit 306 determines the first condition and the second condition. After that, one of the task IDs is output from the third comparison circuit 304 by a determination process equivalent to the execution selection circuit 232. Processing when a wait semaphore system call and a release semaphore system call are executed is as follows.
<Execution of wait semaphore system call>

Here, RUN-task is described as task J.
A1. The task switching circuit 210 detects the semaphore counter of the semaphore specified in the wait semaphore system call from the semaphore table 212. Hereinafter, the process branches according to the value of the semaphore counter.
(When semaphore counter> 0)
A2. The task switching circuit 210 decrements the semaphore counter of the semaphore table 212.
A3. “READY” is set in the task status register 258 of the task J. At this time, the task switching circuit 210 sets the RUN-task timer 252 and starts measuring the READY elapsed time.
(When semaphore counter = 0)
A2. The task switching circuit 210 sets “WAIT” in the task status register 258 of the task J, “waiting for semaphore” in the waiting reason register 262, sets the semaphore ID of the waiting semaphore in the semaphore ID register 264, sets the timer 252 and waits for WAIT Start measuring time.
In this way, the task that executed the wait semaphore system call makes a state transition from RUN to READY or WAIT.
<Execution of release semaphore system call>

B1. The task switching circuit 210 inputs the semaphore ID of the released semaphore to each determination circuit 306. Each determination circuit 306 determines the success or failure of the first condition and the second condition of the semaphore standby cancellation conditions for this semaphore ID. Accordingly, each first comparison circuit 300 selects a task based on the third condition and the fourth condition.
(When any determination circuit 306 outputs “1” and the third comparison circuit 304 outputs any task ID)
B2. “READY” is set in the task status register 258 of the detected task, the waiting reason register 262 and the semaphore ID register 264 are cleared, and the timer 252 is made to measure the READY elapsed time.
B3. The task status register 258 of the task that executed the system call is set to “READY”, and measurement of the READY elapsed time is started.
(None of the determination circuits 306 outputs “1”, and the third comparison circuit 304 does not output any task ID)
B2. The task switching circuit 210 increments the semaphore counter of the semaphore table 212.
B3. The state of the task that executed the system call is changed from RUN to READY.

Since the state storage unit 220 always outputs the state data to the semaphore selection circuit 234, when the task switching circuit 210 inputs the semaphore ID to the determination circuit 306, the semaphore selection circuit 234 can immediately execute the selection process.
[Mutex processing]

Mutexes, like semaphores, are also used for synchronization between tasks. Mutexes and semaphores differ in the following respects.
1. The semaphore counter can set an integer of 1 or more. In contrast, a mutex is a special semaphore with a semaphore counter of 1 or 0. When the semaphore counter is 2 or more, two or more tasks can acquire the same semaphore. However, in the case of a mutex, only one task can acquire a mutex at any given time.
2. A task that can release a semaphore by a release semaphore system call is not limited to a task that has acquired a semaphore by a wait semaphore system call. On the other hand, the task that can release the mutex by the release mutex system call is only the task that has acquired the mutex by the wait mutex system call.

The policy for selecting a READY-task from a plurality of WAIT-tasks when releasing a mutex is as follows.
1. WAIT-task (first condition).
2. Among WAIT-tasks, the task must have a release mutex as a waiting mutex (second condition)
3. When there are a plurality of such tasks, the task has the highest task priority (third condition).
4). When there are a plurality of tasks having the highest task priority, the task that has entered the WAIT state is the oldest task (fourth condition).
These four conditions are collectively referred to as “mutex standby release conditions”.

Accordingly, the processing of the hardware RTOS of the basic example when executing the wait mutex system call and the release mutex system call is as follows. The semaphore table 212 holds a mutex ID and occupation state data indicating whether or not the mutex is occupied by any task. The occupation state data is “0” when not occupied, and becomes the task ID of the task occupying the mutex when occupied.
<Execution of wait mutex system call>

Here, RUN-task is described as task J.
A1. The task switching circuit 210 detects whether the mutex designated in the wait mutex system call is occupied. Hereinafter, the process branches depending on the occupation state of the mutex.
(When the mutex is not occupied)
A2. The task switching circuit 210 records the task ID of the task that executed the system call as the mutex occupation data.
A3. “READY” is set in the task status register 258 of the task J. At this time, the task switching circuit 210 sets the RUN-task timer 252 and starts measuring the READY elapsed time.
(When mutex is occupied)
A2. The task switching circuit 210 sets “WAIT” in the task status register 258 of task J, “waiting for mutex” in the waiting reason register 262, sets the mutex ID of the waiting mutex in the mutex ID register 265, sets the timer 252, and waits for WAIT. Start measuring time.
<Execution of release mutex system call>

B1. The task switching circuit 210 inputs the release semaphore ID to the mutex circuit 240 on the condition that the task that executed the system call occupies the release mutex. The mutex circuit 240 also includes a comparison circuit that is connected in multiple stages as in FIG. 14 and a determination circuit that determines whether the first condition and the second condition of the mutex standby cancellation conditions are successful. This determination circuit outputs “1” only when both the first condition and the second condition of the mutex standby conditions are satisfied for this mutex. When a task that does not occupy the release mutex executes a release mutex system call, the task state is changed from RUN to READY.
(When any judgment circuit outputs "1" and any task ID is output from the mutex circuit 240)
B2. “READY” is set in the task status register 258 of the detected task, the waiting reason register 262 and the mutex ID register 265 are cleared, and the timer 252 is made to measure the READY elapsed time.
B3. The task status register 258 of the task that executed the system call is set to “READY”, and measurement of the READY elapsed time is started.
(None of the determination circuits outputs “1” and the mutex circuit 240 does not output any task ID)
B2. In the semaphore table 212, the task switching circuit 210 sets the mutex to an unoccupied state.
B3. The state of the task that executed the system call is changed from RUN to READY.
[Event processing]

The event management in the basic example will be briefly described. In the event table 214, a flag pattern (hereinafter referred to as “current flag pattern”) is recorded in association with an event ID. The flag pattern is an 8-bit bit pattern.
The set event system call is a system call for setting and changing the current flag pattern, and uses an event ID and a flag pattern (hereinafter referred to as “set flag pattern”) as parameters. When the set event system call is executed, the current flag pattern for the corresponding event is changed to a logical sum with the set flag pattern. For example, when the current flag pattern is “00001100” and the set flag pattern is “00000101”, the current flag pattern is “00001011”. Hereinafter, each flag pattern is referred to as 0th bit, 1st bit,..., 7th bit from the left.

The wait event system call is a system call for waiting for the current flag pattern of the standby event to satisfy a predetermined condition, and uses an event ID, a flag pattern (hereinafter referred to as “standby flag pattern”), and a flag condition as parameters. . When the wait event system call is executed, it is determined whether a flag condition is satisfied between the current flag pattern and the standby flag pattern. The flag condition is logical sum (OR) or logical product (AND). When the flag condition is logical AND (AND), the WAIT cancellation condition is that all the corresponding bits of the current flag pattern are “1” for all the bits that are “1” in the standby flag pattern. When the flag condition is logical sum (OR), the WAIT cancellation condition is that the corresponding bit of the current flag pattern is “1” for any bit that is “1” in the standby flag pattern. For example, in the case of the current flag pattern “00001011”, the standby flag pattern “00000011”, and the flag condition “logical sum (OR)”, the seventh bit of the current flag pattern among the sixth bit and the seventh bit of the standby flag pattern is In this case, the WAIT cancellation condition by the wait event system call is satisfied. On the other hand, when the flag condition is “logical product (AND)”, the sixth bit of the current flag pattern is “0”, so the WAIT cancellation condition is not satisfied.
[1] Event processing by general software RTOS

A general RTOS process at the time of executing the wait event system call and the set event system call is as follows. In general RTOS, an event table is held in a memory for event management. In this event table, not only the event ID and current flag pattern, but also the task ID, standby flag pattern, and flag condition of a task that is normally in a WAIT state with the event as a standby event (hereinafter referred to as “event waiting task”). Are associated and held.
<Execution of wait event system call>

A1. The RTOS reads the current flag pattern of the event designated by the system call from the event table.
A2. The current flag pattern and the standby flag pattern are compared according to the flag condition, and the success or failure of the WAIT cancellation condition is determined.
(When WAIT cancellation condition is satisfied)
A3. The task state of the task that executed the system call is changed from RUN to READY.
(When WAIT cancellation condition is not satisfied)
A3. The task ID of the task that executed the system call is recorded in the event table.
A4. Record the wait flag pattern in the event table.
A5. Record the flag condition in the event table.
A6. The task state of the task that executed the system call is changed from RUN to WAIT.
<Execution of set event system call>

B1. The RTOS reads the current flag pattern, task ID, standby flag pattern, and flag condition from the event table for the set event specified by the system call.
B2. The logical sum of the current flag pattern and the set flag pattern is recorded as a new current flag pattern.
(When there is no event-waiting task for the set event, or even if it exists, the WAIT cancellation condition is not satisfied from the wait flag pattern and flag condition)
B3. The task state of the task that executed the system call is changed from RUN to READY.
(When there is an event waiting task for the set event and the WAIT cancellation condition is satisfied)
B3. The task state of the task waiting for the event is changed from WAIT to READY.
B4. The standby task ID, standby flag pattern, and flag condition in the event table are cleared.
B5. The task state of the task that executed the system call is changed from RUN to READY. In addition, a RUN-task is selected.

When a set event system call is executed, a policy for selecting a READY-task from a plurality of WAIT-tasks is as follows.
1. WAIT-task (first condition).
2. Of the WAIT-tasks, the task must be a set event as a standby event (second condition).
3. The task must satisfy the WAIT cancellation condition by comparing the standby flag pattern, current flag pattern, and flag conditions (third condition)
These three conditions are collectively referred to as “event standby release conditions”.
[2] Event processing by hardware RTOS of basic example

Processing when the task processing apparatus 100 executes the wait event system call and the set event system call is as follows. In the semaphore table 212 built in the task processing apparatus 100, an event ID and a current flag pattern are associated with each other. Information such as a standby task ID and a standby flag pattern is stored in the state storage unit 220.
<Execution of wait event system call>

A1. The task switching circuit 210 reads the current flag pattern from the event table 214.
A2. The task switching circuit 210 compares the current flag pattern and the standby flag pattern according to the flag condition, and determines whether the WAIT cancellation condition is met.
(When WAIT cancellation condition is satisfied)
A3. “READY” is set in the task status register 258 of the task that executed the system call.
(When WAIT cancellation condition is not satisfied)
A3. The task switching circuit 210 “WAIT” in the task status register 258 of the task that executed the system call, “waiting for event” in the wait reason register 262, event ID of the standby event in the event ID register 266, and standby flag in the standby flag register 268. Flag conditions are set in the pattern and flag condition register 270, respectively.
<Execution of set event system call>

B1. The task switching circuit 210 reads the current flag pattern from the event table 214 and inputs the event ID of the set event designated by the system call to the event selection circuit 236.
B2. The task switching circuit 210 logically adds the set flag pattern to the current flag pattern of the event table 214.
B3. The event selection circuit 236 selects a task that satisfies the event standby condition for the input event ID. At this time, a plurality of tasks may be selected regardless of the task priority order and the WAIT elapsed time.
(When there is a task that satisfies the event waiting cancellation condition)
B4. “READY” is set in the task status register 258 of the event waiting task, and the event ID register 266, the standby flag register 268, and the flag condition register 270 are cleared.
B5. The task state of the task that executed the system call is changed from RUN to READY.
(When there is no task that satisfies the event wait cancellation condition)
B4. The task state of the task that executed the system call is changed from RUN to READY.
[Timeout processing]

A task that has transitioned to the WAIT state transitions to the READY state when the WAIT cancellation condition is satisfied. However, if the establishment of the WAIT cancellation condition is hindered due to some external factor or a bug in the application program, the task cannot escape from the WAIT state. Therefore, normally, a timeout value is set when the task is shifted to the WAIT state. The timeout value is decremented periodically, and when it becomes zero, the task transitions from the WAIT state to the READY state even if the WAIT cancellation condition is not satisfied. That is, the task is prevented from stopping in the WAIT state for a time longer than the timeout value.
[1] Time-out processing by general software RTOS

In the case of a general RTOS by software, a timeout value is set in the TCB of a task in a WAIT state, and this timeout value is periodically decremented. The RTOS periodically interrupts the processing of the CPU, checks all TCBs, and detects a WAIT-task whose timeout value has reached zero. When such a task is detected, the RTOS changes the task state of the task from WAIT to READY.
[2] Time-out process by hardware RTOS of basic example

  On the other hand, in the basic example, the task switching circuit 210 periodically decrements the timeout value of each timeout counter 274. The timeout value is set as a parameter when executing the WAIT system call, and the task switching circuit 210 sets the timeout value in the timeout counter 274 of the task that executed the system call.

  Since the CPU 150 is not involved in the timeout value decrement process, the task switching circuit 210 can update the timeout value independently of the task execution process. For this reason, the task control circuit 200 autonomously updates the timeout value while the CPU 150 is executing a task. Since the status data is always input to the timeout detection circuit 238, the timeout detection circuit 238 can detect a task whose timeout count value has become zero at almost the same timing as when the timeout count value is updated. The timeout detection circuit 238 outputs the task ID of such a task. When the task switching circuit 210 receives the task ID from the timeout detection circuit 238, the task switching circuit 210 recognizes that a timeout has occurred, and asserts HC to stop supplying the CPU clock. The task control circuit 200 causes the WAIT-task in which a timeout has occurred to transition to the READY state, and causes the RUN-task to transition to the READY state. The task switching circuit 210 selects a task to be executed next from among the READY-tasks. In addition, the task switching circuit 210 restarts the timer 252 of the task that has timed out, and measures the READY elapsed time.

According to such a processing method, when a timeout occurs during execution of a task, that is, during operation of the CPU clock, it is possible to immediately interrupt the CPU 150 and execute task switching. Further, during the execution of the task, the task switching circuit 210 can independently execute the timeout value update process without borrowing the processing capability of the CPU 150.
[Task switching circuit 210 as a finite state machine]

FIG. 15 is a state transition diagram of the task switching circuit 210 in the basic example.
In the initialization process (A1), all tasks are in the IDLE state. When the initialization process is completed (S10), one of the tasks becomes a RUN-task and enters the task execution state (A2). When an interrupt request signal is detected (S12), the special task becomes a RUN-task, and interrupt processing (A3) is executed. When the interrupt process ends (S14), the task switching circuit 210 selects a RUN-task from the general tasks, and transitions to A2.

When a system call is executed during task execution (A2) (S16), system call processing is executed (A4). If task switching, that is, RUN-task switching does not occur (S18), the process returns to A2. On the other hand, when a task switch occurs due to the system call process (A4) (S20), the task switching circuit 210 selects a RUN-task based on the output of the execution selection circuit 232 (A5). When the task switch is completed (S22), the processing state shifts to A2.
In relation to the basic example, a case where only one of the save circuit 120 and the task control circuit 200 which are main elements of the task processing device 100 is mounted will be additionally described.
[A task processing apparatus 100 of a type that does not include the task control circuit 200]

FIG. 16 is a circuit diagram of the task processing apparatus 100 that does not include the task control circuit 200 in the task processing apparatus 100 of FIG.
Instead of mounting the task control circuit 200, a register switching control circuit 322 and a processing data holding unit 320 are added. Since the task control circuit 200 is not installed, the task scheduling function is realized by software RTOS. Therefore, it becomes necessary for the RTOS to temporarily acquire the right to use the CPU 150 at the time of task switching. The processing data holding unit 320 normally holds processing data for RTOS. When the RTOS acquires the right to use the CPU 150, the processing data holding unit 320 replaces the processing data for RTOS in the processing data holding unit 320 with the processing data for tasks in the special register 156. In the following, the processing process will be described on the assumption that task switching is performed from task A to task B.

A1. When the task A executes a system call, the system call variable and the system call ID are recorded in a part of the general-purpose register 158.
A2. The register switching control circuit 322 moves the processing data of task A to the processing data holding unit 320 and loads the RTOS processing data of the processing data holding unit 320 into the processing register 154. At this stage, the RTOS acquires the right to use the CPU 150.
A3. The register switching control circuit 322 inputs a write signal to the save register 110 a and saves the task A process data in the process data holding unit 320 to the save register 110.
A4. The RTOS executes processing corresponding to the system call based on the system call variable and ID recorded in the general-purpose register 158. Also, the task status data of the task A TCB is set to “READY”, and the task A TCB is added to the task ready list.

B1. Next, the RTOS selects a RUN-task, in this case, task B, according to the RUN task selection condition described above.
B2. The RTOS instructs the register switching control circuit 322 to input a task selection signal designating task B to the load selection circuit 112. The processing data is moved from the save register 110b to the processing data holding unit 320.
B3. The register switching control circuit 322 interchanges the task B process data in the process data holding unit 320 and the RTOS process data in the process register 154. As a result, the task B acquires the right to use the CPU 150.

According to such a processing method, the circuit size of the task processing device 100 as a whole can be made compact compared to the task processing device 100 of FIG. Although the RTOS is realized as software, loading / saving of processing data can be controlled by a signal from the register switching control circuit 322. If the bus connecting the processing register 154, the processing data holding unit 320, the load selection circuit 112, and the save register 110 is set to the number of bits that can be transferred in parallel, the processing data is saved to the TCB or processed from the TCB. Task switching can be performed faster than loading of
[A task processing device 100 of a type that does not include the save circuit 120]

FIG. 17 is a circuit diagram of the task processing apparatus 100 that does not include the save circuit 120 in the task processing apparatus 100 of FIG.
Instead of mounting the save circuit 120, an interrupt interface circuit 324 is added. Since the save circuit 120 is not installed, the processing data is saved in the TCB of the memory. Processing data saving / loading is realized by a software-based RTOS. Therefore, it becomes necessary for the RTOS to temporarily acquire the right to use the CPU 150 at the time of task switching. In the following, the processing process will be described on the assumption that task switching is performed from task A to task B.

  When a task switch occurs due to the execution of a system call, first, the software RTOS saves the processing data of task A in the TCB of task A. Then, the processing data for RTOS is loaded into the processing register 154. The processing method at this time is equivalent to the content described in relation to FIG.

  The software RTOS writes the system call parameters in the interrupt interface circuit 324. The execution control circuit 152 stops the CPU clock of the CPU 150. The interrupt interface circuit 324 causes the task control circuit 200 to execute a task switch. The task switching circuit 210 first sets the task status register 258 of the task A to READY, and selects the task B that is the next RUN-task based on the output from the task selection circuit 230. The task switching circuit 210 instructs the interrupt interface circuit 324 to load task B processing data. Here, the interrupt interface circuit 324 causes the execution control circuit 152 to restart the CPU clock. The interrupt interface circuit 324 notifies the software RTOS that the task B has been selected. The software RTOS accesses the TCB of task B and loads the processing data of task B into the processing register 154.

  Even with such a processing method, the circuit size of the task processing device 100 as a whole can be made compact compared to the task processing device 100 of FIG. Some of the functions of the RTOS are realized as software, but the task selection process can be realized by the task control circuit 200.

  Compared to the software RTOS described with reference to FIGS. 2 and 3, the task processing device 100 of FIGS. 16 and 17 can implement some of the functions of the RTOS as hardware. As described with reference to FIG. 16, the existence of the save circuit 120 eliminates the need to access the TCB for saving / loading the processing data. Therefore, the register switching control circuit 322 can execute processing data save / load processing. As described with reference to FIG. 17, the presence of the task control circuit 200 allows the software RTOS to delegate the task selection function to the task control circuit 200.

As described with reference to FIG. 5, in the case of the task processing device 100 equipped with the save circuit 120 and the task control circuit 200, the RTOS task scheduling function can be completely implemented in hardware. Since there is no need to access the memory TCB at the time of task switching, the task switching process is further accelerated. According to experiments by the present inventors, it has been confirmed that the task processing apparatus 100 in the basic example operates at a speed about 100 times faster than the general software RTOS described with reference to FIG.
{Improvements}

  Next, as an improved example, a task processing apparatus 100 that implements interrupt processing by hardware logic will be described.

FIG. 18 is a time chart of interrupt processing by a general software OS.
When the software OS receives an interrupt request signal from an interrupt controller (not shown), the software OS starts an interrupt handler, that is, a special task in the basic example. Various events such as pressing of the keyboard, reception of a communication packet, completion of DMA transfer, or mere passage of a predetermined time can trigger an interrupt request signal. The special task is a task implemented by software, and executes various interrupt processing corresponding to the interrupt factor.

  In the figure, first, an interrupt request signal INTR is detected during execution of a general task. If it is an interrupt request signal that should be dealt with immediately, the general task being executed is interrupted and the execution right is transferred to the OS (S100). The OS saves the context information of the general task in the TCB (S102) and activates the special task (S104).

  The special task analyzes the interrupt factor (S106). Since various writes to the interrupt factor register (not shown) are executed by the interrupt request signal, the interrupt factor can be specified by examining the interrupt factor register. The special task determines the interrupt process to be executed in response to the interrupt factor, and starts the interrupt process. Various system call instructions are executed in the process of interrupt processing. When the system call instruction is executed, the execution right is transferred again to the OS (S108). The OS executes the designated system call (S110). After executing the system call, the execution right is transferred again to the special task (S112). Since the interrupt process is a high-priority process, the execution right is not normally transferred to the general task unless the special task process is completed.

  The special task continues the interrupt process (S114), and when executing the system call instruction again, the execution right is transferred to the OS (S116). As described above, while the special task and the OS alternately acquire the execution right, the last execution right shifts to the special task (S118), and the special task completes the interrupt process (S120). When the interrupt process is completed, the execution right is transferred to the OS (S122), and a task switch from the special task to the general task is executed (S124). Thus, normal processing by the general task is resumed (S126).

The task processing apparatus 100 shown in the basic example is different from the software OS in that functions as an RTOS are realized by hardware logic, but the basic flow in interrupt processing is almost the same as that of the software OS. However, as described in relation to the basic example, the task switch in S102 and S124 and the execution of system calls such as S110 are significantly faster than the software OS.
In the case of the task processing apparatus 100 of the basic example, the RTOS process is executed after the CPU clock (CLK) is stopped in S100, S108, S116, and S122. Further, after the CPU clock (CLK) is restarted in S104, S112, S118, and S126, the special task and the general task are executed. A special task is a task having a particularly high task priority, but is the same as a general task in that it is a context-based task that operates according to the CPU clock (CLK).

  In the improved example, such interrupt processing, specifically, a part of the function of the special task is realized by hardware logic, thereby further speeding up the interrupt processing.

  The contents of the interrupt process vary, but depending on the interrupt request signal, the process contents are often simple and routine. For example, assume a situation where a general task A starts DMA transfer and waits for completion of DMA transfer. At the start of DMA transfer, the general task A executes a wait event system call and shifts to the WAIT state. When the DMA transfer is completed, a predetermined interrupt request signal is input to the task switching circuit 210 (in the basic example). The special task activated at this time executes a set event system call and sets a flag pattern indicating completion of DMA transfer in the event table 214. When the current flag pattern in the event table 214 changes, the WAIT cancellation condition for the general task A is satisfied, and the general task A shifts to the READY state. As described above, the contents of the interrupt process executed upon completion of the DMA transfer are relatively simple.

  Therefore, the task processing apparatus 100 according to the improved example has a relatively simple interrupt processing content, and preferably registers an interrupt request signal with a high occurrence frequency in advance as a “high-speed interrupt request signal INTR (H)”. deep. The interrupt request signals in the improved example are roughly classified into two types, a high-speed interrupt request signal INTR (H) and a “normal interrupt request signal INTR (N)”.

FIG. 19 is a circuit diagram of the task processing apparatus 100 in the improved example.
The task processing apparatus 100 in the improved example also includes a save circuit 120 and a task control circuit 200 in addition to the CPU 150. An interrupt circuit 400 is further added to the task processing device 100 in the improved example.

  The high speed interrupt request signal INTR (H) is input to the interrupt circuit 400. The configuration of the interrupt circuit 400 and the processing method of the high-speed interrupt request signal by the interrupt circuit 400 will be described later. As in the basic example, the normal interrupt request signal INTR (N) is directly input to the task switching circuit 210 and is interrupted by a special task. Interrupt processing for a high-speed interrupt request signal (hereinafter referred to as “high-speed interrupt processing”) is faster than interrupt processing for a normal interrupt request signal (hereinafter referred to as “normal interrupt processing”). On the other hand, in the case of normal interrupt processing, there is an advantage that details of processing contents can be flexibly defined as a special task of software. The task processing apparatus 100 according to the improved example uses the high-speed interrupt request signal and the normal interrupt request signal in combination to increase the speed while maintaining versatility as an RTOS.

FIG. 20 is a circuit diagram of the interrupt circuit 400.
The interrupt circuit 400 includes a signal selection circuit 402, an operation circuit 404, and a storage unit 406. The i high-speed interrupt request signals INTR (H) _0 to INTR (H) _i−1 are input to the signal selection circuit 402 irregularly. A plurality of high-speed interrupt request signals INTR (H) may be input in a short period of time, or a plurality of high-speed interrupt request signals INTR (H) may be input simultaneously. The signal selection circuit 402 can temporarily store the received high-speed interrupt request signal INTR (H).

  The signal selection circuit 402 selects one high-speed interrupt request signal INTR (H) from the buffered high-speed interrupt request signal INTR (H) based on a predetermined selection rule. The selection rule here may be arbitrarily determined according to the design requirements. For example, a priority is set for each high-speed interrupt request signal INTR (H), and when a plurality of high-speed interrupt request signals INTR (H) are buffered, a high-speed interrupt request with the highest priority among them. The signal INTR (H) may be selected. Alternatively, the fast interrupt request signal INTR (H) with the oldest input timing to the signal selection circuit 402 may be selected, or may be selected at random. When the high-speed interrupt request signal INTR (H) _n (n is an integer from 0 to i−1) is selected, the signal selection circuit 402 asserts the corresponding signal QINT_n.

  When QINT_n is asserted, the operation circuit 404 asserts the ISROP signal. By asserting the ISROP signal, the signal selection circuit 402 is informed that high-speed interrupt processing is in progress. When the ISROP signal is asserted, the signal selection circuit 402 does not assert the next QINT until the ISROP signal is negated. When the ISROP signal is negated, the signal selection circuit 402 can select the high-speed interrupt request signal INTR (H) to be processed next.

  When QINT_n is asserted, the operation circuit 404 also asserts ISR_RQ to request the task switching circuit 210 to execute high-speed interrupt processing. When ISR_RQ is asserted, the task switching circuit 210 stops supplying the CPU clock (CLK). Thus, the execution of the general task is stopped.

  The operation circuit 404 sets a predetermined address ADD [n] in DSC_ADD [k−1: 0] according to QINT_n, in other words, according to the selected high-speed interrupt request signal INTR (H) _n. By inputting DSC_ADD [k−1: 0] = ADD [n], the interrupt operation instruction p0 held at the address ADD [n] in the storage unit 406 is transmitted to the task switching circuit 210 as ISR_DT [31: 0]. Is done. The task switching circuit 210 executes high-speed interrupt processing according to the received interrupt operation instruction p0.

  The interrupt operation instruction in this embodiment is normalized to a 32-bit size as will be described later with reference to FIG. 22, and the presence / absence of a subsequent interrupt operation instruction is indicated by the most significant bit ISR_DT [31]. Note that the interrupt operation instruction may be normalized with an arbitrary size other than 32 bits, such as 64 bits and 128 bits. When the most significant bit ISR_DT [31] = 1, the task switching circuit 210 asserts ISR_NX and requests the operation circuit 404 for a subsequent interrupt operation instruction p1. The operation circuit 404 sets an address ADD [n] +1 obtained by adding one word (32 bits in this embodiment) to the previous address ADD [n] to DSC_ADD [k−1: 0]. The interrupt operation instruction p1 held at the address ADD [n] +1 is transmitted to the task switching circuit 210 as ISR_DT [31: 0]. The task switching circuit 210 continues the high-speed interrupt process according to the received interrupt operation instruction p1.

When the most significant bit ISR_DT [31] = 0, the task switching circuit 210 asserts ISR_END and notifies the operation circuit 404 of completion of the high-speed interrupt processing. The operation circuit 404 negates ISROP. When ISROP is negated, the signal selection circuit 402 can select another high-speed interrupt request signal INTR (H) and newly assert QINT.
In this improved example, the ISR_END signal is input to the operation circuit 404, and the operation circuit 404 negates ISROP to control the signal selection circuit 402. As a modification, the task switching circuit 210 may control the signal selection circuit 402 by transmitting an ISR_END signal directly to the signal selection circuit 402 when the high-speed interrupt processing is completed.

FIG. 21 is a data structure diagram of the storage unit 406.
The storage unit 406 in this improved example is a memory. Addresses “0x000 to 0x0FF” hold an interrupt operation instruction group corresponding to the high-speed interrupt request signal INTR (H) _0. Similarly, an interrupt operation instruction group corresponding to the high-speed interrupt request signal INTR (H) _1 is held at addresses “0x100 to 0x1FF”. The interrupt operation instruction in this improved example is a system call instruction. For example, when the signal selection circuit 402 selects the high-speed interrupt request signal INTR (H) _0, the operation circuit 404 sets “0x000”, which is the first address of the high-speed interrupt request signal INTR (H) _0, to DSC_ADD [k−1. : 0]. The corresponding interrupt operation instruction “systemcall_00” is transmitted from the storage unit 406 to the task switching circuit 210. Since the interrupt operation instruction “systemcall_00” includes the subsequent interrupt operation instruction “systemcall_01”, the most significant bit of the interrupt operation instruction “systemcall_00” is set to “1”. After executing the interrupt operation instruction “systemcall_00”, the task switching circuit 210 asserts ISR_NX to request a subsequent interrupt operation instruction.

  The operation circuit 404 newly designates an address “0x001” obtained by adding one word to “0x000” in DSC_ADD [k−1: 0]. From the storage unit 406, a subsequent interrupt operation instruction “systemcall_01” is transmitted to the task switching circuit 210. The most significant bit of “syscall_01” is set to “0”, and the task switching circuit 210 sets “syscall_01” as the last interrupt operation instruction as high-speed interrupt processing for the high-speed interrupt request signal INTR (H) _0. Can be recognized. When the task switching circuit 210 completes execution of the interrupt operation instruction “syscall_01”, the task switching circuit 210 asserts ISR_END to notify the end of the high-speed interrupt processing.

FIG. 22 shows the data structure of an interrupt operation instruction.
As described above, ISR_DT [31] indicates the presence / absence of a subsequent interrupt operation instruction. The type of system call is indicated by ISR_DT [30:24]. ISR_DT [30:24] = 0000001 indicates a “set event system call”. Therefore, the interrupt operation command 410a is a set event system call execution command. ISR_DT [23: 8] indicates a set flag pattern, and ISR_DT [7: 0] indicates an event ID. When task switching circuit 210 receives interrupt operation instruction 410a, task switching circuit 210 sets event table 214 by the same processing method as in the basic example.

  ISR_DT [30:24] = 0000010 indicates a “release semaphore system call”. Therefore, the interrupt operation instruction 410b is a release semaphore system call execution instruction. ISR_DT [7: 0] indicates the semaphore ID of the released semaphore. ISR_DT [30:24] = 0000011 indicates a “release wait system call”. Therefore, the interrupt operation instruction 410c is a release wait system call execution instruction. ISR_DT [4: 0] indicates the task ID of the task to be released from the WAIT state. ISR_DT [30:24] = 0000100 indicates a “wake-up task system call”. Therefore, the interrupt operation instruction 410d is an execution instruction for the wakeup task system call. ISR_DT [4: 0] indicates the task ID of the task to be released from the WAIT state. ISR_DT [30:24] = 0000101 indicates an “activation system call”. Therefore, the interrupt operation instruction 410e is an execution instruction for an activation system call. ISR_DT [4: 0] indicates the task ID of the task to be activated. Various other system calls may be registered in the storage unit 406 as interrupt operation instructions.

  The storage unit 406 may be provided as a ROM (Read Only Memory) or a readable / writable RAM (Random Access Memory). If the contents of the storage unit 406 can be rewritten by an application, the contents of the high-speed interrupt process can be changed by software.

FIG. 23 is a sequence diagram showing the process of high-speed interrupt processing.
First, the signal selection circuit 402 selects the high-speed interrupt request signal INTR (H) _n to be processed (S130) and asserts QINT_n (S132). The operation circuit 404 asserts ISROP and notifies the signal selection circuit 402 that high-speed interrupt processing is in progress (S134). When ISROP is asserted, the signal selection circuit 402 does not assert QINT even if it receives a new high-speed interrupt request signal and buffers it.

  On the other hand, when QINT_n is asserted, the operation circuit 404 asserts ISR_RQ and requests the task switching circuit 210 to start high-speed interrupt processing (S136). At this time, the task switching circuit 210 stops the CPU clock (CLK) and prepares for the start of high-speed interrupt processing. The operation circuit 404 specifies the address ADD [n] corresponding to QINT_n as DSC_ADD, and reads the interrupt operation instruction p0 from the storage unit 406 (S138). The interrupt operation instruction p0 is transmitted to the task switching circuit 210 as ISR_DT [31: 0] (S140).

  The task switching circuit 210 changes the setting contents of the semaphore table 212, the event table 214, and the state storage unit 220 according to the received interrupt operation command p0. More specifically, the task switching circuit 210 executes a processing process equivalent to when a general task issues a release semaphore system call (signaling semaphore system call) or a set event system call (set flag system call). Thus, the setting contents of the semaphore table 212, the event table 214, and the state storage unit 220 are changed. The processing contents of the interrupt operation instruction are the same as the processing contents of the system call instruction shown in the basic example. If “1” is set in the most significant bit of the interrupt operation instruction, the task switching circuit 210 asserts ISR_NX and requests the operation circuit 404 for the next interrupt operation instruction p1 (S144). The operation circuit 404 loads the next interrupt operation instruction p1 (S146), and the interrupt operation instruction p1 is transmitted to the task switching circuit 210 (S148).

  When the task switching circuit 210 executes the last interrupt operation instruction px, that is, when executing the interrupt operation instruction px having the most significant bit set to “0”, the task switching circuit 210 asserts ISR_END. (S152). The operation circuit 404 recognizes the completion of the high-speed interrupt process and negates ISROP (S154). Thus, the signal selection circuit 402 can select the next high-speed interrupt request signal.

FIG. 24 is a state transition diagram of the task switching circuit 210 in the improved example.
In the improved example, high-speed interrupt processing (A6) is added to the state transition diagram shown in FIG. The normal interrupt process (A3) is the same as the interrupt process (A3) shown in FIG. In addition, the configuration denoted by the same reference numerals as the basic example indicates the same processing content.

  If a high-speed interrupt request signal INTR (H) is detected during task execution (A2) (S24), ISR_RQ is asserted and high-speed interrupt processing (A6) is executed. When the interrupt circuit 400 transmits an interrupt operation command to the task switching circuit 210 (S26), the task switching circuit 210 executes a corresponding system call process (A4). When the execution of the system call instruction is completed, state transition is made to high-speed interrupt processing (A6) (S28). If there are no more interrupt operation instructions to be processed, the high-speed interrupt process is terminated (S30), and the next general task to be executed is selected (A5).

FIG. 25 is a time chart showing the process of high-speed interrupt processing by the task processing apparatus 100 of the improved example.
In the figure, first, an interrupt request signal INTR is detected during execution of a general task. If the interrupt request signal is to be dealt with immediately, the general task being executed is interrupted by stopping the CPU clock (CLK), and high-speed interrupt processing by the interrupt circuit 400 and task switching circuit 210 is started (S160) .

  The interrupt circuit 400 appropriately reads out the interrupt operation instruction, and the task switching circuit 210 executes the system call instruction specified as the interrupt operation instruction. When the high-speed interrupt processing realized by a series of system calls is completed in this way (S162), the task switching circuit 210 selects the next RUN-task (S164). After the selection, the CPU clock (CLK) is restarted and normal processing by the general task is restarted (S166).

  According to the task processing device 100 shown in the improved example, high-speed interrupt processing can be realized at the hardware level by the cooperation of the interrupt circuit 400 and the task switching circuit 210. According to the experiments by the present inventors, it has been confirmed that the task processing device 100 in the improved example operates at a speed about four times that of the task processing device 100 in the basic example. By forming the storage unit 406 as a writable memory, the processing content can be set to some degree of flexibility even in high-speed interrupt processing.

Conventionally, various methods have been attempted to execute software such as an OS at high speed. Such attempts are often directed to increase in scale and complexity such as increase in the number of CPU clocks, increase in memory capacity and register capacity, parallel processing by a plurality of CPUs, and further, network distributed processing.
On the other hand, in the case of the task processing device 100 shown in the present embodiment, the processing efficiency is dramatically improved by adding the save circuit 120 and the task control circuit 200 to the existing CPU 150. In the case of the software OS, in order to realize processing such as a task switch that is originally desired to be executed, incidental processing such as management of TCB and task ready list must be executed. On the other hand, the task processing apparatus 100 is freed from such software-specific overhead because the task switch, task state management, and interrupt processing are realized by hardware logic. For this reason, it is an ideal system that realizes high speed while suppressing increase in power consumption and cost. As shown in the improved example, by realizing the high-speed interrupt processing algorithm with an electronic circuit, a higher speed can be realized.

  In the above, this invention was demonstrated based on the Example. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

  According to the present invention, more efficient task execution control is realized in multitask processing.

Claims (7)

A processing register that temporarily holds data for task execution;
An execution control circuit for loading instructions and operands from memory into the processing register and executing a task in accordance with the instructions and operands of the processing register;
A status register that holds status data indicating the task execution status;
A task switching circuit for controlling the task execution state;
A task selection circuit for selecting a task according to a predetermined selection condition based on the state data;
An interrupt circuit for processing an external interrupt request signal,
The execution control circuit includes an instruction decoder that determines whether or not an instruction to be executed is a predetermined system call instruction, and is predetermined when the first task being executed executes the predetermined system call instruction. System call signal to the task switching circuit,
The task selection circuit selects a task to be executed next from a task in a READY state indicating a state waiting for execution,
The task switching circuit selects a second task to be executed next by an output from the task selection circuit when the system call signal is received, and saves data in the processing register to a predetermined storage area And changing the setting of the state data for the first task from the RUN state indicating that the task is being executed to another state, and storing the data saved in the storage area for the second task in the processing register And the state data for the second task is changed from the READY state to the RUN state, and the execution control circuit is allowed to execute the task,
The execution control circuit executes the second task on condition that the task switching circuit is permitted to execute the task after transmitting the system call signal.
When the interrupt circuit receives the interrupt request signal, the interrupt circuit transmits an interrupt operation command associated with the interrupt request signal in advance to the task switching circuit,
The task switching circuit changes task state data in accordance with the interrupt operation instruction. The interrupt circuit is
A signal selection circuit that receives and temporarily holds an interrupt request signal from the outside, and selects any one of the held interrupt request signals as a processing target from the held one or more interrupt request signals;
An operation circuit for transmitting an interrupt operation instruction corresponding to the selected interrupt request signal to the task switching circuit,
The task switching circuit transmits an operation completion signal to the interrupt circuit when the execution of the interrupt operation instruction is completed,
2. The task processing apparatus according to claim 1, wherein the signal selection circuit transmits an interrupt request signal to be processed next to the operation circuit on condition that the operation completion signal is received. . The task switching circuit, when the execution of the interrupt operation instruction is completed, transmits the operation completion signal to the operation circuit of the interrupt circuit,
When the operation circuit receives the operation completion signal, the operation circuit transmits a selectable signal to the signal selection circuit,
The task processing apparatus according to claim 2, wherein the signal selection circuit transmits an interrupt request signal to be processed next to the operation circuit as a condition that the selectable signal has been received. The interrupt circuit is
A memory that holds an interrupt table in which an interrupt request signal and an interrupt operation instruction are associated with each other;
The operation circuit refers to the interrupt table, specifies an interrupt operation instruction corresponding to the selected interrupt request signal, and transmits the specified interrupt operation instruction to the task switching circuit. 3. The task processing device according to claim 2, wherein The memory holds the interrupt table as a table capable of associating a plurality of interrupt operation instructions with one interrupt request signal,
The task switching circuit transmits a subsequent request signal to the operation circuit when the presence of a subsequent interrupt operation instruction is specified in the interrupt operation instruction received from the interrupt circuit,
When the operation circuit receives the subsequent request signal, it refers to the interrupt table and switches the subsequent interrupt operation command associated with the same interrupt request signal as the interrupt operation command to the task switching. To the circuit,
The task switching circuit completes the operation when execution of the interrupt operation instruction is completed when the absence of a subsequent interrupt operation instruction is specified in the interrupt operation instruction received from the interrupt circuit. The task processing device according to claim 4, wherein a signal is transmitted to the interrupt circuit. The interrupt circuit transmits an interrupt operation instruction for a high-speed interrupt request signal that is a part of a plurality of types of interrupt request signals to the task switching circuit,
When the task switching circuit receives a normal interrupt request signal other than the high-speed interrupt request signal, the task switching circuit loads data for executing a predetermined interrupt task into the processing register, and then the interrupt task The task processing device according to claim 1, wherein a process corresponding to the normal interrupt request signal is executed by the step. A register for saving data in the processing register, further comprising a plurality of save registers respectively associated with a plurality of tasks;
When the task switching circuit receives the system call signal, the task switching circuit saves the data in the processing register in the save register associated with the first task, and saves the data in the save task associated with the second task. The task processing apparatus according to claim 1, wherein data in a register is loaded into the processing register.

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