JP2010045726A - Signal amplification apparatus and signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve circuit protection and to prevent noise generation when any abnormality occurs in input of a source clock in a class-D amplifier. <P>SOLUTION: When a source clock CLK_S to be inputted to a PLL circuit 160 is kept in low output, the PLL circuit 160 is disabled from being locked and an unlock detector makes high-output of an unlock signal S_UL. In response to the high-output, a P-channel FET 151a of a high-side amplification circuit 150a and a P-channel FET 151b of a low-side amplification circuit 150b are turned off. Similarly, outputs of NOR circuits 142a, 142b, to which the unlock signal S_UL is inputted are made low. As a result, an N-channel FET 152a of the high-side amplification circuit 150a and an N-channel FET 152b of a low-side amplification circuit 150b are turned off. Thus, both the high-side amplification circuit 150a and the low-side amplification circuit 150b are brought to high impedance together. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a signal amplification device and a signal processing method, and more particularly to a signal processing device that performs modulation processing with a predetermined clock, and a signal processing method that can be used in such a signal processing device.

  In recent years, the digitization of systems in AV (Audio Visual) devices is progressing. This is because a digital circuit that does not cause such problems and is easy to be integrated is preferred to an analog circuit that easily causes signal degradation and variation problems due to noise.

  The flow is not an exception in television audio circuits and audio equipment. At the entrance of the sound, a standard for handling digital signals such as HDMI (High-Definition Multimedia Interface) is widely adopted, and at the exit of the sound, although not strictly a digital circuit, a class D amplifier that requires a clock is used. Yes. Unlike a so-called analog amplifier, a class D amplifier expresses a signal with the density and width of a pulse waveform and performs power amplification.

  Needless to say, a circuit that requires a clock does not operate if the clock stops. As for the class D amplifier, if the clock (hereinafter referred to as “audio clock”) supplied to the class D amplifier becomes unstable, the sound quality is deteriorated. Further, in the case of an analog input type class D amplifier, if the audio clock stops even for a moment, the amplifier may oscillate. Furthermore, when the pulse is fixed due to the DC voltage applied to the load due to the stop of the clock, for example, as shown in FIG. 16, a large current flows through the load and the load is destroyed. There is a risk of damage to the power amplifier circuit inside.

  For example, in order to simplify the system, there is a configuration in which a clock output from an HDMI receiver is directly used as an audio clock of an amplifier. In this case, the audio clock may stop when the user simply disconnects the HDMI cable, and the above-described problem is easily imagined.

As a technique corresponding to such a situation, the following pulse modulation type power amplifier has been proposed (for example, see Patent Document 1). In this technique, a pulse modulator that receives a clock and an input signal and converts the input signal into a pulse train, a clock detection circuit that detects a stop of the clock and outputs a signal different from that when the clock is normal, and the pulse An output control circuit that inputs the pulse train output from the modulator and the output of the clock detection circuit; and an output circuit that switches according to the output pulse train output from the output control circuit; and Control is performed to stop the switching of the output circuit in response to a signal output from the clock detection circuit that is different from that when the clock is normal.
JP 2007-288431 A

By the way, in the technique disclosed in Patent Document 1, an attempt is made to cope with the stop of the clock, but there is a problem that the case where the clock cycle is extended cannot be dealt with. This is because even if the clock period is extended, the clock detection circuit determines that the clock is “normal” because the level obtained by integrating the same 50% duty clock is the same. This is because the protection operation may not be performed. On the other hand, the pulse modulation circuit may oscillate when the clock is extended. In that case, since the output circuit is not turned off (the protective operation is not performed) and is operating normally, there is a possibility that the output circuit is destroyed as well as the occurrence of abnormal noise. More specifically, there were the following problems.
(1) When the clock stops, the protection operation should be performed immediately, but there is some time between the clock stop and the clock detection circuit detecting the clock stop. Meanwhile, since a large current flows through the load (speaker), there is a possibility that the output circuit will fail.
(2) When the clock is stopped, the output of the output circuit is configured such that the output circuit is instantaneously turned off (high impedance (Hi-Z) output), and unpleasant pop noise is generated for the user. In a system where clock stops frequently occur, it is far from acceptable.

  An object of the present invention has been made in view of such a situation, and an object of the present invention is to provide a technique for realizing circuit protection of a class D amplifier when an abnormality occurs in clock input. Another object of the present invention is to provide a technique for preventing a noise such as a pop sound from being output when an abnormality occurs in clock input.

The apparatus according to the present invention relates to a signal amplifying apparatus. The signal amplifying apparatus includes a modulating unit that modulates an input signal based on a reference clock, an amplifying unit that amplifies and outputs the modulated input signal, a source clock, and a source clock based on the source clock. A phase synchronization unit that generates the reference clock used by the modulation unit and outputs a synchronization state of the acquired source clock and the generated reference clock; and an operation of the amplification unit is set to the synchronization state of the phase synchronization unit. Output control means for controlling accordingly.
The output control unit may turn off the amplification unit when the synchronization state of the phase synchronization unit is unlocked.
The modulation means may perform noise reduction processing before the output control means turns off the amplification means when the synchronization state of the phase synchronization means is unlocked.
Also, a control signal for starting a timer operation with a predetermined timer time when the phase synchronization means is unlocked and turning off the amplification means with respect to the output control means when the timer time is reached May be provided with timer means for outputting.
In addition, when the synchronization state of the phase synchronization means is unlocked, the level adjustment process for lowering the signal level of the input signal input to the modulation means before the output control means turns off the amplification means You may provide the level adjustment means to perform.
The phase synchronization unit may output a warning state that may be unlocked as the synchronization state, and the modulation unit may perform noise reduction processing according to the warning state.
Further, the phase synchronization unit may output a warning state that may be unlocked as the synchronization state, and the level adjustment unit may perform a level adjustment process according to the warning state.
The phase synchronization means may have a synchronizable frequency band, and may output the reference clock in the frequency band even in an unlocked state.
The phase synchronization means may have a frequency band that can be synchronized and may output the reference clock having a frequency close to the frequency band in an unlocked state.
The method according to the present invention relates to a signal processing method. The signal processing method includes a modulation step of modulating an input signal based on a reference clock, an amplification step of amplifying and outputting the modulated input signal, and a phase synchronization process based on the source clock. A reference clock generation step for generating a clock, a synchronization state output step for outputting the synchronization state of the generated reference clock with the source clock, and an output for controlling the operation of the amplification step according to the synchronization state of the phase synchronization processing A control step.
Further, the output control step may turn off the output by the operation of the amplification step when the synchronization state output in the synchronization state output step is unlocked.
In the modulation step, when the synchronization state output in the synchronization state output step is unlocked, noise reduction processing may be performed before the operation of turning off the output due to the operation of the amplification step. Good.
In addition, when the synchronization state output in the synchronization state output step is unlocked, the timer operation starts with a predetermined timer time, and when the timer time is reached, the amplification step operation is turned off. There may be provided a timer operation step for outputting a signal to be used.
In addition, when the synchronization state output in the synchronization state output step is unlocked, the signal level of the input signal input to the modulation step before the operation of turning off the output due to the operation of the amplification step There may be provided a level adjustment process for performing a level adjustment process for lowering.
The synchronization state output step may output a warning state that may be unlocked as the synchronization state, and the modulation step may perform noise reduction processing according to the warning state.
The synchronization state output step may output a warning state that may be unlocked as the synchronization state, and the level adjustment step may perform a level adjustment process according to the warning state.
Further, the synchronization state output step may have a frequency band that can be synchronized, and may output the reference clock of the frequency band even in an unlocked state.
In the synchronization state output step, an upper limit and a lower limit may be provided for the frequency of the reference clock output in the unlock state.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which implement | achieves circuit protection of a class-D amplifier when abnormality in clock input arises can be provided. Further, from another viewpoint, it is possible to provide a technique for preventing a noise such as a pop sound from being output when an abnormality occurs in the clock input.

  Next, the best mode for carrying out the present invention (hereinafter simply referred to as “embodiment”) will be specifically described with reference to the drawings. In the present embodiment, a PLL (Phase-locked loop) circuit is provided as a protection circuit for the class D amplifier, and when an unlocked state occurs in the PLL circuit, the protection process is executed to prevent abnormal noise output and D Class circuit amplifier circuit failure is prevented.

<First Embodiment>
An outline of the present embodiment will be described. In a conventional class D amplifier, a clock stop is detected by applying an LPF (Low Pass Filter) to the clock itself and checking its output level. However, in this case, when the clock cycle is extended, it is not possible to detect a clock failure. As a result, there is a possibility that the pulse modulation circuit oscillates, accompanying noise, and in the worst case, the output circuit may fail. Therefore, in this embodiment, in order to detect not only the stop of the source clock but also the extension of the source clock period, the unlock signal of the PLL circuit is used as a detection signal of the clock unstable state / stop state. Details will be described below.

  FIG. 1 is a functional block diagram showing a schematic configuration of the audio output device 110 according to the present embodiment. The audio output device 110 is mounted on, for example, a television receiver. The audio output device 110 includes a class D amplifier 120 that receives an audio signal S_A of an analog signal or a PCM (Pulse Code Modulation) signal, a speaker SP, and a PLL circuit 160.

  The class D amplifier 120 performs ΔΣ modulation processing by PDM (Pulse Density Modulation) processing and drives the speaker SP by differential driving. The class D amplifier 120 includes a pulse modulation circuit 130, an output control circuit 140, and an amplifier circuit 150 (a high-side amplifier circuit 150a and a low-side amplifier circuit 150b). Note that PWM (Pulse Width Modulation) processing may be used as the modulation method.

  The pulse modulation circuit 130 performs ΔΣ modulation processing by PDM modulation on the input audio signal S_A, and outputs it to the output control circuit 140 as a modulated audio signal S_Am. Note that the modulation process and configuration are general PWM processing or PDM processing techniques, and description thereof is omitted here. In addition, the audio clock CLK_A that functions as a reference clock is acquired from the PLL circuit 160 for PDM processing.

  FIG. 2 is a functional block diagram showing a schematic configuration of the PLL circuit 160. The PLL circuit 160 includes a phase comparator 161, a loop filter 162, a VCO 163, a first frequency divider 164, a second frequency divider 165, and an unlock detector 166. The PLL circuit 160 is a circuit that outputs a signal having a desired frequency by general PLL processing. The phase comparator 161 compares the phase difference between the two signals and generates a difference signal. Here, the source clock CLK_S input as a reference signal from the outside is compared with the signal fed back from the second frequency divider 165.

  The loop filter 162 removes the AC component of the above difference signal and outputs only the DC component. The VCO 163 outputs an oscillation signal having a frequency corresponding to the output level of the loop filter 162 to the first and second frequency dividers 164 and 165. FIG. 3 is a diagram showing the V-F characteristics of the VCO 163.

  The first frequency divider 164 divides the oscillation signal output from the VCO 163 into a predetermined multiple and outputs it. Similarly, the second frequency divider 165 divides the oscillation signal output from the VCO 163 by a predetermined multiple and outputs it to the phase comparator 161 as a feedback signal. The output of the VCO 163 is feedback controlled so that the difference signal becomes zero.

The unlock detector 166 determines whether or not the PLL circuit 160 is properly synchronized, that is, whether or not it is in a locked state. As an unlocking detection method, a known detection method can be applied, and specifically, the following methods 1) to 3) can be exemplified.
1) A method of detecting an abrupt change in the source clock CLK_S by acquiring the output of the phase comparator 161; This method is a method of determining that an unlock state has been established when the error signal suddenly increases. When the frequency of the source clock CLK_S changes slowly, the unlock signal S_UL is not output until it really goes out of the lock range.
2) A method of comparing the output voltage of the loop filter 162 with a reference voltage; there is a feature that the unlocked state can be detected relatively easily without depending on the changing speed of the source clock CLK_S.
3) A method of comparing the output frequency of the VCO 163 with a reference clock; In this method, the output of the VCO 163 (or its frequency-divided signal) is compared with a frequency of a separately prepared fixed frequency crystal oscillation circuit or the like. This method requires the provision of a reference clock that is absolutely reliable, and has the feature that the response is not good because the integrated value of the error signal is seen. However, it detects the unlock regardless of the change rate of the source clock CLK_S. There is an advantage that you can.
By using any one of the above methods or a combination of these methods as appropriate, desired unlock detection accuracy can be realized. Of course, detection methods other than those described above may be used. Then, the unlock detector 166 outputs an unlock signal S_UL indicating the locked state and the unlocked state. In the present embodiment, the unlock signal S_UL is output to the output control circuit 140. Further, the unlock signal S_UL becomes a low output in the locked state, and becomes a high output in the unlocked state.

  The output control circuit 140 includes a high side control circuit 140a, a low side control circuit 140b, and an inverter 143. The output control circuit 140 also includes an audio signal input unit 148 that inputs the modulated audio signal S_Am from the pulse modulation circuit 130 and a control signal input unit 149 that inputs the unlock signal S_UL from the PLL circuit 160.

  The modulated audio signal S_Am is input to the high side control circuit 140a and is inverted and input to the low side control circuit 140b via the inverter 143. The unlock signal S_UL is input to the high side control circuit 140a and the low side control circuit 140b.

  The high side control circuit 140a includes a NAND circuit 141a and a NOR circuit 142a arranged in parallel. More specifically, the modulated audio signal S_Am is input to one input terminal of the NAND circuit 141a, and the unlock signal S_UL is inverted and input to the other input terminal. Further, the modulated audio signal S_Am is input to one input terminal of the NOR circuit 142a, and the unlock signal S_UL is input to the other input terminal. The outputs of the NAND circuit 141a and the NOR circuit 142a are both output to the high side amplifier circuit 150a according to each logic.

  The low side control circuit 140b has a circuit configuration similar to that of the high side control circuit 140a, and includes a NAND circuit 141b and a NOR circuit 142b arranged in parallel. More specifically, the modulated audio signal S_Am inverted by the inverter 143 is input to one input terminal of the NAND circuit 141b, and the unlock signal S_UL is inverted and input to the other input terminal. Further, the modulated audio signal S_Am inverted by the inverter 143 is input to one input terminal of the NOR circuit 142b, and the unlock signal S_UL is input to the other input terminal. The outputs of the NAND circuit 141b and the NOR circuit 142b are both output to the low side amplifier circuit 150b according to each logic.

  The high side amplifier circuit 150a includes a P channel FET 151a and an N channel FET 152a. The P-channel FET 151a and the N-channel FET 152a are connected in series from the positive power supply potential (+ VDD) to the negative power supply potential (−VDD). Specifically, the source terminal of the P-channel FET 151a is connected to the positive power supply potential (+ VDD), and the drain terminal is connected to the drain terminal of the N-channel FET 152a at the connection point T1. The gate terminal is connected to the output part of the NAND circuit 141a. The source terminal of the N-channel FET 152a is connected to the negative power supply potential (−VDD), and the gate terminal is connected to the output part of the NOR circuit 142a. The connection point T1 is connected to one terminal of the speaker SP via an LPF configured by an inductance L1 and a capacitor C1. Note that the negative power supply potential (−VDD) is the ground potential G here.

  The low side amplifier circuit 150b has the same configuration as the high side amplifier circuit 150a, and includes a P-channel FET 151b and an N-channel FET 152b. The P-channel FET 151b and the N-channel FET 152b are connected in series from the positive power supply potential (+ VDD) to the negative power supply potential (−VDD). Specifically, the source terminal of the P-channel FET 151b is connected to the positive power supply potential (+ VDD), and the drain terminal is connected to the drain terminal of the N-channel FET 152b at the connection point T2. The gate terminal is connected to the output part of the NAND circuit 141b. The source terminal of the N-channel FET 152b is connected to the negative power supply potential (−VDD), and the gate terminal is connected to the output part of the NOR circuit 142b. The connection point T2 is connected to the other terminal of the speaker SP through an LPF composed of an inductance L2 and a capacitor C2. Note that the negative power supply potential (−VDD) is the ground potential G here.

  The operation of the above configuration will be described based on the timing chart of FIG. Here, the source clock CLK_S, the audio clock CLK_A, the unlock signal S_UL, the output of the high side amplifier circuit 150a, and the output of the low side amplifier circuit 150b are shown. 4A shows a case in which the source clock CLK_S is stopped, and FIG. 4B shows a case in which the frequency of the source clock CLK_S is reduced and extended.

  As shown in FIGS. 4A and 4B, the source clock CLK_S is normally input during the period of time T10 to T11. In FIG. 4A, the source clock CLK_S is not input at time T11, and the source clock CLK_S input to the PLL circuit 160 remains at a low output.

  Then, since the PLL circuit 160 has a frequency range (lock range) that can be locked, after the input of the source clock CLK_S is stopped, the PLL circuit 160 cannot be locked (time T12), that is, the unlock detector 166 enters the unlocked state. When detected, the unlock signal S_UL is output high.

  Further, as shown in FIG. 4B, the period of the source clock CLK_S becomes unstable at time T11 and becomes unstable, and the clock signal goes out of the lock range at time T12. At that timing, the PLL circuit 160 unlocks the unlock signal S_UL. Is output high.

  Accordingly, in both of FIGS. 4A and 4B, after time T12, the outputs of the NAND circuits 141a and 141b to which the unlock signal S_UL is input become high, and as a result, the high-side amplifier circuit 150a The P channel FET 151a and the P channel FET 151b of the low side amplifier circuit 150b are turned off. Similarly, the outputs of the NOR circuits 142a and 142b to which the unlock signal S_UL is input become low. As a result, the N channel FET 152a of the high side amplifier circuit 150a and the N channel FET 152b of the low side amplifier circuit 150b are turned off. As a result, both the high-side amplifier circuit 150a and the low-side amplifier circuit 150b become high impedance (Hi-Z).

  As described above, according to the present embodiment, for example, when the source clock CLK_S suddenly becomes unstable or stopped and goes out of the lock range of the PLL circuit 160, the PLL circuit 160 falls into a so-called free-run state. However, the audio clock CLK_A can be kept at a frequency that is relatively close to the normal time. That is, although the audio clock CLK_A is not optimal for the class D amplifier, it does not stop, so the pulse modulation circuit 130 continues to operate in a state relatively close to normal for a while. That is, the pulse modulation circuit 130 is unlikely to fall into an oscillation state. Even if the PLL circuit 160 is completely in a free-run state and the clock cycle is extended, the pulse modulation circuit 130 is operating. It will not be in a state to apply. When the PLL circuit 160 is unlocked, the PLL circuit 160 outputs an unlock signal S_UL indicating the unlocked state. Based on this signal, the output control circuit 140 turns off the amplifier circuit 150 before the pulse modulation circuit 130 falls into an abnormal state such as oscillation, so that the class D amplifier 120 is turned off without being destroyed.

<Second Embodiment>
In the present embodiment, the PLL circuit uses the unstable / stopped state of the clock as the detection circuit, and after entering the unstable / stopped state of the clock, that is, after entering the unlocked state, the normal frequency In the pulse modulation circuit, a pop noise generation prevention process by pulse control is performed using a period in which the audio clock operates at a frequency close to. Details will be described below.

  FIG. 5 is a functional block diagram showing a schematic configuration of the audio output device 210 according to the present embodiment. Since the audio output device 210 of the present embodiment has a configuration similar to that of the audio output device 110 of the first embodiment, the same components are denoted by the same reference numerals, description thereof will be omitted as appropriate, and different configurations and operations will be described. .

  The difference from the first embodiment is that the output destination of the unlock signal S_UL of the PLL circuit 260 is not the output control circuit 140 but the pulse modulation circuit 230 in the class D amplifier 220. The configuration of the PLL circuit 260 is the same as that of the PLL circuit 160 of the first embodiment. The control signal input unit 149 of the output control circuit 140 receives the pulse control processing completion signal PF1 output from the pulse modulation circuit 230 instead of the unlock signal S_UL.

  A specific operation will be described based on the timing chart of FIG. In this embodiment, the case where the source clock CLK_S is stopped will be described. However, as a matter of course, the present invention can also be applied when the source clock CLK_S becomes unstable as in the first embodiment.

  During the time T20 to T21, the source clock CLK_S is normally input to the PLL circuit 260. At time T21, the source clock CLK_S is not input to the PLL circuit 260. Then, the PLL circuit 260 cannot control to maintain the locked state, and the unlock detector 166 outputs the unlock signal S_UL high at time T22. Then, the pulse modulation circuit 230 performs a pop noise generation prevention process in a predetermined period of time T22 to T23. For example, if the pulse modulation circuit 230 is a circuit that performs PDM processing, the pop noise generation prevention processing is performed by reducing the pulse width or gradually increasing the pulse period.

  FIG. 7 is a functional block diagram of the pulse modulation circuit 230 having a pop noise occurrence prevention process, and FIG. 8 is a timing chart of the pop noise occurrence prevention process. Here, the ΔΣ modulation process will be briefly described, followed by the pop noise generation prevention process. The pulse modulation circuit 230 performs ΔΣ modulation on the input signal # 10 (audio signal S_A). Then, the amplifier circuit 150 disposed in the subsequent stage amplifies the ΔΣ modulation signal and differentially drives a load such as the speaker SP. The input signal # 10 may be an analog signal or a digital signal such as a PCM signal. Here, illustration of the output control circuit 140 is omitted.

  The pulse modulation circuit 230 includes an integration circuit 1110, a quantization circuit 1120, a pulse width adjustment circuit 1130, a selector 1140, a delay circuit 1150, a mute control circuit 1200, a pulse density measurement circuit 1300, and a transition pulse generation circuit 1400. .

  The integration circuit 1110 receives a difference value obtained by subtracting the value of the delayed switching signal # 60 from the value of the input signal # 10. The integrating circuit 1110 integrates the difference value signal # 20 consisting of this difference value. The integration signal # 30, that is, the integration value output from the integration circuit 1110 is supplied to the quantization circuit 1120.

  The quantization circuit 1120 generates positive and negative switching signals # 41 and # 42 for driving the amplifier circuit 150 by comparing the value of the integration signal # 30 with the threshold Th. The positive and negative switching signals # 41 and # 42 are digital signals for controlling the switching elements of the amplifier circuit 150, and the pulse density of the positive switching signal # 41 (the value of the switching signal # 41 is “1”. The difference between the number of times per unit time) and the pulse density of the negative switching signal # 42 is a pulse density modulation signal that is approximately proportional to the value of the input signal # 10.

  More specifically, the positive switching signal # 41 is a digital signal that takes a logical value “1” when the value of the integral signal # 30 is greater than the threshold Th> 0, and takes a logical value “0” otherwise. The negative switching signal # 42 is a digital signal that takes “1” when the value of the integral signal # 30 is smaller than the negative threshold −Th, and takes a logical value “0” otherwise. The quantization circuit 1120 is configured to be able to change the threshold value Th, and this threshold value Th is determined by the mute control circuit 1200.

  The quantization circuit 1120 quantizes the integration value by the integration circuit 1110, and outputs either “1” or “0” for each operation clock. That is, the switching signals # 41 and # 42 generated by the quantization circuit 1120 are configured by unit pulses having a pulse width corresponding to the operation clock. If the quantization circuit 1120 outputs “1” twice in succession, a switching pulse having two operation clock widths (pulses composed of two unit pulses) is obtained, and the quantization circuit 1120 continues to output “1” three times in succession. ", A switching pulse having a width of three operation clocks (a pulse composed of three unit pulses) is obtained.

  Note that the switching signal for driving the amplifier circuit 150 is not limited to the above, such as a binary digital signal, a ternary digital signal, or a combination thereof. Digital signals can be used. For example, when the amplifier circuit 150 is a single-bridge amplifier circuit, a switching signal that takes a value “1” when the value of the integral signal # 30 is larger than the threshold Th> 0 and a value “0” otherwise is used. May be.

  The pulse width adjustment circuit 1130 widens the pulse widths of the positive and negative switching pulses so that the pulse widths of the switching pulses constituting the positive and negative switching signals # 41 and # 42 do not fall below the lower limit pulse width W. In other words, the value of the switching signal # 41 is corrected so that the time during which the value of the switching signal # 41 is continuously “1” does not fall below the lower limit value W (the same applies to the negative switching pulse # 42). As will be described later, the pulse width adjustment circuit 1130 is configured to be able to change the lower limit pulse width W, and the lower limit pulse width W is determined by the muffling control circuit 1200.

  The positive and negative switching signals # 51 and # 52 obtained by the pulse width adjustment circuit 1130 are supplied to the amplifier circuit 150 and the delay circuit 1150 via the selector 1140. The delay circuit 1150 delays the difference value between the positive switching signal # 51 and the negative switching signal # 52 by N operation clocks. Delayed switching signal # 60 obtained by delaying the difference value between positive switching signal # 51 and negative switching signal # 52 is fed back to integration circuit 1100 described above.

  The output signal # 71 obtained by driving the amplifier circuit 150 (high-side amplifier circuit 150a) with the positive switching signal # 51 is smoothed by the LPF 1170, and the smoothed output signal # 81 is the load (speaker SP). Input to the positive terminal. On the other hand, the output signal # 72 obtained by driving the amplifier circuit 150 (low-side amplifier circuit 150b) with the negative switching signal # 52 is smoothed by the LPF 1170, and the smoothed output signal # 82 is the load (speaker SP). Is input to the negative terminal.

  As described above, since the pulse modulation circuit 230 includes the pulse width adjustment circuit 1130 that widens the pulse width of the switching pulse that drives the amplification circuit 150, for example, the lower limit pulse width of the pulse width adjustment circuit 1130 is set as the operation clock. By setting it to several times, the switching frequency of the amplifier circuit 150 can be reduced to a fraction. Thereby, heat generation and unnecessary radiation in the amplifier circuit 150 can be suppressed.

  However, since the lower limit of the pulse width of the switching pulse is limited, the quantization error in the ΔΣ modulation process increases, and the pop sound accompanying the quantization error generated when the ΔΣ modulation process is stopped also increases.

  Therefore, the pulse modulation circuit 230 has a mute control circuit 1200, a pulse density measurement circuit 1300, and a transition pulse generation circuit as a configuration for reducing the pop sound accompanying the quantization error generated when the ΔΣ modulation process is stopped. 1400.

  The silencer control circuit 1200 supplies the lower limit pulse width instruction signal to the pulse width adjustment circuit 1130 and stops the lower limit pulse width W sequentially before stopping the ΔΣ modulation process. As a result, the quantization error in the ΔΣ modulation can be reduced, and the pop sound generated when the ΔΣ modulation process is stopped can be reduced.

  The silencer control circuit 1200 supplies a threshold value instruction signal to the quantization circuit 1120 and stops the threshold value Th sequentially before stopping the ΔΣ modulation process. As a result, the quantization error in the ΔΣ modulation process can be further reduced, so that the pop sound generated when the ΔΣ modulation process is stopped can be further reduced.

  Further, after lowering the lower limit pulse width W of the switching pulse to one operating clock, the pulse density measuring circuit 1300 measures the pulse density of the switching signal # 51. The transition pulse generation circuit 1400 reads the pulse density measured by the pulse density measurement circuit 1300, and generates transition signals # 91 and # 92 with the pulse density of the read switching signal # 51 as the initial pulse density.

  The transition pulse generation circuit 1400 generates unit pulses having a pulse width corresponding to one operation clock as the transition pulses constituting the transition signals # 91 and # 92 at an appropriate timing so that the pulse density sequentially decreases. It is configured. As a result, the DC component of the applied voltage to the load is reduced by reducing the pulse width of the switching pulse, and then the DC component can be further reduced by reducing the pulse density of the transition pulse. Thereby, the pop sound that can be generated when the generation of the transition pulse is stopped can be sufficiently reduced.

(Silence operation of pulse modulation circuit)
Next, the silencing operation executed under the control of the silencing control circuit 1200 will be described in more detail with reference to FIGS.

  FIG. 8 is a timing chart illustrating the silencing operation of the pulse modulation circuit 230. The mute control circuit 1200 counts the elapsed time T from the time when the mute command is given (time T0), that is, the value of the mute command signal rises from “0” to “1”. Each process of the silencing operation executed by the control of the silencing control circuit 1200 is executed when the elapsed time T reaches preset times T1, T2, T3, and T4, as will be described below. The

  When the elapsed time reaches “time T1”, the mute control circuit 1200 supplies the quantization circuit 1120 with a threshold value instruction signal indicating a threshold value smaller than the standard threshold value Th. The quantization circuit 1120 reduces the threshold to 3/4 of the standard threshold Th based on the value of the threshold instruction signal. At the same time, the mute control circuit 1200 supplies the pulse width adjustment circuit 1130 with a lower limit pulse width instruction signal indicating a pulse width smaller than the standard lower limit pulse width. Based on this lower limit pulse width instruction signal, the pulse width adjustment circuit 1130 lowers the lower limit pulse width, which was originally equivalent to 4 operation clocks, to 3 operation clocks.

  When the elapsed time reaches “time T2”, the mute control circuit 1200 supplies the quantization circuit 1120 with a threshold value instruction signal indicating a smaller threshold value. The quantization circuit 1120 reduces the threshold value to 2/4 of the standard threshold value Th based on the value of the threshold value instruction signal. At the same time, the mute control circuit 1200 supplies the pulse width adjustment circuit 1130 with a lower limit pulse width instruction signal indicating a smaller lower limit pulse width. The pulse width adjustment circuit 1130 reduces the lower limit pulse width to the equivalent of two operation clocks based on the lower limit pulse width instruction signal.

  When the elapsed time reaches “time T3”, the mute control circuit 1200 supplies a threshold value instruction signal indicating a smaller threshold value to the quantization circuit 1120. The quantization circuit 1120 reduces the threshold to ¼ of the standard value Th based on the value of the threshold instruction signal. At the same time, the mute control circuit 1200 supplies a pulse width control signal indicating a smaller lower limit pulse width to the pulse width adjustment circuit 1130. The pulse width adjustment circuit 1130 reduces the lower limit pulse width to the equivalent of one operation clock based on the lower limit pulse width instruction signal.

  Further, the silencing control circuit 1200 raises the value of the pulse density measurement command signal supplied to the pulse density measurement circuit 1300 from “0” to “1” when the elapsed time reaches “time T3”. The pulse density measurement circuit 1300 counts the number of pulses constituting the switching signal # 51 (the number of times the value of the switching signal # 51 becomes “1”) when the value of the pulse density measurement command signal rises to “1”. To start.

  When the elapsed time reaches “time T4”, the mute control circuit 1200 lowers the value of the pulse density measurement command signal supplied to the pulse density measurement circuit 1300 from “1” to “0”. When the value of the pulse density measurement command signal falls to “0”, the pulse count is stopped. The number of pulses counted by the pulse density measuring circuit 1300 is the number of pulses per time Tc = T4−T3 (constant), that is, the average pulse density with the time Tc as a unit time.

  Further, when the elapsed time reaches 74, the silencing control circuit 1200 causes the transition pulse generation circuit 1400 to raise the value of the transition pulse generation command signal supplied to the transition pulse generation circuit 1400 from “0” to “1”. When the value of the transition pulse generation command signal rises to “1”, generation of transition signals # 91 and # 92 with the average pulse density measured by the pulse density measurement circuit 1300 as the initial pulse density is started.

  Further, the mute control circuit 1200 changes the value of the output pulse switching command signal supplied to the selector 1140 from “1” to “2” when the elapsed time reaches T4. When the value of the output pulse switching command signal becomes “2”, the selector 1140 switches the signal supplied to the amplifier circuit 150 from the switching signals # 51 and # 52 to the transition signals # 91 and # 92.

  Thereafter, the silencing control circuit 1200 changes the value of the output pulse switching command signal from “2” to “0” when the pulse density of the transition signals # 91 and # 92 becomes equal to or less than the predetermined value Dth. When the value of the output pulse switching command signal changes to “0”, the selector 1140 switches the signal supplied to the amplifier circuit 150 to a dummy signal whose value is “0”. As a result, no pulse is input to the amplifier circuit 150.

  FIG. 9 is a diagram illustrating a signal waveform obtained as a result of the silencing operation shown in FIG. In the figure, a signal expressed as a pulse is a signal input to the amplifier circuit 150, that is, switching signals # 51 (solid line) and # 52 (dotted line) before the elapsed time T4, and a transition signal after the elapsed time T4. # 91 (solid line) and # 92 (dotted line) are shown. A signal expressed as a curve represents a smoothed output signal # 81. In this way, pop noise generation prevention processing in the pulse modulation circuit 230 is performed. Note that the pop noise generation prevention process described here is an example, and the present invention is not limited to this. For example, only the processing for adjusting the pulse width (processing at times T0 to T4) may be used.

  When the pop noise generation prevention process ends (time T23 in FIG. 6), the pulse modulation circuit 230 outputs the pulse control process completion signal PF1 to the output control circuit 140 (control signal input unit 149). As a result, as in the first embodiment, the high-side amplifier circuit 150a and the low-side amplifier circuit 150b become high impedance (Hi-Z).

  As described above, according to the present embodiment, even when the source clock CLK_S becomes unstable or stopped, the audio clock CLK_A does not stop immediately. Further, the audio clock CLK_A operates at a frequency close to the normal frequency for a while after the source clock CLK_S becomes unstable or stopped for a very short time. Using the time during which the audio clock CLK_A is moving, the pulse modulation circuit 230 can perform pop noise generation prevention processing by pulse control. Then, the output control circuit 140 turns off the amplifier circuit 150 (the high-side amplifier circuit 150a and the low-side amplifier circuit 150b) based on the pulse control processing completion signal PF1 indicating that the processing is completed, which is uncomfortable for the user. It is possible to avoid the destruction of the amplifier circuit 150 due to the unstable state / stopped state of the source clock CLK_S without generating a pop sound.

<Third Embodiment>
In the present embodiment, the PLL circuit uses the unstable / stopped state of the clock as the detection circuit, and after entering the unstable / stopped state of the clock, that is, after entering the unlocked state, the normal frequency In a signal processing circuit arranged upstream of the pulse modulation circuit, a pop noise generation prevention process is controlled by controlling the PCM signal using a period in which the audio clock operates at a frequency close to. Details will be described below.

  FIG. 10 is a functional block diagram showing a schematic configuration of the audio output device 310 according to the present embodiment. Since the audio output device 310 of the present embodiment has a configuration similar to that of the audio output device 110 of the first embodiment, the same components are denoted by the same reference numerals, description thereof will be omitted as appropriate, and different configurations and operations will be described. .

  The difference from the first embodiment is that the output from the PLL circuit 360 is not only for the class D amplifier 320 but also for the signal processing circuit 370 which is a DSP (Digital Signal Processor) that performs PCM signal processing in the preceding stage. Made. Specifically, the unlock signal S_UL is output to the signal processing circuit 370 that performs PCM signal processing. The audio signal S_A subjected to PCM signal processing by the signal processing circuit 370 is output to the pulse modulation circuit 330 via the DAC 371.

  In addition, the audio clock is an output destination of two systems of the first audio clock CLK_A1 output to the pulse modulation circuit 330 and the second audio clock CLK_A2 output to the signal processing circuit 370. When the signal processing circuit 370 obtains a high output of the unlock signal S_UL, which is a signal indicating that the source clock CLK_S has become unstable or stopped, from the PLL circuit 360, the signal processing circuit 370 gradually decreases the attenuation level of the PCM signal. For example, volume adjustment processing is finally performed to set −∞. Note that the target volume level is not limited to -∞ but may be 30%, and is not intended to be limited to a specific level. When the volume adjustment is completed, a PCM signal control process completion signal PF2 indicating the completion is output to the output control circuit 140 (control signal input unit 149). Then, the output control circuit 140 turns off the amplifier circuit 150 based on the signal.

  A specific operation will be described based on the timing chart of FIG. In this embodiment, the case where the source clock CLK_S is stopped will be described. However, as a matter of course, the present invention can also be applied when the source clock CLK_S becomes unstable as in the first embodiment.

  During the period of time T30 to T31, the source clock CLK_S is normally input to the PLL circuit 360. At time T31, the source clock CLK_S is not input to the PLL circuit 360. Then, the PLL circuit 360 cannot be controlled to maintain the locked state, and the first and second audio clocks CLK_A1 and CLK_A2 are gradually extended. At time T32, the PLL circuit 360 cannot be locked, and the unlock detector 166 outputs the unlock signal S_UL high. Then, the signal processing circuit 370 performs volume adjustment processing for lowering the attenuation level of the PCM signal during the period of time T32 to T33. When the volume adjustment process ends at time T33, the signal processing circuit 370 outputs a PCM signal control process completion signal PF2 to the output control circuit 140. Then, based on the PCM signal control processing completion signal PF2, the amplifier circuit 150 becomes high impedance (Hi-Z) and is turned off.

  As described above, according to the present embodiment, even when the source clock CLK_S becomes unstable or stopped, the audio clock (the first and second audio clocks CLK_A1, CLK_A2) does not stop immediately. The audio clock CLK_A (the first and second audio clocks CLK_A1 and CLK_A1, the first and second audio clocks CLK_A1,. CLK_A2) is operating. By using the time during which the audio clocks (first and second audio clocks CLK_A1, CLK_A2) are moving, the signal processing circuit 370 can perform the pop noise generation prevention process by controlling the PCM signal. Then, the output control circuit 140 turns off the amplifier circuit 150 based on the PCM signal control processing completion signal PF2 indicating that the processing is completed, so that the source clock CLK_S is generated without generating an unpleasant pop sound for the user. It is possible to avoid the destruction of the amplifier circuit 150 due to the unstable state / stop state.

  In the present embodiment, the first and second audio clocks CLK_A1 and CLK_A2 supplied to the signal processing circuit 370 and the pulse modulation circuit 330 have the same clock frequency. However, the present invention is not limited to this. In any case, by outputting from one PLL circuit 360, the synchronization between the first and second audio clocks CLK_A1 and CLK_A2 is maintained, and the two circuits are directly connected by a digital signal without a DAC 371 or the like. Even in such a case, data can be transmitted without error. If the DAC 371 is present, the first and second audio clocks CLK_A1 and CLK_A2 may be generated from different PLL circuits.

<Fourth embodiment>
In the present embodiment, the technique is a combination of the second and third embodiments described above. When the PLL circuit is in an unlocked state where synchronization is not possible, volume adjustment processing and pop noise generation prevention processing are performed. FIG. 12 is a functional block diagram showing a schematic configuration of the audio output device 410 according to the present embodiment. Since this audio output device 410 has a configuration similar to that of the audio output device 310 of the third embodiment, the same components are denoted by the same reference numerals, description thereof is omitted as appropriate, and different configurations and operations will be described.

  When the PLL circuit 460 is unlocked, the output destination of the unlock signal S_UL output from the PLL circuit 460 and the first and second audio clocks CLK_A1 and CLK_A2 are the same. A difference is that a PCM signal control processing completion signal PF3 indicating the end of the volume adjustment processing in the signal processing circuit 470 is output to the pulse modulation circuit 430 of the class D amplifier 420 instead of the output control circuit 140. Further, the pulse modulation circuit 430 that has acquired the PCM signal control processing completion signal PF3 performs the pop noise generation prevention processing as shown in the second embodiment, and outputs the pulse control processing completion signal PF4 when the processing ends. High output to the control circuit 140 (control signal input unit 149). As a result, the high-side amplifier circuit 150a and the low-side amplifier circuit 150b finally become high impedance (Hi-Z), and the amplifier circuit 150 is turned off.

  A specific operation will be described based on the timing chart of FIG. In this embodiment, the case where the source clock CLK_S is stopped will be described. However, as a matter of course, the present invention can also be applied when the source clock CLK_S becomes unstable as in the first embodiment.

  During the period from time T40 to T41, the source clock CLK_S is normally input to the PLL circuit 460. At time T41, the input of the source clock CLK_S to the PLL circuit 460 disappears. Then, the PLL circuit 460 cannot control to maintain the locked state, and the first and second audio clocks CLK_A1 and CLK_A2 are gradually extended. At time T42, the PLL circuit 360 cannot be locked, and the unlock detector 166 outputs the unlock signal S_UL high. Then, the signal processing circuit 470 performs volume adjustment processing for lowering the attenuation level of the PCM signal during the period of time T42 to T43. When the volume adjustment process ends at time T43, the signal processing circuit 370 outputs the PCM signal control process completion signal PF3 to the pulse modulation circuit 430. Subsequently, the pulse modulation circuit 430 performs pop noise generation prevention processing during a period of time T43 to T44, and outputs high to the output control circuit 140 (control signal input unit 149) when the processing ends. As a result, the high-side amplifier circuit 150a and the low-side amplifier circuit 150b finally become high impedance (Hi-Z), and the amplifier circuit 150 is turned off.

  As described above, according to the present embodiment, it is possible to avoid the destruction of the amplifier circuit 150 due to the unstable state / stopped state of the source clock CLK_S without generating an unpleasant pop sound for the user. That is, even if the input audio signal is not at a zero level, the signal processing circuit 470 eliminates the pop sound caused by the discontinuity of the audio signal, and the pulse modulation circuit 430 of the class D amplifier 420 further eliminates the pulse discontinuity. By eliminating the pop sound caused by the above, even if the input audio signal is not at the 0 level, the amplifier circuit due to overcurrent when the source clock CLK_S is stopped without producing a very loud pop sound uncomfortable for the user at all. 150 destruction can be prevented.

<Fifth Embodiment>
The output of the unlock signal S_UL from the unlock detector 166 of the PLL circuits 260, 360, and 460 in the first to fourth embodiments is output in two stages of high and low. However, in the present embodiment, the fluctuation state of the source clock CLK_S is output even before being out of the lock range. Then, abnormal noise generation prevention processing is performed immediately in each output destination circuit. In general, even if the frequency of the source clock CLK_S varies, the PLL circuits 260, 360, and 460 follow the variation in the frequency of the source clock CLK_S while being locked to some extent. That is, there is a time difference between the time when the source clock CLK_S is abnormal and the time when the source clock CLK_S deviates from the frequency fluctuation that should be followed and becomes unlocked and outputs the unlock signal S_UL. In the processing in the above-described first to fourth embodiments (particularly, the second to fourth embodiments), the closer to the normal frequency the audio clock CLK_A is, the less likely it is to be in the unlocked state. Accordingly, when the source clock CLK_S is in a suspicious state, the processing shown in the above embodiment is started immediately, so that the period of the audio clock CLK_A is extended before the processing starts or during the processing. To prevent the trouble that becomes too much noise.

  More specifically, for example, the unlock detector 166 uses the difference signal detected by the phase comparator 161 as one of the signals used for the detection, and outputs a signal corresponding to the difference signal. Then, the pulse modulation circuits 230, 330, and 430 and the signal processing circuits 370 and 470 perform a pop noise generation prevention process corresponding to the signal. FIG. 14 is a diagram showing the relationship between the difference signal (phase difference) input to the unlock detector 166 and the output level of the unlock signal S_UL. When the phase difference is smaller than D1, the unlock detector 166 determines that it is the lock region and outputs a low level (“zero”). When the phase difference is D1 to D5, four levels of signals S_UL1 to S_UL1-4 are output as warning areas that may be unlocked. When the phase difference is D5 or more, it indicates that the state is completely unlocked. The signal S_UL0 is output. The signal S_UL0 corresponds to the unlock signal S_UL described above. For example, when applied to the configuration and operation of the second embodiment, in the pulse modulation circuit 230, the signal S_UL3 becomes high even if the signal S_UL0 is not high, that is, the unlock signal state is not obtained. At this point, the operation at time T0 to T5 in FIG. 8 is started.

<Sixth Embodiment>
As described above, even if the frequency of the source clock CLK_S varies, the PLL circuit 160 follows the variation in the frequency of the source clock CLK_S while being locked to some extent. However, when it is known in advance that the fluctuation of the source clock CLK_S is small, the first to fourth implementations described above are provided by providing the upper and lower limits of the audio clock CLK_A output in the unlocked state, that is, the free-run state. This prevents a problem that the clock cycle is excessively extended in the middle of the pop noise generation prevention process in the form and becomes abnormal noise. Therefore, in this embodiment, an upper limit and a lower limit are provided for the voltage of the VCO 163 of the PLL circuit 160. FIG. 15 is a diagram showing the relationship between the voltage of the VCO 163 and the output frequency. As shown in the figure, when the input voltage is V1 to V2, the VCO 163 outputs frequencies f1 to f2 according to the input voltage. However, when the input voltage is less than V1, a signal of frequency f1 is output, and when it is greater than V2, a signal of frequency f2 is output. The upper and lower frequencies f1, f2 are frequencies in the locked state or frequencies close to such frequencies. As a result, even in the unlocked (free-run) state, the frequency can be made close to that of the audio clock in the locked state, and it is possible to prevent the clock cycle from being excessively extended during the pop noise generation preventing process and causing abnormal noise.

<Seventh Embodiment>
FIG. 17 is a functional block diagram showing a schematic configuration of the audio output device 1210 of the present embodiment. This audio output device 1210 is a modification of the audio output device 210 (see FIG. 5) of the second embodiment, and a different configuration is that a timer circuit 290 is added. The same components are denoted by the same reference numerals. The description will be omitted, and different configurations and operations will be described below.

  The PLL circuit 260 of the audio output device 1210 outputs the unlock signal S_UL to the timer circuit 290 together with the pulse modulation circuit 230. Then, the timer circuit 290 outputs a pulse control processing completion time notification signal TM1 to the control signal input unit 149 of the output control circuit 140 instead of the pulse control processing completion signal PF1 output from the pulse modulation circuit 230.

  More specifically, when the pulse modulation circuit 230 of the audio output device 1210 obtains the unlock signal S_UL from the PLL circuit 260, as described with reference to FIGS. Pulse width control processing is performed to reduce the width or gradually increase the pulse period. In the timer circuit 290, a processing time assumed in advance as a period for performing the pulse width control process is recorded as a timer operation time. When the timer circuit 290 obtains the unlock signal S_UL from the PLL circuit 260, the timer circuit 290 starts the timer operation. When the timer operation time is reached, the timer circuit 290 stops the timer operation and outputs the pulse control processing completion time notification signal TM1 to the output control circuit 140. The result is output to the control signal input unit 149. Then, the output control circuit 140 turns off the amplifier circuit 150 based on the pulse control processing completion time notification signal TM1. With such a configuration and operation, the same effects as those of the second embodiment can be obtained.

<Eighth Embodiment>
FIG. 18 is a functional block diagram showing a schematic configuration of the audio output device 1310 of the present embodiment. This audio output device 1310 is a modification of the audio output device 310 (see FIG. 10) of the third embodiment, and is different in that a timer circuit 390 is added, and the same components are denoted by the same reference numerals. The description will be omitted, and different configurations and operations will be described below.

  The PLL circuit 360 of the third embodiment outputs the unlock signal S_UL to the signal processing circuit 370, and when the signal processing circuit 370 finishes the volume processing started by acquiring the unlock signal S_UL, the PCM signal control processing A completion signal PF2 was output. The PLL circuit 360 of the audio output device 1310 of this embodiment outputs the unlock signal S_UL to the timer circuit 390 together with the signal processing circuit 370. Then, instead of the PCM signal control processing completion signal PF2 output from the signal processing circuit 370 in the third embodiment, the timer circuit 390 sends a PCM signal control processing to the control signal input unit 149 of the output control circuit 140. The time notification signal TM2 is output.

  More specifically, when the unlocking signal S_UL is acquired, the signal processing circuit 370 starts a volume adjustment process for gradually decreasing the attenuation level of the PCM signal, as in the third embodiment. The timer circuit 390 stores a processing time estimated to be necessary for the above-described volume processing as a timer time. When the timer circuit 390 acquires the unlock signal S_UL, the timer circuit 390 starts the timer operation with the above-described timer time. Then, the timer circuit 390 outputs the PCM signal control processing time notification signal TM2 to the control signal input unit 149 of the output control circuit 140 when the above timer time is reached. Then, the output control circuit 140 turns off the amplifier circuit 150 based on the PCM signal control processing time notification signal TM2. With such a configuration and operation, the same effects as those of the third embodiment can be obtained.

<Ninth Embodiment>
FIG. 19 is a functional block diagram showing a schematic configuration of the audio output device 1410 of the present embodiment. This audio output device 1410 is a modification of the audio output device 410 (see FIG. 12) of the fourth embodiment, and a different configuration is that a timer circuit 490 is added. The description will be omitted, and different configurations and operations will be described below.

  The fourth embodiment is a technique that combines the second and third embodiments. When the PLL circuit 460 enters an unlocked state in which synchronization is not possible, volume adjustment processing and pop noise generation prevention processing are performed, and the processing ends. Then, finally, the pulse modulation circuit 430 outputs the pulse control processing completion signal PF4 to the output control circuit 140 (control signal input unit 149), and the amplifier circuit 150 is turned off. On the other hand, the present embodiment is a technique that combines the seventh and eighth embodiments. When the PLL circuit 460 of the audio output device 1410 enters an unlocked state that cannot be synchronized, the unlock signal S_UL is transmitted to the signal processing circuit 470 and the timer circuit. Output to 490. The signal processing circuit 470 starts volume adjustment processing as in the fourth embodiment. In the timer circuit 490, the time estimated to be necessary for the volume adjustment processing is set as the first timer time, and the time required for the pop noise generation prevention processing (pulse width control processing) is set to the second time. It is set as the timer time. When the timer circuit 490 acquires the unlock signal S_UL, the timer circuit 490 starts a timer operation based on the first timer time. When the first timer time is reached, the timer circuit 490 outputs the PCM signal control processing time notification signal TM3 to the pulse modulation circuit 430. Subsequently, the pulse modulation circuit 430 that has acquired the PCM signal control processing time notification signal TM3 starts pop noise generation prevention processing. In addition, the timer circuit 490 starts a timer operation based on the second timer time. When the second timer time is reached, the timer circuit 490 outputs a PCM signal control processing time notification signal TM4 to the control signal input unit 149. Then, the output control circuit 140 turns off the amplifier circuit 150 based on the PCM signal control processing time notification signal TM4. By such a configuration and operation, the same effect as that of the fourth embodiment can be obtained.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it is understood by those skilled in the art that various modifications can be made to each of those components and combinations thereof, and such modifications are also within the scope of the present invention.

It is a functional block diagram which shows schematic structure of the audio | voice output apparatus based on 1st Embodiment. 1 is a functional block diagram illustrating a schematic configuration of a PLL circuit according to a first embodiment. It is a figure which shows the VF characteristic of VCO of the PLL circuit based on 1st Embodiment. It is a figure which shows the timing chart of a process of the audio | voice output apparatus when the source clock becomes abnormal based on 1st Embodiment. It is a functional block diagram which shows schematic structure of the audio | voice output apparatus based on 2nd Embodiment. It is a figure which shows the timing chart of a process of the audio | voice output apparatus when the source clock becomes abnormal based on 2nd Embodiment. It is a functional block diagram of a pulse modulation circuit having pop noise generation prevention processing according to a second embodiment. It is a timing chart of the pop noise generation prevention processing according to the second embodiment. It is a figure which illustrates the signal waveform obtained as a result of the pop noise generation | occurrence | production prevention process shown in FIG. 8 based on 2nd Embodiment. It is a functional block diagram which shows schematic structure of the audio | voice output apparatus based on 3rd Embodiment. It is a figure which shows the timing chart of a process of the audio | voice output apparatus when the source clock becomes abnormal based on 3rd Embodiment. It is a functional block diagram which shows schematic structure of the audio | voice output apparatus based on 4th Embodiment. It is a figure which shows the timing chart of a process of the audio | voice output apparatus when the source clock becomes abnormal based on 4th Embodiment. It is the figure which showed the relationship between the output level of the difference signal and unlock signal unlock signal which are input into the unlock detector based on 5th Embodiment. It is the figure which showed the relationship between the voltage of VCO of a PLL circuit, and an output frequency based on 6th Embodiment. It is a figure which shows the timing chart of a process of the audio | voice output apparatus when a source clock becomes abnormal based on a prior art. It is a functional block diagram which shows schematic structure of the audio | voice output apparatus based on 7th Embodiment. It is a functional block diagram which shows schematic structure of the audio | voice output apparatus based on 8th Embodiment. It is a functional block diagram which shows schematic structure of the audio | voice output apparatus based on 9th Embodiment.

Explanation of symbols

110, 210, 310, 410, 1210, 1310, 1410 Audio output devices 120, 220, 320, 420 Class D amplifiers 130, 230, 330, 430 Pulse modulation circuit 140 Output control circuit 140a High side control circuit 140b Low side control circuit 141a , 141b NAND circuit 142a, 142b NOR circuit 148 Audio signal input unit 149 Control signal input unit 150 Amplifier circuit 150a High side amplifier circuit 150b Low side amplifier circuit 151a, 151b P-channel FET
152a, 152b N-channel FET
160, 260, 360, 460 PLL circuit 161 Phase comparator 163 VCO
166 Unlock detector 290, 390, 490 Timer circuit

Claims (18)

Modulation means for modulating an input signal based on a reference clock;
Amplifying means for amplifying and outputting the modulated input signal;
A phase synchronization unit that obtains a source clock and generates the reference clock to be used by the modulation unit based on the source clock, and outputs a synchronization state of the acquired source clock and the generated reference clock;
Output control means for controlling the operation of the amplification means according to the synchronization state of the phase synchronization means;
A signal amplifying apparatus comprising:   2. The signal amplification apparatus according to claim 1, wherein the output control means turns off the amplification means when the synchronization state of the phase synchronization means is unlocked.   2. The modulation unit according to claim 1, wherein the modulation unit performs a noise reduction process before the output control unit turns off the amplification unit when the synchronization state of the phase synchronization unit is unlocked. 2. The signal amplification device according to 2.   A control signal for starting a timer operation with a predetermined timer time when the phase synchronization means is unlocked, and for turning off the amplification means with respect to the output control means when the timer time is reached 4. A signal amplifying apparatus according to claim 3, further comprising a timer means for outputting.   When the synchronization state of the phase synchronization means is unlocked, level adjustment processing is performed to lower the signal level of the input signal input to the modulation means before the output control means turns off the amplification means. 5. The signal amplifying apparatus according to claim 1, further comprising a level adjusting unit. The phase synchronization means outputs a warning state that may be unlocked as the synchronization state,
The signal amplifying apparatus according to claim 1, wherein the modulation unit performs noise reduction processing according to the warning state. The phase synchronization means outputs a warning state that may be unlocked as the synchronization state,
6. The signal amplifying apparatus according to claim 1, wherein the level adjusting unit performs a level adjusting process according to the warning state.   7. The signal according to claim 1, wherein the phase synchronization means has a synchronizable frequency band and outputs the reference clock in the frequency band even in an unlocked state. Amplification equipment.   The said phase synchronization means has a frequency band which can be synchronized, and outputs the said reference clock of the frequency close | similar to the said frequency band in the unlocked state. Signal amplifier. A modulation process for modulating an input signal based on a reference clock;
An amplification step of amplifying and outputting the modulated input signal;
A reference clock generating step for generating the reference clock by phase synchronization processing based on the source clock;
A synchronization state output step of outputting a synchronization state of the source clock and the generated reference clock;
An output control step of controlling the operation of the amplification step according to the synchronization state of the phase synchronization process;
A signal processing method comprising:   11. The signal processing method according to claim 10, wherein the output control step turns off the output due to the operation of the amplification step when the synchronization state output in the synchronization state output step is unlocked. .   In the modulation step, when the synchronization state output in the synchronization state output step is unlocked, a noise reduction process is performed before the operation of turning off the output due to the operation of the amplification step. The signal processing method according to claim 10 or 11.   When the synchronization state output in the synchronization state output step is unlocked, a timer operation is started with a predetermined timer time, and when the timer time is reached, the operation of the amplification step is turned off. The signal processing method according to claim 12, further comprising a timer operation step of outputting a signal.   When the synchronization state output in the synchronization state output step is unlocked, the signal level of the input signal input to the modulation step is lowered before the operation of turning off the output due to the operation of the amplification step The signal processing method according to claim 10, further comprising a level adjustment step of performing level adjustment processing. The synchronization state output step outputs a warning state that may be unlocked as the synchronization state,
The signal processing method according to claim 11, wherein the modulation step performs noise reduction processing according to the warning state. The synchronization state output step outputs a warning state that may be unlocked as the synchronization state,
The signal processing method according to claim 11, wherein the level adjustment step performs level adjustment processing according to the warning state.   17. The synchronization state output step has a synchronizable frequency band, and outputs the reference clock of the frequency band even in an unlocked state. Signal processing method.   17. The signal processing method according to claim 11, wherein the synchronization state output step sets an upper limit and a lower limit for the frequency of the reference clock output in the unlock state.

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