JP2010045279A - Method for polishing both surface of semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for polishing both surfaces of a semiconductor substrate, capable of suppressing sagging within tolerance, by preventing an outer peripheral sagging of the substrate, after polishing as much as possible, in response to the planarity required for the semiconductor substrate. <P>SOLUTION: In the method for polishing both surfaces of the semiconductor substrate, a carrier holding the semiconductor substrate is interposed between a pair of upper and lower polishing pads pressed in a mutually approaching direction, and the carrier is rotated about own axis or revolved between the pair of upper and lower polishing pads, in the presence of abrasive grains. In the method for polishing both surfaces of the semiconductor substrate, both surfaces of the front surface and the back surface of the semiconductor substrate held on the carrier are polished simultaneously by the pair of upper and lower polishing pads. In the method, thickness difference (T-t) between the substrate thickness (T) in the case of completion of polishing of the semiconductor substrate and the thickness (t) of the carrier is controlled to 5 μm or larger and 100 μm or smaller. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for double-side polishing a semiconductor substrate, and relates to a method for manufacturing a semiconductor substrate having excellent flatness, which is used for manufacturing an electronic device.

  In the manufacturing process of electronic devices, microfabrication using photolithography is indispensable, and in this photolithography process, it is necessary to accurately transfer the photomask pattern to the photoresist applied to the surface of the semiconductor substrate. However, if the surface of the substrate is uneven, a focus shift occurs and the photomask pattern cannot be properly transferred. If fine processing as designed is not performed due to the focus shift, the device does not operate as an electronic device, and the product yield decreases. In order to avoid such a situation, it is necessary to polish the surface of the substrate to improve the flatness.

  Conventionally, in polishing a semiconductor substrate, the polishing substrate is fixed to a polishing block with wax or the like, and the front and back surfaces of the semiconductor substrate are polished one by one. However, the thickness of the wax or the like becomes uneven, Particles may enter between the semiconductor substrate and the polishing block, resulting in a non-uniform finish thickness of the substrate at the end of polishing, or a local depression of the substrate, resulting in a flat substrate It was difficult to increase the degree.

  In order to solve this problem, a double-side polishing method has been proposed in which a polishing substrate is sandwiched between an upper surface plate and a lower surface plate, and both surfaces are processed simultaneously. In this double-side polishing method, since the front and back surfaces of the substrate can be polished simultaneously without sticking the substrate to the polishing block, it is possible to omit the sticking step with wax or the like, and the flatness of the substrate compared to the single-side polishing method Quality is improved. In electronic devices that require fine processing by lithography, the flatness quality of the substrate is important, and this double-side polishing method has been widely used in the processing of semiconductor substrates.

  Examples of such a double-side polishing method for a semiconductor substrate include Patent Documents 1, 2, and 3, for example. In Patent Document 1, a protected surface is formed on the main surface of a substrate, and a surface that is not protected is polished at a faster speed than the protected surface by using a double-side polishing apparatus, thereby polishing one surface very flat. A method for producing a manufactured semiconductor substrate has been proposed. Further, Patent Document 2 proposes a semiconductor wafer processing system such as a system for simultaneously buffing or scrubbing both surfaces of a wafer.

In Patent Document 3, the flatness is improved by further improving the double-side polishing method. Specifically, assuming that the surface plate changes to concave or convex due to the polishing heat, the surface plate is raised to a reverse convex or concave shape in advance so that the surface plate is flattened by this polishing heat during polishing. It has been proposed to tailor the surface plate and lower surface plate. However, the polishing conditions are not constant depending on the polishing pad, polishing abrasive grains, polishing load, surface plate rotation speed, etc. Furthermore, since the surface condition of the polishing pad changes with time, how much polishing heat is generated. It is not easy to accurately predict whether it will occur, and even if the amount of polishing heat generated can be predicted to some extent, the shape of the surface plate should be adjusted so as to cancel out the expected amount of thermal deformation of the surface plate. It is not easy to precisely process it into a convex or concave shape.
JP-A-9-45,644 Special Table 2002-509,367 JP 2005-335,047 A

  As described above, by applying the double-side polishing method, it becomes possible to prevent deterioration of flatness quality due to quality defects in the sticking process with wax or the like, and a temporary improvement is made compared to the single-side polishing method. Attempts have been made to improve the flatness by further improving the double-side polishing method. However, the technique for realizing good flatness is complicated and cannot be easily applied in industrial applications.

  In general, in substrate polishing, it is known that the flatness of a substrate after polishing is affected by various polishing conditions such as a polishing pad, polishing abrasive grains, polishing load, and surface plate rotation speed. This is not an exception in the double-side polishing method as described above, and as described above, the substrate thickness after polishing becomes uneven in the surface, and the substrate is locally recessed. However, since the outer peripheral portion of the substrate is polished faster than the central portion during polishing, sagging still occurs in the outer peripheral portion of the substrate, and the flatness of the outer peripheral portion of the substrate deteriorates ( The problem of peripheral sag remains.

  In addition, the permissible range of the outer peripheral sag varies depending on the design rule of the device to be manufactured. This is because the stepper is properly used according to the target design rule, but the depth of focus differs depending on the wavelength of the light source used in each stepper. When it becomes large, defocusing occurs and it becomes difficult to form a fine pattern.

  Here, the permissible range of the peripheral sag required for the substrate is quantitatively explained using the flatness index SBIR defined in ASTM F1241 “Wafer Geometry Characteristics; Chapter 1.15 GEOMETRY MEASUREMENT”. In other words, the flatness index SBIR is an index defined by the difference between the maximum value and the minimum value of the substrate thickness within a predetermined site. In other words, it corresponds to a state where the value of SBIR is large at the site located on the outer periphery. In the case of a single crystal silicon carbide substrate, since a power device using this material is manufactured with a design rule of about 0.5 μm, in lithography, a stepper using the i-line of an Hg lamp as a light source (hereinafter abbreviated as “i-line stepper”) .) Is used. In this i-line stepper, since the depth of focus is about 1 μm, if SBIR ≦ 1 μm at the outer peripheral site, defocus does not occur and it is determined that the outer sagging is within an allowable range. On the other hand, in the case of ULSI using a Si substrate, since the design rule is about 0.05 μm, a stepper using an excimer laser as a light source is used in the lithography process. In the stepper using this excimer laser, since the depth of focus is about 0.1 μm, if SBIR ≦ 0.1 μm at the outer peripheral site, defocusing does not occur, and it can be said that the outer sagging is within an allowable range.

  Therefore, the present inventor can prevent as much as possible the occurrence of peripheral sag in the outer peripheral portion of the substrate in double-side polishing of the semiconductor substrate, and can easily suppress the size of the peripheral sag within the allowable range. The present inventors have intensively studied to develop a double-side polishing method for a semiconductor substrate that can easily industrially manufacture a semiconductor substrate having excellent flatness after polishing.

  In the course of studying this double-side polishing method, the present inventor is known to the extent that the peripheral sagging in the double-side polishing method is a polishing pad, polishing abrasives, polishing load, surface plate rotation speed, etc. Not only is it affected by the conditions, but also the thickness difference between the thickness of the semiconductor substrate and the thickness of the carrier that holds the semiconductor substrate during polishing, and the influence gradually increases toward the end of the polishing process. In the final stage of the polishing process, it was found that this was the main cause of the sagging of the outer periphery, and the present invention was completed.

  That is, in the double-side polishing method, for the original purpose of polishing the semiconductor substrate, the semiconductor substrate is always thicker than the carrier holding the semiconductor substrate, but when the semiconductor substrate is excessively thicker than the carrier. The semiconductor substrate is strongly pressed against the polishing pad. In particular, since the outermost peripheral portion of the semiconductor substrate is a portion where the polishing pad is pushed prior to other portions, friction generated between the polishing pad and the polishing pad increases, and the polishing rate at this portion increases. As a result, sagging occurs at the outermost periphery.

  The degree of strength with which the outer peripheral portion of the substrate is pushed into the polishing pad is affected by polishing conditions such as the hardness of the polishing pad and the polishing load. The polishing speed is also affected by polishing conditions such as polishing abrasive grains and surface plate rotation speed. In general, the softer the polishing pad and the greater the polishing load, the greater the degree to which the substrate is pushed in, resulting in greater outer sag. However, when the substrate polishing progresses and the difference in thickness between the substrate thickness and the carrier thickness becomes small, the polishing pad comes into contact with the carrier as well as the substrate because it has elasticity, The degree to which is pushed is substantially reduced. The most extreme example of this situation is when the substrate and carrier are the same thickness, in which case the substrate is not selectively pushed into the polishing pad, resulting in the hardness of the polishing pad, polishing Regardless of polishing conditions such as weighting, outer periphery sag does not occur.

  According to the study of the present inventor, the relationship between the thickness difference (Tt) between the substrate thickness (T) and the carrier thickness (t) in the polishing process and the size of the peripheral sag is schematically shown. As shown in FIG. 6, in the initial stage of the polishing process (for example, region A in the figure) where the thickness difference (Tt) is large, the size of the outer peripheral sag is determined by the hardness of the polishing pad, the abrasive grains, the polishing It is greatly affected by various polishing conditions such as weighting and surface plate rotation speed, and has a large variation even if the thickness difference (Tt) is constant. However, when the substrate polishing progresses and the thickness difference (Tt) between the substrate thickness (T) and the carrier thickness (t) decreases and the polishing pad comes into contact with the carrier, it is relatively large in the initial stage of the polishing process. The influence of polishing conditions such as polishing abrasives, polishing load, and platen rotation speed, which had an influence, gradually decreases, and the variation width of the outer peripheral sag due to these polishing conditions becomes small, and the final stage of the polishing process (for example, in the figure) In the region B), the influence of the above polishing conditions is reduced to a level that can be almost ignored, and the difference in thickness (Tt) between the substrate thickness (T) and the carrier thickness (t) is the degree of peripheral sagging. It becomes a main factor that decides.

  The present invention has been made on the basis of the analysis on the mechanism of the occurrence of the peripheral sag, and the object thereof is to determine the substrate thickness (T) at the end of polishing of the semiconductor substrate and the carrier holding the semiconductor substrate. A new processing method that performs double-sided polishing using the thickness difference (Tt) from the thickness (t) as a management index, controls the end point of substrate polishing, and suppresses the peripheral sag of the substrate after polishing within an allowable range Is to provide. Specifically, depending on the flatness required for the substrate, the thickness difference between the substrate thickness (T) of the semiconductor substrate at the end of polishing and the thickness of the carrier holding the semiconductor substrate (t) ( By managing the double-side polishing step so that Tt) falls within a predetermined range, the outer periphery sagging of the substrate after polishing is prevented as much as possible and is suppressed within an allowable range.

That is, the gist of the present invention is as follows.
(1) A carrier holding a semiconductor substrate is interposed between a pair of upper and lower polishing pads pressed in a direction approaching each other, and the carrier is interposed between the pair of upper and lower polishing pads in the presence of abrasive grains. A semiconductor substrate double-side polishing method that rotates and revolves and simultaneously polishes both front and back surfaces of a semiconductor substrate held by a carrier with a pair of upper and lower polishing pads, the substrate thickness (T) at the end of polishing of the semiconductor substrate and A method for double-side polishing a semiconductor substrate, wherein a thickness difference (Tt) between the carrier thickness (t) and the carrier thickness (t) is controlled within a range of 5 μm to 100 μm.

  (2) The method for double-side polishing a semiconductor substrate according to (1), wherein the thickness difference (T-t) is 5 μm or more and 30 μm or less.

  (3) The method for double-side polishing a semiconductor substrate according to (1) or (2) above, wherein the semiconductor substrate is a single crystal silicon carbide substrate.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to prevent that the outer peripheral part of a semiconductor substrate is selectively grind | polished, and manufacture of the semiconductor substrate excellent in the flatness without an outer periphery sagging is attained. Further, according to the present invention, the end point of the substrate polishing is managed by the thickness difference (Tt) between the substrate thickness (T) and the carrier thickness (t) at the end of polishing, so that there is no flattening of the outer periphery. Since a semiconductor substrate excellent in temperature can be manufactured, the polishing operation of the semiconductor substrate becomes extremely easy, and a semiconductor substrate excellent in flatness without peripheral sagging can be easily manufactured industrially.

  In the present invention, when the semiconductor substrate is double-side polished, the degree to which the semiconductor substrate is pushed into the polishing pad in view of the situation where the outer periphery of the semiconductor substrate is caused by the outer circumference of the semiconductor substrate being strongly pressed against the polishing pad. Is managed using the thickness difference (Tt) between the substrate thickness (T) at the end of polishing of the semiconductor substrate and the carrier thickness (t) of the carrier holding the semiconductor substrate as an index. Tt) varies depending on the type of semiconductor substrate to be polished, but is usually controlled to 5 μm or more and 100 μm or less, preferably 5 μm or more and 30 μm or less. As a result, it is possible to manufacture a semiconductor substrate having no peripheral sagging.

  For example, when the method of the present invention is applied to double-side polishing of a hard semiconductor substrate such as single crystal silicon carbide, in order to ensure a practical polishing rate, compared with a semiconductor substrate having a general hardness such as silicon. In general, the polishing pressure is increased. However, this causes the outer peripheral portion of the semiconductor substrate to be strongly pressed against the polishing pad, and the outer peripheral sagging of the semiconductor substrate is generated. However, even in this case, as proposed by the present invention, the thickness difference between the substrate thickness (T) at the end of polishing of the semiconductor substrate and the carrier thickness (t) of the carrier holding the semiconductor substrate ( By controlling the Tt) more precisely, specifically, the thickness difference (Tt) is controlled to 5 μm to 30 μm, preferably 5 μm to 20 μm, thereby increasing the pressure with which the polishing carrier is pressed against the polishing pad. The difference between the pressure with which the outer peripheral portion of the semiconductor substrate is pressed against the polishing pad is reduced, and as a result, the state where the outer peripheral portion of the semiconductor substrate protrudes and is pressed against the polishing pad is avoided, and sagging of the outer peripheral portion of the semiconductor substrate is reduced. The

  In addition, when the method of the present invention is applied to a semiconductor substrate having a general hardness such as silicon, the thickness difference (Tt) may be controlled usually from 5 μm to 100 μm, preferably from 5 μm to 30 μm. In such a case, since the pressure with which the outer peripheral portion of the semiconductor substrate is pressed against the polishing pad is further reduced, it is possible to further suppress the outer peripheral sagging, and the semiconductor substrate having better flatness quality Can be produced.

Here, a thickness measuring method for measuring the substrate thickness (T) of the semiconductor substrate and the carrier thickness (t) of the carrier, which are management indexes, will be described below.
First, the method for measuring the substrate thickness (T) is not particularly limited as long as the substrate thickness (T) at the end of polishing can be measured as a result.For example, when the polishing rate is known, or Even if the polishing rate is unknown, if the relationship between the polishing time and the substrate thickness is known in a preliminary experiment, there is a method of managing the polishing time instead of measuring the thickness of the semiconductor substrate. Even when the polishing rate is unknown and the preliminary experiment is not performed, the thickness of the substrate can be managed by measuring the thickness several times in a series of polishing steps. In this case, the measurement frequency may be low in the first half of the polishing step, but the thickness difference (Tt) between the substrate thickness (T) of the semiconductor substrate and the carrier thickness (t) of the carrier in the second half of the polishing step. Since the value of becomes gradually smaller, it is preferable to increase the measurement frequency. Note that the number of measurement targets is the total number of semiconductor substrates to be polished, but it is appropriate to measure each substrate at one or more locations, preferably at two or more locations including one central portion. When the measurement is performed at a plurality of locations, the average value of the measured thicknesses is obtained and set as the substrate thickness (T) of the semiconductor substrate.

  On the other hand, since the carrier is slow to wear, it is sufficient to measure the carrier thickness (t) once in a series of polishing steps. The measurement of the carrier thickness (t) is preferably performed at a plurality of locations along the outer periphery of the hole opened to hold the semiconductor substrate. As an example of the thickness measurement of the carrier thickness (t), there is a method of measuring the thickness four times at 90 ° intervals along the outer periphery of the hole. The interval and the number of measurements may be increased or decreased as necessary. When there are a plurality of holes for holding the semiconductor substrate, the thickness is measured for each hole as described above. An average value of the measured thicknesses is obtained and set as the carrier thickness (t).

  The essential points for producing a semiconductor substrate with excellent flatness without peripheral sag are as described above, but in accordance with the mechanical strength of the semiconductor substrate, the polishing conditions such as the polishing pad, polishing pressure, and the number of rotations of the polishing platen are appropriately selected. It is good to choose. It is preferable to select a polishing pad based on the hardness measured with a Shore A hardness meter. Generally, a polishing pad having a low hardness is used for polishing a soft semiconductor hard semiconductor such as gallium arsenide or indium phosphorus, and a polishing pad having a high hardness is used for polishing a hard semiconductor substrate such as silicon carbide. It is preferable. For example, it is preferable to use a polishing pad having a Shore hardness of 50 ° to 65 ° for gallium arsenide, 60 ° to 80 ° for silicon, and 80 ° to 90 ° for silicon carbide.

The polishing pressure is preferably determined according to the mechanical strength of the semiconductor substrate because it affects both the polishing rate and the peripheral sag of the semiconductor substrate at the initial stage of the polishing process, but in the present invention, the polishing pressure is 50 g / cm ² or more 1000 g / cm ² or less. The rotational speed of the polishing platen is preferably 10 rpm or more and 80 rpm or less.

As the types of abrasive grains, it is common to use silica (SiO ₂ ), alumina (Al ₂ O ₃ ), GC (green SiC), carborundum, diamond, etc. It is preferable to select according to the mechanical strength of the semiconductor substrate. That is, it is preferable to select the type of abrasive grains so that the Vickers hardness of the abrasive grains is higher than the Vickers hardness of the semiconductor substrate to be polished. Specifically, the material of the semiconductor substrate is silicon, gallium arsenide, In the case of indium phosphorus or the like, it is desirable to use silica (SiO ₂ ), alumina (Al ₂ O ₃ ), GC (green SiC), or carborundum, and in the case of silicon carbide or the like, it is desirable to use diamond. .

  Of the size selection of the abrasive grains, the minimum size is uniquely determined according to the roughness of the final surface. On the other hand, it is natural that the abrasive grains are sequentially switched from a larger size to a smaller size, but how many steps should be taken to reduce the abrasive grain size takes into account residual scratches and productivity. Because it is necessary to decide, it cannot be decided uniquely. For example, as an example of polishing a silicon carbide substrate so that its surface roughness Ra is about 0.3 nm, the diamond abrasive grains start with a particle size of 9 μm, and then gradually decrease to 3 μm and 1 μm to obtain a desired surface roughness. There is an example that got the degree. And when performing the polishing operation while sequentially reducing the particle size of the abrasive grains in this way, the measurement of the substrate thickness (T) is performed, for example, when reducing the size of the abrasive grains, or the minimum size When polishing with the polishing abrasive grains, it is preferable to perform the measurement in accordance with the timing at which the polishing operation is interrupted, such as performing a plurality of measurements in accordance with the confirmation of the surface state.

  The carrier that holds the semiconductor substrate during polishing is preferably made of a hard material such as stainless steel, blue steel, or steel because the carrier touches the polishing pad at the same time as the semiconductor substrate is polished and is worn away. However, when polishing both sides of a soft semiconductor substrate such as gallium arsenide or indium phosphide, vinyl chloride, polycarbonate, and epoxy resin are used so that the semiconductor substrate is not easily cracked or chipped by contact or collision with the polishing carrier. An abrasive carrier made of a soft material such as an impregnated aramid fiber, an epoxy resin-containing glass fiber, or an epoxy resin-containing carbon fiber may be used.

[Examples 1 and 2 and Comparative Example 1]
Below, based on an Example and a comparative example, the double-sided grinding | polishing method of the semiconductor substrate of this invention is demonstrated concretely.
Incidentally, in the following Examples 1 and 2 and Comparative Example 1, the double-side polishing apparatus used, as shown in FIG. 1 and FIG. 2, the semiconductor substrate 1 of the three substrate thickness (T) carrier thickness In (t), the substrate 2 of the carrier 2 is disposed so as to be rotatable while maintaining a gap, and is sandwiched between the upper polishing pad 3a and the lower polishing pad 3b from above and below the semiconductor substrate 1 and the carrier 2, and The semiconductor substrate 1 is rotated and revolved between the polishing pads 3a and 3b so that both surfaces of the three semiconductor substrates 1 can be polished simultaneously.

  In Examples 1 and 2 and Comparative Example 1, the semiconductor substrate 1 used was single crystal silicon carbide having a diameter of 3 inches (75 mm), and its crystal polytype was 4H. Nitrogen doping shows n-type conductivity, and the resistivity is 20 mΩcm. The main surface of the semiconductor substrate is the (0001) plane, and the C axis is inclined by 8 ° in the [11-20] direction.

Further, in the double-side polishing of Examples 1 and 2 and Comparative Example 1, polishing was performed with a configuration of three batches, and the polishing carrier was made of stainless steel. A polishing pad having a hardness of 80 ° or more and 90 ° or less measured with a Shore A hardness tester was used. The polishing pressure was controlled between 250 g / cm ^{2 and} 600 g / cm ² . The polishing slurry used diamond as abrasive grains. The grain size was reduced to 3 μm and 1 μm in order starting from a grain size of 9 μm to finish the polished surface. In reducing the size of the particle size, sufficient water washing was performed so that the diamond grains from the previous step did not remain.

  In Examples 1 and 2 and Comparative Example 1, the measurement of the substrate thickness (T) of the semiconductor substrate 1 was performed in synchronization with the size reduction of the abrasive grains. That is, the substrate thickness (T) is measured when the abrasive grains are changed from 9 μm to 3 μm in the first time, and the abrasive grains are changed from 3 μm to 1 μm in the second time. Thereafter, the substrate thickness (T) is measured every 30 minutes, and the thickness difference (Tt) between the measured substrate thickness (T) and the carrier thickness (t) is a predetermined value (in Comparative Example 1) The polishing operation and the measurement of the substrate thickness (T) were repeated until 120 μm, 60 μm in Example 1, and 20 μm in Example 2. The carrier thickness (t) of the carrier 2 is measured at four points every 90 ° along the periphery of the hole (substrate housing portion 2a) for holding the semiconductor substrate 1 before starting polishing, and the average value thereof Asked.

  The flatness quality after double-side polishing was quantified using SBIR defined in ASTM F1241. The site size was a square with a side of 10 mm, and the SBIR was measured under the condition of edge exclusion of 2 mm.

  FIG. 3 shows the case of Comparative Example 1 in which the thickness difference (T) is 120 μm, and the thickness difference between the substrate thickness (T) and the carrier thickness (t) of the carrier 2 after the polishing of the semiconductor substrate 1 is completed. This is a result when (Tt) is excessively large. Specifically, the substrate thickness (T) of the semiconductor substrate is 370 μm, the carrier thickness (t) of carrier 2 is 250 μm, and the difference in thickness (Tt) between the two is 120 μm. Comparing the SBIR of other cells, it can be seen that the value is large in the outermost peripheral cell, and the flatness due to the outer peripheral sag is deteriorated.

  On the other hand, FIG. 4 shows the thickness difference between the substrate thickness (T) and the carrier thickness (t) of the carrier 2 after polishing of the semiconductor substrate 1 in the case of Example 1 to which the method of the present invention was applied ( In this example, Tt) is managed within a predetermined range. In FIG. 4, the substrate thickness (T) after the polishing of the semiconductor substrate 1 is 390 μm, the carrier thickness (t) of the carrier 2 is 330 μm, and the thickness difference (T−t) between the two is 60 μm. In Example 1, it can be seen that compared with Comparative Example 1 shown in FIG. 3, the SBIR in the outermost peripheral cell is small, and the occurrence of peripheral sagging is suppressed.

  FIG. 5 shows a case of Example 2 to which the present invention is applied. Here, the thickness difference (Tt) between the substrate thickness (T) after the polishing of the semiconductor substrate 1 and the carrier thickness (t) of the carrier 2 is within a narrower range than in the case of Example 1. This is a managed example. In FIG. 5, the substrate thickness (T) after polishing of the semiconductor substrate 1 is 370 μm, the carrier thickness (t) of the carrier 2 is 350 μm, and the thickness difference (T−t) between the two is 20 μm. In this case, the SBIR is almost the same in the outermost cell and the other cells, and it can be seen that there is no substrate sagging.

FIG. 1 is an explanatory perspective view showing the positional relationship between a semiconductor substrate and a carrier with upper and lower polishing pads omitted in double-side polishing.

FIG. 2 is a cross-sectional explanatory view showing the shape of the cross section along the line aa in FIG.

FIG. 3 is a site map showing SBIR measurement results of the semiconductor substrate of Comparative Example 1.

FIG. 4 is a site map diagram showing the SBIR measurement result of the semiconductor substrate of Example 1 of the present invention.

FIG. 5 is a site map showing the SBIR measurement results of the semiconductor substrate of Example 2 of the present invention.

Fig. 6 shows the relationship between the thickness difference (Tt) between the substrate thickness (T) and the carrier thickness (t), the size of the peripheral sag, and the polishing conditions (the hardness of the polishing pad and the size of the polishing load). It is explanatory drawing for demonstrating.

Explanation of symbols

  1: Semiconductor substrate, 2: Carrier, 2a: Substrate accommodating portion (hole), 3a: Upper polishing pad, 3b: Lower polishing pad, T: Substrate thickness, t: Carrier thickness.

Claims (3)

  A carrier holding a semiconductor substrate is interposed between a pair of upper and lower polishing pads pressed in directions approaching each other, and the carrier rotates and revolves between the pair of upper and lower polishing pads in the presence of abrasive grains. A semiconductor substrate double-side polishing method for simultaneously polishing both front and back surfaces of a semiconductor substrate held by a carrier with a pair of upper and lower polishing pads, the substrate thickness (T) at the end of polishing of the semiconductor substrate and the carrier A method for double-side polishing a semiconductor substrate, wherein a thickness difference (Tt) between the thickness (t) and the thickness (t) is controlled within a range of 5 μm to 100 μm.   2. The double-side polishing method of a semiconductor substrate according to claim 1, wherein the thickness difference (T-t) is 5 μm or more and 30 μm or less.   3. The double-side polishing method for a semiconductor substrate according to claim 1, wherein the semiconductor substrate is a single crystal silicon carbide substrate.

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