JP2010041639A - Phase-locked loop circuit, information reproduction device, electronic apparatus, and gain control method of the phase-locked loop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide various methods as a lock determination technique when shortening a capture time or enhancing an error rate by automatically controlling a PLL gain. <P>SOLUTION: During a PLL operation in medium reproduction, information indicating a PLL lock state is used to switch a PLL gain, thereby obtaining a robust PLL. For the detection of the PLL lock state, either a frame sync detection result or an integration amount of an absolute value of a phase error is measured as an evaluation index, and a magnitude of the evaluation index in a fixed interval is determined, thereby generating an RF quality signal RQ indicating whether or not a phase-locked loop is locked on the basis of a result of the determination. A detection interval of a frame synchronizing signal is monitored and on the basis of a result of the monitoring, the RF quality signal RQ may be generated. The RF quality signal RQ becomes H when the PLL is locked, or becomes L when unlocked, approximately. A PLL gain is controlled so as to obtain low magnification in a zone where the RF quality signal RQ is at an H-level, and to obtain high magnification in a zone where the RF quality signal RQ is at an L-level. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a phase synchronization circuit, an information reproducing device, an electronic apparatus, and a gain control method for a phase synchronization circuit.

  For example, in various electronic devices such as receiving and transmitting communication devices such as television devices and mobile phones, and information recording and reproducing devices such as optical disk devices, it generates oscillation signals with high spectrum accuracy and data signals. In order to generate a frequency / phase-locked clock signal, a phase locked loop (PLL) circuit may be incorporated. Examples include wireless communication including a cellular phone, serial communication through various cables, or a digital recording data reproduction system (read channel) from a disk medium.

  For example, when reproducing an optical disc, a clock synchronized with the RF signal is generated using a PLL in order to reproduce binary data from a so-called RF (Radio Frequency) signal. In the operation of the PLL, a phase error signal at a zero cross of a DC-free RF signal in which a direct current (DC) component is cut by a coupling capacitor is used. By multiplying the error signal by gain and performing feedback, the response of the PLL is appropriately adjusted.

  When the gain of the PLL is increased, the capture range is widened, and the time required from when the PLL is not locked to when the PLL is locked becomes shorter, but the error rate is lowered due to a decrease in stability against disturbance. Conversely, if the gain of the PLL is reduced, the tolerance to disturbance during PLL operation is improved and the error rate is improved, but the time required for the PLL to lock from unlocking increases. As described above, when the PLL gain is set to a fixed value, the stability against disturbance, the error rate, and the capture range are in a trade-off relationship, so neither is the best.

  As a countermeasure, it is conceivable to perform control such as increasing the gain at the start of PLL operation and decreasing the gain when the PLL is locked. However, when a disturbance occurs during the PLL operation and the PLL is unlocked, if the PLL gain is lowered, it takes time until the PLL is locked again, increasing the number of errors during playback. End up.

  As a countermeasure, there is a demand for a mechanism for determining whether or not the PLL is locked during the operation of the PLL and automatically controlling the gain of the PLL based on the determination result. For example, a mechanism described in Patent Documents 1 and 2 is required. Has been proposed.

JP 2006-270372 A JP 2007-080468 A

  As described above, a new mechanism for automatically controlling the gain of the PLL is required. If there is a new mechanism different from the mechanisms described in Patent Documents 1 and 2, the range of selection of the phase synchronization circuit in accordance with the intended use is widened.

  Also, when automatically controlling the PLL gain, it should be considered that the circuit scale, applicability of the detection method, detection performance, etc. are affected by how the PLL state is detected. is there. For example, even if the detection performance is good but the circuit scale is large and the detection performance is somewhat inferior but there is a small circuit scale, it is not possible to decide which one will be adopted. It is thought that it depends on whether to do. In other words, it can be said that the existence of these two mechanisms broadens the range of selection of the phase synchronization circuit in accordance with the intended use.

  In addition, if the method detects a PLL state based on a signal or information peculiar to a certain system, the applicable range is naturally limited. In other words, a detection method based on a signal or information that can be generally used as a PLL, not based on a signal or information peculiar to a certain system, is preferable because it can be applied regardless of use and the applicable range is widened. Therefore, realization of such a method is required.

  Further, for example, when the detection method depends on the amplitude of the signal, care must be taken in application to a system in which the signal amplitude varies due to disturbance, for example. In other words, a detection method whose detection performance does not depend on the signal amplitude is preferable because it can be applied regardless of the application and the applicable range is widened, and the realization of such a method is required.

  The present invention has been made in view of the above circumstances, and provides a phase synchronization circuit having a new circuit configuration different from that of the prior art, thereby increasing the range of selection and application of the phase synchronization circuit according to the intended use. The purpose is to provide a mechanism that can be expanded.

  In the present invention, in adopting a mechanism for automatically controlling the gain of the PLL, the determination of whether or not the phase-locked loop is locked and the acquisition of the quality signal indicating the determination result are performed by any of the following.

1) In combination with a mechanism for acquiring a reproduction signal from a recording medium in an information recording / reproducing apparatus, a synchronization signal is detected from the reproduction signal reproduced from the recording medium to acquire a frame synchronization signal, and the detection / acquisition result Whether or not the phase locked loop is locked is determined based on the above.
2) In a phase-locked loop that can be mounted on a general electronic device, whether or not the phase-locked loop is locked based on an integrated amount of absolute values of phase differences detected by a phase detector (that is, an oscillation control signal). Determine.

  If it is determined whether or not the phase-locked loop is locked, the magnification in the amplifying unit is controlled based on the determination result. The basic idea is that the magnification is low when the phase-locked loop is generally locked, and is high when the phase-locked loop is not locked (when unlocked).

  According to one embodiment of the present invention, a phase synchronization circuit having a new circuit configuration different from that of the prior art is realized, and the selection and application range of the phase synchronization circuit in accordance with the intended use is expanded.

  By a mechanism not disclosed in Patent Documents 1 and 2, it can be determined whether or not the phase-locked loop is locked. Based on the determination result, when the phase-locked loop is locked, the magnification becomes low and the phase-locked loop is When not locked, the predetermined magnification in the amplifying unit can be automatically controlled so as to obtain a high magnification. A new phase synchronization circuit capable of automatically controlling a predetermined multiplication in the amplification unit is realized. As a result, it is possible to expand the range of selection of the phase synchronization circuit in accordance with the intended use.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. When distinguishing each functional element according to the embodiment or the comparative example, an uppercase English reference is added, such as A, B,... Is omitted. The same applies to the drawings.

<Outline of recording / reproducing apparatus>
FIG. 1 is a block diagram showing an embodiment of an information recording / reproducing apparatus (optical disk apparatus) which is an example of an electronic apparatus having a phase synchronization circuit.

  The information recording / reproducing apparatus 1 of the present embodiment includes an optical pickup 14 that includes a laser light source for recording additional information on an optical disk PD (Photo Disk) or reading information recorded on the optical disk PD. The signal processing system includes a servo system, a recording / reproducing system, and a controller system. Here, as the servo system, the information recording / reproducing apparatus 1 includes a rotation servo system, a tracking servo system, and a focus servo system. The tracking servo system and the focus servo system are collectively referred to as a pickup servo system.

  As the optical disk PD, in addition to a so-called reproduction-only optical disk such as a CD (compact disk) or a CD-ROM (Read Only Memory), a write-once optical disk such as a CD-R (Recordable) or a CD-RW (Rewritable). Such a rewritable optical disc may be used. Furthermore, it is not limited to a CD-based optical disk, but may be an MO (magneto-optical disk), a normal DVD (Digital Versatile Disk), or a DVD system such as a next-generation DVD using a blue laser having a wavelength of about 407 nm, for example. It may be an optical disc. Further, it may be a so-called double density CD (DDCD; DD = Double Density), CD-R, or CD-RW in which the recording density is approximately double that of the current format while following the current CD format. .

  Specifically, the information recording / reproducing apparatus 1 includes, as a rotary servo system, a spindle motor 10 that rotates an optical disk PD on which information to be reproduced such as music is recorded, a motor driver 12 that drives the spindle motor 10, and a motor. And a spindle motor control unit 30 that is an example of a rotation control unit (rotation servo system) that controls the driver 12.

  Although not shown, the spindle motor control unit 30 includes a rough servo circuit, a speed servo circuit, a phase servo circuit, and a selector that switches and outputs each output of each servo circuit.

  The rough servo circuit roughly controls the rotation speed of the optical disc PD. The speed servo circuit adjusts the rotation speed with higher accuracy based on the synchronization signal. The phase servo circuit matches the phase of the reproduction signal with the phase of the reference signal. The selector switches the outputs of the rough servo circuit, the speed servo circuit, and the phase servo circuit and outputs them to the motor driver 12.

  The optical disk PD is fixed to the rotating shaft 10 a of the spindle motor 10 by chucking 11. The spindle motor 10 is controlled by the motor driver 12 and the spindle motor control unit 30 so that the linear velocity is constant. The linear velocity can be changed stepwise by the motor driver 12 and the spindle motor control unit 30.

  In addition, the information recording / reproducing apparatus 1 includes a pickup control unit 40 that controls a focus / tracking / sled motor as a tracking servo system and a focus servo system. For example, the pickup control unit 40 controls the radial position and focus of the optical pickup 14 with respect to the optical disc PD.

  Although not shown, the pickup control unit 40 includes, for example, a sub-coding detection circuit that reads sub-coding recorded on the optical disc PD, a track error signal detected by a track error detection circuit (not shown), and a sub-coding detection circuit. And a tracking servo circuit for controlling the radial position of the optical pickup 14 relative to the optical disc PD based on the detected address information. The pickup control unit 40 controls a track actuator and a seek motor (not shown) to position the laser spot of the laser beam emitted from the optical pickup 14 at a target location (data recording position or data reproduction position) on the optical disc PD. To control.

  The optical pickup 14 includes a known semiconductor laser (not shown), an optical system, a focus actuator, a track actuator, a light receiving element, a position sensor, and the like. The optical pickup 14 irradiates the recording surface of the optical disc PD with laser light and emits reflected light. It is configured to receive light and convert it into an electrical signal. The semiconductor laser of the optical pickup 14 is driven by a laser driver (not shown). By driving the laser driver, a light beam having a predetermined reproduction power is emitted during data reproduction, and a predetermined recording is performed during information recording. A power light beam is emitted.

  The optical pickup 14 is configured to be movable in a sledge (radius) direction by a seek motor (slide motor) (not shown). These focus actuators, track actuators, and seek motors cause the laser spot of the laser beam on the optical disk PD by the motor driver 12, the spindle motor control unit 30 and the pickup control unit 40 based on signals obtained from the light receiving elements and position sensors. It is controlled so as to be located at a target location (data recording position or data reproduction position).

  The information recording / reproducing apparatus 1 also serves as an example of an information recording unit that records information via the optical pickup 14 and a recording / signal processing unit that reproduces information recorded on the optical disk PD as a recording / reproducing system. Part 50 is provided. A configuration example of the recording / signal processing unit 50 will be described later, but at least a phase synchronization unit which is an example of a phase synchronization circuit is provided.

  The information recording / reproducing apparatus 1 includes a controller 62 that controls the entire information recording / reproducing apparatus 1 and an interface unit 64 that performs an interface (IF) function as a controller system. The controller 62 is constituted by a microprocessor (MPU: Micro Processing Unit), and controls the operation of the servo system having the spindle motor control unit 30 and the pickup control unit 40 and the recording / signal processing unit 50. The interface unit 64 has an interface (connection) function with the host apparatus 3 that performs various types of information processing using the information recording / reproducing apparatus 1. The interface unit 64 is provided with a host IF controller. As the host device 3, for example, a personal computer (personal computer) which is an example of an information processing device is used. The information recording / reproducing apparatus 1 and the host device 3 constitute an information recording / reproducing system (optical disk system).

  In the information recording / reproducing apparatus 1 having such a configuration, at the time of reproduction processing, an optical signal read from the optical disc PD by the optical pickup 14 is converted into an electric signal by a light receiving element built in the optical pickup 14, and the electric signal is converted into an electric signal. The servo motor (control system) having the spindle motor control unit 30 and the pickup control unit 40 for controlling the spindle motor 10 and the optical pickup 14 and the recording / signal processing unit 50 for recording / reproducing data are sent.

  The spindle motor control unit 30 and the pickup control unit 40 adjust the number of rotations of the spindle motor 10 and the focusing and tracking of the optical pickup 14 based on this electric signal under the control of the controller 62.

  At the same time, the recording / signal processing unit 50 converts the obtained analog electric signal into digital data, decodes it, and passes it to the host device 3 using the information recording / reproducing apparatus 1. The host device 3 reproduces the image / sound data based on the decoded data.

  In the recording process for recording data on the optical disk PD, the spindle motor control unit 30 and the pickup control unit 40 rotate the optical disk PD at a constant speed under the control of the controller 62. At the same time, in the recording / signal processing unit 50, contrary to reproduction, the data is encoded and supplied to a laser diode or the like built in the optical pickup 14, thereby converting the electrical signal into an optical signal, which is recorded on the optical disc PD. Record information.

<Overview of recording / signal processing unit>
The recording / signal processing unit 50 includes an RF amplification unit 52, a PLL & ADC processing unit 53, a digital signal processing unit 56 composed of a DSP (Digital Signal Processor), and a recording current control unit 57.

  The RF amplification unit 52 is an AGC processing unit including a voltage gain amplifier (VGA) having a variable gain amplifier configuration. The RF amplification unit 52 is an example of a signal processing unit that acquires a reproduction signal from the optical disc PD (recording medium) as one of the two signals supplied to the phase comparison unit 203. An automatic gain control circuit (AGC loop) is configured by the voltage gain amplifier and the gain control unit provided in the controller 62. The RF amplifying unit 52 controls the reproduction amplitude to be constant with respect to a minute RF (high frequency) signal (reproduced RF signal) read by the optical pickup 14 under the control of the gain control unit provided in the controller 62. To do.

  The PLL & ADC processing unit 53 generates a clock synchronized with the reproduction RF data, and AD converts the analog RF signal with the clock to generate digital RF data.

  The digital signal processing unit 56 includes a modulation processing unit 110, a binarization processing unit 120, and a demodulation processing unit 130. The binarization processing unit 120 performs processing such as PRML (Partial Response Maximum Likelihood) and reproduces binarized data from digital RF data.

  For example, in recent years, the recording density has been increased. When the performance of a recording / reproducing apparatus such as an optical disk or an optical pickup as a recording medium is determined, the shortest recordable wavelength is determined accordingly. If the recording density is increased without changing the given shortest wavelength, so-called intersymbol interference occurs in which the reproduction waveform of the adjacent code is superimposed and read out. In the conventional binarization method, proper reproduction is performed. It has become impossible to process. PRML is used as an example of a technique for solving such a problem in high density.

  The demodulation processing unit 130 demodulates the digital RF data (digital data string) output from the PLL & ADC processing unit 53 and performs digital signal processing such as decoding digital audio data or digital image data. For example, the demodulation processing unit 130 includes a demodulation unit, an ECC correction unit, an address decoding unit, and the like, and performs demodulation / ECC correction and address decoding. The demodulated data is transferred to the host device 3 via the interface unit 64.

  The recording current control unit 57 controls (on / off) the recording current of the laser beam for recording information on the optical disc PD. Although not shown, the recording current control unit 57 includes a write strategy unit (Write Strategy) and a driving unit (Laser Diode Driver). The write strategy unit multi-pulse modulates the optical output power according to the material and recording speed of the optical disc PD. The drive unit includes an APC (Auto Power Control) control circuit for holding a light output (light intensity, light output power) of laser light emitted from a laser light source (in the optical pickup 14) at a constant value.

  The recording light beam emitted from the laser light source is converted into parallel light by a collimator lens (not shown) in the optical pickup 14, then passes through a beam splitter (not shown) and is focused by an objective lens (not shown). The optical disk PD that is driven to rotate is irradiated. At this time, since the recording light beam is modulated in accordance with the information for recording, a pit row corresponding to the information is formed at a predetermined position (information recording area) of the optical disc PD. Information will be recorded in At this time, in the present embodiment, the data strategy due to the distortion of the shape of the pit (record mark) is suppressed in the write strategy section.

  For example, as a laser used as a light source, in recent years, a semiconductor laser using a semiconductor element is widely used as a light source of various apparatuses because it is extremely small and responds to a drive current at high speed. As rewritable optical disks PD used as recording and reproducing media, phase change optical disks, magneto-optical disks, and the like are widely known, and the output of laser light irradiated when recording, reproducing, and erasing is different.

  Generally, in order to create a recording mark called a pit on the optical disc PD during recording, the output of the laser beam is increased (for example, 30 mW or more), but information is read without destroying the recording pit during reproduction. Therefore, the optical disc PD is irradiated with a laser beam having a weaker output (for example, 3 mW) than that at the time of recording. In order to obtain an error rate capable of recording and reproduction in an optical disc PD with a high density and a high transfer rate in recent years, it is necessary to sufficiently control the intensity of these laser beams.

  However, since the temperature characteristics of the drive current and the optical output characteristics of the semiconductor laser change remarkably, a circuit for controlling the optical output of the semiconductor laser at a constant level, that is, a so-called APC control circuit is required to set the optical output to a desired intensity. Become. In APC control, a laser feedback power is controlled to be constant by configuring a negative feedback control loop in which a feedback current obtained by monitoring an optical signal at the time of writing information becomes a predetermined power reference current.

  Here, in the writable optical disc PD in recent years, mark edge recording for recording changes at both ends of the recording mark has become mainstream due to the advantage of high density. As a technique for suppressing data errors due to distortion of the mark shape during mark edge recording, a write strategy technique is employed in the write strategy section that multi-pulse modulates the laser output power in accordance with the disk material and recording speed.

<PLL operation state detection method>
At the time of reproducing an optical disc, a clock synchronized with the RF signal is generated using a PLL in order to reproduce the binarized data from the reproduced RF signal, but it is required to appropriately adjust the response of the PLL according to the operation state. . For example, the gain is increased at the start of the PLL operation, and the gain is decreased when the PLL is locked. When a disturbance occurs during the PLL operation and the PLL is unlocked, the gain is increased and the PLL is locked again. The gain of the PLL is automatically controlled based on the result of determining whether or not the PLL is locked during the operation of the PLL, for example, by shortening the time until the operation is completed.

  In automatic control of the PLL gain, if it is determined whether or not the phase-locked loop is locked, the magnification in the amplifying unit is controlled based on the determination result. The basic idea is that the magnification is low when the phase-locked loop is generally locked, and is high when the phase-locked loop is not locked (when unlocked).

  In order to adopt such a mechanism, how to detect / determine whether or not the PLL is locked depends on the difficulty of implementation, circuit scale, detection performance, application range (applicability of the detection method) ) Etc.

  For example, when adopting a mechanism for automatically controlling the gain of the PLL, it is conceivable to determine whether or not the phase-locked loop is locked and to acquire a quality signal indicating the determination result by either of the following.

1) In combination with a mechanism for acquiring a reproduction signal from a recording medium in an information recording / reproducing apparatus, a synchronization signal is detected from the reproduction signal reproduced from the recording medium to obtain a frame synchronization signal (frame sync), and this detection -Determine whether the phase-locked loop is locked based on the acquisition result.
2) In a phase-locked loop that can be mounted on a general electronic device, whether or not the phase-locked loop is locked based on an integrated amount of absolute values of phase differences detected by a phase detector (that is, an oscillation control signal). Determine.
3) In combination with a mechanism for acquiring a reproduction signal from a recording medium in an information recording / reproducing apparatus, is the phase-locked loop locked based on the jitter component of one of the two signals to be phase-compared? Determine whether or not.
4) In combination with a mechanism for acquiring a reproduction signal from a recording medium in an information recording / reproducing apparatus, it is determined whether or not the phase-locked loop is locked based on a metric difference during Viterbi decoding.
5) In combination with a mechanism for acquiring a reproduction signal from a recording medium in an information recording / reproducing apparatus, the absolute value of an LMS (Least-Mean Square) equalization error is measured as an evaluation index, The magnitude of the evaluation index in a certain section is determined, and it is determined whether or not the phase locked loop is locked based on the determination result.
6) In a combination of a mechanism for acquiring a reproduction signal from a recording medium in an information recording / reproducing apparatus and a digital PLL that digitally performs phase error detection, a synchronization signal is detected from the reproduction signal reproduced from the recording medium, and a frame synchronization signal is detected. Is acquired, the detection interval of the frame synchronization signal is monitored, and it is determined whether or not the phase locked loop is locked based on the monitoring information.

  Basically, any signal that is related to the operation of the PLL can be used to generate the RF quality signal. For example, not only the integrated value of the absolute value of the phase error of the frame synchronization signal or PLL but also the information indicating the RF jitter, the information indicating the metric difference during Viterbi decoding, the integrated value of the absolute value of the LMS equalization error, etc. It is preferable to measure the evaluation index in real time and switch L and H of the RF quality signal according to the size of the evaluation index in a certain section.

  Among these mechanisms, the methods 1) and 6) using the frame synchronization signal are limited to application to the information recording / reproducing apparatus, but are relatively simple methods and do not depend on the amplitude of the reproduction RF signal. There are advantages such as high effect. On the other hand, the method 2) has an advantage that the application range is not limited because the integrated amount of the absolute value of the phase difference that can be obtained from a general phase synchronization circuit is used. On the other hand, although the methods 3) to 5) can be realized in principle, it is difficult to think that the effect when realized is so great.

  Based on these, the first embodiment adopts the method 1). In the second embodiment, the method 2) is adopted. In the third embodiment, the method 6) is adopted. Each will be described below.

<Configuration Example of Recording / Signal Processing Unit: First Embodiment>
FIG. 2 is a diagram illustrating a configuration example of the recording / signal processing unit 50A (particularly, the PLL & ADC processing unit 53 and the binarization processing unit 120) according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of the recording / signal processing unit 50X (particularly, the PLL & ADC processing unit 53 and the binarization processing unit 120) of the first comparative example.

  The PLL & ADC processing unit 53 includes an AD conversion unit 54 (ADC; Analog to Digital Converter) and a clock reproduction unit 55. The AD converter 54 converts the analog RF signal input from the RF amplifier 52 into digital data. The clock recovery unit 55 is an example of a signal processing unit that performs signal processing based on a signal output from a phase synchronization unit described later, and is also an example of a phase synchronization circuit of the present invention.

  The clock reproduction unit 55 reproduces a clock signal based on the digital data string output from the AD conversion unit 54. The clock recovery unit 55 includes a data recovery type phase synchronization unit that generates a clock signal by locking to the digital data (digital data string Din) from the AD conversion unit 54. The clock recovery unit 55 supplies the recovered clock signal to the AD conversion unit 54 as an AD clock (sampling clock) CKad, or supplies it to other functional units. The AD converter 54 converts an analog signal into digital data based on the AD clock CKad.

  The clock recovery unit 55 includes a phase synchronization unit 200 configured by a PLL circuit, and a PLL operation sequencer 300 (phase synchronization control unit) that controls the phase synchronization unit 200. The PLL operation sequencer 300 controls the operation of the PLL by the operation enable signal EN and the PLL gain switching signal GC.

  The phase synchronization unit 200 generates an output oscillation signal Vout having an oscillation frequency fosci based on an oscillation control signal CN (here, oscillation control voltage Vcnt), and an oscillation frequency of the output oscillation signal Vout output from the oscillation unit 201. A frequency dividing unit 202 is provided that divides fosci by 1 / α to obtain a divided oscillation signal Vout1. In this example, the oscillation unit 201 is shown as an example of a voltage controlled oscillation circuit (VCO: Voltage Controlled Oscillator), but a current controlled oscillation circuit (CCO: Current Controlled Oscillator) can also be adopted. A configuration in which the frequency dividing unit 202 is omitted may be employed.

  The phase synchronization unit 200 further includes a phase comparison unit 203 that detects a phase error between two signals, a loop filter driving unit 204, and a loop filter unit 206. The phase comparison unit 203 compares the phase of the input signal Vin (analog RF signal) with the output oscillation signal Vout from the oscillation unit 201 or the divided oscillation signal Vout1 (collectively referred to as a clock) from the frequency division unit 102, and compares them. A comparison result signal (phase error signal Comp) indicating the phase error as a result is output. The PLL operation sequencer 300 performs on / off control of the PLL operation by supplying the operation enable signal EN to the phase comparison unit 203. The phase comparison unit 203 detects a phase error and outputs a phase error signal Comp when the operation enable signal EN is active.

  The loop filter drive unit 204 includes a gain multiplication unit 205 which is an example of an amplification unit. The gain multiplication unit 205 multiplies the phase error signal Comp from the phase comparison unit 203 by a predetermined magnification to change the amplitude of the phase error signal Comp. A value to be multiplied (predetermined magnification) is called a gain here. The gain is changed based on the PLL gain switching signal GC from the PLL operation sequencer 300. For example, when the PLL gain switching signal GC is at the L level, the gain multiplication unit 205 sets the magnification to be low (the value to be multiplied is small), and when the PLL gain switching signal GC is at the H level, to the high magnification (the value to be multiplied is large).

  The loop filter unit 206 includes at least a capacitance element having a capacitance value C (loop filter capacitance), and a low-pass filter that extracts a low-frequency component of the phase error by integrating (smoothing) the phase error signal Vcomp. LPF (Low Pass Filter) function. The loop filter unit 206 obtains an integrated value of the phase error signal Vcomp by smoothing the gained phase error signal Vcomp from the loop filter driving unit 204, and uses this integrated value as the oscillation frequency fosci of the oscillating unit 201. An oscillation control signal CN for controlling Note that the loop filter unit 206 may include a resistance element having a resistance value R (loop filter resistance) in addition to the capacitive element. The oscillation control signal CN that is an LPF output from the loop filter unit 206 is an accumulated phase error amount. The oscillation unit 201 oscillates at a corresponding frequency by the oscillation control signal CN input from the loop filter unit 206.

  In the phase synchronization unit 200 having such a configuration, the input signal Vin from the RF amplification unit 52 and the output oscillation signal Vout from the oscillation unit 201 (or the divided oscillation signal Vout1 by the frequency division unit 102) are sent to the phase comparison unit 203. Based on the input phase error signal Comp indicating the phase error, the oscillation unit 201 is oscillated by, for example, a charge pump PLL technique to obtain an output oscillation signal Vout phase-locked to the input signal Vin.

  The binarization processing unit 120 includes a PR equalization processing unit 122 and a Viterbi processing unit 124 (Viterbi). The PR equalization processing unit 122 performs PR equalization processing. Specifically, for the binarization process in the Viterbi processing unit 124, a filter process for adjusting the RF data to a frequency characteristic suitable for it in advance is performed as necessary. The Viterbi processing unit 124, for binarization, decodes digital RF data into binary data of 0 and 1 by Viterbi decoding processing, and has a demodulation, ECC correction, and address decoding processing function. To 130.

  An optical disc PD with data recorded on the board is loaded into the information recording / reproducing apparatus 1. The spindle motor 10 rotationally drives the optical disc PD mounted on the information recording / reproducing apparatus 1. The optical pickup 14 converts the optical signal obtained from the recording surface of the rotating optical disk PD into an electrical signal, and thereby extracts a reproduction signal (analog RF signal). The RF amplification unit 52 adjusts the amplitude of the reproduction signal based on the gain control signal Sagc from the controller 62.

  Thereafter, the reproduction signal is equalized (waveform equalization) to an appropriate PR waveform in an equalizer unit (RF waveform shaping unit) (not shown), and then supplied to the AD conversion unit 54 as a reproduction signal. The AD converter 54 converts the reproduction signal from an analog format to a digital format. Then, the reproduction data (digital RF data) subjected to AD conversion by the AD conversion unit 54 is sent to the PR equalization processing unit 122. For example, the PR equalization processing unit 122 suppresses asymmetry (asymmetry) by nonlinear signal processing, or compensates for the shortage of PR equalization by adaptive equalization. The Viterbi processing unit 124 binarizes the data from the PR equalization processing unit 122. After being binarized by the Viterbi processing unit 124, it is sent to the demodulation processing unit 130. The PR waveform is binarized by the Viterbi processing unit 124 and sent to the processing subsequent to the demodulation processing unit 130. Since the Viterbi processing unit 124 is processed digitally, the AD conversion unit 54 is necessary before that. .

  Although not shown in the figure, the Viterbi processing by the Viterbi processing unit 124 requires signal values at data points that exist at approximately constant intervals in the reproduction signal. Therefore, PLL (Phase-locked loop: phase synchronization) is applied so that the AD conversion sampling timing by the AD converter 54 coincides with the data point, or the AD conversion is sampled with a fixed clock and the data point is obtained by digital signal processing. It is necessary to have a mechanism for determining the value of.

  Up to this point, both the recording / signal processing unit 50A of the first embodiment and the recording / signal processing unit 50X of the first comparative example have the same configuration. In addition to this configuration, the recording / signal processing unit 50A of the first embodiment includes a quality signal generation unit 310 that generates an RF quality signal RQ indicating whether or not the phase-locked loop is locked. There is a feature in that it has. In particular, the quality signal generation unit 310 of the first embodiment is different from the second embodiment described later in that it includes a frame sync processing unit 312 that detects the frame sync FS from the reproduction signal and performs synchronization protection.

  The frame sync processing unit 312 detects the frame sync FS (Frame Sync) from the binarized data output from the Viterbi processing unit 124, and confirms the interval of the frame sync FS (frame sync interval) to protect synchronization. Do. The synchronization protection means that synchronization is not disturbed due to generation of a fake frame sync FS due to disturbance or the like. As a synchronization protection method, for example, when detecting a synchronization signal encoded in units of data frames and taking a frame sync FS, the protection for a predetermined width is used so that the frame sync FS is detected at the original generation timing. Use this window. Since a false synchronization signal (fake sync) generated due to the influence of disturbance or the like after normal synchronization is obtained cannot pass through the synchronization detection window, synchronization is not disturbed by the false sync.

  The quality signal generation unit 310 generates the RF quality signal RQ based on the detection / confirmation result of the frame sync FS by the frame sync processing unit 312. The quality signal generation unit 310 notifies the generated RF quality signal RQ to the PLL operation sequencer 300 as information indicating the locked state of the PLL (in other words, the unlocked state).

  The PLL operation sequencer 300 generates a PLL gain switching signal GC based on the RF quality signal RQ generated by the quality signal generating unit 310, and supplies the PLL gain switching signal GC to the gain multiplying unit 205 of the loop filter driving unit 204. Thus, the gain (PLL gain) is controlled. The PLL operation sequencer 300 includes a function of a gain control unit that supplies a PLL gain switching signal GC to the loop filter driving unit 204 and controls the gain in the loop filter driving unit 204. As the direction of gain control, the gain in the gain multiplier 205 is controlled so that the magnification is low when the phase-locked loop is locked and becomes high when the phase-locked loop is not locked.

  Robust PLL control is realized by switching the gain of the PLL using information indicating the lock state during the PLL operation of the reproduction RF signal during reproduction of the optical disc PD. In particular, in the mechanism of the first embodiment, the detection result of the frame sync FS by the frame sync processing unit 312 is used to detect the locked state of the PLL.

  The frame sync FS is defined in the optical disc standard, and a pattern (synchronization signal: hereinafter referred to as a unique pattern) that does not exist in the user data is defined as a synchronization signal. For example, a unique pattern in a standard of a next-generation DVD using a blue laser having a wavelength of about 407 nm is “101000000000001000001” in NRZ expression. In addition, the frame sync FS is inserted at regular intervals in the continuous reproduction signal. Therefore, for example, by detecting the above-mentioned unique pattern and determining whether or not the unique pattern can be detected at equal intervals, that is, by determining the quality of the detection of the unique pattern, the RF reproduction state or PLL lock The state can be confirmed. By inputting such an RF quality signal RQ to the PLL operation sequencer 300 and switching the gain of the PLL according to the RF reproduction state, the re-convergence of the PLL at the time of disturbance recovery can be accelerated.

<Operation: First Embodiment>
4 to 8 are diagrams for explaining the operation of the recording / signal processing unit 50A according to the first embodiment. Here, FIG. 4 is a diagram for explaining a general analog PLL operation example. FIG. 5 is a diagram for explaining the PLL sequence operation at the start of the operation of the analog PLL. FIG. 6 is a diagram for explaining the operation in the case where a disturbance occurs in the phase synchronization unit 200 in the recording / signal processing unit 50X of the first comparative example. FIG. 7 is a diagram for explaining a method for generating an RF quality signal RQ by the frame sync processing unit 312 provided in the recording / signal processing unit 50A of the first embodiment. FIG. 8 is a diagram for explaining the operation when a disturbance occurs in the phase synchronization unit 200 in the recording / signal processing unit 50A of the first embodiment.

  4, (1) shows the operation when the PLL gain is small, and (2) shows the operation when the PLL gain is large. Further, (1-1) and (2-1) are phase error signals Vcomp obtained by multiplying the phase error signal by gain, that is, LPF input signals, and (1-2) and (2-2) are respectively (1-1). ), (2-1) is a signal resulting from passing through the loop filter unit 206 (LPF), that is, an oscillation control signal CN for controlling the oscillation unit 201.

  4 (1) and 4 (2) both show an operation in which the phase synchronization unit 200 is operated from time 0, the phase error decreases, and converges to near zero. In this example, as shown in FIG. 4 (1-1) and FIG. 4 (2-1), the amplitude of the phase error signal Vcomp (LPF input signal) differs depending on the PLL gain, and as a result, FIG. 4 (2-2), the oscillation control signal CN which is an LPF output converges earlier in FIG. 4 (2-2) having a larger amplitude. In this example, the detailed operation of the phase synchronization unit 200 that is not directly related to the present embodiment will be omitted.

  FIG. 5 shows a PLL sequence operation at the start of the operation of the phase synchronization unit 200. An operation enable signal EN and a PLL gain switching signal are output from the PLL operation sequencer 300, whereby the operation of the PLL is controlled. The gain multiplier 205 uses the PLL gain switching signal GC to increase the PLL gain in a certain interval from the time when the operation enable signal EN becomes active H (high) and the operation of the phase synchronization unit 200 is started. Thereafter, the PLL gain is decreased at a position where the operation of the phase synchronization unit 200 will have converged. This is because if the PLL gain is increased, the phase synchronization converges faster, but on the other hand, the stability is deteriorated and the phase synchronization is easily lost in response to a disturbance. Therefore, by the control as described above, after the phase synchronization is converged, the PLL gain is lowered to increase the stability.

  Here, in the recording / signal processing unit 50X of the first comparative example, an operation when a disturbance enters the phase synchronization unit 200 will be considered. FIG. 6 shows an example of the operation. For example, when there is dust or scratches on the surface of the optical disk PD, it becomes a disturbance to the input RF signal. In that case, the input RF signal may be strange in a section with disturbance, and a false signal may be output as the phase error signal Comp.

  In FIG. 6, Ta is a section having a disturbance (disturbance section Ta), and a false output is output as the phase error signal Comp in this disturbance section Ta. In this case, after passing through the disturbance section Ta, a certain time is required until convergence from the state where the phase error of the PLL is large. In FIG. 6, a section indicated by Tb (reconvergence section Tb) corresponds to this, and is a section required for the PLL to perform re-retraction. While the phase synchronization unit 200 is operating, if the PLL gain is lowered in order to stabilize the phase synchronization operation, it takes an extra time until the phase synchronization converges compared to when the PLL gain is increased. The data until the phase synchronization converges again tends to cause an error, and if it takes time to converge, there arises a problem that the reproduction quality deteriorates.

  Next, in the recording / signal processing unit 50A of the first embodiment, an operation when a disturbance enters the phase synchronization unit 200 will be considered. FIG. 7 shows an example of generating the RF quality signal RQ by the frame sync processing unit 312. FIG. 7A shows a unique pattern detection result in the frame sync FS. In the unique pattern detection process in the frame sync processing unit 312, the pattern matching of the unique pattern defined by the binary data and the format of the optical disc PD is performed, and the RF quality is determined based on whether or not they match. In FIG. 7 (1), the portion that can be detected is indicated by a solid line, and the portion that should have been originally detected but cannot be detected by a disturbance or the like is indicated by a dotted line. In the figure, a unique pattern can be detected at time points (a), (b), (c), (e), and (f), whereas a unique pattern can be detected at time point (d). Absent.

  FIG. 7B shows a window operation for checking the frame sync interval. When the unique pattern is detected, the frame sync processing unit 312 generates a detection window near the position where the next unique pattern can be detected if there is no disturbance. In this example, the center of the detection window is indicated by a solid line as the position of the frame sync FS when there is no disturbance. In the drawing, the frame sync FS is found at the predicted position at the positions (a), (c), and (f), but at the position (b), the frame sync FS is found at a location that is off. Further, at the position (e), since the immediately preceding frame sync FS was not found, the frame sync FS was detected without generating the predicted position detection window.

  FIG. 7 (3) shows the RF quality signal RQ. The RF quality signal RQ is H (high) when the frame sync FS is found at the predicted position from the immediately preceding frame sync FS, and is found out of the predicted position or not found within the detection window. In this case, the signal is L (low). In the example of the figure, the frame sync FS is found at the predicted position, and the frame sync FS is found at the position (a), (c), (f) where the frame sync FS is off from the predicted position. It becomes L at the position, the position (d) where the unique pattern cannot be detected, and the position (e) where the frame sync FS is detected in the state where the detection window of the predicted position is not generated.

  The fact that the RF quality signal RQ is at the L level indicates that a frame sync FS was found at a location deviating from the predicted position, or that a unique pattern could not be detected, suggesting the occurrence of disturbance. , Indicates that the PLL has transitioned from the locked state to the unlocked state. The fact that the RF quality signal RQ is switched from the H level to the L level indicates that the disturbance section Ta can be detected. The fact that the RF quality signal RQ has become H level indicates that the frame sync FS has been found at the predicted position, and indicates that the PLL has transitioned from the unlocked state to the locked state. Therefore, the PLL operation sequencer 300 uses the gain multiplying unit 205 by means of the PLL gain switching signal GC so that the PLL gain of the gain multiplying unit 205 is increased during the period when the RF quality signal RQ is at the L level and decreased during the period when the RF quality signal RQ is at the H level. 205 is controlled.

  Next, in the recording / signal processing unit 50A of the first embodiment, an operation when a disturbance enters the phase synchronization unit 200 will be considered. FIG. 8 shows an example of the operation. The recording / signal processing unit 50A according to the first embodiment includes the frame sync processing unit 312 so that the PLL reconvergence after the occurrence of the disturbance can be shortened as shown in FIG.

  That is, when the operation example of the first comparative example shown in FIG. 8A (same as FIG. 6) is compared with the operation example of the first embodiment shown in FIG. 8B, the reconvergence section Tb is shortened. It is clear that In the case of the mechanism of the first embodiment, the frame sync processing unit 312 detects the disturbance section Ta and notifies the PLL operation sequencer 300 of the RF quality signal RQ indicating the section. The PLL operation sequencer 300 sets the PLL gain switching signal GC to the L level when the RF quality signal RQ becomes the H level, and sets the PLL gain switching signal GC to the H level when the RF quality signal RQ becomes the L level.

  The gain multiplication unit 205 multiplies the phase error signal Comp at a low magnification while the PLL gain switching signal GC is at the L level until reaching the disturbance section Ta. As a result, the amplitude of the phase error signal Vcomp (LPF input signal) is small. As described above, when the phase synchronization unit 200 is operating and no disturbance occurs, the PLL gain is lowered to stabilize the phase synchronization operation, thereby improving the error rate.

  Thereafter, when entering the disturbance section Ta and when the PLL gain switching signal GC is in the H level, the gain multiplier 205 multiplies the phase error signal Comp at a high magnification. As a result, the amplitude of the phase error signal Vcomp (LPF input signal) increases. For this reason, the phase-synchronized reconvergence section Tb can be shortened. The capture time can be shortened.

  The gain multiplier 205 multiplies the phase error signal Comp at a low magnification during a period in which the PLL gain switching signal GC after the reconvergence section Tb in which the phase synchronization has converged is at the L level. As a result, the amplitude of the phase error signal Vcomp (LPF input signal) is reduced, and the error rate can be improved. After the occurrence of the disturbance, the re-convergence time of the PLL can be shortened. As a result, the data error interval is reduced, thereby improving the reproduction performance. Also, when the PLL gain is lowered, the so-called PLL capture range is reduced. Therefore, the PLL may not be able to converge after the occurrence of a disturbance with the gain in the steady state of the PLL, and the lock may be released. In the mechanism, when a disturbance is detected, the PLL gain is increased, so that the capture range is secured and the PLL is likely to converge.

  As described above, in the mechanism of the first embodiment, when the PLL is locked, the PLL gain is lowered in order to stabilize the phase synchronization operation, and when the PLL lock becomes unstable due to disturbance, the PLL gain is increased. Thus, the time until the phase synchronization converges can be shortened, and then the PLL gain is lowered again when the PLL is locked. By detecting the disturbance section Ta based on the frame sync FS and automatically controlling the PLL gain according to the RF quality signal RQ based on the detection result, it is possible to reduce the capture time and improve the error rate. Since the RF quality signal RQ and the PLL gain switching signal GC can be switched between L and H in units of frame sync FS, the PLL gain can be controlled in units of frame sync FS, and whether the PLL is locked or unlocked and the result of the determination The PLL gain can be automatically controlled based on the above.

  The mechanism according to the first embodiment has an advantage that the PLL lock determination can be easily performed when the PLL is applied to a mechanism for reproducing a signal from a medium. In addition, since the method using the frame sync FS does not use an error signal that depends on the amplitude, there is an advantage that there is no amplitude dependency of the input RF. It is possible to accurately detect that the PLL state is bad, and by performing PLL gain switching, it is possible to quickly recover the PLL from disturbance, and when the PLL is stable, unintended gain switching occurs. Such a device is realized.

  On the other hand, for example, error information such as a value correlated with an error rate such as phase error detection or sequence amplitude margin (SAM) value is used, or after integrating it, a PLL state is detected with a threshold value. In this method, when the RF amplitude fluctuates due to disturbance, there may be a detection failure or a false detection.

  In the first embodiment, when the RF quality signal RQ is generated, the frame sync interval detection method is not limited to the method described above, and various modifications can be considered. For example, a method may be employed in which the RF quality signal RQ is set to H when a certain number or more of frame syncs FS are found within a certain section in which a plurality of frame syncs FS are included, and set to L otherwise.

  In the case of this modification, the sensitivity of the RF quality signal RQ is different when compared with the above-described mechanism. Specifically, in the above-described mechanism, when the frame sync FS cannot be detected due to a minute scratch on the medium, the RF quality signal RQ becomes low level even though the PLL is not unstable. As a result, it malfunctions. On the other hand, in this modification, if a certain number or more of frame syncs FS are found in a certain section, the H level is set. On the other hand, in this modified example, since a section enough to contain a plurality of frames is required for detection, the detection delay of PLL instability increases, whereas in the above-described mechanism, the RF quality signal RQ is changed for each frame sync FS. Since it can be updated, the response is better and fine control is possible. However, in any mechanism, there is no amplitude dependency of the reproduction RF signal.

<Configuration Example of Recording / Signal Processing Unit: Second Embodiment>
FIG. 9 is a diagram illustrating a configuration example of the recording / signal processing unit 50B (particularly, the clock reproduction unit 55) of the second embodiment. The second embodiment is characterized in that the integrated amount of the absolute value of the phase error of the phase synchronization unit 200 is used as the RF quality signal RQ. The integrated amount of the absolute value of the phase error is used to detect the locked state of the PLL.

  As shown in the figure, the PLL & ADC processing unit 53 of the recording / signal processing unit 50B of the second embodiment generates a quality signal RQ based on the oscillation control signal CN output from the loop filter unit 206 of the phase synchronization unit 200. A signal generation unit 310 is provided. The quality signal generation unit 310 of the second embodiment includes a phase error threshold determination unit 314 that binarizes the oscillation control signal CN (LPF output) and determines a phase error based on the binarization result.

  The phase error threshold value determination unit 314 binarizes the oscillation control signal CN (that is, the accumulated phase error amount) from the loop filter unit 206 based on whether the absolute value with respect to the AC center is equal to or greater than a predetermined threshold value Th. . For example, the phase error threshold value determination unit 314 sets a positive-side threshold value Th (+) and a negative-side threshold value Th (−) with respect to the AC center of the oscillation control signal CN, and the oscillation control signal CN is set to the threshold value Th (+ ) Is exceeded or the threshold value Th (−) is below the threshold value Th (−), the binarized phase error signal Comp2 is set to active H. Then, the quality signal generation unit 310 of the second embodiment generates the RF quality signal RQ based on the binarized phase error signal Comp2 generated by the phase error threshold determination unit 314.

<Operation: Second Embodiment>
FIG. 10 is a diagram for explaining the operation of the recording / signal processing unit 50B of the second embodiment. Here, FIG. 10 shows an operation when a disturbance occurs in the phase synchronization unit 200 in the recording / signal processing unit 50B of the second embodiment.

  FIG. 10A shows the phase error signal Comp before gain multiplication. The phase error signal Comp shown in FIG. 10 (1) shows how the disturbance position and the output of the phase comparison unit 203 are in this example, and the second embodiment in the case of such an input. The operation of the embodiment will be described below.

  FIG. 10B shows the accumulated phase error amount (that is, the oscillation control signal CN) output from the loop filter unit 206. FIG. 10 (3) shows the binarized phase error signal Comp2 generated by the phase error threshold value determination unit 314. As shown in FIG. 10 (3), the phase error threshold value determination unit 314 determines whether or not the oscillation control signal CN shown in FIG. 10 (2) exceeds the threshold value Th (+) with respect to the AC center. When it falls below Th (-), the binarized phase error signal Comp2 is set to active H. That is, the phase error threshold value determination unit 314 binarizes whether the absolute value of the accumulated phase error amount with respect to the AC center is equal to or greater than the predetermined threshold value Th.

  In FIG. 10 (2), for the sake of explanation, not the absolute value but the positive threshold value Th (+) and the negative threshold value Th (−) are shown. The threshold values Th (+) and Th (−) are appropriately set according to the characteristics of the phase comparison unit 203 and the loop filter unit 206. As described above, since the accumulated amount of the phase error can be expected to be larger than that in the normal PLL locked state in a part where there is a disturbance and a part where the PLL re-draws, the phase error signal Comp is changed to the RF quality signal. Can be used to generate RQ.

  For example, it is conceivable to use the binarized phase error signal Comp2 generated by the phase error threshold determination unit 314 as the RF quality signal RQ as it is, but here, a measure for preventing flapping of the binarized phase error signal Comp2 is taken. For example, in the example shown in FIG. 10 (2), the oscillation control signal CN once largely fluctuates to the plus side when the disturbance section Ta is reached, exceeds the threshold value Th (+) on the plus side, and is pulled back in the subsequent reconvergence section Tb. On the other hand, it fluctuates greatly on the minus side, exceeds the minus threshold value Th (−), and then converges gradually.

  In such a case, as shown in FIG. 10 (3), the phase error signal Comp once becomes an L level after generating an active H in the disturbance section Ta, then becomes an active H when entering the reconvergence section Tb, and thereafter When approaching stability, it becomes L level. As described above, in the binarized phase error signal Comp2 output from the phase error threshold value determination unit 314 of the second embodiment, a flutter phenomenon that once becomes the L level when moving from the disturbance interval Ta to the reconvergence interval Tb is observed. It is done.

  Therefore, the quality signal generation unit 310 of the second embodiment, as shown in FIG. 10 (4), re-convergence interval from the disturbance interval Ta in the binarized phase error signal Comp2 output from the phase error threshold value determination unit 314. The period of the L level when moving to Tb is also forcibly set to the H level as the RF quality signal RQ. As shown in the figure, a signal obtained by extending the falling timing with respect to the binarized phase error signal Comp2 is defined as an RF quality signal RQ. As a method of extending the falling timing, for example, there is a method of counting for a certain time with a timer circuit or the like from the falling of the binarized phase error signal Comp2. Here, a fixed timer time Tt is indicated by a solid arrow.

  The quality signal generation unit 310 notifies the PLL operation sequencer 300 of the RF quality signal RQ generated in this way, as in the first embodiment. As shown in FIG. 10 (5), the PLL operation sequencer 300 uses the RF quality signal RQ as it is as the PLL gain switching signal GC. In the following, the gain multiplication unit 205 multiplies the phase error signal Comp at a low magnification during the period in which the PLL gain switching signal GC is at L level, and the PLL gain switching signal GC is at H level, as in the first embodiment. During this period, the phase error signal Comp is multiplied at a high magnification.

  As a result of the above processing, as can be seen from the LPF output after gain multiplication shown in FIG. 10 (5), the PLL gain can be switched at the time of the occurrence of the disturbance and at the time of the disturbance recovery also in the second embodiment. When the PLL is locked, the PLL gain is lowered in order to stabilize the phase synchronization operation. If the PLL lock becomes unstable due to disturbance, the PLL gain is increased to increase the time until the phase synchronization converges. If the PLL is locked after that, the PLL gain is lowered again.

  In the second embodiment, the disturbance interval Ta is detected based on the integrated amount of the absolute value of the phase error of the phase synchronization unit 200, and the PLL gain is automatically controlled according to the RF quality signal RQ based on the detection result, thereby obtaining the capture time. Shortening and improvement of error rate can be realized. The RF quality signal RQ and the PLL gain switching signal GC are switched between L and H depending on whether or not the integrated amount of the absolute value of the phase error exceeds a predetermined threshold value.

  Since the mechanism of the second embodiment binarizes the loop filter output, it can be applied to a general phase-locked loop, and there is an advantage that there is no restriction in the application field.

  The mechanism of Japanese Patent Laid-Open No. 2004-228867 is “phase-synchronized with a signal that is input in a random mixture of a signal with a short inversion interval that includes a large level phase fluctuation component and a signal with a long inversion interval and a small phase fluctuation component. In relation to `` a mechanism for generating an oscillation output signal that oscillates at a frequency '', `` the integrated value of the number within the range limited by the limiter unit '' is obtained, and considerable processing is required until the integrated value is obtained turn into. On the other hand, in the second embodiment, there is a difference in that “the integrated amount of the absolute value of the phase error of the PLL” is obtained, and the acquisition is simple.

<Configuration Example of Recording / Signal Processing Unit: Third Embodiment>
FIG. 11 is a diagram illustrating a configuration example of the recording / signal processing unit 50C (particularly, the PLL & ADC processing unit 53 and the binarization processing unit 120) according to the third embodiment. FIG. 12 is a diagram illustrating a configuration example of the recording / signal processing unit 50Y (particularly, the PLL & ADC processing unit 53 and the binarization processing unit 120) of the second comparative example.

  In the third embodiment, in combination with a digital PLL that performs phase error detection digitally, when detecting a synchronization signal from a reproduction RF signal reproduced from an optical disc PD (information recording medium) and acquiring a frame sync FS, It is characterized in that the detection interval of the frame sync FS is monitored, it is determined whether the PLL is locked based on the monitoring information, and the RF quality signal RQ is acquired.

  In order to perform phase error detection “digitally”, the third embodiment is based on the first embodiment, and the second comparative example is based on the first comparative example, with the following modifications. Specifically, the input to the phase comparison unit 203 is digital RF data after AD conversion by the AD conversion unit 54, and phase error detection is performed as shown in the figure, and from there to the output part of the loop filter unit 206 is digitally processed. To do. A DA converter 209 that returns the output to an analog signal is added and input to the analog oscillator 201.

  Then, the quality signal generation unit 310 of the third embodiment monitors the detection interval of the frame sync FS, determines whether the PLL is locked based on the monitoring information, and acquires the RF quality signal RQ. This is basically the same as in the first embodiment.

<Operation: Third Embodiment>
13 to 18 are diagrams illustrating the operation of the recording / signal processing unit 50C of the third embodiment. FIG. 13 is a diagram for explaining a method of detecting a phase error in a general digital PLL. FIG. 14 is a diagram for explaining a problem when the detection method shown in FIG. 13 is adopted. FIGS. 15 to 18 respectively correspond to FIGS. 4 to 8 (excluding FIG. 7) illustrating the operation of the first embodiment.

  The problem with the conventional PLL state detection signal is that the detection accuracy may be poor during disturbance. In the method of using the error information as it is, such as phase error detection or SAM, or integrating the error information, the PLL state is determined by the threshold value. If the RF amplitude fluctuates due to a disturbance, detection error or false detection may occur. There is a case.

  Specifically, depending on the phase error detection method, the output level of the phase error depends on the amplitude. In recent digital PLLs, there is a method in which phase error detection is performed by adding RF data before and after zero crossing.

  FIG. 13 shows an example of this phase error detection. (A) is an analog RF waveform before AD conversion, which is an input to the PLL & ADC processing unit 53. (B) is a sample point RFsmp (i) of the digital RF data after AD conversion, which is an output of the PLL & ADC processing unit 53 and an input of the phase comparator 203. (C) is the RF phase error amount PE to be originally obtained. As a method of approximately obtaining the phase error amount PE, the phase error PEa is obtained by adding RFsmp at the zero cross portion as shown in (d). On the circuit, the phase error PEa becomes an output of the phase comparator 203.

  Note that Gain_a in the description of (d) is not a gain of the loop filter driving unit 204 (gain multiplication unit 205), but a gain for making the phase error amount PE and the phase error PEa close as an output of the phase comparison unit 203. This selects an appropriate value at the time of design.

  The method using the phase error PEa as shown in FIG. 13D is very simple and the circuit can be made small. However, in this method, there is a problem that the gain of the phase error signal is interlocked with the RF reproduction amplitude. Therefore, when the amplitude is reduced due to disturbance, the phase error signal output is small even when the PLL is subjected to disturbance, so that the phase error does not reach the threshold value, resulting in detection failure. .

  FIG. 14 shows an example of the problem. (1) and (2) in the figure have the same phase error amount PE, but have different values of PEvert due to different reproduction RF amplitudes. As a result, the phase error PEa is also linked, and a difference is produced in the output result of the phase error. In particular, during disturbances, the playback RF amplitude often moves in a direction that decreases, and the amount of fluctuation in the playback RF amplitude varies depending on the type of disturbance. As a result, an error occurs in the output of the phase error. Alternatively, the integration does not reach the detection threshold of PLL instability, resulting in detection failure.

  Further, as a method of using a value correlated with an error rate as error information, a method of using a sequence of error of an input signal with respect to a target, such as SAM, equalizing a reproduction RF signal to a target PR class can be considered. (See Patent Document 2). In this method, it is assumed that the amplitude of the reproduction RF signal is adjusted by auto gain control (AGC) and desired PR equalization is performed by an adaptive equalizer or the like. However, when a sudden amplitude fluctuation occurs due to a disturbance, the response of the RF amplitude auto gain control (AGC) and the adaptive equalization filter cannot catch up, so the error increases in the amplitude fluctuation portion and exceeds the threshold value. A problem occurs. At this time, even when the PLL is not actually disturbed, the PLL gain is switched, and as a result, the PLL jitter increases and the error rate may deteriorate.

  In the third embodiment, a technique for solving these difficulties is realized. Specifically, the detection interval of the frame sync FS is monitored in the same manner as shown in FIG. 7, and the quality signal generation unit 310 generates an RF quality signal RQ from the monitoring information and notifies the PLL operation sequencer 300 of it. Thus, PLL gain switching is realized. A shift in the detection interval of the frame sync FS means that the clock increases or decreases from the predetermined number of cycles between the frame syncs, which can only occur due to a disturbance in the PLL. Further, since an error signal that depends on the amplitude is not used, there is no amplitude dependency of the input RF. By adopting such a mechanism, it is accurately detected that the PLL state is bad. Based on this result, the PLL can be quickly restored from the disturbance by switching the gain of the PLL. Moreover, when the PLL is stable, unintended gain switching does not occur.

  The operation in the third embodiment is basically the same as that in the first embodiment. The difference is that if the phase error is digitized, all detection examples of the phase error need to be corrected. Specifically, in the first embodiment, the phase error amount is also indicated by the width, but since it is described by the height, FIGS. 4 to 8 for explaining the operation of the first embodiment are respectively shown. 15 to 18 as shown.

  For example, in FIG. 18, when describing the phase error amount not in width but in height, in (2), the increment due to increasing the gain (assuming that the gain has been doubled) is indicated by a thick line for easy understanding. Show.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, the application example to the information recording / reproducing apparatus such as the optical disk apparatus has been described. However, the information recording / reproducing apparatus is not limited to the optical disk apparatus, but includes, for example, a hard disk driving apparatus. A recovery circuit or a write clock generation circuit may be used. The mechanism of the above embodiment can be applied to the clock recovery circuit and the write clock generation circuit.

  The same applies to a clock recovery circuit that generates a reproduction clock based on phase information of a reproduction signal read from a recording medium in other recording / reproduction apparatuses such as a digital VTR and a digital VCR, as well as an optical disk device and a hard disk drive device. It is applicable to.

  In addition to the information recording / reproducing device, for example, a technology for reproducing the timing of the received signal sequence such as serial communication using a twisted pair metal cable or fiber cable as a medium, an input / output interface for inter-chip transmission, and other electronic devices. It is also applicable to.

It is a block diagram which shows one Embodiment of the information recording / reproducing apparatus which is an example of the electronic device which equipped with the phase-synchronization circuit. It is a figure which shows the structural example of the PLL & ADC process part of 1st Embodiment, and a binarization process part. It is a figure which shows the structural example of the PLL & ADC process part of a 1st comparative example, and a binarization process part. It is a figure explaining the example of a general analog PLL operation | movement. It is a figure explaining the PLL sequence operation | movement at the time of the operation | movement start of an analog PLL. It is a figure explaining operation | movement when disturbance enters into a phase-synchronization part in the recording / signal processing part of the 1st comparative example. It is a figure explaining the production | generation method of RF quality signal by the frame sync processing part with which the recording / signal processing part of 1st Embodiment was equipped. It is a figure explaining operation | movement when a disturbance enters into a phase-synchronization part in the recording / signal processing part of 1st Embodiment. It is a figure explaining the structural example of the clock reproduction | regeneration part of 2nd Embodiment. It is a figure explaining operation | movement of the recording / signal processing part of 2nd Embodiment. It is a figure which shows the structural example of the PLL & ADC processing part and binarization processing part of 3rd Embodiment. It is a figure which shows the structural example of the PLL & ADC process part of a 2nd comparative example, and a binarization process part. It is a figure explaining the detection method of the phase error in a general digital PLL. It is a figure explaining a problem when the detection method shown in FIG. 13 is employ | adopted. It is a figure explaining the example of a general digital PLL operation | movement. It is a figure explaining PLL sequence operation at the time of operation start of digital PLL. It is a figure explaining operation | movement when disturbance enters into a phase-synchronization part in the recording / signal processing part of the 2nd comparative example. It is a figure explaining operation | movement when a disturbance enters into a phase-synchronization part in the recording / signal processing part of 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Information recording / reproducing apparatus, 10 ... Spindle motor, 110 ... Modulation processing part, 120 ... Binarization processing part, 122 ... PR equalization processing part, 124 ... Viterbi processing part, 130 ... Demodulation processing part, 14 ... Optical pick-up , 200 ... phase synchronization unit, 201 ... oscillation unit, 203 ... phase comparison unit, 204 ... loop filter driving unit, 205 ... gain multiplication unit, 206 ... loop filter unit, 208 ... DA conversion unit, 3 ... host device, 30 ... Spindle motor control unit, 300 ... PLL operation sequencer (gain control unit), 310 ... quality signal generation unit, 312 ... frame sync processing unit, 314 ... phase error threshold determination unit, 40 ... pickup control unit, 50 ... recording / reproduction signal Processing unit 52... RF amplification unit 53. PLL & ADC processing unit 54... AD conversion unit 55... Clock reproduction unit 56. , 57 ... recording current control unit

Claims (7)

A phase detection unit for detecting a phase difference between a reproduction signal reproduced from the recording medium and the other signal;
An amplifying unit for multiplying the information of the phase difference detected by the phase detecting unit by a predetermined value;
A loop filter unit for accumulating the phase difference information output from the amplification unit to generate an oscillation control signal;
An oscillation unit that generates an oscillation output signal having a frequency corresponding to the oscillation control signal as the other signal;
A quality signal generating unit that detects a synchronization signal from the reproduction signal to acquire a frame synchronization signal, and generates a quality signal indicating whether or not the phase-locked loop is locked based on a result of the detection and acquisition;
A phase synchronization circuit comprising: a gain control unit that controls the predetermined multiplication in the amplification unit based on the quality signal generated by the quality signal generation unit. The phase synchronization circuit according to claim 1, wherein the quality signal generation unit monitors a detection interval of the frame synchronization signal and generates the quality signal based on the monitoring result. An AD converter for converting the analog reproduction signal into digital data;
A DA converter that converts a digital oscillation output signal output from the loop filter unit into an analog signal and supplies the analog signal;
Further comprising
The phase synchronization circuit according to claim 1, wherein the phase detection unit detects a phase difference between the digital reproduction signal converted by the AD conversion unit and the other signal. A signal processing unit for obtaining a reproduction signal from the recording medium as one of the two signals;
A phase detector for detecting a phase difference between the two signals;
An amplifying unit for multiplying the information of the phase difference detected by the phase detecting unit by a predetermined value;
A loop filter unit for accumulating the phase difference information output from the amplification unit to generate an oscillation control signal;
An oscillation unit that generates an oscillation output signal having a frequency corresponding to the oscillation control signal as the other signal;
A synchronization signal is detected from the reproduction signal acquired by the signal processing unit to acquire a frame synchronization signal, and a quality signal indicating whether or not the phase locked loop is locked is generated based on the detection / acquisition result A quality signal generator to
An information reproducing apparatus comprising: a gain control unit that controls the predetermined multiplication in the amplification unit based on the quality signal generated by the quality signal generation unit. A phase detector for detecting a phase difference between two signals;
An amplifying unit for multiplying the information of the phase difference detected by the phase detecting unit by a predetermined value;
A loop filter unit for accumulating the phase difference information output from the amplification unit to generate an oscillation control signal;
An oscillation unit that generates an oscillation output signal having a frequency corresponding to the oscillation control signal as the other of the two signals;
A quality signal generating unit that determines the magnitude of the oscillation control signal output from the loop filter unit and a predetermined threshold, and generates a quality signal indicating whether or not the phase-locked loop is locked based on the determination result; ,
A phase synchronization circuit comprising: a gain control unit that controls the predetermined multiplication in the amplification unit based on the quality signal generated by the quality signal generation unit. A signal processing unit for acquiring one of the two signals;
A phase detector for detecting a phase difference between the two signals;
An amplifying unit for multiplying the information of the phase difference detected by the phase detecting unit by a predetermined value;
A loop filter unit for accumulating the phase difference information output from the amplification unit to generate an oscillation control signal;
An oscillation unit that generates an oscillation output signal having a frequency corresponding to the oscillation control signal as the other of the two signals;
A quality signal generating unit that determines whether the oscillation control signal output from the loop filter unit and a predetermined threshold are large and generates a quality signal indicating whether the phase-locked loop is locked based on the determination result;
An electronic device comprising: a gain control unit that controls the predetermined multiplication in the amplification unit based on the quality signal generated by the quality signal generation unit. The phase detector detects the phase difference between the two signals,
The information of the phase difference detected by the phase detection unit is multiplied by a predetermined value by the amplification unit,
The oscillation filter signal is generated by integrating the phase difference information output from the amplification unit by the loop filter unit,
An oscillation output signal having a frequency corresponding to the oscillation control signal is generated by the oscillation unit as the other of the two signals,
As a result of detection / acquisition when the synchronization signal is detected from the reproduction signal reproduced from the recording medium that is one of the two signals and the frame synchronization signal is acquired, the level detected by the phase detection unit is detected. Any one of the absolute values of the phase difference is measured as an evaluation index, the magnitude of the evaluation index in a certain section is determined, and the predetermined multiple in the amplification unit is controlled based on the determination result A gain control method for a synchronous circuit.

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