JP2010035312A - Dc motor controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of a conventional system that there is a risk that the overload state of a drive might last long in case that motor load becomes heavy diachronically. <P>SOLUTION: A DC motor controller includes a motor drive, which drives a DC motor, a speed detector, which detects the rotational speed of the DC motor, a current detector, which detects the output current of the motor drive, and a control unit, which controls the motor drive, by the drive of the motor drive and besides based on the speed detected by the speed detector and the output current detected by the current detector. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a DC motor control device.

Conventionally, a DC motor control device detects the rotational speed of a DC motor, and if a predetermined rotational speed is not reached within a predetermined time, an abnormal signal is output to the CPU in the DC motor control device. Had stopped.
Japanese Patent Laid-Open No. 05-10270

  However, in the conventional DC motor control device, if the DC motor reaches a predetermined rotational speed within a predetermined time, it is determined that the DC motor is normally driven. There was a possibility that the overload state could not be detected for a long time.

  In order to solve the above problems, the present invention has the following configuration.

  The DC motor control device of the present invention includes a motor drive unit that drives a DC motor, a speed detection unit that detects the rotational speed of the DC motor, a current detection unit that detects an output current of the motor drive unit, and the motor And a controller that controls the motor driver based on the speed detected by the speed detector and the output current detected by the current detector.

  According to the present invention, the DC motor is decelerated when the DC motor does not reach the rotation speed determined within a predetermined time, or when the energization current to the DC motor at the predetermined rotation speed exceeds a predetermined current value. By doing so, the overload state can be suppressed in a short time.

  Embodiments of the present invention will be described below. The DC motor described here is a three-phase brushless motor.

FIG. 1 is a block diagram illustrating a configuration of the DC motor control device according to the first embodiment.
As shown in the figure, the DC motor control device 1 has a control unit 2, a driver 4, a position detection unit 5, a speed detection unit 6, and a current detection unit 7, and the DC motor control device 1 drives a DC motor 3. Let

The control unit 2 includes a CPU 8, a timer 9, a state storage unit 10, and a motor control unit 11.
The CPU 8 is a unit that operates according to a program written in a ROM (READ ONLY MEMORY) (not shown).

  The timer 9 measures whether a predetermined time at which the predetermined DC motor 3 should reach a certain rotation speed has been reached when the DC motor 3 is started. The timer 9 outputs a timer data signal 16 to the CPU 8 when the measured time reaches a predetermined time. The CPU 8 sets the timer value of the timer 9 and transmits the timer reset signal 14 to cause the timer 9 to perform measurement for a predetermined time.

  In the state storage unit 10, when the DC motor 3 is activated, if the predetermined rotational speed is not reached within a predetermined time, or the predetermined rotational speed is reached within the predetermined time, the current supplied to the DC motor 3 is rated. When the current is exceeded, the CPU 8 writes “1” of the flag write signal 15 indicating abnormality in the state storage unit 10.

If the CPU 8 does not reach the predetermined rotational speed within the predetermined time when the DC motor 3 is activated, the CPU 8 checks whether the predetermined rotational speed is reached within the limit time set beyond the predetermined time. If the predetermined rotational speed is not reached, the DC motor 3 is stopped.
On the other hand, when the rated current is exceeded once after starting, the CPU 8 once stops the DC motor 3 and restarts it again. Since the CPU 8 has already stored “1” of the flag write signal 15 indicating an abnormality in the state storage unit 10 at the time of restart, if the above abnormality occurs again, the CPU 8 determines that the flag of the state storage unit 10 When the data signal 17 is read and it is confirmed that “1” is stored, the DC motor 3 is stopped.

The CPU 8 outputs “Hi” of the start / stop signal 12 to the motor control unit 11 when the DC motor 3 is started. Further, the CPU 8 outputs “Lo” of the start / stop signal 12 to the motor control unit 11 at the time of stop (deceleration).
Further, the CPU 8 transmits a CLK signal 13 for detecting the rotation speed and phase of the DC motor 3 to the motor control unit 11.

  Further, the CPU 8 receives a LOCK signal 18 for determining whether or not the DC motor 3 has reached a predetermined rotational speed from the motor control unit 11, and a rated current for determining whether or not the rated current is exceeded from the current detection unit 7. An abnormal signal 19 is input.

  The driver 4 is composed of a total of six power MOSFETs, three high side and three low side, as switching elements. The motor control unit 11 receives the gate signal and drives the power MOSFET.

Next, the position detection unit 5, the speed detection unit 6, and the motor control unit 11 will be described with reference to FIG.
FIG. 2 is a circuit block diagram of the motor control unit, the position detection unit, and the speed detection unit according to the first embodiment.

The position detection unit 5 includes a Hall element 20 that detects the phase of the rotor (rotor) of the DC motor 3.
In the present invention, a three-phase brushless motor is applied as the DC motor 3. Accordingly, a total of three Hall elements 20 for detecting the phase of the rotor, Hall element U, Hall element V, and Hall element W, are used.

The speed detector 6 is made of a copper foil wire called an FG (frequency generator) pattern 21 that can detect the rotational speed of a rotor provided on a substrate (not shown) near the rotor.
The rotor speed detection FG pattern 21 is composed of a power generation copper foil wire equal to the number of magnetic poles of the FG magnet integrated with the rotor. The FG pattern 21 is opposed to the FG magnet, and is formed in an annular shape by connecting the power generation copper foil wires in series.
When the FG magnet rotates integrally with the rotor, a speed detection signal having a frequency corresponding to the rotational speed of the rotor is induced in the FG pattern 21 due to a change in the magnetic flux relative to the FG magnet.

  The motor control unit 11 includes a hall amplifier 22, an FG amplifier 23, a speed comparator 24, a phase comparator 25, a VCO (voltage controlled oscillator) 26, a counter 27, an integrating amplifier 28, a PWM (PULSE WIDTH MODULATION) frequency oscillator 29, A pulse comparator 30 and a PWM-DUTY output unit 31 are included.

  The Hall amplifier 22 is an amplifier for amplifying each waveform from the Hall element U, the Hall element V, and the Hall element W, which are the Hall elements 20, and shaping the waveform. Each waveform-shaped signal is transmitted to the PWM-DUTY output unit 31 as a hall amplifier output signal 44.

  The FG amplifier 23 is an amplifier for amplifying the output of the FG pattern 21 and shaping the waveform. The waveform-shaped signal is output to the speed comparator 24 and the phase comparator 25 as the FG signal 32.

  The speed comparator 24 compares the above-described FG signal 32 with a count signal 35 indicating one clock cycle from the counter 27 described later to detect a difference between the rotational speed of the DC motor 3 and a predetermined rotational speed. It is a vessel. Further, the speed comparator 24 outputs the detected speed difference pulse signal 33 to the integrating amplifier 28. The speed comparator 24 determines that there is an abnormality in the rotation of the DC motor 3 when the speed difference is 6.25% or more with respect to the time of one clock cycle, and the LOCK is used to notify the CPU 8 of the abnormality. The signal 18 “Hi” is transmitted to the CPU 8. For example, if one clock cycle is 10 ms and the speed difference is 0.625 ms or more, it is determined as abnormal.

  The phase comparator 25 is a comparator for comparing the phases of the FG signal 32 and the CLK signal 13 output from the CPU 8 to detect a phase difference. Further, the phase comparator 25 transmits the detected phase difference as a phase difference pulse signal 34 to the integrating amplifier 28.

  The VCO 26 is a voltage-controlled oscillator. When the CLK signal 13 is received from the CPU 8, the VCO 26 converts it to a voltage level that can be received by the counter 27. The VCO 26 transmits the converted signal to the counter 27.

  The counter 27 transmits to the speed comparator 24 a count signal 35 in which one cycle of the signal received from the VCO 26 is one pulse.

  When the integrating amplifier 28 receives the speed difference pulse signal 33 and the phase difference pulse signal 34, the integrating amplifier 28 integrates it and transmits it to the pulse comparator 30 as an integrated output signal 36.

  The PWM frequency oscillator 29 is an oscillator that outputs a triangular wave signal set to the drive frequency of the DC motor 3.

  The pulse comparator 30 is a comparator for comparing the output of the integrating amplifier 28 and the triangular wave signal of the PWM frequency oscillator 29. The pulse comparator 30 transmits, to the PWM-DUTY output unit 31, a PWM signal 38 that is switched by switching the ON / OFF DUTY ratio of the rectangular wave.

  The PWM-DUTY output unit 31 is a pre-driver that employs a totem pole method in which the drive signal 39 can output a large current so that the gate capacitance of the power MOSFET that is a component of the driver 4 can be charged and discharged rapidly. It is. The driver 4 to which the drive signal 39 from the PWM-DUTY output unit 31 is input is composed of a total of six power MOSFETs including three high sides and three low sides as switching elements.

Next, the current detection unit 7 will be described.
FIG. 3 is a circuit block diagram of the rated current detection unit and the maximum current detection unit of the first embodiment.
The current detection unit 7 shown in FIG. 1 includes a rated current detection unit 40 and a maximum current detection unit 41 as shown in FIG.

The rated current detector 40 includes a resistor R1, a resistor R2, a capacitor C1, and a voltage comparator 46.
The resistor R1 converts the DC motor current into a voltage.
The signal converted into a voltage is smoothed by an integrating circuit including a resistor R2 and a capacitor C1.

  A reference voltage is applied to one of the two input parts of the voltage comparator 46, and the above-mentioned smoothed signal is input to the other, and the voltages of both input signals are compared. For example, if the circuit configuration is low active, the voltage comparator 46 transmits a “Lo” signal to the CPU 8 as the rated current abnormality signal 19 when the reference voltage is exceeded. If the reference voltage is not exceeded, a “Hi” signal is transmitted to the CPU 8.

  When the “Lo” signal is input as the rated current abnormality signal 19, the CPU 8 determines that the rated current is abnormal and transmits the “Hi” signal of the start / stop signal 12 to the motor control unit 11 to stop the DC motor 3. .

On the other hand, the maximum current detection unit 41 includes a voltage comparator 42 and a PWM-DUTY output unit 31 of the motor control unit 11.
The voltage comparator 42 reads a signal obtained by converting the energization current to the DC motor 3 into a voltage in the same manner as the voltage comparator 46 during constant speed driving, and determines whether or not a predetermined maximum current value is exceeded. When it exceeds, the maximum current abnormality signal 43 “Lo” is output to the PWM-DUTY output unit 31 and the DC motor 3 is stopped.

Next, a method for changing the phase of the motor drive signal will be described.
FIG. 4 is a timing chart of the drive signal of the DC motor and the output signal of the hall amplifier according to the first embodiment.

  Description will be made starting from t1 shown in the figure. When the PWM-DUTY output unit 31 shown in FIG. 2 detects the falling edge of the Hu signal of the Hall amplifier output signal 44 at t1, the PWM-DUTY output unit 31 converts the UH signal of the drive signal 39 into a “Hi” signal. Set. At the same time, the WH signal of the drive signal 39 can be set to the “Lo” signal. In addition to the WH signal that can be set to the “Lo” signal, the switching of the VH signal and the UH signal to the Lo level has passed the ON time of the PWM signal 38 in conjunction with the edge detection of the Hall amplifier output signal 44 described above. It is switched depending on whether or not.

  Next, at t2 indicating a point rotated by an electrical angle of 60 °, when the PWM-DUTY output unit 31 detects the rising edge of the Hw signal of the Hall amplifier output signal 44, the PWM-DUTY output unit 31 receives the drive signal 39. At the same time, the WL signal of the drive signal 39 is set to the “Hi” signal.

  Next, at t3 indicating a point rotated by an electrical angle of 60 °, when the PWM-DUTY output unit 31 detects the falling edge of the Hv signal of the Hall amplifier output signal 44, the PWM-DUTY output unit 31 It is possible to switch the 39 UH signal to the “Lo” signal, and simultaneously set the VH signal of the drive signal 39 to the “Hi” signal.

  Next, at t4 indicating a point rotated by an electrical angle of 60 °, when the PWM-DUTY output unit 31 detects the rising edge of the Hu signal of the Hall amplifier output signal 44, the PWM-DUTY output unit 31 receives the drive signal 39. At the same time, the WL signal of the drive signal 39 is set to the “Lo” signal.

  Next, at t5 indicating a point rotated by an electrical angle of 60 °, when the PWM-DUTY output unit 31 detects the falling edge of the Hw signal of the Hall amplifier output signal 44, the PWM-DUTY output unit 31 The VH signal of 39 can be switched to the “Lo” signal, and at the same time, the WH signal of the drive signal 39 is set to the “Hi” signal.

  Next, at t6 indicating a point rotated by an electrical angle of 60 °, when the PWM-DUTY output unit 31 detects the rising edge of the Hv signal of the Hall amplifier output signal 44, the PWM-DUTY output unit 31 outputs the drive signal 39. At the same time, the VL signal of the drive signal 39 is set to the “Hi” signal. After t6, the phase is switched by repeating the above-described operations from t1 to t6.

Next, speed control and phase control during motor constant speed driving will be described.
FIG. 5 is a timing chart of speed control and phase control when the motor is driven at a constant speed according to the first embodiment.
The speed comparator 24 of the motor control unit 11 detects the rising edge of the FG signal 32 and the falling edge of the count signal 35, and the phase comparator 25 of the motor control unit 11 detects the falling edge of the FG signal 32 and CLK The falling edge of the signal 13 is detected.

  When the speed comparator 24 of the motor control unit 11 detects the rising edge of the FG signal 32 at the point t7 shown in the figure, the counter 27 starts counting the one cycle time of the CLK signal 13 from the counter 27.

  The phase comparator 25 detects the falling edge of the CLK signal 13 at the point t8 shown in the figure, but has not detected the falling edge of the FG signal 32, and thus starts detecting the time of the phase difference pulse signal 34. .

  When the phase comparator 25 detects the falling edge of the FG signal 32 at the point t9 shown in the figure, the time of the phase difference pulse signal 34 is calculated, and t9-t8 = phase delay time.

  Next, at the point t10 shown in the figure, the speed comparator 24 has reached one cycle of the CLK signal 13 from the counter 27, and thus finishes counting. At this time, if the rising edge of the FG signal 32 cannot be detected, the speed comparator 24 starts detecting the time of the speed difference pulse signal 33.

  When the speed comparator 24 detects the rising edge of the FG signal 32 at the point t11 shown in the figure, the time of the speed difference pulse signal 33 is calculated, and t11-t10 = speed delay time. Here, the speed comparator 24 makes an abnormality if the speed delay time is ± 6.25% or more of the clock count value, and transmits the LOCK signal 18 “Hi” to the CPU 8.

  The above is the operation when the speed and phase are delayed with respect to the CLK signal 13 and the count signal 35. Next, the operation when the speed and phase are advanced with respect to the CLK signal 13 and the count signal 35 is described with reference to FIG. This will be described after t11.

  When the speed comparator 24 detects the rising edge of the FG signal 32 at the point t11 shown in the figure, the counter 27 starts counting the one cycle time of the CLK signal 13 from the counter 27.

  Next, at the time point t12 shown in the drawing, the phase comparator 25 detects the falling edge of the FG signal 32, but if the falling edge of the CLK signal 13 cannot be detected, the time of the phase difference pulse signal 34 is detected. Start detecting.

  When the phase comparator 25 detects the falling edge of the CLK signal 13 at the point t13 shown in the figure, the time of the phase difference pulse signal 34 is calculated, and t13−t12 = phase advance time.

Even if the speed comparator 24 detects the rising edge of the FG signal 32 at the point t14 shown in the figure, if the counter 27 has not finished counting one cycle time of the CLK signal 13,
Detection of the time of the speed difference pulse signal 33 is started.

  Next, at the time t15 shown in the drawing, the speed comparator 24 calculates the time of the speed difference pulse signal 33 when counting of one cycle time of the CLK signal 13 is completed, and t15-t14 = speed advance time. Here, the speed comparator 24 makes an abnormality when the speed advance time is ± 6.25% or more of the clock count value, and transmits the LOCK signal 18 “Hi” to the CPU 8.

  Further, the phase difference pulse signal 34 and the speed difference pulse signal 33 are integrated by the integrating amplifier 28 and gain-adjusted, and output to the pulse comparator 30 as an integration output signal 36. On the other hand, the PWM frequency oscillator 29 transmits a PWM setting signal 37 to the pulse comparator 30.

  When the pulse comparator 30 receives the integrated output signal 36 and the PWM setting signal 37 and reaches the integrated output signal 36 at the rising edge of the PWM setting signal 37, the pulse comparator 30 changes the PWM signal 38 to the “Hi” signal. When the pulse comparator 30 reaches the integral output signal 36 at the falling edge of the PWM setting signal 37, the pulse comparator 30 changes the PWM signal 38 to the “Lo” signal.

  As described above, the “Hi” signal and the “Lo” signal of the PWM signal 38 are determined, so that the DUTY ratio is determined and the ON time of each of the UH, VH, and WH signals of the drive signal 39 shown in FIG.

Next, speed control and phase control during motor acceleration will be described.
FIG. 6 is a timing chart of speed control and phase control during motor acceleration driving according to the first embodiment.

  The motor control unit 11 outputs the PWM signal 38 when the “Lo” signal of the start / stop signal 12 and the CLK signal 13 are input. As for the output of the PWM signal 38, the speed comparator 24 detects the rising edge of the FG signal 32 and the falling edge of the count signal 35 as in the case of constant speed driving, and the phase comparator 25 of the motor control unit 11 outputs the FG signal. By detecting the falling edge of 32 and the falling edge of the CLK signal 13, the integrated output signal 36 is extracted from the speed difference pulse signal 33 and the phase difference pulse signal, and the PWM signal 38 is generated.

  However, the integrated output signal 36 at the time of acceleration is low because the phase difference and the speed difference are large from the stop state until the constant speed rotation is reached. Therefore, there is a possibility that the integrated output signal 36 does not reach the voltage signal that intersects the triangular wave of the PWM setting signal 37. Therefore, the DUTY ratio of the drive signal 39 is output at a fixed period t17 in the acceleration section shown in the figure. In addition, if the t17 period is ± 6.25% or more of the clock count value for the phase delay and speed delay periods, the LOCK signal 18 “Hi” is output to the CPU 8, but the CPU 8 outputs the LOCK signal 18 during acceleration. It is used whether or not the drive speed of the DC motor 3 has reached a constant speed. When the speed comparator 24 is driven at a constant speed, the speed comparator 24 transmits a LOCK signal 18 “Lo” to the CPU 8. Even if the maximum current abnormality signal 43 is an “Lo” signal indicating abnormality until t16 interval due to the acceleration interval, the CPU 8 determines normal abnormality only during constant speed driving without determining abnormality.

Next, speed control and phase control during motor deceleration will be described.
FIG. 7 is a timing chart of speed control and phase control during motor deceleration driving according to the first embodiment.

When the “Hi” signal of the start / stop signal 12 is input from the CPU 8, the motor control unit 11 applies a short brake by turning on all the drive signals 39 to perform the deceleration process of the DC motor 3.
The CPU 8 outputs a “Hi” signal of the start / stop signal 12 and simultaneously transmits a fixed signal of “Hi” or “Lo” so that the CLK signal 13 does not become high impedance.

  During the short brake, the rising / falling edge of the FG signal 32 and the falling edge of the CLK signal 13 are not detected.

Next, the operation of the DC motor control device 1 will be described using a flowchart.
FIG. 8 is a flowchart illustrating the operation of the DC motor control device according to the first embodiment.

  Hereinafter, step S1 to step S19 will be described in the order of steps with reference to FIGS.

(Step S1)
The CPU 8 outputs the “Lo” signal of the start / stop signal 12 and the CLK signal 13, transmits the drive signal 39 by the PWM-DUTY output unit 31 to drive the driver 4, and activates the DC motor 3. At startup, the PWM-DUTY ratio of the drive signal 39 is fixed regardless of the speed / phase difference.

(Step S2)
The CPU 8 transmits “0” as the flag write signal 15 to the state storage unit 10 for storage.

(Step S3)
The CPU 8 transmits a timer reset signal 14 to the timer 9, resets the timer count once, and starts the timer count again.

(Step S4)
The CPU 8 reads the timer data signal 16 being counted and checks the read timer value and the reference value t20 in order to confirm whether or not the reference time from the start of starting until reaching a predetermined rotation speed has elapsed. Compare. If the reference value t20 is exceeded, the process proceeds to step S5.

(Step S5)
If the timer value exceeds the reference value t20, the CPU 8 determines whether the LOCK signal 18 is outputting “Lo” or “Hi” in order to confirm whether or not the predetermined rotational speed has been reached. . If “Lo”, the process proceeds to step S16, and if “Hi”, the process proceeds to step S6.

(Step S6)
If the CPU 8 determines that the LOCK signal 18 is “Hi”, then in the rated current detector 40, it is determined whether the voltage comparator 46 outputs “Lo” or “Hi” as the rated current abnormality signal 19. judge. If it is “Lo”, the process proceeds to step S7, and if it is “Hi”, the rotation of the DC motor 3 is continued normally.
If the LOCK signal 18 is determined to be “Hi”, the CPU 8 determines that the motor has reached a predetermined rotational speed, and detects the speed difference / phase difference from the PWM-DUTY fixed driving system. It changes to the drive system by the DUTY ratio based on this.

(Step S7)
In response to “Lo” of the rated current abnormality signal 19, the CPU 8 transmits “1” as the flag writing signal 15 to the state storage unit 10 for storage.

(Step S8)
The CPU 8 transmits a start / stop signal 12 “Hi” to the motor control unit 11 in order to stop the DC motor 3 in response to an abnormality in the rated current.

(Step S9)
Next, the CPU 8 transmits the start / stop signal 12 “Lo” and the CLK signal 13 to the motor control unit 11 to restart the DC motor 3 after the DC motor 3 has stopped, and restarts the DC motor 3. .

(Step S10)
The CPU 8 transmits a timer reset signal 14 to the timer 9, resets the timer count once, and starts the timer count again.

(Step S11)
The CPU 8 reads the timer data signal 16 being counted and compares the read timer value with the reference value t20 in order to check whether or not the reference time has elapsed from the start of starting until a predetermined rotation speed is reached. To do. If the reference value t20 is exceeded, the process proceeds to step S12.

(Step S12)
If the timer value exceeds the reference value t20, the CPU 8 determines whether the LOCK signal 18 is outputting “Lo” or “Hi” in order to confirm whether or not the predetermined rotational speed has been reached. . If it is “Lo”, the process proceeds to step S14, and if it is “Hi”, the process proceeds to step S13.

(Step S13)
If the CPU 8 determines that the LOCK signal 18 is “Hi”, then in the rated current detector 40, it is determined whether the voltage comparator 46 outputs “Lo” or “Hi” as the rated current abnormality signal 19. judge. If it is “Lo”, the process proceeds to step S14, and if it is “Hi”, the rotation of the DC motor 3 is continued normally.
If the LOCK signal 18 is determined to be “Hi”, the CPU 8 determines that the motor has reached a predetermined rotational speed, and detects the speed difference / phase difference from the PWM-DUTY fixed driving system. It changes to the drive system by the DUTY ratio based on this.

(Step S14)
When the voltage comparator 46 outputs a “Lo” signal in the rated current detection unit 40, the CPU 8 reads the flag data signal 17 written in the state storage unit 10 in order to confirm the state.

(Step S15)
When the CPU 8 reads the flag data signal 17 “1” written in the state storage unit 10, it outputs the “Hi” signal of the start / stop signal 12, and when the DC motor 3 is decelerated, the DC motor 3 eventually stops. .

(Step S16)
On the other hand, if the “Lo” signal of the LOCK signal 18 cannot be detected in step S 5, the CPU 8 writes “1” as the flag write signal 15 in the state storage unit 10.

(Step S17)
The CPU 8 outputs a timer reset signal 14 to the timer 9 to reset the timer count, and then starts the timer count again.

(Step S18)
The CPU 8 reads the timer data signal 16 and compares the read timer value with the reference value t21. t21 is set to a value obtained by subtracting t20 from a numerical value equal to or longer than the motor acceleration time when the rated torque of the DC motor 3 is output.

(Step S19)
If the timer value is longer than the reference value t21, the CPU 8 determines whether the LOCK signal 18 is a “Lo” signal. If it is the “Lo” signal, the process proceeds to step S13, and the CPU 8 determines whether or not the voltage comparator 46 outputs the “Lo” signal. On the other hand, if it is not the “Lo” signal, the process proceeds to step S14, and the CPU 8 reads the flag data signal 17 “1” written in the state storage unit 10 and stops the DC motor 3.

  As described above, according to the first embodiment, when the DC motor does not reach the rotation speed determined within the predetermined time, or when the energization current to the DC motor at the predetermined rotation speed exceeds the predetermined current value. The overload state can be suppressed in a short time by slowing down the DC motor.

In the second embodiment, it is detected that the time until the DC motor reaches the predetermined rotational speed exceeds a predetermined time, or it is detected that the current flowing to the DC motor at the predetermined rotational speed is equal to or higher than the rated current. In such a case, the motor speed is set to ½ and the DC motor is restarted, and it is detected again that the time until the DC motor reaches a predetermined rotation speed exceeds a predetermined time or a predetermined rotation The DC motor is stopped when it is detected that the current flowing to the DC motor at the speed is greater than or equal to the rated current.
In the second embodiment, it is possible to avoid a DC motor start-up failure (adhesion, sticking, etc.) by retrying at a low speed, and it is possible to detect a load change due to a change with time as in the first embodiment. An overload condition can be suppressed in a short time.

FIG. 9 is a block diagram illustrating a configuration of the DC motor control device according to the second embodiment.
As shown in the figure, the DC motor control device 100 includes a control unit 102, a DC motor 3, a driver 4, a position detection unit 5, a speed detection unit 6, and a current detection unit 7.

  The control unit 2 includes a CPU 8, a timer 9, a state storage unit 10, and a motor control unit 11, and the second embodiment is different from the first embodiment in that an SRAM 45 is further provided.

  Only portions different from the first embodiment will be described in detail below. The same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted.

  The SRAM 45 stores two kinds of initial values A (Hz) and A / 2 (Hz) as the frequency of the CLK signal 13.

Next, the operation of the second embodiment will be described.
FIG. 10 is a flowchart illustrating the operation of the DC motor control device according to the second embodiment.
In the following, step S20 to step S44 will be described in the order of steps with reference to FIG.

(Step S20)
The CPU 8 outputs the “Lo” signal of the start / stop signal 12 and the A (Hz) signal that is the CLK signal 13, the drive signal 39 is output by the PWM-DUTY output unit 31, the driver 4 is driven, and the DC The motor 3 is started. In addition, the PWM-DUTY ratio is fixed when the motor is started regardless of the speed / phase difference. Further, if the motor speed of the CLK signal A (Hz) is A ′ (rpm), the relational expression is as follows.
A (Hz) = A ′ (rpm) / 60 × FG pulse number (Pulse)

(Step S21)
The CPU 8 writes a flag write signal 15 “0” in the state storage unit 10.

(Step S22)
The CPU 8 outputs a timer reset signal 14 to the timer 9 to reset the timer count, and then starts the timer count again.

(Step S23)
The CPU 8 reads the timer data signal 16 and compares the read timer value with the reference value t22. t22 is set to a numerical value within the motor acceleration time when the motor rated torque is output at A ′ (rpm) rotation.

(Step S24)
If the timer value is longer than the reference value t22, the CPU 8 determines whether or not the LOCK signal 18 is a “Lo” signal.

(Step S25)
When the CPU 8 determines that the LOCK signal 18 is the “Lo” signal, the rated current detection unit 40 determines whether the voltage comparator 46 outputs the “Lo” signal.
Further, when the CPU 8 determines that the LOCK signal 18 is the “Lo” signal, the CPU 8 determines that the DC motor 3 has been driven at a constant speed, and the DC motor 3 driving method is changed from PWM-DUTY fixed to DUTY based on speed difference / phase difference detection. Switch to a drive system that changes the ratio.

(Step S26)
The CPU 8 writes the flag write signal 15 “1” in the state storage unit 10.

(Step S27)
When the voltage comparator 46 outputs the “Lo” signal in the rated current detection unit 40, the CPU 8 outputs the “Hi” signal of the start / stop signal 12 and decelerates the DC motor 3.

(Step S28)
Next, the CPU 8 outputs the “Lo” signal of the start / stop signal 12 and the CLK signal 13: A (Hz), and outputs the drive signal 39 by the PWM-DUTY output unit 31 to drive the driver 4. Then, the DC motor 3 is restarted.
The DC motor 3 is restarted in consideration of the time until the motor is decelerated and stopped.

(Step S29)
The CPU 8 outputs a timer reset signal 14 to the timer 9 to reset the timer count, and then starts the timer count again.

(Step S30)
The CPU 8 reads the timer data signal 16 and compares the read timer value with the reference value t22.

(Step S31)
If the timer value is longer than the reference value t22, the CPU 8 determines whether or not the LOCK signal 18 is a “Lo” signal. If the LOCK signal 18 is not the “Lo” signal, the process proceeds to step S37. If the LOCK signal 18 is the “Lo” signal, the process proceeds to step S36.

(Step S32)
On the other hand, when the “Lo” signal of the LOCK signal 18 cannot be detected in step S25, the CPU 8 writes the flag write signal 15 “1” in the state storage unit 10.

(Step S33)
The CPU 8 outputs a timer reset signal 14 to the timer 9 to reset the timer count, and then starts the timer count again.

(Step S34)
The CPU 8 reads the timer data signal 16 and compares the read timer value with the reference value t21. t21 is set to a value obtained by subtracting t22 from a numerical value equal to or longer than the motor acceleration time when the rated torque of the DC motor 3 is output.

(Step S35)
If the timer value is longer than the reference value t21, the CPU 8 determines whether the LOCK signal 18 is a “Lo” signal. If it is the “Lo” signal, the process proceeds to step S 36, and the CPU 8 determines whether or not the voltage comparator 46 outputs the “Lo” signal. On the other hand, if it is not the “Lo” signal, the process proceeds to step S43, and the CPU 8 reads the flag data signal 17 “1” written in the state storage unit 10 to confirm the state, and stops the DC motor 3.

(Step S36)
The CPU 8 determines whether or not the voltage comparator 46 outputs a “Lo” signal.

(Step S37)
When the voltage comparator 46 outputs the “Lo” signal in the rated current detector 40, the CPU 8 outputs the “Hi” signal of the start / stop signal 12, starts the motor deceleration, and the DC 8 The motor 3 is stopped.

(Step S38)
Next, the CPU 8 sets the “Lo” signal of the start / stop signal 12 and the CLK signal 13 to A / 2 (Hz), which is the first half speed, and outputs it, and is driven by the PWM-DUTY output unit 31. The signal 39 is output, the driver 4 is driven, and the DC motor 3 is restarted. The restart of the DC motor 3 is executed in consideration of the time from deceleration to stop.

(Step S39)
The CPU 8 outputs a timer reset signal 14 to the timer 9 to reset the timer count, and then starts the timer count again.

(Step S40)
The CPU 8 reads the timer data signal 16 and compares the read timer value with the reference value t23. t23 is set to a value within the motor acceleration time when the rated torque of the DC motor 3 is output during rotation of A ′ / 2 (rpm).

(Step S41)
If the timer value is longer than the reference value t23, the CPU 8 determines whether or not the LOCK signal 18 is a “Lo” signal. If it is the “Lo” signal, the process proceeds to step S42, and the CPU 8 determines whether or not the voltage comparator 46 is outputting the “Lo” signal. On the other hand, if it is not the “Lo” signal, the process proceeds to step S43, and the CPU 8 reads the flag data signal 17 “1” written in the state storage unit 10 to confirm the state, and stops the DC motor 3.

(Step S42)
The CPU 8 determines whether or not the voltage comparator 46 outputs a “Lo” signal.

(Step S43)
When the voltage comparator 46 outputs a “Lo” signal in the rated current detection unit 40, the CPU 8 reads the flag data signal 17 written in the state storage unit 10 in order to confirm the state.

(Step S44)
When the CPU 8 reads the flag data signal 17 “1” written in the state storage unit 10, it outputs the “Hi” signal of the start / stop signal 12, and when the DC motor 3 is decelerated, the DC motor 3 eventually stops. .

As described above, according to the second embodiment, it is detected that the time until the DC motor reaches the predetermined rotation speed exceeds the predetermined time or the energization current to the DC motor at the predetermined rotation speed is greater than the rated current. If it is detected, the motor speed is set to 1/2 and the DC motor is restarted, and it is detected that the time until the DC motor reaches the predetermined rotational speed has exceeded the predetermined time. Or the DC motor is stopped when it is detected that the current flowing to the DC motor at a predetermined rotational speed is equal to or higher than the rated current.
In the second embodiment, it is possible to avoid a DC motor start-up failure (adhesion, sticking, etc.) by retrying at a low speed, and it is possible to detect a load change due to a change with time as in the first embodiment. An overload condition can be suppressed in a short time.

  The motor control unit, driver, position detection unit, speed detection unit, and current detection unit in the DC motor control device of the present invention may be included in a one-chip IC.

It is a block diagram which shows the structure of the DC motor control apparatus of Example 1. FIG. 3 is a circuit block diagram of a motor control unit, a position detection unit, and a speed detection unit according to the first embodiment. FIG. 3 is a circuit block diagram of a rated current detection unit and a maximum current detection unit according to the first embodiment. 3 is a timing chart of a drive signal of a DC motor and an output signal of a hall amplifier according to the first embodiment. 4 is a timing chart of speed control and phase control during constant motor driving according to the first embodiment. 3 is a timing chart of speed control and phase control during motor acceleration driving according to the first embodiment. 4 is a timing chart of speed control and phase control during motor deceleration driving according to the first embodiment. 3 is a flowchart illustrating the operation of the DC motor control device according to the first embodiment. It is a block diagram which shows the structure of the DC motor control apparatus of Example 2. FIG. It is a flowchart which shows operation | movement of the DC motor control apparatus of Example 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC motor control apparatus 2 Control part 3 DC motor 4 Driver 5 Position detection part 6 Speed detection part 7 Current detection part 8 CPU
9 Timer 10 Status memory 11 Motor controller

Claims (2)

A motor drive unit for driving a DC motor;
A speed detector for detecting the rotational speed of the DC motor;
A current detection unit for detecting an output current of the motor drive unit;
Based on the speed detected by the speed detection unit and the output current detected by the current detection unit by driving the motor drive unit,
A DC motor control device comprising: a control unit that controls the motor driving unit. The controller is
A time measuring unit for measuring the time from the start of driving of the DC motor to reaching a predetermined rotational speed;
A determination unit for determining using each value detected by the speed detection unit and the current detection unit,
When the output current of the motor drive unit is a predetermined value or more and the time measured by the time measurement unit is a predetermined time or more,
The DC motor control device according to claim 1, wherein the motor driving unit is controlled to decelerate the DC motor.

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