JP2010028574A - Information processing apparatus, method of controlling the same, and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent disturbance of image or voice caused by underflow of a packet and overflow of a buffer due to overflow in an information processing apparatus for performing high quality picture processing for a packet. <P>SOLUTION: The device includes: a generating means for dividing data including a video and audio, and for generating a packet with a timestamp; one or more processing means for performing a prescribed processing for high quality of data by any one of a plurality of modes of different processing velocities; and a coupling means for reconstituting data by coupling packets which are subjected to the prescribed processing. When a value which is obtained by subtracting a time shown by a timestamp included in an arriving packet from an arrival time of the packet at the coupling means is outside a prescribed range, at least any of the processing means switches a mode and processes a packet which has subsequently arrived at the processing means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, a control method thereof, and a computer program.

  The video processing system needs to synchronize data such as video and audio when outputting video data. In order to enable synchronization between video and audio, MPEG1 and MPEG2 which are international standard encoding schemes add a time stamp which is output timing information in the header of packet data.

  FIG. 10 is an example of a schematic block diagram of the video processing system. The video processing system includes a packet transmission device 1020 and a packet reception device 1040. When the video packet generation circuit 1021 of the packet transmission device 1020 receives video data from the video input device 1010, the video data is packetized and transmitted. At this time, a time stamp is generated based on the time indicated by the system time clock generation circuit 1022 and added to the header of the packet.

  The packet transmitted by the packet transmission device 1020 is received by the packet reception device 1040 via the transmission path 1030. The packet receiving device 1040 restores the video data and transmits it to the video output device 1050 when the time indicated by the system time clock recovery circuit 1042 matches the time indicated by the time stamp in the packet header. The system time clock generation circuit 1022 periodically transmits the system time clock as a packet in order to synchronize with the system time clock recovery circuit 1042. The time from when the packet transmitting apparatus 1020 transmits a packet until the packet receiving apparatus 1040 receives the packet is constant depending on the system. Therefore, the time stamp can be generated based on the system time clock generation circuit 1022.

  In the video processing system described above, a packet processing device for performing image quality enhancement processing of video data may be disposed between the packet transmission device 1020 and the packet reception device 1040. In this case, since the processing time varies depending on the state of the packet processing device, the packet reception device 1040 cannot output the video data at the time indicated by the time stamp, and the video may be disturbed. This phenomenon is called underflow. On the other hand, if the time stamp is set too late, the capacity of the packet to be held by the packet receiving device 1040 increases and the buffer may overflow. This phenomenon is called overflow.

Patent Document 1 proposes an IP telephone terminal device in which the transmission device adjusts the packet transmission interval and the like based on the time when the reception device receives the packet. However, in the case of video data, it is necessary to display frames at regular intervals, so underflow and overflow cannot be prevented simply by adjusting the transmission interval.
JP 2005-217863 A

  An object of the present invention is to prevent video or audio disturbance due to packet underflow or buffer overflow due to overflow in an information processing apparatus that processes packets.

In view of the above problems, an information processing apparatus according to the present invention provides:
Generating means for dividing data including video and audio and generating a packet with a time stamp;
One or more processing means for performing predetermined processing for improving the quality of the data in any one of a plurality of modes having different processing speeds on the packet;
Combining means for combining the packets subjected to the predetermined processing to reconstruct the data;
Each of the packets arrives at the combining unit from the generating unit via at least one of the one or more processing units based on the processing path set by the generating unit,
In a first case where a value obtained by subtracting the time indicated by the time stamp included in the arriving packet from the time when the packet arrived at the combining means is larger than a first threshold, the processing means that has performed the processing At least one of the modes is switched to a mode having a higher processing speed than the current mode, and processing is subsequently performed on packets that arrive at the processing means.
In a second case where the value obtained by subtracting the time indicated by the time stamp included in the arriving packet from the time when the packet arrived at the combining means is smaller than a second threshold, the processing means that has performed the processing At least one of the above is characterized in that the mode is switched to a mode having a slower processing speed than the current mode, and processing is performed on packets that have arrived at the processing means thereafter.

  According to the present invention, it is possible to prevent video or audio disturbance due to underflow and buffer overflow due to overflow. This makes it possible to efficiently use hardware resources such as the buffer size.

  Embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>
An information processing apparatus 100 according to the present invention will be described with reference to FIG. FIG. 1 is a diagram illustrating an example of a functional block diagram of the information processing apparatus 100 according to the present embodiment. The information processing apparatus 100 includes a generation unit 110, processing units 120 to 122, and a combining unit 130. Although the present embodiment deals with a case where the three processing units 120 to 122 are provided, any number of processing units may be used as long as the number is one or more. In addition, the generation unit 110, the processing units 120 to 122, and the combining unit 130 may each be configured as a single device.

  The generation unit 110 includes a video acquisition unit 111, a tile division unit 112, a processing determination unit 113, and a packetization unit 114, and divides data including video and audio into packets and transmits the packets to the processing unit 120. Hereinafter, the case where the data is video data will be mainly described, but the present invention can be similarly applied to the case where the data is audio data. The video acquisition unit 111 acquires video data. Video data may be acquired via a network or may be acquired from a recording medium. Moreover, you may acquire the video data which the other structural element not shown of the information processing apparatus 100 produced | generated. The video acquisition unit 111 outputs the acquired video data to the tile division unit 112 and the process determination unit 113.

  The tile dividing unit 112 divides each frame of the input video data into video tiles and outputs the video tiles to the packetizing unit 114. In this embodiment, an example in which each frame is divided into video tiles of 8 pixels × 128 pixels is handled, but the present invention is not limited to this size. The processing determining unit 113 determines the path of the processing unit that performs packet processing and the processing mode of the video data by each processing unit based on the input video data. In the present embodiment, it is assumed that the packet is processed through the processing path of the processing unit 120, the processing unit 121, and the processing unit 122. The processing mode will be described later.

  The packetizing unit 114 transmits the packet to the processing unit 120 based on the inputs from the tile dividing unit 112 and the processing determining unit 113. The packet to be transmitted may be a command packet for transmitting a command to the processing units 120 to 122 or a video tile packet for transmitting a video tile. Details of the packet will be described later. The packet includes the time when the video display unit 134 included in the combining unit 130 should display the frame including the video tile as a time stamp. The “time” in the present embodiment includes not only the actual time but also those having a time measuring function such as a clock cycle of the information processing apparatus 100.

  The processing unit 120 performs predetermined processing on the received packet. The processing performed here includes, for example, high-resolution conversion, error correction, sharpness conversion, and progressive conversion for improving the image quality of the video data. In the case of audio data, there are error correction, SBR (Spectal Band Replication), and the like. The present invention is not limited to the processing for improving the quality, and any processing can be applied as long as the processing has a plurality of modes with different processing speeds. In the present embodiment, the image quality enhancement processing will be described below as a representative example. The processing unit 120 has a plurality of modes for processing a packet with high image quality. It is assumed that a longer processing time is required for a mode in which video data has a higher image quality. In this embodiment, a case where the processing unit has two types of modes of “high quality” and “high speed” is handled, but the number of modes is not limited to two. Here, it is assumed that the “high image quality” mode requires a longer processing time than the “high speed” mode. The processing unit 120 can also transfer the packet as it is without performing the image quality enhancement process. As a matter of course, when the packet is transferred as it is, the time from when the processing unit 120 receives the packet to when the packet is transmitted is shorter than when the image quality enhancement process is performed. Since the processing units 121 and 122 are the same as the processing unit 120, description thereof is omitted. In the following description, the description of the processing unit 120 also applies to the processing units 121 and 122 unless explicitly mentioned. The processing unit that has finished the image quality enhancement process transmits the packet to the next processing unit or combining unit 130 according to the route determined by the processing determination unit 113.

  The combination unit 130 includes a header analysis unit 131, a tile combination unit 132, a time difference detection unit 133, and a video display unit 134. The combination unit 130 combines received packets to reconstruct and display a frame. The header analysis unit 131 analyzes the header of the packet received from the processing unit 122. If the received packet is a command packet as a result of analyzing the header, the packet is discarded without any processing. When the packet is a video tile packet, the packet is separated into a header and a video tile, the video tile is output to the tile combining unit 132, and the header is output to the time difference detection unit 133. The tile combining unit combines the received video tiles to restore the frame, and outputs the frame to the video display unit 134. The video display unit 134 displays the output frame according to a designated time stamp. The time difference detection unit 133 detects a difference between the time indicated by the time stamp specified in the packet and the time actually received by the combining unit 130. If this difference is not within the range defined in advance, the processing determining unit 113 is notified that it is not within the range. The detected time difference may also be transmitted along with this notification.

  FIG. 2 is an example of a block diagram illustrating a hardware configuration of the information processing apparatus 100. FIG. 2 shows a minimum configuration for realizing the configuration of the information processing apparatus 100 corresponding to the embodiment of the present invention, and other mechanisms related to the information processing apparatus 100 are described for simplicity. Is omitted.

  A CPU 201 that is a microprocessor controls the information processing apparatus 100 based on programs, data, and the like stored in a storage medium set in the ROM 203, hard disk (HD) 212, and external memory drive 211.

  The RAM 202 functions as a work area for the CPU 201 and holds programs stored in the ROM 203, the HD 212, and the like.

  The storage medium set in the ROM 203 and the external memory drive 211 or the HD 212 stores a program executed by the CPU 201 as shown in a flowchart to be described later. Moreover, the video data to be processed may be stored.

  A keyboard controller (KBC) 205 controls input from a keyboard (KB) 209 or a pointing device such as a mouse (not shown). A display controller (DPC) 206 controls display on the display 210. The display 210 functions as the video display unit 134 shown in FIG. A disk controller (DKC) 207 controls access to the HD 212 and the external memory drive 211, and reads and writes various programs and various data such as font data, user files, and edit files to and from these storage media. A network controller (NC) 208 performs communication with the network 220. The video data to be processed may be acquired via the network 220.

  The CPU 201 executes, for example, a display information area allocated on the RAM 202 or an outline font development (rasterization) process to a dedicated video memory (VRAM), and enables display on the display 210. Further, the CPU 201 opens various registered windows based on commands instructed by a mouse cursor or the like on the display 210 and executes various data processing.

  Subsequently, a packet format in the present embodiment will be described with reference to FIGS. 3 to 5. As described above, the information processing apparatus 100 according to the present invention transmits video tiles and commands using packets. There are two types of packets 300, the command packet 400 shown in FIG. 4 and the video tile packet 500 shown in FIG. 5. Both packets include the common header 301 shown in FIG.

  First, the format of the header 301 will be described with reference to FIG. FIG. 3 is a diagram for explaining an example of the configuration of the header 301 included in the packet 300. The packet 300 includes a header 301 and a payload 302.

  A packet path 310 represents a path through which the processing units 120 to 122 process the packet 300. First, the packetizing unit 114 designates a pair of a port and an index of a processing unit that wants to process the packet 300 first as a port 0 and an index 0 of the packet path 310. Here, the port 311 is an input port number of the processing unit, which uniquely identifies the processing unit. The index 312 is a static parameter number to be used by the processing unit. In the present embodiment, the processing unit 120 corresponds to this. Next, the packetizing unit 114 designates a pair of a port and an index of a processing unit that wants to process the packet 300 secondly as a port 1 and an index 1 of the packet path 310, respectively. In the present embodiment, the processing unit 121 corresponds to this. Since the same is true for the following port and index pairs, the description thereof will be omitted. As described above, the packetizing unit 114 specifies a pair of a port and an index in a left-justified manner in the order of processing units to be processed. After processing the packet 300, the processing unit that has received the packet shifts the packet path 310 to the left by 8 bits. As a result, the set of the port and index of the processing unit that should process the packet 300 next moves to the head of the packet path 310. Based on the first set, the processing unit transmits the packet 300 to the processing unit that should process the packet 300 next. When the subsequent processing unit set is not designated, the packet 300 is transmitted to the combining unit 130. The packet path 310 stores 15 sets of the port 311 and the index 312.

  The time stamp 313 represents the time when the video display unit 134 starts to display a frame including the image tile data included in the packet 300. This field has a meaning when the packet 300 is a video tile packet, and has no meaning when it is a command packet. The AV packet end 314 indicates that the video tile packet 500 included in one frame ends with this packet. The packet number 315 represents a packet number in the frame. The tile combination unit 132 restores the frame from the video tile based on the packet number 315. The packet number 315 is 0 in the first video tile of the frame, and is incremented by 1 in the subsequent video tiles. Type 316 indicates whether the packet 300 is a command packet 400 or a video tile packet 500. The payload length 317 represents the number of bytes of the payload.

  FIG. 4 is a diagram for explaining an example of the configuration of the command packet 400. When receiving the command packet 400, the processing units 120 to 122 access the register according to the description of the payload 302. The command packet 400 performs register access to the processing units 120 to 122 that process the video tile packet 500. The processing mode is set by changing the register setting. Hereinafter, information included in the payload 302 will be described. The unit ID 401 indicates the ID of the target processing units 120 to 122. The processing units 120 to 122 that have received the command packet 400 compare the unit ID 401 with the ID of the processing unit 120 to 122 to determine whether the command is a command for itself. The register number 402 indicates the number of the register to be changed. A storage address 403 indicates a storage location of read data when register reading of the target processing unit is performed. A command 404 indicates an instruction to the target processing units 120 to 122. There are two types of commands 404, write and read. A data field 405 indicates data used by the command 404.

  FIG. 5 is a diagram for explaining an example of the configuration of the video tile packet 500. When receiving the video tile packet 500, the combining unit 130 processes the video tile included in the payload 302. The payload 302 has a data amount of 8 Kbytes and stores data of 1024 pixels corresponding to an image tile of 8 pixels × 128 pixels. The data amount of one pixel is 8 bytes, and is composed of RGB data expressed in 16 bits, 8-bit α data, and 8-bit Z data.

  Next, the operation of the information processing apparatus 100 according to this embodiment will be described with reference to FIG. FIG. 6 is a flowchart for explaining an example of the operation of the information processing apparatus 100. This flowchart is processed by the CPU 201 executing the computer program stored in the ROM 203.

  In step S <b> 601, the video acquisition unit 111 acquires video data and outputs the video data to the tile division unit 112 and the process determination unit 113.

  In step S <b> 602, the process determining unit 113 determines the route of the processing units 120 to 122 that process the image quality enhancement of the packet and the processing mode in each processing unit, and outputs the contents to the packetizing unit 114. In the present embodiment, packet quality enhancement processing is performed in the order of the processing unit 120, the processing unit 121, and the processing unit 122. Further, the processing mode is set to the “high speed” mode in all processing units as an initial state.

  In step S603, the packetizing unit 114 creates a packet 300 based on the input information and transmits the packet 300 to the processing unit. The packetizing unit 114 generates a command packet 400 that has a setting specified by the processing determining unit 113 of each processing unit, and transmits the command packet 400 to each processing unit. Since command packet 400 has been described with reference to FIG. 4, description thereof will not be repeated. Note that the initial mode of each processing unit may not be set by the command packet 400 as described above, but may be set as a default value when the processing unit is activated.

  In step S604, the packetizing unit 114 determines a time stamp that is a time at which the video display unit 134 displays the processing target frame.

  In step S <b> 605, the packetizing unit 114 transmits the video tile packet 500 in which the above-described tile stamp is added to the video tile divided by the tile dividing unit 112 to the processing unit 120. Since the details of the video tile packet 500 have been described with reference to FIG.

  In step S606, each processing unit performs image quality enhancement processing on the received packet in the set mode, and transmits the packet to the next processing unit or combining unit 130. Step S606 is processed in all the processing units on the route determined by the processing determination unit 113.

  In step S <b> 607, when the received packet is the video tile packet 500, the header analysis unit 131 outputs the header 301 to the time difference detection unit 133 and outputs the payload 302 to the tile combination unit 132. The time difference detection unit 133 calculates a value obtained by subtracting the time stamp included in the header 301 from the time when the combining unit 130 receives the packet.

  In step S608, the time difference detection unit 133 determines whether the calculated value is within a specified range. If it is within the range (“YES” in step S608), the process proceeds to step S611, and if it is not within the range (“NO” in step S608), the process proceeds to step S609. In this case, the calculated value is equal to or less than the upper limit value, which is the first threshold value, and is equal to or greater than the lower limit value, which is the second threshold value. It is defined in advance based on the time required for frame restoration and the size of the buffer that holds the video tiles, and the upper limit value and the lower limit value are dynamically changed by the combining unit 130 according to the state of the information processing apparatus 100. If the calculated difference is larger than the upper limit value (first case), it means that the packet arrived at the combining unit 130 earlier than the specified time, whereas the calculated difference is the lower limit value. In the case remote small (the second case), so that the packet arrived late binding portion 130 than the time as defined.

  In step S609, the time difference detection unit 133 notifies the processing determination unit 113 that the calculated difference is not within the specified range. In accordance with this notification, the calculated difference may be transmitted. The processing determination unit 113 changes the processing content and the route of each processing unit based on the received content.

  The processing contents and route change of each processing unit will be described with reference to FIGS. FIG. 7 is a diagram for explaining an example of processing mode transition. Since the initial processing mode of each processing unit in this embodiment is the “high speed” mode, the image quality level is 3. Here, in the first case described above, since the packet arrives at the combining unit 130 earlier than the time defined by the packet, it is necessary to lengthen the processing time required by the processing unit. Therefore, the processing mode of the processing unit 122 is changed from the current “high speed” to “high image quality”. By changing in this way, the image tile can be further improved in image quality and the processing speed can be lowered. On the other hand, in the second case described above, since the packet arrives at the combining unit 130 later than the time defined by the packet, it is necessary to shorten the processing time required by the processing unit. Therefore, the processing unit 120 does not perform processing. This state is represented by “OFF” in FIG. By changing in this way, although the image quality of the video tile is lowered, the processing speed can be increased. The image quality level may be changed step by step, or may be changed with different widths based on the calculated difference. For example, when the calculated difference exceeds the upper limit value beyond a certain value, the setting of each processing unit is changed to increase the image quality level by two levels.

  Instead of changing the processing unit 120 to “OFF”, the processing path may be changed. This will be described with reference to FIG. FIG. 8 is a diagram for explaining another example of the transition of the processing mode. At image quality level 3, image quality enhancement processing is performed through the route of the processing unit 120, processing unit 121, and processing unit 122. In order to increase the processing speed from this image quality level, the path is changed to the processing unit 121 and the processing unit 122. That is, the processing speed is increased by changing to a route that does not pass through the processing unit 120.

  Further, the transition of the processing mode is not limited to this example. FIG. 9 is a diagram for explaining still another example of processing mode transition. In this example, the processing unit 122, the processing unit 121, and the processing unit 120 are set in such an order that the image quality enhancement processing is preferentially performed. Hereinafter, a case where the image quality level is lowered will be described, but the same applies to a case where the image quality level is raised. From the image quality level 0 to the image quality level 2, the processing mode of the processing unit 120 is lowered while maintaining the mode of the processing unit 121 and the processing unit 122 at “high image quality”. Subsequently, when the processing mode of the processing unit 120 can no longer be lowered, the processing mode of the processing unit 121 is changed from the image quality level 3 to the image quality level 4 while keeping the mode of the processing unit 122 at “high image quality”. Reduce. Finally, when the processing mode of the processing unit 121 can no longer be lowered, the processing mode of the processing unit 121 is lowered from the image quality level 5 to the image quality level 6. In this way, it is possible to specify a processing unit for which priority is given to image quality enhancement processing.

  The transition of the processing mode is not limited to the examples of FIGS. 7 to 9, and the priority may be defined in more detail for each mode of each processing unit.

  Returning to FIG. 6, the description of the flowchart will be continued. In step S610, the packetizing unit 114 generates a command packet 400 based on the contents changed by the processing determining unit 113 and transmits the command packet 400 to each processing unit. The processing unit that has received the command packet 400 changes the processing mode according to the content of the command. Alternatively, the packetizing unit 114 changes the packet route 310 of the header 301 attached to the subsequent video tile packet 500 in order to change the route based on the change contents by the processing determining unit 113 described above.

  In step S611, when the received video tiles are accumulated for one frame, the tile combination unit 132 restores the frames and displays them on the video display unit 134 at the time designated by the time stamp 313.

  In step S612, the packetizer 114 determines whether or not the video tile packet 500 for one frame has been transmitted to the receiver. If not transmitted (“NO” in step S612), the process returns to step S605, and a new video tile packet 500 is generated and transmitted. If transmitted (“YES” in step S612), the process proceeds to step S613.

  In step S613, the packetizing unit 114 determines whether all frames of the video data have been transmitted. If there is an untransmitted frame (“NO” in step S613), the process returns to step S604, and the time stamp 313 used for the next frame is determined. If all the frames have been transmitted (“YES” in step S613), the process ends after the video display unit 134 finishes displaying all the frames.

  As described above, in the present embodiment, the time at which the video tile packet 500 arrives at the combining unit 130 can be adjusted. Therefore, it is possible to prevent video or audio disturbance due to underflow and buffer overflow due to overflow.

<Other embodiments>
Note that the present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, and a printer), and a device (for example, a copying machine and a facsimile device) including a single device. You may apply to.

  The object of the present invention can also be achieved by supplying, to a system, a storage medium that records the code of a computer program that realizes the functions described above, and the system reads and executes the code of the computer program. In this case, the computer program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the computer program code constitutes the present invention. In addition, the operating system (OS) running on the computer performs part or all of the actual processing based on the code instruction of the program, and the above-described functions are realized by the processing. .

  Furthermore, you may implement | achieve with the following forms. That is, the computer program code read from the storage medium is written in a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer. Then, based on the instruction of the code of the computer program, the above-described functions may be realized by performing a part or all of the actual processing by the CPU or the like provided in the function expansion card or function expansion unit.

  When the present invention is applied to the above-described storage medium, the computer program code corresponding to the flowchart described above is stored in the storage medium.

It is a figure explaining an example of the functional block diagram of the information processing apparatus 100 in embodiment of this invention. It is an example of the block diagram which shows the hardware constitutions of the information processing apparatus 100 in embodiment of this invention. It is a figure explaining an example of composition of header 301 with which packet 300 in an embodiment of the present invention is provided. It is a figure explaining an example of composition of command packet 400 in an embodiment of the present invention. It is a figure explaining an example of a structure of the video tile packet 500 in embodiment of this invention. It is a flowchart explaining an example of operation | movement of the information processing apparatus 100 in embodiment of this invention. It is a figure explaining an example of transition of the processing mode in the embodiment of the present invention. It is a figure explaining another example of transition of the processing mode in the embodiment of the present invention. It is a figure explaining another example of transition of a processing mode in an embodiment of the present invention. 1 is an example of a schematic block diagram of a video processing system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Information processing apparatus 110 Generation part 111 Image | video acquisition part 112 Tile division part 113 Processing determination part 114 Packetization part 120 Processing part 121 Processing part 122 Processing part 130 Combining part 131 Header analysis part 132 Tile combining part 133 Time difference detection part 134 Part

Claims (8)

Generating means for dividing data including video and audio and generating a packet with a time stamp;
One or more processing means for performing predetermined processing for improving the quality of the data in any one of a plurality of modes having different processing speeds on the packet;
Combining means for combining the packets subjected to the predetermined processing to reconstruct the data;
Each of the packets arrives at the combining unit from the generating unit via at least one of the one or more processing units based on the processing path set by the generating unit,
In a first case where a value obtained by subtracting the time indicated by the time stamp included in the arriving packet from the time when the packet arrived at the combining means is larger than a first threshold, the processing means that has performed the processing At least one of them switches the mode to a mode having a higher processing speed than the current mode, and subsequently processes packets that arrive at the processing means,
In a second case where the value obtained by subtracting the time indicated by the time stamp included in the arriving packet from the time when the packet arrived at the combining means is smaller than a second threshold, the processing means that has performed the processing At least one of the information processing apparatuses is characterized in that the mode is switched to a mode having a slower processing speed than the current mode, and processing is performed on a packet that has arrived at the processing means thereafter. Priorities for the processing are defined for the processing means, respectively.
Among the processing means capable of switching to a mode having a higher processing speed than the current mode in the first case, the processing means having the lowest priority performs the switching,
The processing unit having the highest priority among the processing units capable of switching to a mode having a slower processing speed than the current mode in the second case performs the switching. The information processing apparatus described.   The information processing apparatus according to claim 1, wherein the processing unit transfers the packet without performing the predetermined processing in a mode in which the processing speed is the fastest.   2. The method according to claim 1, wherein, in the first case, the generation unit changes to a processing path excluding at least one of the processing units that have performed the processing on the packet that has arrived at the combining unit. 4. The information processing apparatus according to any one of 3.   The switching of the processing mode is performed based on a packet generated by the generation unit and including a command for causing the processing unit to switch the mode. Information processing device.   6. The predetermined process includes any one of high resolution conversion, error correction, sharpness conversion, and progressive conversion for improving the image quality of the data. Information processing device. A generating step of generating data by dividing the data including video and audio and attaching a time stamp;
A processing step in which one or more processing means performs predetermined processing for improving the quality of the data in any one of a plurality of modes having different processing speeds on the packet;
A combining unit, which combines the packets subjected to the predetermined processing to reconstruct the data;
In the combining step, when the value obtained by subtracting the time indicated by the time stamp included in the arrived packet from the time when the packet arrived is larger than a first threshold, the mode is set in the processing step. Switch to a mode that has a faster processing speed than the current mode, process the packets that arrive after that,
In the combining step, in the second case where the value obtained by subtracting the time indicated by the time stamp included in the arrived packet from the arrival time of the packet is smaller than a second threshold, the mode is set in the processing step. A control method for an information processing apparatus, wherein the mode is switched to a mode having a slower processing speed than the current mode, and processing is performed on packets that arrive thereafter.   A computer program that causes a computer to function as the information processing apparatus according to claim 1.