JP2010021482A - Semiconductor device, thin film transistor substrate, display, and mobile device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having new-structure transistors enabling resistance values of diffusion layers of two transistors formed on the same insulating substrate to be equal. <P>SOLUTION: The first transistor (left in the figure) includes a first insulating film 303a formed under a first gate electrode 304a, and a second insulating film 303b formed on diffusion layer regions 302a2 and 302a3. A first gate electrode 304a is located in an upper portion over the first insulating film 303a and the second insulating film 303b. The first insulating film 303a is thinner than the second insulating film 303b. The second insulating film 303b of the first transistor is formed from an edge of the lower surface of the first gate electrode 304a to the inside thereof. The diffusion layer regions 302a2 and 302a3 are formed to overlap under the first insulating film 303a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a TFT substrate including the semiconductor device, a display device using the TFT substrate (a liquid crystal display, an organic EL display, etc.), and a mobile device (notebook personal computer, mobile phone, Portable information terminal).

  Usually, in the semiconductor device process, activation is performed at a high temperature of 800 ° C. or higher. However, in the case of a liquid crystal display device, since a glass plate is used as a substrate, it can be heated only up to a temperature of about 600 ° C., and it is necessary to activate a silicon layer at a lower temperature than that of a semiconductor device.

  When activation is performed at a low temperature, a region serving as a nucleus of recrystallization is required in order for activation to occur within a realistic time as a process. For this reason, it is important to control the profile of ion implantation (ion implantation) so that nuclei remain at the bottom of the source region and drain region into which ions are implanted (ions are implanted).

  However, this implantation profile greatly depends on the thickness of the insulating film formed on the semiconductor layer through which ions pass. For this reason, JP-A-11-97696 discloses a method as described below. The method will be described below with reference to FIG.

  First, a semiconductor layer 1814 made of polysilicon is formed in a groove 1812 formed on the surface of the insulating substrate 1810. The groove 1812 includes a first portion 1812a in which a channel region 1814a is formed, and a second portion 1812b in which a source region 1814b and a drain region 1814c are formed, and the second portion 1812b is formed deeper than the first portion 1812a. Has been. On the other hand, the upper surface of the entire semiconductor layer 1814 is located on the same plane as the surface of the insulating substrate 1810.

  In this way, by increasing the thickness of the semiconductor layer of only the source region and the drain region into which ions are implanted, it is possible to easily create a region in which nuclei for recrystallization remain at the bottom of the semiconductor layer. Therefore, even when the thickness of the insulating film on the semiconductor layer changes slightly, it is possible to prevent defective activation of the silicon layer after ion implantation, thereby suppressing fluctuations in the resistance value of the diffusion layer. Yes.

Incidentally, a gate insulating film 1816 is formed on the surfaces of the semiconductor layer 1814 and the insulating substrate 1810, and a gate electrode 1818 is formed on the gate insulating film 1816 so as to face the channel region 1814a. An interlayer insulating film 1820 is formed over the gate electrode 1818. Over the interlayer insulating film 1820, a source electrode 1822 and a drain electrode 1824 are formed to face the source region 1814b and the drain region 1814c, respectively. The source electrode 1822 and the drain electrode 1824 are connected to the source region 1814b and the drain region 1814c through contact holes 1826 and 1827, respectively. The drain electrode 1824 is connected to the pixel electrode 1828 made of ITO formed on the interlayer insulating film 1820 and has a structure in which a passivation 1830 is formed so as to cover the source electrode 1822 and the drain electrode 1824. .
JP-A-11-97696

  As described above, in the process of embedding polysilicon in the insulating substrate described above, it is possible to prevent a defective activation because a nucleus for recrystallization can be left by changing the thickness of the insulating film on the semiconductor layer. . However, it is inevitable that the amount of ion implantation changes due to a change in the implantation profile. For this reason, the resistance value of the diffusion layer varies depending on the thickness of the insulating film on the diffusion layer region.

That is, when two TFTs having different thicknesses of insulating films on a semiconductor layer are formed on the same substrate, if ion implantation is performed, ions are implanted into the semiconductor layer due to the influence of insulating films having different thicknesses. The amount is different. For this reason, the resistance value of the diffusion layer varies depending on the thickness of the insulating film.
In order to prevent this change in the resistance value of the diffusion layer, it is necessary to perform ion implantation separately for each transistor having a different insulating film thickness when performing ion implantation, which increases the number of ion implantation steps. It was.

  The present invention was devised to solve such problems, and its purpose is to mount a transistor with a new structure that can make the resistance values of the diffusion layers of two transistors formed on the same insulating substrate the same. An object of the present invention is to provide a semiconductor device, a TFT substrate including the semiconductor device, a display device using the TFT substrate, and a portable device equipped with the display device.

  In order to solve the above problems, a semiconductor device according to the present invention is a semiconductor device in which a first transistor and a second transistor are formed on the same insulating substrate, and the first transistor is formed below the first gate electrode. A second insulating film formed on the diffusion layer region, and the second transistor is formed on the lower part of the second gate electrode and on the diffusion layer region. The first and second gate electrodes are disposed above the first insulating film and the second insulating film, respectively, and the first insulating film is the second insulating film. It is formed thinner than the insulating film. In this case, the second insulating film of the first transistor is formed so as to penetrate from the lower surface edge of the first gate electrode to the inside, and the diffusion layer region of the first transistor is formed of the first transistor. Overlapping to the bottom of the insulating film is formed.

  As described above, in the first and second transistors having different insulating film thicknesses below the gate electrode, by adopting a structure in which the insulating film thickness on the diffusion layer region is made the same, the implantation profile and the ion implantation are performed. The same amount. For this reason, the resistance values of the diffusion layers of the first and second transistors can be made the same by one ion implantation without ion implantation for each transistor. Therefore, an increase in manufacturing cost such as an increase in the ion implantation process can be suppressed. In addition, since the first transistor has a thinner insulating film under the gate electrode than the second transistor, a structure suitable for driving at a lower voltage than that of the second transistor can be obtained.

  In addition, by adopting a structure in which the thick second insulating film is overlapped to the bottom of the gate electrode, even if the gate electrode formed after forming the first and second insulating films is misaligned, the first It is possible to suppress the thin first insulating film from protruding from the lower part of the gate electrode.

  Further, the diffusion layer region of the first transistor is formed so as to overlap below the first insulating film. That is, the diffusion layer overlaps below the thin first insulating film. Since the diffusion layer is formed under the thick second insulating film region, the inversion layer may be formed only under the thin first insulating film region. Therefore, by applying the gate voltage, it is possible to easily connect the source and the drain with the inversion layer. In addition, since a part of the diffusion layer overlaps even under the thin first insulating film, the charge for forming the inversion layer can be supplied smoothly, so that the inversion layer can be formed efficiently. Can do. Therefore, a large amount of on-state current can be supplied to the transistor. That is, it is possible to prevent the diffusion layer from being offset from the gate electrode.

  In the semiconductor device of the present invention, the first and second transistors are formed on the same insulating substrate. The first transistor is formed on the lower portion of the first gate electrode and the diffusion layer region. The second transistor includes a second insulating film formed below the second gate electrode and the first insulating film formed on the diffusion layer region. The first and second gate electrodes are disposed above the first insulating film and the second insulating film, respectively, and the first insulating film is thinner than the second insulating film. Is formed. In this case, the second insulating film of the second transistor is formed to extend from the lower surface edge of the second gate electrode to the diffusion layer region, and the diffusion layer region of the second transistor is The second gate electrode overlaps with the second gate electrode.

  As described above, in the first and second transistors having different insulating film thicknesses below the gate electrode, by adopting a structure in which the insulating film thickness on the diffusion layer region is made the same, the implantation profile and the ion implantation are performed. The same amount. For this reason, the resistance values of the diffusion layers of the first and second transistors can be made the same by one ion implantation without ion implantation for each transistor. Therefore, an increase in manufacturing cost such as an increase in the ion implantation process can be suppressed. Further, since the insulating film under the gate electrode is thicker than that of the first transistor, the second transistor can have a structure suitable for driving with a higher voltage than the first transistor.

  In addition, since the thick second insulating film overlaps the diffusion layer region, even if the gate electrode formed after forming the first and second insulating films is misaligned, the thick first insulating film is overlapped. It is possible to suppress the second gate electrode from protruding from above the second insulating film.

  Further, the diffusion layer region of the second transistor is formed so as to overlap below the second gate electrode. This overlap width is, for example, about 10 nm. However, since there is no region that needs to be covered by the overlap, a small width is sufficient, and the above 10 nm or less is also possible. There is no limit to the lower limit value, and it may be 1 nm, for example. With such a structure, since the charge for forming the inversion layer under the gate electrode is supplied through the overlap portion, the inversion layer can be easily formed. Therefore, a large amount of on-state current can be supplied to the transistor. That is, it is possible to prevent the diffusion layer from being offset from the gate electrode.

  According to the semiconductor device of the present invention, the diffusion layer region of the first transistor is formed in the low concentration diffusion layer region and the high concentration diffusion layer region, and the low concentration diffusion region is formed on the gate electrode side. It is good also as the structure made.

  When the junction between the channel region and the diffusion layer is steep (for example, in the case of a junction composed of a high-concentration diffusion layer region and a channel region), if current is passed through the junction, carriers are accelerated and flow. , Hot carriers are likely to occur. When the generation of hot carriers increases, the hot carriers collide with the gate insulating film to generate defects. For this reason, the connection between the channel region and the diffusion layer region is preferably a connection through the low concentration diffusion layer region. When bonding is performed in this manner, the bonding becomes loose, generation of hot carriers can be suppressed, damage to the gate insulating film can be suppressed, and deterioration of the transistor can be prevented as a result.

  Further, according to the semiconductor device of the present invention, the diffusion layer region of the first transistor is formed in the low concentration diffusion layer region and the high concentration diffusion layer region, and in the region of the diffusion layer region, on the upper side. A region having a gate electrode is defined as the low concentration diffusion layer region. As described above, the diffusion layer region has a diffusion layer structure in which a portion under the gate electrode is a low concentration diffusion region and a portion having no gate electrode on the upper portion is a high concentration diffusion layer region. The concentration diffusion layer region can be easily formed. That is, the low concentration diffusion layer region is formed before the gate electrode is formed, the gate electrode is formed on the low concentration diffusion layer region, and the high concentration diffusion layer region is increased in a self-aligned manner by implantation using the gate electrode as a mask. A boundary between the concentration diffusion layer region and the low concentration diffusion layer region can be formed.

  Further, the diffusion layer region of the second transistor is formed in a low concentration diffusion layer region and a high concentration diffusion layer region, and a region having the second insulating film on the upper side in the region of the diffusion layer region. The low concentration diffusion layer region is used. In this way, the diffusion layer structure has a high-concentration diffusion layer region where the insulating film is thin and a low-concentration diffusion region region where the insulating film is thick. The layer region can be easily formed. In other words, by utilizing the characteristic that the resistance of the diffusion layer changes depending on the thickness of the insulating film, and by setting the implantation profile so that many ions are implanted under the thin insulating film, Less ion implantation. Therefore, a low-concentration diffusion layer in the diffusion layer region is formed on the gate electrode side (under the thick insulating film) in a self-aligned manner, and the low-concentration diffusion layer region and the high-concentration diffusion layer region are separately formed according to the insulating film thickness. It is done. Further, the boundary can be set at the same position as the boundary between the thin insulating film and the thick insulating film.

  According to the semiconductor device of the present invention, the lower surface of the connecting portion between the first insulating film and the second insulating film may be connected flat.

  In this way, since there is no step or inclination on the lower surface of the connecting portion of the insulating film, the diffusion layer, inversion layer, or accumulation layer formed under the insulating film is flattened. In this case, it is possible to suppress electric charge scattering and to allow a current to flow smoothly.

  According to the semiconductor device of the present invention, the inclination angle of the connection portion between the first insulating film and the second insulating film with respect to the substrate surface is set to any angle within the range of 5 degrees to 50 degrees. That's fine.

  In this way, when an electrode is formed on the insulating film by adopting a structure in which the inclination angle with respect to the substrate surface of the connection part of the insulating film having different thicknesses is 50 degrees or less, the insulating film angle is reduced. It is possible to alleviate the electric field concentration on the portion and suppress the breakdown of the insulating film. Moreover, it can suppress that the area of an inclination part becomes large by making an inclination-angle into 5 degree | times or more.

  According to the semiconductor device of the present invention, the first and second insulating films include a silicon oxide film, and one or both of the insulating films further include a silicon nitride film layer. Good. As described above, since the insulating film includes the silicon nitride film layer having a higher dielectric constant than the silicon oxide film, the electric field of the gate electrode can be efficiently applied to the channel region.

  Further, according to the semiconductor device of the present invention, the silicon oxide film may be formed above and below the silicon nitride film. In this way, by sandwiching a silicon nitride film having a relatively large number of levels in the film or at the interface with the silicon oxide film, unnecessary charges enter from above and below by electrolysis and are captured by the silicon nitride film or the interface. Can be suppressed.

  Further, according to the semiconductor device of the present invention, one of the first and second insulating films may be formed with a thin EOT (equivalent oxide film thickness). Thereby, a transistor with a thin EOT can be used as a low-voltage driving transistor.

  Moreover, according to the semiconductor device of the present invention, the transistor may be used as a memory. That is, since charges can be intentionally injected and captured in a silicon nitride film having many levels, this phenomenon can be used as a memory.

  According to the semiconductor device of the present invention, the wiring for fixing the potential of the channel region of the transistor or the potential of the channel region of the transistor is fixed to one diffusion layer region formed in the transistor. It may be a body contact region that contacts from the wiring. That is, since the diffusion layer with reduced manufacturing cost can be applied in the region where wiring or contact is made, the manufacturing cost can be reduced. The body contact region is an N-type diffusion layer. The N-type diffusion layer is formed using a large element having an atomic weight of 30 or more, such as phosphorus, arsenic, and antimony. Such a large element that forms an N-type diffusion layer has a very high probability of destroying the crystal of the semiconductor layer when ion implantation is performed, and it is likely to cause activation failure, so that it is difficult to control the resistance value. . Therefore, when the diffusion layer is N-type, the change in resistance can be effectively suppressed by adopting the transistor structure. The diffusion layer regions of the transistor are a source region and a drain region. That is, the manufacturing cost can be suppressed by applying the diffusion layer whose manufacturing cost is reduced in the source region and the drain region. Further, the transistor is an N-type transistor. The N-type diffusion layer constituting the N-type transistor is formed using a large element having an atomic weight of 30 or more, such as phosphorus, arsenic, and antimony. It is difficult to control the resistance value of such a large element that forms an N-type diffusion layer because it is very likely to destroy the crystal of the semiconductor layer when ion implantation is performed and it is highly likely to cause activation failure. . Therefore, when the diffusion layer is N-type, the change in resistance can be effectively suppressed by adopting the transistor structure.

  The TFT substrate of the present invention has a configuration in which the transistors of the semiconductor devices having the above-described configurations are arranged in an array. Thereby, a memory function can be given to the TFT substrate. It is also possible to mount a circuit using low voltage transistors.

  Further, the display device of the present invention has a configuration including the TFT substrate having the above configuration. Thereby, a display device such as a liquid crystal display can have a memory function. Further, since a circuit using low voltage transistors can be mounted together, power consumption can be reduced.

  Further, the display device of the present invention may be configured such that the voltage correction value and the display gamma correction value of the TFT counter substrate are stored in the memory in the configuration including the TFT substrate having the above configuration. As described above, by storing the correction value unique to the display device, the number of components of the memory of the liquid crystal display can be reduced.

  Further, the portable device of the present invention is configured to include the display device having the above configuration. That is, since the display device has a reduced number of parts, a space-saving (slim) portable device can be manufactured.

  According to the present invention, in the first and second transistors having different thicknesses of the insulating film under the gate electrode, by adopting a structure in which the thickness of the insulating film on the diffusion layer region is made the same, the implantation profile and the ion The amount injected can be the same. That is, even if ion implantation is not performed for each transistor, the resistance values of the diffusion layers of the first and second transistors can be made the same by one ion implantation. Therefore, an increase in manufacturing cost such as an increase in the ion implantation process can be suppressed.

  In addition, according to the present invention, the diffusion layer region of the first transistor is formed so as to overlap below the first insulating film. It can be easily connected with an inversion layer. In addition, since the charge for forming the inversion layer can be supplied smoothly, the inversion layer can be formed efficiently.

  In addition, according to the present invention, since the diffusion layer region of the second transistor is formed so as to overlap below the second gate electrode, the charge for forming the inversion layer under the gate electrode is reduced. Since it is supplied through the overlap portion, the inversion layer can be easily formed, so that a large amount of on-state current of the transistor can flow.

  Embodiments of the present invention will be described below with reference to the drawings. However, the contents and drawings described below are merely examples, and the scope of the present invention is not limited to these drawings and the following description contents.

<Embodiment 1>
The semiconductor device according to the first embodiment will be described with reference to FIGS. However, FIG. 21 is a cross-sectional view of a semiconductor device having a basic structure for comparison with the semiconductor device of Embodiment 1, and illustrates a structure in which the resistance value of the diffusion layer changes. FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment designed to improve the change in resistance value of the basic structure shown in FIG. In both FIG. 1 and FIG. 21, the transistor on the left side of the drawing (hereinafter referred to as the first transistor) is a transistor that is driven at a low voltage, so that the thickness of the insulating film under the gate electrode is designed to be thin in accordance with the voltage. Since the transistor on the right side of the drawing (hereinafter referred to as the second transistor) is a transistor driven at a high voltage, the insulating film (gate insulating film) under the gate electrode is designed to be thick.

  First, a method for manufacturing the semiconductor device shown in FIG. 21 will be described.

  First, a glass substrate 1701 serving as an insulating substrate is prepared. Then, an N-type MOS transistor is formed thereon. Here, a glass substrate is used as the insulating substrate, but a plastic substrate (a resin substrate made of transparent acrylic, polycarbonate, polyimide, or the like) is also possible. In the case where the transistor formed on the glass substrate 1701 is used for a display substrate such as a liquid crystal display, a transparent substrate is preferable. Moreover, when manufacturing a flexible display, it is good to use a plastic substrate (resin substrate).

  Next, in order to prevent impurity contamination from the glass, a silicon oxide film (SiO) of 100 nm is formed on the glass substrate (insulating substrate) 1701 (not shown). A silicon nitride film (SIN) or a silicon oxynitride film (SiON) may be formed under the silicon oxide film (between the glass substrate and the silicon oxide film).

  Next, a 50 nm-thick polysilicon film to be the semiconductor layer 1702 is formed on the silicon oxide film. This time, the amorphous silicon was irradiated with an excimer laser to form a polysilicon film. However, a method of directly forming the polysilicon film by LP-CVD (Low Pressure Chemical Vapor Deposition) method or a high temperature (over 600 degrees) ) And a method of forming a polysilicon film by CLC (CW Lateral Crystallization) or SLS (Sequential Lateral Solidification).

  Next, the semiconductor layer 1702 is processed into necessary regions 1702a and 1702b in an island shape using lithography and etching. By processing the semiconductor layers 1702a and 1702b processed into island shapes into a trapezoidal shape, the insulating film 1703 formed in the upper layer portion is likely to be flat, and as a result, leakage from an acute angle portion of the semiconductor layer is likely to occur. It is possible to prevent the current and the insulating film from being broken. Therefore, the semiconductor layers 1702a and 1702b are preferably trapezoidal.

  Next, in order to form a channel region, ion implantation is performed on the entire semiconductor layers 1702a and 1702b to make the semiconductor layer P-type. Here, boron is used for this ion implantation. However, the present invention is not limited to boron, and any material that can form a P-type semiconductor layer may be used. This step may be performed after the insulating film 1703 is formed. That is, by implanting ions after forming the insulating film and before the step of forming the insulating film in two thicknesses, it is possible to prevent unnecessary impurities from entering the semiconductor layer 1702 and to implant through the insulating film. The injection energy and the injection amount can be easily controlled. However, ion implantation may be performed after the step of separately forming the insulating film into two thicknesses. In this case, since the thickness of the insulating film varies depending on the location, the resistance value may be made the same by ion implantation. It becomes difficult.

  Next, an insulating film (gate insulating film) of 80 nm is deposited on the entire surface. This insulating film uses a silicon oxide film this time, but is not limited to this, and can also be a silicon nitride film. Furthermore, it is called a high dielectric constant film such as hafnium silicate, nitrogen-added hafnium aluminate, or yttrium. It is also possible to use a film or the like.

  After that, the region 1703aW where the gate insulating film is desired to be thinned is etched with a chemical solution containing lithography and hydrofluoric acid until the desired thickness becomes 30 nm (t1). Thus, a thin insulating film 1702a and a thick insulating film 1703b can be formed. The thin insulating film 1703a is 30 nm (t1), and the thick insulating film 1703b is 80 nm (t2). This time, wet etching is used as the etching method and hydrofluoric acid is used. However, the present invention is not limited to this, and other chemicals capable of obtaining an etching rate with respect to the insulating film are also possible and reactive. Dry etching using a gas, ions, or radicals is also possible.

  In this way, two thicknesses of insulating films 1703a and 1703b can be manufactured on the same substrate.

  Next, 400 nm of tungsten to be the gate electrodes 1704a and 1704b is deposited and patterned using lithography and etching. In addition to the tungsten (W) used here, a refractory metal such as Ti (titanium), Cr (chromium), Ta (tantalum) and Pd (palladium) can be used. As the metal film, it is preferable to select a metal having a melting point that can cope with the heat treatment in the steps after the film formation. In addition, when the heat treatment temperature in the steps after film formation is low, Al, Au, Cu, and Ag, which are low-resistance metals, can also be used. The high melting point metal, low resistance metal, and the like mentioned here can be mixed with other metals and impurities as necessary, and used as an alloy. In addition, since the tungsten used this time tends to peel off on the oxide film, TaN or TiN may be formed between the oxide film and tungsten in order to prevent peeling.

Next, diffusion layers 1702a2, 1702a3, 1702b2, and 1702b3 are formed by ion implantation using the gate electrodes 1704a and 1704b as masks. The regions 1702a1 and 1702b1 under the gate electrode remain as P-type semiconductor layers because the gate electrodes 1704a and 1704b serve as masks and are not ion-implanted, and these regions serve as channel regions. Although phosphorus is used as the implanted ions this time, arsenic or antimony may be used, and the present invention is not limited to these as long as it can form an N-type semiconductor layer. The conditions for phosphorus implantation are an implantation energy of 45 Kev and an implantation amount of 5 × 10 ¹⁵ / cm ³ .

  Next, in order to activate the implanted ions, an annealing process is performed for 30 minutes at a temperature of 550 ° C. in a nitrogen gas atmosphere as an inert gas. If the annealing temperature is high, ions are activated in a short period of time. Therefore, the annealing temperature is preferably as high as possible. However, it is necessary to determine the temperature in consideration of the heat resistance temperature of the substrate and other materials. In addition, since treatment at a low temperature may not be activated within a realistic time, care must be taken to reduce the temperature too much. In the case of using the substrate and material this time, the range of 500 ° C. to 600 ° C. is preferable. When activation cannot be performed normally, the resistance value of the diffusion layer is increased. This activation treatment can also be performed by lamp annealing, and the activation atmosphere is not limited to the inert gases nitrogen, argon, and helium, and can be performed in oxygen, hydrogen, or the atmosphere. It is sufficient if it can be activated.

  In this way, a transistor element is completed.

-Explanation of measurement evaluation-
Next, measurement evaluation of the semiconductor device having the above configuration (shown in FIG. 21) will be described.

  That is, the measurement evaluation of the semiconductor device of FIG. 21 is first performed to confirm that the resistance value of the diffusion layer changes.

  In this measurement and evaluation, in order to measure the resistance values of the transistor element and the diffusion layer shown in FIG. 21, an interlayer insulating film is deposited, and a contact hole is opened in the interlayer insulating film to draw out a wiring. Such wiring drawing is performed in the same manner in other embodiments described below.

Here, the resistance value of the diffusion layer was evaluated using the Kelvin method. As a result, the respective sheet resistance values were as follows.
Diffusion layers 1702a2, 1702a3: 2250Ω / □
Diffusion layers 1702b2, 1702b3: 610Ω / □
From this result, the resistance value of the diffusion layer differs 3.5 to 4 times.

  With an implantation energy of 45 Kev, the implantation target is set above the semiconductor layers 1702b2 and 1702b3. On the other hand, since the upper insulating film thickness is small on the semiconductor layers 1702a2 and 1702a3 side, the target of implantation is implanted deeper than the semiconductor layer 1702b (implanted near the center of the semiconductor layers 1702a2 and 1702a3). Therefore, in the semiconductor layers 1702b2 and 1702b3, crystal nuclei necessary for recrystallization remain on the lower side of the film, so that the semiconductor layers 1702b2 and 1702b3 can be sufficiently activated and have a low resistance value. On the other hand, in the semiconductor layers 1702a2 and 1702a3, most of the crystal nuclei of the semiconductor layer were destroyed by phosphorus ions, indicating that the activation did not proceed due to few crystal nuclei of the semiconductor layer when activated. Yes. This problem can be prevented by destroying most of the crystal nuclei by using the conventional method shown in the background art, but there is a problem that the target position (depth direction) of implantation is different. Therefore, the injection amount is different. That is, when the implantation position is at the center of the semiconductor, most of the ions are implanted and the resistance value is lowered, but when the implantation position is above the semiconductor layer, the amount of implantation is relatively reduced. For this reason, even if activated, the resistance value of the diffusion layer varies due to the number of ions.

  From the above, it can be predicted that the resistance value of the diffusion layer can be made the same when the thickness of the insulating film on the semiconductor layer is made the same. An embodiment according to this prediction will be described below.

  FIG. 1 shows the structure of the semiconductor device according to the first embodiment, and the semiconductor device manufacturing method uses the same method as the semiconductor device manufacturing method shown in FIG. The difference is in the region where the insulating film is thinned. That is, the area 1703aw in FIG. 21 is only the area corresponding to the area 103aw and the gate electrode in FIG. In short, the insulating film is thinned only in the portion under the gate electrode.

  More specifically, in FIG. 21, the semiconductor layer 1702a is entirely covered with the thin (t1) insulating film 1703a, whereas the semiconductor layer 102a of the first transistor on the left side of FIG. Is that only the insulating film 103a having a small thickness (t1) is covered under the gate electrode which is shaded during ion implantation. On the other hand, the diffusion layer regions 102a2 and 102a3 are thick (t2) insulating films 103b. The thick insulating film 103b has the same thickness as the insulating film 103b of the second transistor on the right side. For this reason, in the region where ion implantation is performed, since the thickness of the insulating film on the semiconductor layer is the same, the same amount of ions is implanted and the resistance value of the diffusion layer becomes the same.

As a result of creating a sample having such a structure and evaluating the resistance value (sheet resistance value) of the diffusion layer in the same manner as the above measurement evaluation,
Diffusion layers 102a2, 102a3: 610Ω / □
Diffusion layers 102b2, 102b3: 620Ω / □
The resistance value was almost the same.

  This proves that the insulating film structure shown in FIG. 1 is effective in changing the thickness of the insulating film.

  That is, the semiconductor device of Embodiment 1 is a semiconductor device in which the first and second transistors are formed on the same insulating substrate 101, and the first transistor (the transistor on the left side in FIG. 1) is the first gate electrode. 104a includes a first insulating film 103a formed below 104a2 and a second insulating film 103b formed on the diffusion layers 102a2 and 102a3, and the second transistor (the transistor on the right side in FIG. 1) The second insulating film 103b is formed below the gate electrode 104b and the diffusion layers 102b2 and 102b3, and the first and second gates are formed above the first insulating film 103a and the second insulating film 103b. The electrodes 104a and 104b are respectively disposed, and the first insulating film 103a (t1) is formed thinner than the second insulating film 103b (t2). It has a t1 <t2) structure.

  As described above, in the first and second transistors having different insulating film thicknesses below the gate electrode, by adopting a structure in which the insulating film thickness on the diffusion layer region is made the same, the implantation profile and the ion implantation are performed. The same amount. For this reason, the resistance values of the diffusion layers of the first and second transistors can be made the same by one ion implantation without ion implantation for each transistor. Therefore, an increase in manufacturing cost such as an increase in the ion implantation process can be suppressed. In addition, since the first transistor has a thinner insulating film under the gate electrode than the second transistor, a structure suitable for driving at a lower voltage than that of the second transistor can be obtained.

  In the first embodiment, it is expressed that the first and second gate electrodes 104a and 104b are arranged above the first insulating film 103a and the second insulating film 103b, respectively. This is an expression used to prevent the first and second insulating films from being mixed with the interlayer insulating film.

  Here, the interlayer insulating film will be described with reference to FIG.

  20 has a structure in which an interlayer insulating film 1610 is added to FIG. For example, when the interlayer insulating film 1610 is formed on the first and second insulating films 103a and 103b, it is ambiguous from where the first or second insulating film is. The insulating films (first and second insulating films) referred to in the present invention are those formed below the gate electrode. Therefore, the interlayer insulating film 1610 which is a layer above the gate electrode and formed later is not related to the present invention. Therefore, the positional relationship between the gate electrode and the insulating film (first and second insulating films) is limited. As a method of limitation, the expression “the insulating film is formed in a layer below the gate electrode” is also possible, but in this specification, “the first insulating film is formed above the first and second insulating films. The expression “first and second gate electrodes are respectively disposed” is employed.

  Note that the diffusion layer shown in FIG. 1 is a source / drain region. This diffusion layer can be an N-type diffusion layer or a P-type diffusion layer. Further, the diffusion layer can be used as a diffusion layer (application example 1) of a body contact region, which will be described later, in addition to being used for the source / drain regions. In this case, the diffusion layer does not need to sandwich the channel region, and either one (one) may be arranged.

<Embodiment 2>
In the first embodiment, as shown in FIG. 1, the thickness of the insulating film in the portion to be implanted is matched with the insulating film thickness of the second transistor (the transistor on the right side in FIG. 1) on the thicker side of the gate insulating film. Structure. On the other hand, in the second embodiment, as shown in FIG. 2, the thickness of the insulating film in the portion to be implanted is set to the insulating film of the first transistor on the thin side of the gate insulating film (the transistor on the left side in FIG. 2). By adopting an insulating film structure that matches the thickness, a structure in which a change in resistance value is similarly prevented.

  The semiconductor device manufacturing method of the second embodiment uses the same method as the semiconductor device manufacturing method shown in FIG. The difference is in the region where the insulating film is thinned. That is, the region 1703 aw in FIG. 21 is the entire region other than the region 203 aw and the second gate electrode 204 b in FIG. 2. In short, the insulating film is thickened only in a portion below the second gate electrode 204b, and the other region 203aw is thinned.

  The thickness of the insulating film is 30 nm (t1) in the region 203a and 80 nm (t2) in the region 203b.

  That is, the thickness 30 nm (t1) of the insulating film 203a in the region where ion implantation is performed in the second embodiment is thinner than the thickness 80 nm (t2) of the insulating film 103b in the region where ion implantation is performed in the first embodiment. Therefore, the ion implantation energy is changed from 45 Kev to 10 Kev. Accordingly, since ion implantation is performed so as to aim at the upper part of the semiconductor layer, it is possible to prevent the crystal nuclei of the semiconductor layer from being completely destroyed. In addition, since the insulating film thickness in the ion-implanted region is unified (t1), the resistance values of the diffusion layers in the regions 202a2, 202a3, 202b2, and 202b3 to be the diffusion layers can be made the same.

As a result of creating a sample having such a structure and evaluating the resistance value (sheet resistance value) of the diffusion layer in the same manner as the above measurement evaluation,
Diffusion layers 202a2, 202a3: 600Ω / □
Diffusion layers 202b2, 202b3: 590Ω / □
The resistance value was almost the same.

  Therefore, it has been proved that the insulating film structure shown in FIG. 2 is also effective in changing the thickness of the insulating film.

  That is, the semiconductor device of the second embodiment is a semiconductor device in which the first and second transistors are formed on the same insulating substrate 201, and the first transistor (the transistor on the left side in FIG. 2) is the first gate electrode. 204a and a first insulating film 203a formed on the diffusion layers 202a2 and 202a3, and the second transistor (the transistor on the right side in FIG. 2) is a second transistor formed below the second gate electrode 204b. An insulating film 203b and a first insulating film 203a formed on the regions of the diffusion layers 202b2 and 202b3 are provided, and the first and second gates are formed above the first insulating film 203a and the second insulating film 203b. The electrodes 204a and 204b are respectively disposed, and the first insulating film 203a (t1) is formed thinner than the second insulating film 203b (t2). It has a t1 <t2) structure.

  As described above, in the first and second transistors having different insulating film thicknesses below the gate electrode, by adopting a structure in which the insulating film thickness on the diffusion layer region is made the same, the implantation profile and the ion implantation are performed. The same amount. For this reason, the resistance values of the diffusion layers of the first and second transistors can be made the same by one ion implantation without ion implantation for each transistor. Therefore, an increase in manufacturing cost such as an increase in the ion implantation process can be suppressed. In addition, since the insulating film under the gate electrode of the second transistor is thicker than that of the first transistor, a structure suitable for driving with a higher voltage than that of the first transistor can be obtained.

<Embodiment 3>
The third embodiment is obtained by improving the first embodiment in order to increase productivity. The third embodiment will be described below with reference to FIGS. 3 (a) and 3 (b).

  In the manufacturing process, misalignment always occurs. Therefore, even if an attempt is made to produce the same structure as in the first embodiment, as shown in FIG. 3A, the first gate electrode 304a may cause misalignment. is there. For this reason, the first gate electrode 304a is displaced even though the ion implantation region is covered with the thick second insulating film 303b, so that the thin insulating film region 305a is formed. As a result of performing ion implantation in this state, the resistance value is changed. In this case, the ion implantation of the portion of the first semiconductor layer (first diffusion layer) 302a2 corresponding to the thin insulating film region 305a is aimed at the center of the film from the surface of the first semiconductor layer 302a2. Therefore, it can be predicted that the resistance increases as described above.

  A structure for solving this problem is the structure of FIG. 3B according to the third embodiment. As shown in FIG. 3B, a portion 306a of the thick second insulating film 303b on the diffusion layer region overlaps to the bottom of the first gate electrode 304a. By forming the insulating film in this way, even if the first gate electrode 304a is displaced, a thin insulating film region 305a as shown in FIG. 3A is not formed. In the third embodiment, the overlap amount is set to 2 μm. However, since this depends on the alignment accuracy of the semiconductor manufacturing apparatus to be used, it is necessary to take the overlap amount in accordance with the apparatus performance. However, if the overlap amount is excessively large, the area of the transistor increases, which hinders integration and miniaturization, and is preferably 2 μm or less. This 2 μm or less is not applicable when not integrated and miniaturized. Even if these are taken into consideration, the upper limit for manufacturing the TFT needs to be 100 μm or less. The lower limit is not particularly limited as long as it can be aligned, but is limited to 5 nm in consideration of the material surface accuracy of the substrate (insulating substrate such as glass) and the material (resist) and the accuracy of the semiconductor process.

  That is, the semiconductor device of Embodiment 3 is a semiconductor device in which the first and second transistors are formed on the same insulating substrate 301, and the first transistor (the transistor on the left side in FIG. 3) is the first gate electrode. The second transistor (the transistor on the right side in FIG. 3) includes a first insulating film 303a formed below 304a and a second insulating film 303b formed on the diffusion layers 302a2 and 302a3. The second insulating film 303b is formed below the gate electrode 304b and the diffusion layers 302b2 and 302b3, and the first and second gates are formed above the first insulating film 303b and the second insulating film 303a. The electrodes 304a and 304b are respectively disposed, and the first insulating film 303a (t1) is formed thinner than the second insulating film 303b (t2). t1 <t2), and the second insulating film 303a of the first transistor is formed (region 306a) so as to enter (overlap) from the lower surface edge of the first gate electrode 304a to the inside. It has a structure.

  Thus, after the first and second insulating films 303a, 306a, and 303b are formed by adopting a structure in which the thick second insulating film 303b is overlapped to the bottom of the first gate electrode 304a. Even when the formed first gate electrode 304a is displaced, it is possible to prevent the first insulating film 303a having a small thickness from protruding from the lower portion of the first gate electrode 304a.

<Embodiment 4>
The fourth embodiment is obtained by improving the second embodiment in order to increase productivity. The fourth embodiment will be described below with reference to FIGS. 4 (a) and 4 (b).

  In the manufacturing process, misalignment always occurs. Therefore, even if an attempt is made to produce the same structure as in the second embodiment, the second gate electrode 404b may cause misalignment as shown in FIG. is there. For this reason, the second gate electrode 404b is displaced even though the gate electrode to which a high voltage is applied is covered with the thick second insulating film 403b. A thin insulating film region 405b is generated below 404b. As a result, the second gate electrode 404b formed over the thick second insulating film 403b is also formed over the thin insulating film region 405b. That is, the structure includes a region 405b where a high voltage is applied to the thin insulating film. Therefore, the thin insulating film region 405b is destroyed, and a leakage current may flow through the second gate electrode 404b.

  A structure for solving this problem is the structure of FIG. 4B according to the fourth embodiment. The thick second insulating film 403b under the second gate electrode 404b is overlapped (region 406b) to the regions on the diffusion layer regions 402b2 and 402b3. Accordingly, even when the second gate electrode 404b is displaced, the second gate electrode 404b can be prevented from being formed over the thin first insulating film 403a. In the fourth embodiment, the overlap amount is set to 2 μm as in the third embodiment. However, since it depends on the alignment accuracy of the semiconductor manufacturing apparatus to be used, it is necessary to take the overlap amount according to the apparatus performance. There is. However, if the overlap amount is excessively large, the area of the transistor increases, which hinders integration and miniaturization, and is preferably 2 μm or less. This 2 μm or less is not applicable when not integrated and miniaturized. Even if these are taken into consideration, the upper limit for manufacturing the TFT needs to be 100 μm or less. The lower limit is not particularly limited as long as it can be aligned, but is limited to 5 nm in consideration of the material surface accuracy of the substrate (insulating substrate such as glass) and the material (resist) and the accuracy of the semiconductor process.

  That is, the semiconductor device of the fourth embodiment is a semiconductor device in which the first and second transistors are formed on the same insulating substrate 401. The first transistor (the transistor on the left side in FIG. 4) is the first gate electrode. The second transistor (the transistor on the right side in FIG. 4) includes a first insulating film 403a formed on the lower part of 404a and on the diffusion layers 402a2 and 402a3, and the second transistor formed on the lower part of the second gate electrode 404b. An insulating film 403b and a first insulating film 403a formed on the regions of the diffusion layers 402b2 and 402b3 are provided, and the first and second gates are provided above the first insulating film 403a and the second insulating film 403b. The electrodes 404a and 404b are disposed, and the first insulating film 403a (t1) is formed thinner than the second insulating film 403b (t2). The second insulating film 403b of the second transistor is formed to extend from the lower surface edge of the second gate electrode 404b to the diffusion layers 402b2 and 402b3 (region 406b). It has a structure.

  As described above, the second insulating film 403b having a large thickness is overlapped on the diffusion layers 402b2 and 402b3, thereby forming the first and second insulating films 403a and 403b. Even if the second gate electrode 404b is displaced, it is possible to prevent the second gate electrode 404b from protruding from the thick second insulating film 403b.

<Embodiment 5>
The fifth embodiment is an embodiment in which the first transistor (the left-side transistor) in FIG. 3B is improved in order to improve the on-current of the transistor. Hereinafter, the fifth embodiment will be described with reference to FIG.

  The improvement of the fifth embodiment is the overlap of the diffusion layers.

  In FIG. 3B, each of the diffusion layers (source and drain) 302a2 and 302a3 extends to the side of the first gate electrode 304a, and a thin gate insulating film region (first film) under the first gate electrode 304a. The insulating film 303a) is not overlapped (not covered). That is, in FIG. 3B, the gate insulating film is composed of a thick region (part 306a of the second insulating film 303b) and a thin region (first insulating film 303a). A portion 306a of the second insulating film 303b, which is a thick region, is formed on the source side and the drain side (that is, both edges of the first gate electrode 304a), and the first region, which is a thin region, is formed therebetween. Insulating film 303a is formed.

  In the case of such a shape, the following problem occurs when a voltage is applied to the first gate electrode 304a to form the inversion layer.

  When a voltage is applied to the first gate electrode 304a, an inversion layer is formed in the semiconductor layer 302a1 under the gate insulating film. However, in FIG. 3B, since the second insulating film 303b having a large thickness and the second insulating film 303a having a small thickness are mixed, the second insulating film 303a is formed below the thin second insulating film 303a. Even if the inversion layer is formed, the inversion layer is not formed under the thick second insulating film 303b. This is because an electric field is not easily transmitted through the thick second insulating film 303b. For this reason, the inversion layer portion 302a11 under the thick second insulating film 303b (specifically, below the portion 306a) where the inversion layer is difficult to form has a high resistance, and as a result, the transistor is turned on. This causes a problem that current is reduced. This problem is a peculiar problem that occurs in the case of the insulating film structure of the first transistor on the left side of FIG.

  Therefore, in order to solve these problems, in the fifth embodiment, as shown in FIG. 5, the diffusion layers (sources and drains) 302a2 and 302a3 are formed so as to overlap below the first gate electrode 304a. is doing. That is, the overlapped diffusion layer portions 302a21 and 302a31 cover the entire portion 306a of the thick second insulating film 303b, and further overlap the portion 308a of the thin first insulating film 303a. Is formed. That is, the diffusion layers 302a2 and 302a3 overlap (302a21 and 302a31) below the thin first insulating film 303a.

  With such a structure, since the diffusion layers 302a21 and 302a31 are formed under the thick first insulating film 303b (specifically, under the portion 306a), an inversion layer is formed. The region may be only under the first insulating layer 303a having a small thickness. That is, since there is no region (inversion layer portion 302a11) where it is difficult to form an inversion layer as shown in FIG. 3B, by applying a gate voltage, the source-drain (between diffusion layers 302a2 and 302a3) can be connected to the inversion layer. It can be easily connected with 302a1.

  In this manner, each diffusion layer (source and drain) 302a2 and 302a3 is formed so as to overlap with a portion 308a of the thin insulating film region, thereby forming a “thick insulating film and a thin insulating film”. "Film connection" and "Diffusion layer edge" can address the problem that the thick insulating film region cannot be covered due to manufacturing variations (such as variations in processing dimensions and alignment). it can. In other words, each diffusion layer (source, drain) 302a2 and 302a3 is formed so as to overlap with a portion 308a of the thin insulating film region, thereby manufacturing variation (processing) corresponding to the width of the region 306a. Even if dimensional variations, alignment variations, etc.) occur, a thick insulating film region can always be covered with a diffusion layer within the range of the portion 308a. In addition, since the portions 302a21 and 302a31 of the diffusion layer overlap to below the thin insulating film (first insulating film 303a), the charge for forming the inversion layer can be supplied smoothly. An inversion layer can be formed efficiently.

  With the above structure, the inversion layer can be easily formed by applying a gate voltage, and the source and drain can be easily connected by the inversion layer. Accordingly, a large amount of on-state current of the transistor can flow. That is, it is possible to prevent the diffusion layer from being offset from the gate electrode.

<Embodiment 6>
The sixth embodiment is an embodiment in which productivity is improved while preventing deterioration of the transistor with respect to the first transistor (left-side transistor) in FIG. Hereinafter, the sixth embodiment will be described with reference to FIG.

(A) Description of transistor deterioration prevention In the fifth embodiment, the impurity concentrations of the diffusion layers 302a2 and 302a3 are all the same. In the sixth embodiment, the impurity concentrations of the diffusion layers 302a2 and 302a3 are different depending on the regions. I have created it. That is, one diffusion layer 302a2 is formed in the high concentration diffusion layer region 302a25 and the low concentration diffusion layer region 302a26, and the other diffusion layer 302a3 is formed in the high concentration diffusion layer region 302a35 and the low concentration diffusion layer region 302a36. The low-concentration diffusion regions 302a26 and 302a36 are formed on the first gate electrode 304a side. That is, the diffusion layer regions having the first gate electrode 304a on the upper side are the low concentration diffusion regions 302a26 and 302a36.

  When the junction between the channel region and the diffusion layer region is steep, for example, in the case of connection between the high concentration diffusion layer region and the channel region, carriers are accelerated and flow when current is passed through the connection portion. , Hot carriers are likely to occur. When the generation of hot carriers increases, the hot carriers collide with the gate insulating film to generate defects. The same problem occurs in a gate insulating film structure including a thick region (insulating film region 306a) and a thin region (insulating film region 308a) as shown in FIG.

  For this reason, the connection between the channel region and the diffusion layer region is preferably a connection through the low concentration diffusion layer region. That is, as shown in FIG. 6, it is preferable that the channel region (inversion layer 302a1) is passed through the low concentration diffusion layer region 302a26 or 302a36 to the high concentration diffusion layer region 302a25 or 302a35. In this way, the bonding becomes loose and the generation of hot carriers can be suppressed. As a result, damage to the gate insulating film can be suppressed, and as a result, deterioration of the transistor can be prevented. Here, the impurity concentration of the low-concentration diffusion layer regions 302a26 and 302a36 may be lower than that of the high-concentration diffusion layer regions 302a25 and 302a35, but more preferably less than half of the high-concentration diffusion layer region. .

The impurity concentration in the high concentration diffusion layer region is preferably 1 × 10 ¹⁹ / cm ³ or more because the resistance can be reduced. Note that the low-concentration diffusion layer region referred to here is not a buffer region that is naturally formed between the junction between the high-concentration diffusion layer region and the channel region, but a region that is intentionally formed. It is a region formed by

  According to the sixth embodiment, the electric field at the junction of the diffusion layer is weakened by forming two regions, a high concentration region and a low concentration region, in the diffusion layer region with reduced manufacturing cost. Generation of hot electrons can be suppressed. For this reason, deterioration of the insulating film or the like due to hot electrons can be suppressed.

(B) Description of Improvement of Transistor Productivity As described above, in the sixth embodiment, one diffusion layer region is separated into a low concentration region and a high concentration region.

  In the structure shown in FIG. 5, the concentrations of the diffusion layers are all the same, and it is difficult to largely overlap the high concentration diffusion layers as shown in FIG. There are a method of thermal diffusion by high-temperature annealing at 600 ° C. or higher, and a method of overlapping as shown in FIG. 5 by an ion implantation method from an oblique direction. A more efficient and easy production method can be proposed.

  That is, in the sixth embodiment, all of the diffusion layer regions 302a26 and 302a36 under the first gate electrode 304a are formed as low concentration diffusion layer regions. The low-concentration diffusion layer regions 302a26 and 302a36 are formed under the thick insulating film region 306a under the first gate electrode 304a and under the thin insulating film region 308a. Except for the concentration, the structure is the same as the structure shown in FIG. 5 described above, that is, the structure of the overlap portion where the diffusion layers are overlapped in order to improve the on-current. The same effect can be obtained as the effect of the overlap.

  With such a structure, manufacturing is facilitated for the following reason.

Low concentration N-type diffusion layers (corresponding to the diffusion layer regions 302a26 and 302a36) are formed in the process up to the formation of the first gate electrode 304a. The low concentration diffusion layer is an impurity concentration whose concentration is half or less than that of the high concentration diffusion layer (corresponding to the diffusion layer regions 302a25 and 302a35). The low impurity concentration is preferably a diffusion layer having a concentration of less than 1 × 10 ¹⁹ / cm ³ . This is to prevent the junction with the channel region from becoming sharp.

  The low-concentration diffusion layers (corresponding to the diffusion layer regions 302a26 and 302a36) are formed under the thick insulating film region 306a and under the thin insulating film region 308a. For this reason, when ions are implanted through a thick insulating film and a thin insulating film, the resistance value of the diffusion layer changes depending on the insulating film thickness. For this reason, a method that is preferable to a method of forming a low-concentration diffusion layer after forming a thick insulating film and a thin insulating film will be described below.

  The first method is a method of performing ion implantation in a state where an insulating film is not formed on the surface of the semiconductor layer until the first gate electrode 304a is formed. In the second method, when an insulating film having a certain thickness until the gate electrode is formed is uniformly formed (separately forming a thick insulating film and a thin insulating film) This is a method of ion implantation before. In these two methods, a region for ion implantation is a region 309 in a range indicated by an arrow in FIG. A thick insulating film and a thin insulating film are formed over the low-concentration diffusion layer region 309 formed by these methods, and then a first gate electrode 304a is formed. Further, the high concentration diffusion layers 30a25 and 302a35 are formed using the first gate electrode 304a as a mask. Thus, a high concentration diffusion layer is formed even in a portion of the low concentration diffusion layer region 309 that protrudes from the first gate electrode 304a (that is, a part of the low concentration diffusion region is the first gate electrode 304a). It becomes a high-concentration diffusion region at the edge of this). Under the first gate electrode 304a, since the ions are not implanted, the low concentration diffusion layer region remains. By adopting such a method, a low-concentration diffusion layer formed with the edge portion of the first gate electrode 30a as a boundary can be formed in a self-aligned manner below the first gate electrode 304a. Becomes a high concentration diffusion layer region.

<Embodiment 7>
In the seventh embodiment, the second transistor (the right-side transistor) in FIG. 4B is improved to improve the on-current of the transistor. Hereinafter, the fifth embodiment will be described with reference to FIG.

  The improvement of the seventh embodiment is the overlap of the diffusion layers.

  In FIG. 7, unlike FIG. 4B, the diffusion layers 402b2 and 402b3 are formed so as to overlap to the portions 402b21 and 40b31 below the second gate electrode 404b. The width of the overlap portions 402b21 and 40b31 is, for example, about 10 nm. However, since there is no region that needs to be covered by the overlap, a small width is sufficient, and the above 10 nm or less is also possible. There is no limit to the lower limit value, and it may be 1 nm, for example. With such a structure, charges for forming the inversion layer under the second gate electrode 404b are supplied through the overlap portions 402b21 and 402b31, so that the inversion layer can be easily formed. In addition, since the diffusion layer is securely attached (bite into) the channel region, the inversion layer and the diffusion layer can be easily connected. Therefore, a large amount of on-state current can be supplied to the transistor. As a method of overlapping, there are a method of diffusing down to the second gate electrode 404b by thermal diffusion, and a method of ion implantation obliquely at the time of ion implantation. Since a small amount of overlap (less than 10 nm) is sufficient, it is possible to easily overlap with this method.

  In this manner, the diffusion layers 402b2 and 402b3 are overlapped from below the thin first insulating film 403a to below the thick second insulating film 403b below the second gate electrode 404b. Thus, the inversion layer or storage layer 402b1 formed under the thick second insulating film 403b under the gate insulating film and the diffusion layers 402b2 and 402b3 can be easily formed by applying the gate voltage. Further, the inversion layer or accumulation layer 402b1 can be easily connected to the diffusion layers 402b2 and 402b3. That is, it is possible to prevent the diffusion layer from being offset from the gate electrode.

<Eighth embodiment>
The eighth embodiment is an embodiment in which productivity is improved while preventing deterioration of the second transistor (right-side transistor) in FIG. Hereinafter, the eighth embodiment will be described with reference to FIG.

(A) Description of transistor deterioration prevention In the eighth embodiment, a low-concentration diffusion layer region is formed on the second gate electrode 404b side as in the sixth embodiment. That is, the portions 402b21 and 40b31 of the diffusion layers 402b2 and 402b3 under the second gate electrode 404b are formed in the low concentration diffusion layer region, and the other portions are formed in the high concentration diffusion layer region. Thereby, the effect similar to the said Embodiment 6 can be acquired.

  In this way, by forming two regions of the diffusion layer regions 402b2 and 402b3, a region having a high concentration and a region having a lower concentration, the electric field at the junction of the diffusion layer is weakened and the generation of hot electrons is suppressed. it can. For this reason, deterioration of the insulating film or the like due to hot electrons can be suppressed.

(B) Description of Improvement in Transistor Productivity In the structure shown in FIG. 7, the diffusion layer under the thick second insulating film 403b is all a high-concentration diffusion layer region. Then, the diffusion layers under the second insulating film 403b are all low-concentration diffusion layer regions 402b21 and 402b31.

  With such a structure, manufacturing is facilitated for the following reason.

  That is, an insulating film is formed over the semiconductor layer 402b, and a second gate electrode 404b is formed thereover. Thereafter, ion implantation for forming a diffusion layer is performed. The target depth of ion implantation is a semiconductor layer under the thin first insulating film 403a. Accordingly, ions are implanted into the semiconductor layer under the second insulating film 403b with a larger thickness than in the semiconductor layer under the first insulating film 403a with a smaller thickness. Therefore, a high concentration diffusion layer is formed under the thin first insulating film 403a in a self-aligned manner, and a low concentration diffusion layer is formed under the thick second insulating film 403b. In addition, these ion implantations are performed not by implanting ions perpendicularly from right above the substrate on which the semiconductor layer is formed, but by implanting ions obliquely by tilting the substrate. Ions can be implanted under the electrode 404b. As another method, after ion implantation is performed vertically from directly above, heat at 500 ° C. or higher is applied when thermal activation is performed, whereby impurity ions are diffused and moved below the second gate electrode 404b. Can do. In this manner, the semiconductor device (device) shown in FIG. 8 can be manufactured.

  In other words, by utilizing the characteristic that the resistance of the diffusion layer changes depending on the thickness of the insulating film, and by setting the implantation profile so that many ions are implanted under the thin insulating film, Less ion implantation. Therefore, a low-concentration diffusion layer in the diffusion layer region is formed on the gate electrode side (under the thick insulating film) in a self-aligned manner, and the low-concentration diffusion layer region and the high-concentration diffusion layer region are separately formed according to the insulating film thickness. It is done. Further, the boundary can be set at the same position as the boundary between the thin insulating film and the thick insulating film.

<Ninth Embodiment>
The ninth embodiment has a structure in which a step on the lower surface of the connection portion between the second insulating film having a large thickness and the first insulating film having a small thickness formed in each of the above embodiments is eliminated and connected flatly. Is. Hereinafter, the step structure on the lower surface of the connecting portion and the manufacturing method thereof will be described. Here, the lower surface of the insulating film connecting portion is an interface between the insulating film and the semiconductor layer (diffusion layer).

  Specifically, a connection portion between the second insulating film having a large thickness and the first insulating film having a small thickness is a portion 307 indicated by ◯ in FIG. In the ninth embodiment, a contact surface between the semiconductor layer and the insulating film in the portion 307 will be described with reference to FIGS. 9 is an enlarged view of a portion 307 indicated by ◯ in FIG. 3B and a portion 407 indicated by ◯ in FIG. 4B.

  In the first embodiment, the thick and thin portions of the insulating film are separately formed by using a method of etching the thinned portion until the target film thickness is reached. As another method, there is a method in which all the thinned portions are removed and a second insulating film is formed over the entire surface. In this method, since the film thickness is determined only by the deposit (that is, it is different from that determined by both the deposit and the etching amount), the stability of the film thickness and the like is good. In the present embodiment, the prototype is manufactured by such a method.

  First, the step structure will be described with reference to FIG.

  As a method for forming an insulating film, there is a method in which a semiconductor layer is oxidized to form an insulating film. However, in a device using a thin semiconductor layer, the voltage is not lowered and the gate insulating film is thick. For this reason, when the method of selectively oxidizing the semiconductor layer is used, the semiconductor layer is surely reduced (the oxidized portion is thinned). The selective oxidation method mentioned here is a method of oxidizing in an oxidizing atmosphere (oxygen or water vapor) using an oxidation resistant film such as a silicon nitride film as a mask, or a method of implanting oxygen by an ion implantation method using a resist as a mask. It is. Therefore, as in the semiconductor layer 502a1 illustrated in FIG. 9A, the oxidized portion bites into the semiconductor layer and a step is formed. In this portion, an insulating film as indicated by reference numeral 503ab is formed. After that, even if an insulating film is deposited or oxidized on the entire surface by a CVD method to form the insulating film 503au, the step formed in the semiconductor layer is not eliminated. For this reason, the interface between the semiconductor layer 502a1 and the insulating film 503ab has an uneven shape, and a current cannot flow smoothly as indicated by reference numeral 502ad.

  Therefore, the connection structure according to the ninth embodiment, which will be described below, can solve such problems caused by selective oxidation. The connection structure will be described with reference to FIG.

  As a method for forming the insulating film, the insulating film is deposited by the CVD method described in the first embodiment. In the case where the unnecessary portion is selectively etched after the film is deposited on the entire surface, the surface of the semiconductor layer can be kept flat if etching is performed with an etching method that is selective to the semiconductor layer. Examples of this etching method include the etching method using hydrofluoric acid shown in the first embodiment. Even in this method, since the number of semiconductor layers is not reduced, the flatness of the interface between the semiconductor layer 502a1 and the insulating film 503ab can be maintained as shown in FIG. 9B. After that, even if the insulating film 503au is deposited on the entire surface, the interface between the semiconductor layer 502a1 and the insulating films 503ab and 503au remains flat. For this reason, as indicated by reference numeral 502ad, the path through which the current flows can be linearly shortened so that the current can flow smoothly.

  In this way, since there is no step (or slope) on the lower surface of the connecting portion of the insulating film, the diffusion layer, inversion layer, or storage layer formed under the insulating film becomes flat. In the case of flowing, electric current scattering can be suppressed by suppressing the scattering of electric charges.

<Embodiment 10>
The tenth embodiment is an embodiment relating to the upper surface of the insulating film, unlike the lower surface of the connecting portion of the insulating film of the ninth embodiment. Here, the upper surface of the insulating film is an interface between the insulating film and the gate electrode. Hereinafter, the tenth embodiment will be described with reference to FIG. 10 is an enlarged view of a portion 307 indicated by ◯ in FIG. 3B and a portion 407 indicated by ◯ in FIG. 4B. In the portion 407 indicated by ◯ in FIG. 4B, the gate electrode does not exist in the upper part, but the gate electrode can be arranged in the upper part. In the present embodiment, the description is given in the case where a gate electrode is arranged in the circle portion 407. In this case, since there is a risk of breakdown of the insulating film, it is necessary to design the semiconductor layer and the gate electrode in consideration thereof.

  Also in the tenth embodiment, the method of forming the thick insulating film and the thin insulating film uses the method of depositing the insulating film of the ninth embodiment twice. In the tenth embodiment, a wet etching method using hydrofluoric acid is used as the etching method after the first deposition of the insulating film (first insulating film). However, any other method may be used as long as it can selectively etch the underlying semiconductor layer, for example, a dry etching method. In the dry etching method, it is easy to give selectivity to the underlying semiconductor layer depending on the etching gas, and unlike the wet etching method, the lateral control (line width control) is easy. In particular, the effect is large in anisotropic etching. However, there is a problem that the shape of the edge portion after etching becomes a vertical shape. Hereinafter, this problem will be described with reference to FIG.

  The portion indicated by reference numeral 603ab in FIG. 10A is the shape of the insulating film when anisotropic etching is performed after the first deposition of the insulating film, and the edge portion 603ab1 has a vertical stepped portion. It has become. In this state, even if the second insulating film (second insulating film) 603au is deposited, the vertical step shape of the edge portion 603ab1 cannot be improved, and the second insulating film 603au also has an edge portion ( Step portion) 603au1 remains. Then, when the gate electrode 604a is formed in this portion, a protrusion 604ab is formed on the gate electrode 604a. For this reason, when a voltage is applied to the gate electrode 604a, electric field concentration occurs in the projection 604ab, which causes breakdown of the insulating film. Therefore, it is better to avoid the edge portion formed in the insulating film from having a vertical step shape.

  Therefore, in the tenth embodiment, as described above, a wet etching method using a chemical solution containing hydrofluoric acid is used. In the case of the dry etching method, isotropic etching is preferably used. In these methods, the shape of the edge portion can be easily controlled to be an inclined shape (a shape inclined with respect to the substrate surface, more precisely a shape inclined with respect to the surface of the semiconductor layer) instead of a vertical step shape.

  FIG. 10B shows the shape of the insulating film prepared by these methods, and the shape of the edge portion 603ab2 of the first insulating film 603ab is an inclined shape with an inclination angle of about 40 degrees. When the second insulating film 603au is deposited thereon, the edge portion 603au2 of the second insulating film 603au also has an inclined shape with an inclination angle of about 40 degrees, and does not have a vertical step shape. Accordingly, even when the gate electrode 604a is formed over the insulating film 603au, it is possible to suppress the formation of protrusions on the gate electrode 604a and suppress the breakdown of the insulating film.

  As for the inclination angle, an arbitrary inclination angle within a range of 5 degrees close to flat to 50 degrees close to vertical is ideal. In particular, the tilt angle should be close to flat (close to 0 degrees), but in the case of a small angle, the sloping distance from the thick part to the thin part becomes long, which hinders integration. Become. Therefore, in consideration of integration, the inclination angle is ideally 5 degrees or more.

  Note that anisotropic etching can also be used as the first insulating film etching method. That is, when the first insulating film is etched with the resist mask, the resist mask can be etched together by reducing the selectivity with respect to the resist. As a result, the resist pattern also recedes in the lateral direction while the insulating film is etched, and as a result, the insulating film in the receded portion is etched with a delay. In this way, it is possible to suppress the edge portion from having a vertical step shape. Therefore, this etching method can also be implemented.

  That is, in the semiconductor device of Embodiment 6, the inclination angle of the connection portion 603ab2 between the first insulating film 603ab and the second insulating film 603au with respect to the substrate surface (here, the surface of the semiconductor layer 602a1) is 5 degrees to 50 degrees. It is formed at any angle within the range of degrees.

  In this way, by adopting a structure in which the inclination angle of the connection portion of the insulating films having different thicknesses is set to a gentle inclination angle of 50 degrees or less, when an electrode is formed on the insulating film, the electric field with respect to the insulating film corner portion is reduced. The concentration can be relaxed and the breakdown of the insulating film can be suppressed. Moreover, it can suppress that the area of an inclination part becomes large by making an inclination-angle into 5 degree | times or more.

<Application example 1>
This application example 1 is an example in which a P-type transistor and an N-type transistor having a body contact region are formed using a thick insulating film, a thin insulating film, and a diffusion layer that can be implemented by the above-described method. Hereinafter, this application example 1 is demonstrated with reference to FIG.11 and FIG.12. 11 is a top view of the P-type transistor, FIG. 12A is a cross-sectional view taken along line AA in FIG. 11, and FIG. 12B is a cross-sectional view taken along line BB in FIG.

  The body contact region of the P-type transistor is formed with the left insulating film 705a structure (the structure in which the diffusion film 706a region is thick) shown in FIG. 12B, and the right insulating film 703b1 structure shown in FIG. (The structure below the gate electrode 704b and the diffusion layer 702b2, 702b3 is a thick insulating film 703b, which is the same insulating film as the thick insulating film 705a of the left P-type transistor), and the source region 702b2 of the N-type transistor And the drain region 702b3 is formed. That is, the insulating film (gate insulating film) 703a1 under the gate electrode 704a of the P-type transistor has a structure thinner than the gate insulating film 703b1 of the N-type transistor. Further, a P-type transistor (third transistor) is also formed (not shown) with the same insulating film structure as the N-type transistor on the right side of FIG. This transistor is the same as the N-type transistor on the right side of FIG. 12B except that the transistor type is N-type or P-type.

  The body contact region of this application example 1 will be described in more detail with reference to FIGS. 11 and 12. An insulating film (not shown in FIG. 11) is formed on the entire surface of the semiconductor layer 702a formed in an inverted T shape. ) And a gate electrode 704a is formed thereon. Then, P-type ion implantation is performed on the semiconductor layer portion protruding from the gate electrode 704a to the left and right to form a source region 702a2 and a drain region 702a3, and below the gate electrode 704a sandwiched between the source region 702a2 and the drain region 702a3. The semiconductor layer portion becomes a channel region 702a1. Further, the semiconductor layer portion 706a protruding rearward (upper side in FIG. 11) from the gate electrode 704a is N-type ion-implanted and becomes an N-type diffusion layer, which becomes a body contact region. The body contact region 706a is covered with a thick insulating film 705a, and the source region 702b2 and the drain region 702b3 of the other N-type transistor (the N-type transistor on the right side of FIG. 12A) have the same thickness. It is covered with 703b. Therefore, the ion implantation of the body contact region 706a can be performed simultaneously with the N-type ion implantation of the right N-type transistor. Thereby, the resistance value of each diffusion layer can be made the same.

  The body contact region 706a can be used to fix the potential of the channel region 702a1 or to apply a voltage to the channel region 702a1. Since the body contact region 706a is formed of a diffusion layer, the pattern can be extended as it is and used as a wiring. Further, a separate wiring may be connected to the body contact region 706a.

The insulating film is thin in the region other than the body contact region 706a, below the gate electrode 704a and above the source region 702a2 and the drain region 702a3. Each film thickness is the same as the thin film thickness in the first embodiment. As the ion implantation conditions through the thin insulating film, boron is ion-implanted with an implantation energy of 40 Kev and an implantation amount of 9 × 10 ¹⁵ / cm ³ in order to form a P-type diffusion layer. This is because the depth of the third transistor is aimed through the thick insulating film and aimed at the upper side of the semiconductor layer (interface with the thick insulating film). Therefore, in the left transistor in FIG. 12B, ion implantation is performed through a thin film, and the implantation depth is aimed at the center of the semiconductor layer.

(Control of P-type diffusion layer)
The region where the source region 702a2 and the drain region 702a3 are formed has a small insulating film thickness, and thus the third transistor (P-type transistor) having the same structure as the other N-type transistor (the right side shown in FIG. 12A). When a P-type diffusion layer to be a source / drain region is formed at the same time, if the ions are simultaneously implanted, the resistance value of the diffusion layer changes. That is, the resistance value varies depending on the thickness of the insulating film.

  However, since the ions to be implanted are boron, the atomic weight is as small as 11, so that the crystal of the semiconductor layer is not broken so that activation failure does not occur. That is, since boron does not cause activation failure, it can also be implanted with the lower side of the semiconductor layer as a target. In other words, since the target position is free, it is possible to adopt a method in which the target depth is divided into several times in accordance with the insulating film thickness. Therefore, it is possible to obtain substantially the same resistance value under the thick insulating film and under the thin insulating film. However, there is a problem that the resistance value of the diffusion layer changes when ion implantation is performed in which the amount of implanted ions is different without causing activation failure.

  However, the amount of change in resistance value due to the difference in the amount of implanted ions is smaller than the amount of change in resistance value due to defective activation. Specifically, since a thin insulating film is aimed at the semiconductor film, a large amount of boron is injected into the film. For this reason, a density | concentration becomes high and resistance becomes low. On the other hand, on the thicker side of the insulating film, the upper side of the semiconductor layer (interface with the thicker insulating film) is aimed, so the amount injected is less than the target in the semiconductor film and the resistance is reduced. The value becomes higher.

A sample having this structure was prepared, and the resistance value (sheet resistance value) of the semiconductor layer (diffusion layer) was measured and evaluated. The results were as follows.
Thick semiconductor layer: 1.8KΩ / □
Thin semiconductor layer: 0.7KΩ / □
In this measurement result, the difference in resistance value was about 2.5 times, but this difference did not cause a fatal change in resistance value. Incidentally, in the “measurement evaluation” of FIG. 19, they are 2250Ω / □ and 610Ω / □, which is a difference of about 3.5 times.

On the other hand, when it is desired to improve the change in the resistance value due to the difference in the amount of boron implanted, instead of implanting once at 40 KeV, the amount of implantation is divided in half and divided into 30 Kev for thin film and 50 Kev for thick film. The resistance value can be made almost equal by using the method of double injection. The results of doing so are shown below.
Thick semiconductor layer: 10. KΩ / □
Thin semiconductor layer: 0.9KΩ / □
From the above results, when forming a P-type diffusion layer, the resistance value does not change significantly due to activation failure, and it is possible to perform ion implantation in two steps. The resistance value can be made the same value to some extent between the thick semiconductor layer and the thin semiconductor layer.

(Control of N-type diffusion layer)
The N-type diffusion layer is formed by using a large element having an atomic weight of 30 or more, such as phosphorus, arsenic, and antimony. The large element forming the N-type diffusion layer is very likely to break the crystal of the semiconductor layer when ion implantation is performed, and it is likely to cause activation failure. Therefore, it is difficult to control the resistance value.

  For example, when the target depth of ion implantation is set below the semiconductor layer, most crystals in the semiconductor layer are destroyed. This results in the same result even when ion implantation is performed with the implantation amount being halved. Therefore, there is no other method than injecting the semiconductor layer. In this case, as described above, when ion implantation is performed at a place where the thickness of the insulating film is different, activation failure is suppressed even if the ion implantation is performed in accordance with each film thickness in two steps. It is not possible. That is, since the atomic weight is large, the degree to which the crystal of the semiconductor layer is broken is large. Therefore, even if half the amount of ion implantation is performed, the problem cannot be solved. Therefore, by implanting deeply for a thick insulating film, the semiconductor layer under the thin insulating film is implanted deeper, and as a result, most of the crystals in the semiconductor layer under the thin insulating film are destroyed and active. The resistance value becomes high due to the occurrence of defective formation. On the other hand, with only the implantation depth corresponding to the thin insulating film, sufficient implantation cannot be performed on the thick insulating film (diffusion layer), and as a result, the resistance value increases due to the small amount of implantation.

  The above is summarized as follows.

  In the case of forming a transistor having N-type and P-type diffusion layers (having a body contact region), the insulating film thickness of the region where the N-type diffusion layer is formed is equal to the thickness of the insulating film of the other transistor. There is no other way to match. Furthermore, it is best to match the thickness of the insulating film on the N-type diffusion layer of the other transistor.

  On the other hand, the resistance value of the P-type diffusion layer varies depending on the film thickness. However, as long as it is within an allowable range, the transistor may have a structure in which the thickness of the insulating film varies depending on the transistor described in Application Example 1. A method of increasing the thickness of the insulating film on the source / drain so as to be on the body contact region may be used. Furthermore, regarding the P-type diffusion layer, it is possible to match the resistance value by a method in which the above-described implantation is performed in two steps.

  That is, in the semiconductor device according to the first application example, one diffusion layer region formed in the P-type transistor fixes the potential of the channel region of the transistor or the potential of the channel region of the transistor. It is a body contact region that contacts from the wiring. That is, since the diffusion layer with reduced manufacturing cost can be applied in the region where wiring or contact is made, the manufacturing cost can be reduced.

  Further, in the semiconductor device of this application example 1, the body contact region is formed of an N-type diffusion layer. Therefore, the following effects can be obtained. That is, when an N-type diffusion layer is formed, it is formed using a large element having an atomic weight of 30 or more, such as phosphorus, arsenic, and antimony. The large element forming the N-type diffusion layer is very difficult to control the resistance value because it is highly likely to break the crystal of the semiconductor layer when ion implantation is performed, and is likely to cause activation failure. Therefore, the diffusion layer can effectively suppress a change in resistance value by adopting the transistor structure (particularly, the insulating film structure on the diffusion layer) in the case of the N type.

<Application example 2>
This application example 2 is an example in which the body contact region of the application example 1 is not provided and the transistor is an N-type transistor. That is, both the left transistor and the right transistor are N-type transistors. Hereinafter, a description will be given with reference to FIGS. 13A is a top view of the left transistor, and FIG. 13B is a cross-sectional view.

  Reference numeral 802a in the drawing is a semiconductor layer of the right transistor, on which an insulating film (not shown in FIG. 13A) is formed, and a gate electrode 804a is formed thereon. Of the semiconductor layer 802a, regions indicated by 802a2 and 802a3 are N-type diffusion layers in the source region and the drain region. A lower region of the gate electrode 804a sandwiched between the source region 802a2 and the drain region 802a3 is a channel region 802a1. In the structure of the insulating film 803a over the semiconductor layer 802a, the lower portion of the gate electrode 804a is a thin film 803a1, and the upper portion of the source region and the drain region is a thick film 803a2. That is, it is the same as the structure on the left side of FIG. As shown in FIG. 13B, the thick insulating film 803a2 is the same as the insulating film 803b of the right N-type transistor. This is also the same as FIG. For this reason, when performing ion implantation of the N-type diffusion layer of the right transistor, ion implantation can be performed at the same time, and the resistance of the diffusion layer can be made the same. The manufacturing method is the same as that of the first embodiment.

  In the case of forming an N-type transistor, it is essential to form an N-type diffusion layer. Therefore, as described in Application Example 1, it is necessary to adjust the thickness of the insulating film to be equal. Otherwise, the resistance value of the diffusion layer cannot be made the same.

  In other words, the semiconductor device of Application Example 2 is characterized in that the diffusion layer regions of the first transistor (left-side transistor) are the source region and the drain region. That is, the manufacturing cost can be suppressed by applying the diffusion layer whose manufacturing cost is reduced in the source region and the drain region.

  In addition, the semiconductor device of Application Example 2 is characterized in that the first transistor is an N-type transistor. That is, when the N-type diffusion layer constituting the N-type transistor is formed, it is formed using a large element having an atomic weight of 30 or more, such as phosphorus, arsenic, and antimony. The large element forming the N-type diffusion layer is very likely to break the crystal of the semiconductor layer when ion implantation is performed, and it is likely to cause activation failure. Therefore, it is difficult to control the resistance value. Therefore, when the diffusion layer is N-type, the change in resistance value can be effectively suppressed by adopting the transistor structure.

<Embodiment 11>
In the eleventh embodiment, the film structure of the thin insulating film and the thick insulating film described in the above embodiments and application examples will be described. Hereinafter, description will be made with reference to a cross-sectional view shown in FIG. However, in FIG. 14, only an insulating film is shown, and illustrations of portions such as a gate electrode, a source electrode, and a drain region are omitted. In FIG. 14, the left side is described as a thin insulating film and the right side is described as a thick insulating film.

(Example of introducing a film having a high dielectric constant)
In recent years, miniaturization and voltage reduction have been promoted in TFT devices. For this reason, it is essential to reduce the thickness of the gate insulating film. However, if the gate insulating film is made thinner, it causes variation and stable production cannot be performed. Therefore, there is a method of changing the electrical thickness without changing the physical thickness of the insulating film. It is a method that can effectively apply a voltage to the channel region even if the film thickness is the same by using a film having a higher dielectric constant than the current silicon oxide film. A familiar material is a silicon nitride film, which has a dielectric constant approximately twice that of a silicon oxide film. For this reason, when all the gate insulating films are replaced with silicon nitride films, when the gate voltage is the same and the gate voltage is the same, the efficiency of applying the voltage to the channel region is approximately doubled, and EOT (equivalent oxide thickness) Can be halved. That is, the same effect can be obtained as when the gate insulating film is thinned to about ½. Therefore, in this embodiment, a silicon nitride film is used as at least a thin insulating film among a thick insulating film and a thin insulating film.

  Hereinafter, the present embodiment will be described with reference to FIG.

  In this example, the method of manufacturing the thin insulating film and the thick insulating film uses the method of depositing the insulating film of the ninth embodiment twice as in the tenth embodiment.

  That is, a 50 nm silicon oxide film 9031 to be an insulating film is formed on the semiconductor layer 902, and a 10 nm silicon oxide film 9032 and a 20 nm silicon nitride film 9033 are continuously formed on the entire surface. These films were formed using a plasma CVD method. With such a structure, the silicon nitride film 9033 can be included in the thin insulating film. As a result of such a structure, the thin insulating film can be made 20 nm in EOT (equivalent oxide film thickness), and the thicker insulating film can be made 70 nm in EOT (equivalent oxide film thickness). It was.

  In this embodiment, the silicon oxide film 9032 is formed in the lower layer without using the silicon nitride film 9033 as a whole for the thinner insulating film. This is because a level is likely to be generated at the interface between the semiconductor layer 902 and the silicon nitride film 9033, and the silicon oxide film 9032 is interposed between the semiconductor layer 902 and the silicon nitride film 9033 in the sense of interface treatment. In addition, when a silicon nitride film is present near the semiconductor layer 902, charges may be trapped at the interface level of the silicon nitride film or the level in the film. Therefore, as in this embodiment, the silicon nitride film 9033 may be formed with a distance of, for example, 10 nm.

  Here, the thickness of the silicon oxide film 9032 can be changed as appropriate. For example, only the formation of a 1 nm silicon oxide film 9032 is effective. The ratio with the silicon nitride film can also be changed.

  In FIG. 14A, the silicon nitride film 9033 is formed as a whole. However, since the thicker insulating film is often used for a TFT driven at a high voltage, the silicon nitride film 9033 is driven at a high voltage. There may be a case where electric charge is injected into the inside. For this reason, as shown in FIG. 14B, the thicker insulating film may have a structure in which the upper silicon nitride film is removed (the removed part is indicated by a broken line).

  Further, although a silicon nitride film is exemplified as a film having a higher dielectric constant than that of the silicon oxide film, an insulating film called a high dielectric constant insulating film (high-K) can also be implemented.

  That is, the semiconductor device of this embodiment is characterized in that the first and second insulating films include a silicon oxide film, and one or both of the insulating films further include a silicon nitride film layer. As described above, since the insulating film includes the silicon nitride film layer having a higher dielectric constant than the silicon oxide film, the electric field of the gate electrode can be efficiently applied to the channel region.

(Example in which a silicon nitride film is sandwiched between silicon oxide films)
As described above, since the silicon nitride film has many levels, there is a high possibility that charges are trapped in that portion. For this reason, it is good not only to form a silicon oxide film in the lower layer but also to form a silicon oxide film in the upper layer. FIG. 14 (c) shows this state. A difference from FIG. 14A is that a silicon oxide film 9034 is further formed on the entire surface of the silicon nitride film 9033 to a thickness of 10 nm. With such a structure, charge injection from the gate electrode side can be prevented.

  A thick insulating film is often used for a TFT driven at a high voltage. In FIG. 14C, the silicon oxide film 9034 on the silicon nitride film 9033 is as thin as 10 nm. For this reason, it may be considered that charges are injected into the silicon nitride film 9033 by tunneling through the thin silicon oxide film 9034 by a high voltage (for example, a voltage of 16 V or more). For this reason, as shown in FIG. 10D, a structure in which the silicon oxide film 9033 and the silicon nitride film 9034 on the thick insulating film are removed (the removed part is indicated by a broken line) may be used.

  That is, the semiconductor device of this embodiment is characterized in that the silicon oxide films 9032 and 9034 are formed above and below the silicon nitride film 9033. In this way, by sandwiching the silicon nitride film 9033 with relatively many levels in the film and at the interface between the silicon oxide films 9032 and 9034, unnecessary charges enter from above and below by electrolysis and are trapped in the silicon nitride film or the interface. Can be suppressed.

(Example in which EOT (equivalent oxide film thickness) is different)
When a circuit is configured and operated using TFT transistors, power consumption is reduced by driving with a low voltage. For this reason, it is sufficient that the power consumption of all TFTs can be reduced, but there are many cases where the voltage cannot be reduced in an input / output unit or the like.

  On the other hand, in the case of forming TFTs, conventionally, since the gate insulating film could not be prepared with a plurality of film thicknesses, the gate insulating films of all TFTs were designed for high voltage. For this reason, all TFTs including a gate insulating film designed for high voltage can only be used in common, and low power consumption cannot be realized. However, according to the present invention, it has become possible to easily form an insulating film having two or more different thicknesses by EOT.

  For example, when a thick film and a thin film are formed with the same silicon oxide film, the EOT also has a thick film and a thin film according to it. Further, as shown in FIGS. 14B and 14D of this embodiment, by introducing a film having a high dielectric constant into an insulating film region where a thin EOT is desired to be realized, an insulating film having a thick EOT and a thin insulating film can be obtained. It can be divided into membranes. Therefore, by doing in this way, it is possible to reduce the voltage of the circuit constituted by the TFT.

  In other words, the semiconductor device of this embodiment is characterized in that either one of the first and second insulating films is formed with a thin EOT (equivalent oxide film thickness). Thereby, a transistor with a thin EOT can be used as a low-voltage driving transistor.

(Example of forming a memory)
The memory mentioned here is a non-volatile memory. In order to form a memory, a charge holding film and a transistor capable of applying a high voltage capable of writing / erasing to the film are required. All of these materials are already included in the contents described above.

  A silicon nitride film having many levels can be used for the charge retention film. The fact that unnecessary charges are trapped by this level can be used for writing and erasing. In addition, since these writing and erasing are performed intentionally, if the writing and erasing are not performed in a short time (for example, 1 second or less), the usability is reduced, so that a high voltage needs to be applied. In order to apply a high voltage, a transistor having a gate insulating film thicker than that of the memory portion is required. However, since these structures can also be achieved in each of the above embodiments, it may be used.

  For the memory portion, as shown in FIG. 14C and FIG. 14D, a structure having a recon nitride film sandwiched between silicon oxide films is optimal, and the charge captured by the write or erase operation is external. Can be prevented from escaping.

  In addition, when performing a write / erase operation of a memory, in many cases, a write / erase operation can be efficiently performed if a voltage can be applied to the channel region. For example, there are a case where charges are taken in and out by FN injection, and a case where charges are injected by generating a reverse junction current in the channel region and the source / drain regions. In order to implement these, it is necessary to be able to apply a voltage to the channel region, and it is optimal to adopt a memory structure having a body contact region 706a as shown in FIGS.

  That is, since charges can be intentionally injected and captured in a silicon nitride film having many levels, this phenomenon can be used as a memory.

<Twelfth embodiment>
The twelfth embodiment relates to a TFT substrate manufactured using TFTs having different EOTs that can be realized in the above-described embodiments. Hereinafter, the TFT substrate of Embodiment 12 will be described with reference to FIG. However, FIG. 15 is a top view of the TFT substrate.

  A TFT substrate in which TFTs are formed in an array is used for a liquid crystal display panel, an organic EL panel, and the like, and the demand is increasing. In addition, cost reduction is important, and the number of parts is being reduced. Furthermore, low power consumption is also regarded as important due to environmental problems.

  This TFT substrate controls a pixel region 1002 in which a TFT array for controlling pixels by TFTs is formed on a glass substrate 1001, a gate driver region 1003 for controlling the gate voltage of the pixel TFT, and a source voltage of the pixel TFT. A source driver region 1004 and a non-volatile memory unit (attached component) 1006 that holds display correction data are formed.

  In the twelfth embodiment, since a low voltage TFT can be formed, a low consumption TFT can be designed by using a low voltage TFT as a TFT for calculating signal data to be transmitted to the pixel TFT of the output unit. Become. In addition, since the nonvolatile memory can be formed as described above, the components of the nonvolatile memory portion 1006 that are separately attached are not necessary, and the nonvolatile memory 1007 can be formed in the empty space by the TFT. For this reason, the cost of the TFT substrate can be reduced.

<Embodiment 13>
The thirteenth embodiment relates to a liquid crystal panel on which a TFT substrate manufactured using TFTs having different EOTs that can be realized in the above-described embodiments is mounted. The liquid crystal panel of the present embodiment will be described with reference to FIGS. However, FIG. 16 is a cross-sectional view of the liquid crystal panel.

  The liquid crystal panel of the thirteenth embodiment is manufactured by enclosing a liquid crystal 1103 through a sealing material 1104 between the TFT substrate 1101 and the color filter substrate 1102 created in the above twelfth embodiment. The power consumption and cost of the liquid crystal panel can be reduced depending on the performance of the substrate 1101. Moreover, it can be used not only for a liquid crystal panel but for an organic EL display, and the same effect can be obtained.

  In addition, when the liquid crystal panel shown in FIG. 16 is manufactured, the reference value of the voltage applied to the color filter substrate 1102 side needs to be stored in the liquid crystal panel, and the nonvolatile storage formed in 1007 in FIG. Can be used. It is also possible to store a gamma correction value used for display in the non-volatile memory 1007 in that area. These “reference value of voltage applied to the color filter substrate side” and “gamma correction value used for display” are data attached to the liquid crystal panel, and therefore can be designed and arranged with TFTs in the substrate constituting the liquid crystal panel. However, the design is easier and the development cost can be reduced than using the pasted component (nonvolatile memory portion 1006 in FIG. 15). In addition, the memory designed with the TFT in the substrate has the advantage that the wiring is shorter and the access can be made faster.

  Here, the reference value of the voltage applied to the color filter substrate side will be described with reference to FIG.

  In FIG. 17, a lower portion 1201 surrounded by a circle is the TFT substrate side, and a liquid crystal 1203 is disposed on the drain side of the TFT. An upper portion 1202 surrounded by a circle on the opposite side of the liquid crystal is the color filter substrate side, and has a common electrode for all pixels, so that a common voltage can be applied to the entire liquid crystal. The voltage reference value is a reference value of a voltage applied to the common electrode.

  The voltage reference value is a correction value that takes into account the variation of each liquid crystal panel. The correction value is stored in the memory unit 1204, and data is sent from the correction value to the voltage generation circuit 1205, whereby a reference voltage is generated in the voltage generation circuit 1205.

  Next, gamma correction values used for display will be described with reference to FIG.

  The gamma correction value is all information used on the TFT substrate in terms of circuit and has no electrical relationship with the color filter substrate. Specifically, a digital signal serving as display data is input to the DA converter 1302 from a display data generation circuit 1301 outside the liquid crystal panel. The DA converter 1302 converts a digital signal into an analog signal and transmits the analog signal to the output circuit 1303, and the output circuit 1303 transmits image data to the display unit 1304. At this time, the DA converter 1302 needs to adjust the correlation between the digital gradation data and the voltage of the analog gradation signal so that the color of the image displayed on the display unit 1304 is naturally reproduced. This correlation adjustment is adjusted based on the gamma correction value stored in the memory unit 1305. This gamma correction has a different value for each product model.

<Embodiment 14>
The fourteenth embodiment is an embodiment relating to a portable device equipped with the liquid crystal panel of the thirteenth embodiment. A portable device according to the fourteenth embodiment will be described with reference to FIG.

  FIG. 19 is an example applied to a mobile phone, and is an exploded view showing the liquid crystal panel 1403 inside so that the upper side 1401 and the lower side 1402 of the exterior are separated. The liquid crystal panel 1403 is the liquid crystal panel shown in the thirteenth embodiment, has low power consumption and a memory function, and achieves cost reduction. That is, conventionally, the non-volatile memory portion 1006 (see FIG. 15), which is an attached component, is attached to the lower region 1404 of the liquid crystal panel 1403. However, since this component is eliminated, an empty space is generated. In recent years, since the thickness and weight have been reduced and the design has been overcrowded, the location where the nonvolatile memory unit 1006 existed is not an extra space, and the liquid crystal panel can be further miniaturized by eliminating this part. be able to. Thereby, an exterior can also be made small correspondingly. In other words, the length of the mobile phone in the vertical direction can be shortened by the length indicated by reference numeral 1406 in the figure.

  In addition, since this liquid crystal panel is a component that has achieved low power consumption and low cost, even mobile phones equipped with this liquid crystal panel have low power consumption and extended usage time that can be used with a single charge. Various effects can be brought about.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 7 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 8 of this invention. It is a partially expanded sectional view which shows the structure of the semiconductor device which concerns on Embodiment 9 of this invention. It is a partially expanded sectional view which shows the structure of the semiconductor device which concerns on Embodiment 10 of this invention. It is a top view which shows the structure of the semiconductor device which concerns on the application example 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the application example 1 of this invention. It is the top view and sectional drawing which show the structure of the semiconductor device which concerns on the application example 2 of this invention. It is a partially expanded sectional view which shows the structure of the semiconductor device which concerns on Embodiment 11 of this invention. It is a top view of the TFT substrate which concerns on Embodiment 12 of this invention. It is sectional drawing which shows the structure of the liquid crystal panel which concerns on Embodiment 13 of this invention. It is a circuit block diagram for demonstrating the reference value of the voltage applied to the color filter substrate side of the liquid crystal panel which concerns on Embodiment 13 of this invention. It is a circuit block diagram for demonstrating the gamma correction value used for the display of the liquid crystal panel which concerns on Embodiment 13 of this invention. It is an exploded view which shows the structure of the mobile telephone based on Embodiment 14 of this invention. It is sectional drawing which shows the structure of an interlayer insulation film. It is sectional drawing of the semiconductor device which has a basic structure for contrasting with the semiconductor device of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device.

Explanation of symbols

101, 201, 301, 401 Insulating substrate 102a, 202a, 302a, 402a Semiconductor layer 102b, 202b, 302b, 402b Semiconductor layer 102a2, 202a2, 302a2, 402a2 Diffusion layer 102a3, 202a3, 302a3, 402a3 Diffusion layer 102b2, 202b2, 302b2 , 402b2 Diffusion layer 102b3, 202b3, 302b3, 402b3 Diffusion layer 103a, 203a, 303a, 403a First insulating film 103b, 203b, 303b, 403b Second insulating film 104a, 204a, 304a, 404a First gate electrode 104b , 204b, 304b, 404b Second gate electrode 502a1 Semiconductor layer 503ab, 603ab Insulating film 503au, 603au Insulating film 603ab1 Edge portion 604 Gate electrode 604ab Protrusion 702a Semiconductor layer 703b1 Insulating film 702a1 Channel region 702a2, 702b2 Source region 702a3, 702b3 Drain region 702b2, 702b3 Diffusion layer 703b, 705a Insulating film 703a1, 703b1 Gate insulating film 704a, 704b Layer 802a2 source region 802a3 drain region 802a1 channel region 803a2 insulating film 804a gate electrode 902 semiconductor layer 9031, 9032 silicon oxide film 9033 silicon nitride film 100 glass substrate 1002 pixel region 1003 gate driver region 1004 source driver region 1006 non-volatile memory part Attached parts)
1007 Nonvolatile memory 1101 TFT substrate 1102 Color filter substrate 1103 Liquid crystal 1104 Sealing material 1203 Liquid crystal 1204 Memory unit 1205 Voltage generation circuit 1301 Display data generation circuit 1302 DA converter 1303 Output circuit 1304 Display unit 1305 Memory unit

Claims (15)

In the semiconductor device in which the first and second transistors are formed on the same insulating substrate,
The first transistor includes a first insulating film formed under the first gate electrode and a second insulating film formed on the diffusion layer region,
The second transistor includes the second insulating film formed on the lower portion of the second gate electrode and the diffusion layer region,
The first and second gate electrodes are disposed above the first insulating film and the second insulating film, respectively, and the first insulating film is formed thinner than the second insulating film. And
The second insulating film of the first transistor is formed so as to penetrate from the lower surface edge of the first gate electrode to the inside,
The semiconductor device according to claim 1, wherein the diffusion layer region of the first transistor is formed so as to overlap under the first insulating film. In the semiconductor device in which the first and second transistors are formed on the same insulating substrate,
The first transistor includes a first insulating film formed below the first gate electrode and on the diffusion layer region,
The second transistor includes a second insulating film formed below the second gate electrode, and the first insulating film formed on the diffusion layer region,
The first and second gate electrodes are disposed above the first insulating film and the second insulating film, respectively, and the first insulating film is formed thinner than the second insulating film. And
The second insulating film of the second transistor is formed to extend from the lower surface edge of the second gate electrode to the diffusion layer region;
The diffusion layer region of the second transistor is formed so as to overlap below the second gate electrode. In the first transistor according to claim 1 or the second transistor according to claim 2,
A semiconductor device, wherein a diffusion layer region is formed in a low concentration diffusion layer region and a high concentration diffusion layer region, and the low concentration diffusion region is formed on a gate electrode side. The semiconductor device according to claim 1,
The diffusion layer region of the first transistor is formed in a low concentration diffusion layer region and a high concentration diffusion layer region, and a region having a gate electrode on the upper side in the diffusion layer region is the low concentration diffusion layer region. A semiconductor device characterized by the above. The semiconductor device according to claim 2,
The diffusion layer region of the second transistor is formed in a low-concentration diffusion layer region and a high-concentration diffusion layer region, and the region having the second insulating film on the upper side in the region of the diffusion layer region is the low-concentration diffusion layer region. A semiconductor device which is a concentration diffusion layer region. The semiconductor device according to claim 1, wherein:
A semiconductor device, wherein a lower surface of a connection portion between the first insulating film and the second insulating film is connected flatly. The semiconductor device according to claim 1, wherein:
The semiconductor device according to claim 1, wherein an inclination angle of the connection portion between the first insulating film and the second insulating film with respect to the substrate surface is any angle within a range of 5 degrees to 50 degrees. The semiconductor device according to any one of claims 1 to 7,
The semiconductor device, wherein the first and second insulating films include a silicon oxide film, and one or both of the insulating films further include a silicon nitride film layer. The semiconductor device according to claim 8.
A semiconductor device, wherein the silicon oxide film is formed above and below the silicon nitride film. In the semiconductor device according to claim 8 or 9,
One of the first and second insulating films is formed with a thin EOT (equivalent oxide film thickness). The semiconductor device according to any one of claims 8 to 10,
A semiconductor device using the transistor as a memory.   12. A TFT (Thin-Film Transistor) substrate, wherein the transistors of the semiconductor device according to any one of claims 8 to 11 are arranged in an array.   A display device comprising the TFT substrate according to claim 12. The display device according to claim 13,
The display device, wherein the memory stores a voltage correction value and a display gamma correction value for the TFT counter substrate.   A portable device comprising the display device according to claim 14.

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