JP2010009628A - Server system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a server system which has, in addition to extensibility of scale-out type of a conventional blade server system, extensibility of scale-up type by making SMP (Symmetric Multi Processing) coupling among a plurality of blade server modules. <P>SOLUTION: A node controller in each blade server module has an SMP coupling interface, and is coupled via a back plane. Links among individual blade server modules are laid through equidistant wiring lines on a back plane and besides a loop wiring line having length equal to that of the links among the individual blade server modules on the back plane is also laid in each blade server module, thereby setting up synchronization. Each blade server module has a reference clock distribution unit mounted on the back plane and adapted to distribute reference clocks and by switching reference clocks by a clock distribution circuit inside each blade server module, synchronization of reference clocks for SMP coupled blade server modules can be established. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a server system capable of constructing a high-performance scale-up server by tightly coupling a plurality of scale-out type server modules. In particular, the present invention relates to a multi-node SMP server apparatus in a symmetric multiprocessor system (SMP).

  As a means for expanding the arithmetic processing capability in the conventional server device, it can be classified into two methods called “scale-out” and “scale-up”. The scale-out method is an expansion method that improves the overall processing capacity by distributing the processing to multiple server devices, as represented by the blade server system. Effective in some cases. The scale-up method is an expansion method that improves the processing capacity of a single server device by increasing the speed and increasing the number of processors and increasing the memory capacity, as represented by SMP (Symmetric Multi Processing) systems. It is effective for high-load single process processing. As described above, since the blade server system and the SMP system have different characteristics, it is general to select an appropriate method according to the application and business contents when constructing the system. In fact, in the Internet Data Center (IDC), a blade server device suitable for scale-out as a WEB server that executes a large amount of relatively light processing such as WEB front-end processing performs processing that requires a large amount of memory, such as a large-scale database. The database server to be used is properly used as an SMP server device suitable for scale-up. At first glance, this seems to be very efficient at the right place for the right person, but because each server has its own dedicated server device, it becomes cumbersome to manage and is not necessarily efficient in terms of operational costs. It is hard to say that it is in good condition. In addition, as a known solution to a sudden change in system requirements in a rapidly changing business environment, firstly, the addition of hardware can be mentioned. For example, in a scale-out type blade server, an increase in the blade server module, in a scale-up type SMP server, an increase in hardware resources such as a processor and memory, or an increase in hardware resources with higher performance, This is also one of the factors that hinder TCO reduction.

  In a multi-node SMP configuration, it is necessary to transmit a memory address, maintain cache coherency, and transfer data in units of blocks of the size of the cache line. The processor has a cache memory that stores frequently used data blocks. Common cache block sizes are 32, 64, or 128 bytes and are called cache lines. If the required data is not in the cache (cache miss), the processor requests the required data from another processor. If there is no modified copy of the requested block in any processor or I / O controller, the block is retrieved from memory. In order to obtain permission to change a block, the processor that fetches the block from memory must become the owner of the block. When a processor with change permission becomes the owner, all other devices invalidate the copy held, and the previous owner passes the data requested by the processor with change permission to the new owner. After passing the data requested by the processor to which the previous owner has obtained permission to change to the new owner, if another processor attempts to share a read-only copy of the requested data from the owning processor, the data Provided by (not memory). When the owning processor needs free space in the cache to write new data, it writes the cache block to memory and the memory becomes the owner again. The process of finding the latest copy of a cache block is called “cache coherency”. System designers maintain memory consistency from the perspective of each processor using two main methods: broadcast coherency and directory coherency.

  In broadcast coherency, all addresses are sent to all nodes. Each device examines (snoops) what state the requested cache line is in the local cache. Broadcast coherency minimizes latency because the system determines the overall snoop result after several cycles after each device examines the state of the requested cache line in the local cache. To the limit.

  In directory coherency, in response to an access request from a processor, an address is transmitted only to a node (home node) that manages the address of a specific cache block. The hardware manages which nodes share or own which cache block using a directory in memory, special RAM, or a control device. Since the "directory" is embedded in the memory, the controller needs to check the directory information by accessing the memory every time. In principle, the protocol becomes complicated, so the delay becomes longer and the delay varies. growing.

  In order to realize a multi-node SMP configuration, a crossbar switch is generally used when cache coherency control is controlled between multiple nodes. However, the fact that the transaction must pass through the crossbar switch has a problem that the latency becomes worse because one device is added to the path through which the transaction must pass, compared to the case where there is no crossbar switch. Looking at the round trip path between the request system transaction and the response system transaction, there is a considerable difference in latency when the crossbar switch is used and when it is not used.

  Currently, there is a multi-node SMP configuration that does not have a crossbar switch, but a directory-based SMP configuration of a directory coherency method is generally used, which is one of the causes of system performance degradation due to an increase in coherency delay.

  Further, as a method for directly interconnecting nodes on a backplane, there is an example described in Patent Document 4. This shows a method of directly interconnecting nodes, but the maintenance mode of cache coherency and the transaction processing method are not specified.

JP 2004-110791 A JP2004-079930 JP 2003-216595 A JP2004070954

  An object of the present invention is to provide a server apparatus capable of physically SMP coupling between a plurality of blade server modules in addition to a function as a blade server module (also referred to as a node). An object is to realize a multiprocessor server device that can be realized simultaneously.

  It is a further object of the present invention to reduce latency in a multi-node SMP configuration. Another object is to reduce the number of parts of the apparatus, reduce the cost, reduce the failure rate, and reduce resources.

  The present invention is a server device comprising a plurality of server modules and a management unit for managing the entire device, each server module comprising a module management unit for switching the operation mode of the server module, and the module management unit comprising the management unit According to the configuration information transmitted from the server, each server module switches between operating independently or operating cooperatively with other server modules in the SMP configuration.

  The present invention further includes a server device having an SMP configuration composed of a plurality of server modules (nodes), and further comprising a backplane that mounts the plurality of nodes and connects the nodes to each other, and each node includes its own node. A node controller that transmits and receives transactions with all nodes is provided, and the node controller orders transactions.

  The present invention is further characterized in that the links between the nodes are wired with the same length on the backplane, and the synchronization is achieved by making the loop wiring with the same length with the links between the nodes on the backplane even within the own node. .

  The present invention further comprises a server device comprising a plurality of server modules, a management unit that manages the entire apparatus, and a reference clock distribution unit that distributes a common reference clock to the plurality of server modules. A reference clock generation circuit for generating a reference clock of the reference clock, and switching between a reference clock generated by the reference clock generation circuit and a common reference clock distributed from the reference clock distribution unit. A clock distributor distributed in the server module; and a module management unit that instructs the clock distributor to switch a reference clock distributed in the server module in accordance with configuration information transmitted from the management unit. To do.

  The present invention further relates to a server device comprising a plurality of server modules, a management unit that manages the entire device, and a backplane that mounts the plurality of server modules and the management unit and enables mutual signal transmission. Each server module receives a reference clock generation circuit that outputs a reference clock, and receives the reference clock signal output from the reference clock generation circuit and outputs it to the second clock distributor of the server module. A first clock distributor that outputs to the second clock distributor of the local server module and other server modules via a plane, and a reference clock signal that is output from the first clock distributor of the local server module; The local server module and other server modules input via the backplane The second clock distributor that selects and distributes one of the reference clock signals from the reference clock signal from within the server module, and the server module according to the configuration information transmitted from the management unit And a module management unit that instructs the second clock distributor to switch the reference clock to be distributed.

  According to the present invention, there is provided a server device and a blade server module having a scale-up type expandability by SMP coupling between a plurality of blade server modules in addition to a scale-out type expandability of a conventional blade server system. As a result, the server that executes these applications flexibly expands or reduces resources and optimizes them according to changes in business requirements after the system is installed. Can be reduced.

  Furthermore, according to the present invention, a crossbar switch is not required for link connection between nodes in a server device of a multi-node configuration multiprocessor, and in a multi-node SMP configuration, latency is reduced and system performance can be improved. Also, by eliminating the need for a crossbar switch, it is possible to reduce the failure rate, reduce costs, and reduce resources by reducing the number of components.

It is a system configuration figure of one embodiment of the present invention. It is a figure which shows the link between each node of 4 node SMP structure. It is an example of a structure of each node of 4 node SMP structure. It is another example of a structure of each node of 4 node SMP structure. It is another example of a structure of each node of 4 node SMP structure. It is a figure which shows the link between each node of 4 node SMP structure. It is another example of a structure of each node of 4 node SMP structure. It is a figure explaining the broadcast and coherency response in 4 node SMP structure. It is a figure explaining the example of the overtaking of a transaction. It is a figure explaining the synchronization of the transaction response using a waiting circuit. It is a structural example of a node controller. It is a structural example of a node controller. It is a processing flow figure of a node controller. It is a system block diagram for demonstrating the specific operation | movement of FIG. It is a system configuration | structure figure of other embodiment of this invention. It is a block diagram of a general blade server system.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 16 is a configuration diagram of a general blade server system. At least two or more blade server modules 110 (# 0 to #n), a service processor unit 111 that manages the entire server apparatus, and a backplane 113 that realizes signal transmission between the units by mounting these units. ing. At least one or more CPUs 22 can be mounted on the blade server module 110, the node controller 20 and the I / O circuit 24 for controlling the CPU 22 and the memory 23, and power control, configuration management, environmental monitoring, etc. inside the blade server module 110, etc. By providing the module management unit 25 having the above functions, it has a function as one server device. Each blade server module 110 includes a reference clock distribution circuit 121 including a reference clock generator 26 and a clock distributor 27, and the reference clock S21 is distributed to the LSIs operating in synchronization in the blade server module 110. However, as described above, one blade server module 110 is independent as one server device, and this clock does not need to be synchronized with a reference clock in other blade server modules.

  FIG. 1 shows an embodiment of a multiprocessor server apparatus according to the present invention. Each blade includes a plurality of blade server modules 10 (# 0 to #n), a service processor unit 11 that manages the entire server device, and a backplane 13 that implements signal transmission between the units by mounting these units. The node controller 20 in the server module 10 has an SMP coupling interface S20, and has a function of realizing a multi-node SMP configuration via the backplane 13.

  FIG. 2 shows an example of the configuration of a multi-node SMP server based on a broadcast system without a crossbar switch according to the present invention. In this figure, the case of 4 nodes is taken as an example.

  In broadcast coherency, as shown in FIG. 8, all addresses are broadcast to all nodes, and each node makes a coherency response. Each node determines the overall snoop result and makes a coherency response after several cycles of examining what state the requested cache line is in the local cache.

  As shown in FIG. 9, the time required from address broadcast to coherency response is overtaken by transactions when there are nodes near and far from the node that broadcast the address, that is, when there are short nodes and long nodes between the nodes. Will occur. In order to control the overtaking of transactions that occur due to the difference in wiring length between nodes, it is generally avoided by implementing a crossbar switch, but this method does not have a crossbar switch. The question is how to order transactions. Therefore, in FIG. 2, the links between the nodes are made the same cycle by wiring the same length in the backplane 201, and synchronization between the nodes is achieved by keeping the latency constant.

  Further, as shown in FIG. 10, the coherency response to the node itself that broadcasts the address does not need to pass through the wiring between the nodes, so there is no time for crossing the node, and more than the coherency response from the other node that issued the transaction request. Because it becomes fast, overtaking of the transaction occurs. In order to control the overtaking of transactions that occur due to lack of time for crossing nodes, a waiting circuit was implemented in the node controller.

  FIG. 11 shows the configuration of the node controller 1002. As shown in FIG. 13, the transaction issued from the CPU 1101 is transferred to the sequencer 1107 by the HOSTi / f 1106 (steps 1301, 1302). Next, the transaction is passed to the tag control circuit 1104 under the control of the sequencer 1107. The tag control circuit 1104 confirms the tag information 1103 (step 1306). In the case of Modify or Shared read on the cache, the tag control circuit 1104 returns to the sequencer 1107 (steps 1307 and 1303), and the memory i / f 1109 controls to store the memory 1111. Access is made (steps 1304 and 1305). Here, when neither Modify nor Shared read is performed on the cache, a transaction is issued from the coherency transmission unit 1105 to another node for a snoop inquiry (Steps 1308 and 1310). At this time, it is sent to the coherency response waiting circuit 1110 to the own node (step 1309).

  FIG. 12 shows an example in which a waiting circuit 1204 is mounted on the node controller 1201. The coherency response returned after the snoop process in the other node is completed is received by the coherency receiving unit 1205 on the node controller 1201. The timing of the coherency response that has been changed at the same timing by synchronization and the timing of the coherency response to the own node that is timed by the delay by the waiting circuit 1204 coincide. The transaction received by the coherency receiving unit 1105 is transferred to the sequencer 1203 and accesses the memory 1111 under the control of the memory i / f 1109.

  As shown in the circuit of FIG. 12, when the server is started, the firmware 1206 calculates the response time from each node of the transaction request destination and the time required for the response time after passing through the waiting circuit in the own node before starting the server. . Adjustment is performed by the firmware 1206 from the calculation of the time required for this response. The nodes are synchronized by making the wiring between the nodes equal in length, mounting a waiting circuit (loop wiring) in the node controller, and adjusting the response time by the firmware 1206. By synchronizing the nodes, it is guaranteed that the response after the determination of the snoop result for the corresponding broadcast address is constant, and the transaction selection order is always the same. Note that when each node is in the form of an independent server expansion, the broadcast shown in FIG. 8 does not occur.

  FIG. 3 shows a configuration example of each node in a four-node configuration of a multi-node SMP server. On the node 301, an inter-node coupling interface 307 for coupling a plurality of nodes to form one SMP is provided. Further, a node link controller 303 is mounted on the node controller 302. A node link controller interface 306 is provided on the node controller 302, and the node controllers are connected one to one by the node link controller interface 306 of each node, thereby realizing the SMP configuration. The node link controller interface 306 functions as a crossbar switch together with the node link controller 303 inside the node controller. By performing local loop wiring from the node link controller 303 to the node link controller 303 across the latch 304, the timing with the response from each node is matched, and the same cycle is achieved by synchronizing all nodes. A function that matches the timing of the transaction response is realized by keeping the latency constant. Ordering of transactions is guaranteed by realizing a function that matches the timing of transaction responses.

  The node controller 302 has a transaction transmission function and a reception function that are independent, and the node controller 302 can process the transmission and reception of transactions in parallel. The node link controller 303 broadcasts coherent transactions to all nodes in the same order. The node controller 302 having the node link controller interface 306 transfers the coherent transaction received from each node into the node controller in the same order. The node link controller interface 306 has functions of inter-node transfer of a broadcast transaction, inter-node transfer of a coherency response transaction, and inter-node transfer of a 1 to 1 transaction. Transactions flowing through the node link are protected by ECC (Error Correction Coding).

  Broadcast transactions are classified into request transactions and response transactions. The node controller 302 with node link controller interface 306 and node link controller 303 is duplexed for request transaction and response transaction, but the request transaction and response transaction are transferred without distinction on the node link. The 1 to 1 transactions are classified into address transactions and data transactions. The 1 to 1 transaction is duplicated for the address transaction and the data transaction, but the data included in the address transaction and the corresponding data transaction is continuously transferred on the node link.

  By having a calculation circuit in the node controller that calculates how many cycles it took to transfer the link at each node, the shift between the links is notified to the firmware of each node, and the number of cycles between each node is synchronized. This is done by correcting the firmware. In addition to equal-length wiring, there is no shift between links, so it is guaranteed that the snoop for the broadcast address will be constant, and the function that matches the timing of the transaction response will be realized, and the transaction will be ordered. Guaranteed. Even if the nodes are synchronized, a node that has enough time to wait for the processing of a node that takes a long time to respond by firmware control so that the response timing does not shift due to the queue status in the node controller. The transaction selection order is guaranteed to be the same.

  FIG. 4 shows another configuration example of each node in a four-node configuration. The length of the local loop 404 in the node controller 402 is set between the nodes in the backplane 201 shown in FIG. By providing equal-length wiring and equal-length loop wiring, it is possible to realize a function that aligns the timing of transaction responses from each node, so a `` broadcast (snoopy) coherency '' snoop base that eliminates the need for crossbar switches The SMP configuration can be realized.

  FIG. 5 shows still another configuration example of each node in a four-node configuration. Snoop-based SMP configuration of the “broadcast (snoopy) coherency” method that eliminates the need for a crossbar switch even by using the backplane 201 having equal length wiring between the node links shown in FIG. 2 and the node link interface shown in FIG. Can be realized. On the node controller 502 shown in FIG. 5, there are link ports (number of nodes−1) having a function of transmitting data transfer transactions to other nodes and link ports having the function of receiving data transfer transactions to other nodes (number of nodes− 1) In addition to the inter-node connection interface 506, a node link controller interface 505 having a transmission link port for a data transfer transaction for a local loop and a reception link port for a data transfer transaction to its own node that issues a transaction request is implemented. is doing. Since the transaction transmission function and the reception function of the node controller 502 are independent, the node controller can process the transmission and reception of transactions in parallel. As shown in FIG. 4, the route 405 on the node after leaving the node link controller interface 404 has a role of delay by wiring the same length as between the node links, and the transaction response from each node The function that aligns the timing with is realized.

  FIG. 6 shows still another configuration example of each node in a four-node configuration. In addition to the equal length wiring between the nodes in the backplane 201 shown in FIG. 2, the loop wiring 606-609 to each node in the backplane 601 as shown in FIG. By wiring with the same length, the transaction response timing is aligned. In this case, as shown in FIG. 7, the inter-node connection interface 705 simply prepares the node link ports of the data request transaction transmission unit and the reception unit in the node controller 702, and latches in the node controller. It is not necessary to provide interleaved loop wiring and loop wiring of the same length between the nodes.

  Further, the present invention is a blade server in which each node is a server blade in a multi-node configuration multiprocessor server apparatus, and requires an external crossbar switch by ordering data transfer transactions inside the node controller. The inter-node link connection method is adopted, and it is possible to add a processor to the target multiprocessor configuration or to add an independent server.

  In FIG. 1, since it is indispensable that the reference clocks are synchronized between the server modules in order to make the SMP coupling between the blade server modules 10 higher performance, the reference clocks can be distributed to all the blade server modules 10. The reference clock distribution unit 14 is mounted on the backplane 13, the distributed reference clocks are wired in the backplane 13 at the same length, and the reference clock is distributed by the clock distributor 27 in the reference clock distribution circuit 21 in each blade server module 10. By switching these, the synchronization of the reference clocks of all the blade server modules 10 can be realized.

  The above-described clock switching operation will be specifically described with reference to a typical system configuration example with reference to FIG. In this system configuration example, four blade server modules 10 (# 0 to # 3) are mounted on the backplane 13, and # 0 and # 1 are coordinated as one SMP server. When the configuration is to be used as an independent blade server, the user first sets the system configuration information for the service processor unit 11 via the management software. The configuration information set here is stored in the memory 28 in the service processor unit 11 and is not erased even when the power is turned off. The module in the blade server module 10 from the service processor unit 11 every time the system is started. This is transmitted to the management unit 25. Each module management unit 25 instructs the reference clock distribution circuit 21 to switch the reference clock to be used according to the configuration information transmitted from the service processor unit 11. In this configuration example, the SMP server is configured by synchronizing the reference clocks of # 0 and # 1 by switching the reference clock of the blade server modules # 0 and # 1 to the external reference clock, and the blade server module # 2, By switching the reference clock of # 3 to the internal reference clock, it can operate as an independent server. By providing system configuration information related to clock switching of each blade server module 10 in the memory 28 in the service processor unit 11, even when a failure occurs in the blade server module 10 and maintenance replacement is performed, the configuration information is not taken over. There is an effect that the procedure is unnecessary. Further, it is possible to improve the reliability of the entire system by duplicating the service processor unit 11 for centrally managing the system configuration information as shown in the figure.

  In FIG. 15, another embodiment different from the embodiment described in FIGS. 1 and 14 will be described. 15 is the same as the embodiment shown in FIGS. 1 and 14 except for functions related to clock distribution, and therefore illustration and description thereof are omitted. In the embodiment described so far, the reference clock is distributed from the reference clock distribution unit 14 to each blade server module 10 as shown in FIGS. 1 and 14, but in the embodiment of FIG. The function is incorporated in the blade server module 10. First, the output clock signal of the reference clock generator 26 is input to the first clock distributor 30, and the output of this clock distributor includes the second clock distributor 29 and the backplane 13, including itself. Are connected to the clock distributors 29 in all blade server modules 10 that can constitute the SMP server by equal-length wiring. The output of the second clock distributor 29 is switched by the module management unit 25. For example, in the configuration of FIG. 15, the second clock distributor 29 on the blade server module # 0 selects the clock signal S22, and the second clock distributor 29 on the blade server module # 1 selects the clock signal S23. Assume that the second clock distributor 29 on the blade server module # 2 selects the clock signal S24, and the second clock distributor 29 on the blade server module # 3 selects the clock signal S25. By doing so, it is possible to configure one SMP server A 1500 with the blade server modules # 0 and # 1, and configure one SMP server B 1501 with # 2 and # 3. As described above, according to this embodiment, since the reference clocks of the two SMP servers are completely independent, the combination of blade server modules # 0, # 1 and # 2, # 3 It is possible to implement the same server chassis mixed mounting of SMP servers composed of blade server modules having different frequencies, for example, heterogeneous or next generation blade server modules.

10 blade server module 11 service processor unit 13 backplane 14 reference clock distribution unit 20 node controller 21 reference clock distribution circuit 22 CPU
23 Memory 24 I / O Circuit 25 Module Management Unit 26 Reference Clock Generation Unit 27 Clock Distributor 28 Memory in Service Processor Unit 29 Second Clock Distributor 30 First Clock Distributor 1500 SMP Server A
1501 SMP server B
S20 SMP coupling interface S21 to S25 Reference clock 201 Backplane 202 to 205 Node (blade server module)
301 nodes (blade server module)
302 Node controller 303 Node link controller 304 Latch 305 Local loop wiring 306 in the node controller Node link controller interface 307 Inter-node connection interface 401 Node (blade server module)
402 Node controller 403 Node link controller 404 Local loop wiring 405 on the node controller Node link controller interface 406 Internode connection interface 501 Node (blade server module)
502 Node controller 503 Node link controller 504 Node link controller interface 505 Local loop wiring on node 506 Internode connection interface 601 Backplane 602 to 605 with equal length wiring between node links Node (blade server module)
606 to 609 Local loop wiring 701 to the own node Node (blade server module)
702 Node controller 703 Node link controller 704 Node link controller interface 705 Inter-node connection interface 801-804 Node (blade server module)
1101 CPU
1102 Node controller 1103 Tag 1104 Tag control circuit 1105 Coherency transmission unit 1106 HOSTi / f
1107 Sequencer 1108 Coherency receiver 1109 Memory i / f
1110 Waiting circuit 1111 Memory 1201 Node controller 1202 Coherency transmission unit 1203 Sequencer 1204 Waiting circuit 1205 Coherency reception unit 1206 Firmware

Claims (6)

In an SMP server device composed of a plurality of server modules (hereinafter referred to as nodes),
A backplane for mounting the plurality of nodes and interconnecting the nodes;
Each node
A node controller having a transmission unit that transmits a transaction with all nodes including its own node and a reception unit that receives a transaction with all nodes including its own node;
Receiving a transaction transmitted from the transmission unit of the own node, and after a predetermined time delay, comprising a waiting circuit for transmitting the received transaction to the reception unit of the own node,
A server apparatus, wherein the node controller orders transactions.   2. The node controller according to claim 1, wherein each node controller has a path for transferring a transaction to another node controller and the own node controller, and the number of transfer cycles between all nodes including the own node is the same. Server device.   3. The server apparatus according to claim 2, further comprising means for adjusting the number of transfer cycles in a transfer path between the nodes within each node.   2. The server apparatus according to claim 1, wherein each node controller includes means for adjusting a response time of a transaction between other nodes and between the own nodes.   The server device according to claim 1, wherein the node controller includes the waiting circuit.   The server device according to claim 5, wherein the waiting circuit is a latch.

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