JP2009301453A - Distributed memory type multiprocessor system, masked reverse shift communication method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a distributed memory type multiprocessor system capable of accelerating the execution speed of parallel loops and reducing a used memory amount. <P>SOLUTION: The distributed memory type multiprocessor system for dividing and arranging array data on the storage means of a calculation node and parallelly executing a loop in a program for using and defining the array data on a calculation means includes a masked reverse shift communication means for having the calculation node store a value for use and definition in a buffer for masked reverse shift communication secured in an area continued to the array data of its own calculation node during parallel loop execution, communicate the value in the buffer for the masked reverse shift communication for which the definition is performed through an inter-calculation-node communication means to another calculation node after the parallel loop execution and reflect it on a corresponding array element arranged on another calculation node, in the case that an array element defined by each calculation node is the array element divided and arranged on the storage means of another calculation node. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention comprises a plurality of calculation nodes each having calculation means and storage means, divides and arranges array data on the storage means of the calculation nodes, and uses a loop in a program for using / defining the array data as the calculation means. The present invention relates to a distributed memory type multiprocessor system to be executed in parallel, a masked reverse shift communication method and program for the distributed memory type multiprocessor system.

  In general, in a distributed memory multiprocessor system, array data is divided and arranged in calculation nodes, and when a loop in a program that uses and defines such array data is executed in parallel on a calculation means, When the array element defined by the computation node is an array element that is divided and arranged on another computation node, communication via the computation node communication means is required.

  When communication between computation nodes as described above becomes necessary, the entire array to be defined is copied to a temporary array immediately before the parallel loop, and in the parallel loop, the temporary array is referenced and the parallel loop is executed. Later, parallel execution is performed by copying the value from the temporary array to the original defined array and writing back the value.

  In the parallel execution of the above-described method, the memory capacity of the entire defined array is required for the temporary array, and between the entire defined array and the temporary array before and after the parallel loop execution, respectively. There was a problem that the performance deteriorated because a copy accompanied by communication occurred.

For example, as shown in FIG.
In the case of a program in the Performance Fortran) language, as shown in FIG. 7, in the related technology method, the entire array B to be defined is copied to the temporary array BUFF immediately before the parallel loop, and in the parallel loop, the temporary array BUFF is copied. The parallel execution is performed in such a manner that the reference is performed, and after the parallel loop is executed, the value is copied from the temporary array BUFF to the original defined array B and the value is written back.

  In this case, the temporary array BUFF requires a memory capacity corresponding to the entire defined array B, and between the entire defined array B and the temporary array BUFF before and after execution of the parallel loop, respectively. Performance drops due to the occurrence of copying with communication.

(Object of invention)
An object of the present invention has been made in view of the above problems, and is a distributed memory multiprocessor system capable of increasing the execution speed of a parallel loop and reducing the amount of memory used, and reverse shift with mask. It is to provide a communication method and a program.

A distributed memory type multiprocessor system according to the present invention comprises a plurality of calculation nodes having calculation means and storage means, divides and arranges array data on the storage means of the calculation node, and uses / defines the array data. A distributed memory type multiprocessor system that executes the loops in parallel on the calculation means, and the array elements defined in each calculation node are array elements that are divided and arranged on the storage means of other calculation nodes During parallel loop execution, the value to be used / defined is stored in the reverse shift communication buffer with mask secured in the area contiguous with the array data of its own computation node, and the mask defined after execution of the parallel loop The value of the reverse shift communication buffer is communicated to the other calculation node via the communication means between the calculation nodes, and is placed on the other calculation node. An inverse shifting communication means with the mask to be reflected in the corresponding array element.

  A reverse shift communication method with a mask according to the present invention comprises a plurality of calculation nodes having calculation means and storage means, and arranges and arranges the array data on the storage means of the calculation node, and uses / defines the array data. A reverse shift communication method with a mask of a distributed memory type multiprocessor system that executes a loop in parallel on a calculation means, wherein array elements used and defined in each calculation node are divided and arranged on a storage means of another calculation node When the parallel loop is running, the value to be used / defined is stored in the masked reverse shift communication buffer secured in the area contiguous with the array data of its own computation node. Communicates the value of the defined reverse shift communication buffer with mask to the other calculation node via the communication node between calculation nodes, and performs the other calculation. Is reflected in the corresponding array elements are arranged on the over-de.

  A program according to the present invention includes a plurality of calculation nodes each having calculation means and storage means, divides and arranges array data on the storage means of the calculation node, and uses a loop in the program that uses and defines the array data on the calculation means. Is a program that executes reverse shift communication with a mask of a distributed memory type multiprocessor system that is executed in parallel, and array elements that are used and defined in each computation node are divided and arranged on the storage means of other computation nodes If it is an array element, the value to be used / defined is stored in the reverse shift communication buffer with mask secured in the area contiguous with the array data of its own computation node during parallel loop execution, and defined after executing the parallel loop Communicating the value of the masked reverse shift communication buffer that has been performed to other computation nodes via the computation node communication means To execute the reverse shift communication processing with the mask to be reflected in the corresponding array elements are arranged on the over-de.

  According to the present invention, the execution speed of the parallel loop can be increased, and the amount of memory used can be reduced.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(Configuration of the embodiment)
Referring to FIG. 1, data of a program executed on the distributed memory multiprocessor system 100 is divided and arranged on a storage unit 103 (for example, a main storage memory) of a calculation node 101, and a certain calculation node 101 When the data necessary for the calculation executed by the calculation unit 102 (CPU) is divided and arranged on the storage unit 103 of the other calculation node 101, communication via the inter-calculation node communication unit 104 is performed.

  As described above, the masked reverse shift communication means 200, when it is necessary to communicate via the inter-computation node communication means 104, in the buffer area secured in the area continuous with the array data during execution of the parallel loop. Once defined values are stored, and after execution of the parallel loop, communication via the computation node communication means 104 is performed in order to reflect the defined buffer area values in the corresponding array elements. As a result, the execution speed of the parallel loop is increased.

  In FIG. 2, the masked reverse shift communication means 200 includes a parallelized reference access pattern analysis means 201, a data mapping analysis means 202, an access pattern analysis means 203, a reverse shift vector analysis means 204, and a reverse shift index analysis means. 205 and reverse shift communication generation means 206 with a mask.

  In FIG. 2, a parallel loop nest including a parallelization target loop that is parallelized based on the reference access pattern of the reference array of parallelization is included in the program executed on the distributed memory type multiprocessor system 100 in FIG. In the case where there are several, first, the parallelization reference access pattern analysis unit 201 sets the subscript s of the reference access pattern for each parallel loop nest in each distributed dimension of the reference array for parallelization as the condition in FIG. 301 is checked, and only the parallel loop nest satisfying the condition is selected as the target parallel loop nest of the masked reverse shift communication.

  Next, the data mapping analysis unit 202 performs the data mapping of each array appearing in the parallel loop nest for each of the target parallel loop nests of the masked reverse shift communication selected by the parallelization reference access pattern analysis unit 201. Analyze and extract a sequence having the same mapping as the reference sequence for parallelization.

  Next, the access pattern analysis unit 203 extracts the parallelization criterion extracted by the data mapping analysis unit 202 for each target parallel loop nest of the reverse shift communication with mask selected by the parallelization criterion access pattern analysis unit 201. For each occurrence of each array having the same mapping as the array in the parallel loop nest, an access pattern in which the subscript s ′ corresponding to the distributed dimension of the parallelized reference array satisfies the condition 302 in FIG. Select as target access pattern for reverse shift communication with mask.

  At this time, the dimension satisfying the condition 302 in FIG. 3 is referred to as a target dimension of the masked reverse shift communication.

  Further, an array having an appearance selected as a target access pattern for masked reverse shift communication by the access pattern analyzing unit 203 is referred to as a masked reverse shift communication target array.

  Next, the inverse shift vector analysis unit 204 applies the reference access pattern in the distributed dimension of the parallelized reference array to each of the target parallel loop nests of the masked reverse shift communication selected by the parallelization reference access pattern analysis unit 201. For each corresponding combination of the subscript and the target access pattern of the reverse shift communication with mask selected by the access pattern analysis means 203, the subscript of the target dimension of the reverse shift communication with mask is represented by the condition 303 in FIG. A certain “o′−o” is calculated as an inverse shift vector.

  The reverse shift vector is called downward when it is a negative value, upward when it is a positive value, and its absolute value is called a reverse shift width.

  Further, the reverse shift vector analysis unit 204 corresponds to the masked reverse shift communication target array selected by the access pattern analysis unit 203, and is the target access pattern of the masked reverse shift communication selected by the access pattern analysis unit 203. The maximum positive value and the minimum negative value are calculated from the set of inverse shift vectors of the target dimension of masked inverse shift communication for all occurrences.

  These absolute values are referred to as the upward reverse shift communication buffer width and the downward reverse shift communication buffer width in the dimension of the masked reverse shift communication target array, respectively.

  When there is no positive value, the maximum positive value is “0”, and when there is no negative value, the minimum negative value is “0”.

  Next, the reverse shift target index analysis unit 205 adds each mask selected by the access pattern analysis unit 203 to each target parallel loop nest of the reverse shift communication with mask selected by the parallelized reference access pattern analysis unit 201. A value satisfying the condition 304 in FIG. 3 among subscripts of the target dimension of masked reverse shift communication of the target access pattern of reverse shift communication is calculated as a reverse shift target index.

  Next, the masked reverse shift communication generation unit 206 selects the mask selected by the access pattern analysis unit 203 for each target parallel loop nest of the masked reverse shift communication selected by the parallelization reference access pattern analysis unit 201. When the allocated reverse shift communication target array is dividedly arranged on the storage means 103 of the calculation node 101 in FIG. 1, when the distribution index allocation index range in each calculation node is (lb: ub), the upward direction, In order to allocate the reverse shift communication buffer with mask by the upward reverse shift communication buffer width hs and the downward reverse shift communication buffer width ls calculated by the reverse shift vector analysis unit 204 in the downward direction, Extend to (lb−ls: ub + hs).

  Further, the masked reverse shift communication generation means 206 communicates from the corresponding array element to the masked reverse shift communication buffer of the masked reverse shift communication target array, that is, in FIG. Communication via the inter-computation node communication means 104 (shift communication) from the computation node 101 in which the array element corresponding to the buffer is arranged to the computation node 101 in which the corresponding masked reverse shift communication buffer is arranged ) Is generated before executing the parallel loop nest.

  In addition, the masked reverse shift communication generating unit 206 has a corresponding array from the reverse shift communication buffer corresponding to the reverse shift target index determined by the reverse shift target index analyzing unit 205 for each masked reverse shift communication target access pattern. Communication between elements, that is, between calculation nodes in FIG. 1, from the calculation node 101 in which the reverse shift communication buffer corresponding to the reverse shift target index is arranged to the calculation node 101 in which the corresponding array element is arranged A command for performing communication (reverse shift communication) via the communication unit 104 after executing the parallel loop nest is generated.

  By the above method, since the array element defined in each computation node 101 is an array element that is divided and arranged on the storage means 103 of another (remote) computation node 101 during parallel loop execution, When communication via the node-to-node communication means 104 is required, the reverse with a mask reserved for the (local) computation node that performs the operation, not the other (remote) computation node, during execution of the parallel loop The value is used / defined for the shift communication buffer, and after execution of the parallel loop, the value of the masked reverse shift communication buffer that has been defined is placed on another (remote) computation node. In order to reflect in corresponding array elements, parallel execution can be performed at high speed by performing communication via the inter-computation node communication means 104.

(Operation of the embodiment)
Next, the overall operation of this embodiment will be described in detail. Here, the overall operation of this embodiment will be described in detail with reference to a program example in the HPF language shown in FIG.

  Referring to FIG. 1, the data A, B, and C of the program in the HPF language shown in FIG. 4 executed on the distributed memory multiprocessor system 100 are divided and arranged on the storage means 103 of the computation node 101. When the data necessary for the calculation executed by the calculation means 102 of the calculation node 101 is divided and arranged on the storage means 103 of the other calculation node 101, communication via the inter-calculation node communication means 104 is performed.

  The reverse shift communication means 200 with a mask shown in FIG. 2 is configured such that the program in the HPF language in FIG. 4 executed on the distributed memory multiprocessor system 100 in FIG. When there is a parallel loop nest of “DO J” and “DO I” including a parallelization target loop “DO J” that is parallelized based on (:, J), the operation is as follows.

  In the program in the HPF language of FIG. 4, the parallel reference array and reference access pattern are explicitly specified by the ON directive, but this may be specified by an option specification by the user, The compiler may decide automatically.

  In this case, as shown in FIG. 5, each array is divided and arranged on six processors P, and each processor P (k) (k = 1, 2,..., 6) 101, and the parallelization target loop DO J causes each processor to execute only the iteration of the loop in which the elements of the reference access pattern A (:, J) of the reference array A for parallelization are arranged. To be parallelized.

First, the parallelization reference access pattern analysis unit 201 applies a reference access pattern A to the parallel loop nest composed of “DO J” and “DO I” in the second dimension which is the distribution dimension of the reference array A for parallelization. Recognizing that the subscript of (:, J) satisfies the following condition corresponding to the condition 301 in FIG.
The parallel loop nest consisting of “J” and “DO I” is selected as the target parallel loop nest of masked reverse shift communication.

Condition 301:
“With respect to the subscript J of the reference access pattern A (:, J) in the second dimension, which is the distributed dimension of the reference array A for parallelization, a control variable is included in the parallel loop nest consisting of“ DO J ”and“ DO I ”. There exists a parallelization target loop DO J whose J is J and satisfies the following condition. "
“J can be expressed as J's linear expression J = 1 * J + 0, and the coefficient 1 of the linear expression and the 0th-order term 0 are invariant expressions for each loop in the parallel loop nest. "

  Next, the data mapping analysis unit 202 analyzes the data mapping of the arrays A, B, and C appearing in the loop, and the arrays A and B are evenly distributed in the second dimension, and the array C is distributed. In addition, the sequences A and B having the same mapping as the parallel reference sequence A are extracted.

Next, the access pattern analysis unit 203 applies to the parallel loop nest composed of “DO J” and “DO I” which are the target parallel loop nests of the masked reverse shift communication selected by the parallelization reference access pattern analysis unit 201. The subscript of the reference access pattern A (:, J) in the second dimension, which is the distribution dimension of the reference array A for parallelization, is used as a primary expression for the control variable J of the parallelization target loop in the parallel loop nest.
= 1 * J + 0, each occurrence A (I, I, I) of the arrays A and B having the same mapping as the reference array A for parallelization extracted by the data mapping analysis unit 202 is expressed in the parallel loop nest. For J), B (I, J), and B (I, J-1), the subscript s ′ corresponding to the distributed dimension of the parallel reference array is an access pattern that satisfies the condition 302 in FIG. Select as target access pattern for reverse shift communication with mask.

  Here, the access pattern analysis means 203 performs the conditions in FIG. 3 for each occurrence A (I, J), B (I, J), B (I, J-1) in the parallel loop nest as follows. Whether there is an access pattern that satisfies 302 is analyzed.

1. When the subscript of each dimension corresponding to the second dimension, which is the distributed dimension of the parallel reference array, is A (I, J) J = 1 * J + 0, where 0 is an invariant expression for each loop in the parallel loop nest.
2. A (I, J) on the left side of the assignment statement is defined in the same access pattern of the same array.
3. 0-0 is the constant 0. (Not non-zero constant)
4). There is no other access pattern in the same sequence

In the case of B (I, J) J = 1 * J + 0, where 0 is an invariant expression for each loop in the parallel loop nest.
2. B (I, J) on the left side of the assignment statement is defined in the same access pattern of the same array.
3. 0-0 is the constant 0. (Not non-zero constant)
4). Other access patterns B (I, J-1) in the same array also satisfy the above conditions 1 and 2, and (-1) -0 is a constant.

In the case of B (I, J-1) J = 1 * J + (−1), where −1 is an invariant expression for each loop in the parallel loop nest.
2. B (I, J-1) on the left side of the assignment statement is defined in the same access pattern of the same array.
3. (-1) -0 is a non-zero constant -1.
4). Other access patterns B (I, J) in the same array also satisfy the above conditions 1 and 2, and 0-0 is a constant.

  From the above analysis results, it is recognized that only B (I, J-1) is a target access pattern for masked reverse shift communication that satisfies the condition 302 in FIG.

  At this time, the target dimension of B (I, J-1) masked reverse shift communication is the second dimension. Array B is a masked reverse shift communication target array.

  Next, the inverse shift vector analysis unit 204 performs parallelization on the parallel loop nest composed of DO J and DO I, which are target parallel loop nests of the masked inverse shift communication, selected by the parallelization reference access pattern analysis unit 201. The subscript of the reference access pattern A (:, J) in the second dimension, which is the distribution dimension of the reference array A, is J = 1 * J + 0 as a primary expression of the control variable J of the parallelization target loop in the parallel loop nest. The second-dimensional subscript J, which is the target dimension of masked reverse shift communication, of B (I, J−1), which is the target access pattern of masked reverse shift communication, selected by the access pattern analysis unit 203 For −1 = 1 * J + (− 1), (−1) −0 = −1 is calculated as an inverse shift vector according to the condition 303 in FIG.

  Here, since the reverse shift vector is a negative value, it is downward, and its absolute value 1 is the reverse shift width.

  Further, the reverse shift vector analysis means 204 is the target access pattern B (I) of the masked reverse shift communication selected by the access pattern analysis means 203 for the masked reverse shift communication target array B selected by the access pattern analysis means 203. , J−1), the maximum positive value 0 and the negative minimum value −1 of the second-order reverse shift vector, which is the target dimension of the masked reverse shift communication, are calculated.

  The absolute values 0 and 1 are referred to as the second-direction upward reverse shift communication buffer width and the downward reverse shift communication buffer width of the second dimension, which are the dimensions of the masked reverse shift communication target array, respectively.

  Next, the reverse shift target index analyzing unit 205 performs inverse processing on the parallel loop nest composed of DO J and DO I which are the target parallel loop nests of the masked reverse shift communication selected by the parallelization reference access pattern analyzing unit 201. The shift target index is calculated as follows.

The subscript of the reference access pattern A (:, J) in the second dimension, which is the distribution dimension of the reference array A for parallelization, is defined as J = 1 as a primary expression of the control variable J of the parallelization target loop in the parallel loop nest. * Expressed as J + 0,
The subscript of the second dimension, which is the target dimension of the masked reverse shift communication, of B (I, J-1) that is the target access pattern of the masked reverse shift communication selected by the access pattern analysis unit 203 is J −1. = 1 * J + (-1)
According to the condition 304 in FIG. 3, the product (2 * 1) of 2 which is the increment value of the parallelized loop having J as a control variable and the coefficient 1 of the linear expression is modulo 1 * 2 + (−1) and A congruent value, that is, an odd value is calculated as a reverse shift target index.

  Next, the masked reverse shift communication generation unit 206 performs the parallel loop nest composed of DO J and DO I which are the target parallel loop nests of the masked reverse shift communication selected by the parallelization reference access pattern analysis unit 201. The processor P (k) corresponding to each calculation node 101 when the masked reverse shift communication target array B selected by the access pattern analysis means 203 is divided and arranged on the storage means 103 of the calculation node 101 in FIG. ) With respect to the allocation index range (5 * (k−1) +1: 5 * (k−1) +5) of the second dimension of the dispersion dimension, the reverse shift vector analysis means 204 is respectively upward and downward. The reverse shift communication buffer with mask is allocated only for the calculated upward reverse shift communication buffer width 0 and downward reverse shift communication buffer width 1. Therefore, the allocation index range is expanded to (5 * (k−1): 5 * (k−1) +5).

  In FIG. 6, the allocation range in each processor of the array B is illustrated, and the hatched elements are masked reverse shift communication buffers.

  Further, the masked reverse shift communication generation means 206 communicates from the corresponding array element to the masked reverse shift communication buffer of the masked reverse shift communication target array B, that is, in FIG. Communication via the inter-computation node communication means 104 (shift) from the computation node 101 in which the array element corresponding to the communication buffer is arranged to the computation node 101 in which the corresponding masked reverse shift communication buffer is arranged As shown by reference numeral 601 in FIG. 6, an instruction for performing communication) before parallel loop nest execution is generated.

  Further, the masked reverse shift communication generation unit 206 performs reverse shift corresponding to the reverse shift target index determined by the reverse shift target index analysis unit 205 for the masked reverse shift communication target access pattern B (I, J−1). Communication from the communication buffer to the corresponding array element, that is, from the calculation node 101 in FIG. 1 in which the reverse shift communication buffer corresponding to the odd index value that is the reverse shift target index is arranged. Then, an instruction for performing communication via the inter-computation node communication means 104 to the computation node 101 in which the corresponding array element is arranged after execution of the parallel loop nest is generated as indicated by 602 in FIG.

  By the above method, since the array element defined in each computation node 101 is an array element that is divided and arranged on the storage means 103 of another (remote) computation node 101 during parallel loop execution, When communication via the node-to-node communication means 104 is required, the reverse with a mask reserved for the (local) computation node that performs the operation, not the other (remote) computation node, during execution of the parallel loop Correspondence that the value of the masked reverse shift communication buffer is defined on another (remote) computation node after the parallel loop is executed and the value is used / defined for the shift communication buffer. In order to reflect in the array elements to be performed, by performing communication via the inter-computation node communication means 104, parallel execution can be performed at high speed.

(Effects of the first embodiment)
The effect by this Embodiment is demonstrated.
The first effect is that the execution speed of the parallel loop can be increased even when there is remote access to the defined array element. The reason is that when array elements to be used / defined are placed on other computation nodes, values are temporarily stored in the buffer area reserved in the area adjacent to the array data during parallel loop execution.・ Use and remote access is required by communicating the value corresponding to the defined element in the buffer area to the corresponding array element of the other computation node after reflecting the value after the parallel loop is used. This is because the overhead of copying between the array and the temporary array can be reduced.

  The second effect is that the amount of used memory can be reduced. The reason is that, when the array element to be defined is placed on another computation node, it is defined in an area adjacent to the array data, rather than assigning a temporary array having the same shape as the entire array. This is because the buffer area is allocated for the remote elements.

  That is, as the buffer area, it is only necessary to allocate an array element that is divided and arranged on the storage means of another calculation node, so that the memory area can be saved and the buffer area can be saved. Of these, only the defined elements need to be communicated after execution of the parallel loop, so that the overhead of copying between the entire defined array and the temporary array can be reduced.

  Although the present invention has been described with reference to the preferred embodiments and examples, the present invention is not necessarily limited to the above-described embodiments and examples, and various modifications can be made within the scope of the technical idea. Can be implemented.

1 is a block diagram showing a configuration of a distributed memory multiprocessor system according to an embodiment of the present invention. It is a block diagram which shows the structure of the reverse shift communication means with a mask in the distributed memory type | mold multiprocessor system by embodiment of this invention. It is a figure which shows the content of the conditions used in the reverse shift communication means with a mask by embodiment of this invention. It is a figure which shows the example of the program by the HPF language performed on a distributed memory type | mold multiprocessor system. It is a figure explaining operation | movement of the distributed memory type | mold multiprocessor system by embodiment of this invention. It is a figure explaining operation | movement of the distributed memory type | mold multiprocessor system by embodiment of this invention. It is a figure for demonstrating the system of the parallel execution by related technology.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100: Distributed memory type multiprocessor system 101: Computation node 102: Computation means 103: Storage means 200: Reverse shift communication means with mask 201: Parallelization reference access pattern analysis means 202: Data mapping analysis means 203: Access pattern analysis means 204 : Inverse shift vector analysis means 205: Inverse shift index analysis means 206: Inverse shift communication generation means with mask

Claims (21)

A plurality of calculation nodes having a calculation means and a storage means are provided, array data is divided and arranged on the storage means of the calculation node, and a loop in a program for using / defining the array data is executed in parallel on the calculation means A distributed memory multiprocessor system,
The compute node is
When the array element defined in each calculation node is an array element that is divided and arranged on the storage means of another calculation node, during execution of the parallel loop, the area is contiguous with the array data of its own calculation node. The value to be used / defined is stored in the masked reverse shift communication buffer, and after execution of the parallel loop, the value of the masked reverse shift communication buffer that has been defined is transferred to the other via the inter-computation node communication means. A distributed memory type multiprocessor system, comprising: a masked reverse shift communication means for communicating with a corresponding computation node and reflecting the result to a corresponding array element arranged on another computation node. The masked reverse shift communication means comprises:
A parallelization reference access pattern analysis means for recognizing a parallel loop nest that is parallelized based on a reference access pattern of a parallel reference array to be subjected to masked reverse shift communication;
Data mapping that analyzes the data mapping of each array appearing in the parallel loop nest for each parallel loop nest of the reverse shift communication target with mask, and extracts the array having the same mapping as the reference array for parallelization Analysis means;
For each occurrence of the array in the parallel loop nest, an access pattern analyzing means for selecting the masked reverse shift communication target array, access pattern and target dimension;
Reverse shift vector analysis means for calculating the reverse shift communication direction and width required for the masked reverse shift communication target access pattern, and the reverse shift communication buffer width;
Reverse shift target index analysis means for calculating an index for reverse shift communication target with mask;
Extending the allocation range of the masked reverse shift communication target array by the reverse shift communication buffer width, and immediately before the parallel loop nest of the masked reverse shift communication target, from the array element corresponding to the reverse shift communication buffer, Generate a shift communication command to the reverse shift communication buffer, and immediately after the parallel loop nest of the masked reverse shift communication target, from the element corresponding to the masked reverse shift communication target index of the reverse shift communication buffer, 2. The distributed memory type multiprocessor system according to claim 1, further comprising: a reverse shift communication generation unit with a mask for generating a reverse shift communication command to an array element to be processed. The parallel reference access pattern analysis means is
For each parallel loop nest, in each distributed dimension of the parallel reference array, check whether the subscript of the reference access pattern satisfies the predetermined condition, and mask only the parallel loop nest satisfying the predetermined condition 3. The distributed memory type multiprocessor system according to claim 2, wherein a parallel loop nest for reverse shift communication is selected. The access pattern analysis means is
For each occurrence in the parallel loop nest of each array having the same mapping as the parallel reference array extracted by the data mapping analysis means, a subscript of each dimension corresponding to the distributed dimension of the parallel reference array is: 4. The distributed memory multiprocessor system according to claim 2, wherein an access pattern satisfying a predetermined condition is selected as an access pattern for masked reverse shift communication. The inverse shift vector analysis means includes
For each parallel loop nest of the reverse shift communication target with mask selected by the parallelization reference access pattern analysis means, the subscript of the reference access pattern in the distributed dimension of the parallelization reference array and the access pattern analysis means selected A reverse shift vector is calculated for each corresponding combination of subscripts in the target dimension of masked reverse shift communication for each masked reverse shift communication target access pattern,
Corresponding to the masked reverse shift communication target array selected by the access pattern analyzing means, the masked reverse shift of all occurrences that are the target access patterns of the masked reverse shift communication selected by the access pattern analyzing means Calculates the maximum positive value and the minimum negative value in the set of reverse shift vectors of the communication target dimension, and reverses the absolute value of the maximum positive value and the minimum negative value with a mask. The distributed memory multiprocessor system according to any one of claims 2 to 4, wherein an upper reverse shift communication buffer width and a lower reverse shift communication buffer width of the dimension of the shift communication target array are used. The reverse shift target index analysis means comprises:
For each of the target parallel loop nests of the masked reverse shift communication selected by the parallelization reference access pattern analysis means, the masked inverse of the target access pattern of each masked reverse shift communication selected by the access pattern analysis means 6. The distributed memory multiprocessor system according to claim 2, wherein a value satisfying a predetermined condition among subscripts of a target dimension of shift communication is calculated as an index for reverse shift. The masked reverse shift communication generating means comprises:
For the reverse shift communication with mask from the computation node in which the array element corresponding to the buffer for reverse shift communication with mask is arranged for the buffer for reverse shift communication with mask of the target array for reverse shift communication with mask Generate an instruction to perform shift communication via the inter-computation node communication means to another computation node in which the buffer is arranged before executing the parallel loop nest,
For each masked reverse shift communication target access pattern, the corresponding array element is arranged from the calculation node in which the reverse shift communication buffer corresponding to the reverse shift target index determined by the reverse shift target index analyzing means is arranged. The distributed memory according to any one of claims 2 to 6, wherein an instruction to perform reverse shift communication via the inter-computing node communication means to a computing node after execution of the parallel loop nest is generated. Type multiprocessor system. A plurality of calculation nodes having a calculation means and a storage means are provided, array data is divided and arranged on the storage means of the calculation node, and a loop in a program for using / defining the array data is executed in parallel on the calculation means A masked reverse shift communication method for a distributed memory multiprocessor system, comprising:
When the array element defined in each calculation node is an array element that is divided and arranged on the storage means of another calculation node, during execution of the parallel loop, the area is contiguous with the array data of its own calculation node. The value to be used / defined is stored in the masked reverse shift communication buffer, and after execution of the parallel loop, the value of the masked reverse shift communication buffer that has been defined is transferred to the other via the inter-computation node communication means. A masked reverse shift communication method comprising: executing a masked reverse shift communication step of communicating with a corresponding calculation node and reflecting the result on a corresponding array element arranged on another calculation node. The masked reverse shift communication step comprises:
A parallelization reference access pattern analysis step for recognizing a parallel loop nest that is parallelized based on a reference access pattern of a reference array for parallelization to be subjected to masked reverse shift communication;
Data mapping that analyzes the data mapping of each array appearing in the parallel loop nest for each parallel loop nest of the reverse shift communication target with mask, and extracts the array having the same mapping as the reference array for parallelization An analysis step;
For each occurrence of the array in the parallel loop nest, an access pattern analysis step for selecting the masked reverse shift communication target array, access pattern and target dimension;
A reverse shift vector analysis step for calculating a reverse shift communication direction and width required for the masked reverse shift communication target access pattern, and a reverse shift communication buffer width;
Inverse shift target index analysis step for calculating an index for reverse shift communication target with mask;
Extending the allocation range of the masked reverse shift communication target array by the reverse shift communication buffer width, and immediately before the parallel loop nest of the masked reverse shift communication target, from the array element corresponding to the reverse shift communication buffer, Generate a shift communication command to the reverse shift communication buffer, and immediately after the parallel loop nest of the masked reverse shift communication target, from the element corresponding to the masked reverse shift communication target index of the reverse shift communication buffer, 9. The masked reverse shift communication method according to claim 8, further comprising a masked reverse shift communication generation step for generating a reverse shift communication command to an array element to be masked. In the parallelization reference access pattern analysis step,
For each parallel loop nest, in each distributed dimension of the parallel reference array, check whether the subscript of the reference access pattern satisfies the predetermined condition, and mask only the parallel loop nest satisfying the predetermined condition 10. The reverse shift communication method with a mask according to claim 9, wherein the reverse shift communication target parallel loop nest is selected. In the access pattern analysis step,
For each occurrence in the parallel loop nest of each array having the same mapping as the parallel reference array extracted in the data mapping analysis step, a subscript of each dimension corresponding to the distributed dimension of the parallel reference array is 11. The masked reverse shift communication method according to claim 9, wherein an access pattern that satisfies a predetermined condition is selected as an access pattern for masked reverse shift communication. In the inverse shift vector analysis step,
For each parallel loop nest of the reverse shift communication target with mask selected in the parallelization reference access pattern analysis step, the subscript of the reference access pattern in the distributed dimension of the parallelization reference array and the selection in the access pattern analysis step A reverse shift vector is calculated for each corresponding combination of subscripts in the target dimension of masked reverse shift communication for each masked reverse shift communication target access pattern,
Corresponding to the masked reverse shift communication target array selected in the access pattern analyzing step, the masked reverse shift of all occurrences that are the target access patterns of the masked reverse shift communication selected in the access pattern analyzing step Calculates the maximum positive value and the minimum negative value in the set of reverse shift vectors of the communication target dimension, and reverses the absolute value of the maximum positive value and the minimum negative value with a mask. The masked reverse shift communication method according to any one of claims 9 to 11, wherein an upper reverse shift communication buffer width and a lower reverse shift communication buffer width in the dimension of the shift communication target array are used. In the reverse shift target index analysis step,
For each target parallel loop nest of masked reverse shift communication selected in the parallelization reference access pattern analysis step, the masked inverse of the target access pattern of each masked reverse shift communication selected in the access pattern analysis step The masked reverse shift communication method according to any one of claims 9 to 12, wherein a value satisfying a predetermined condition among subscripts of a target dimension of shift communication is calculated as a reverse shift target index. In the masked reverse shift communication generation step,
For the reverse shift communication with mask from the computation node in which the array element corresponding to the buffer for reverse shift communication with mask is arranged for the buffer for reverse shift communication with mask of the target array for reverse shift communication with mask Generate an instruction to perform shift communication via the inter-computation node communication means to another computation node in which the buffer is arranged before executing the parallel loop nest,
For each masked reverse shift communication target access pattern, the corresponding array element is arranged from the calculation node in which the reverse shift communication buffer corresponding to the reverse shift target index determined in the reverse shift target index analyzing step is arranged. 14. A command with a mask according to claim 9, wherein an instruction for performing reverse shift communication via a communication means between calculation nodes to a calculation node after execution of parallel loop nest is generated. Reverse shift communication method. A plurality of calculation nodes having a calculation means and a storage means are provided, array data is divided and arranged on the storage means of the calculation node, and a loop in a program for using / defining the array data is executed in parallel on the calculation means A program for executing masked reverse shift communication of a distributed memory multiprocessor system,
In the compute node,
When the array element defined in each calculation node is an array element that is divided and arranged on the storage means of another calculation node, during execution of the parallel loop, the area is contiguous with the array data of its own calculation node. The value to be used / defined is stored in the masked reverse shift communication buffer, and after execution of the parallel loop, the value of the masked reverse shift communication buffer that has been defined is transferred to the other via the inter-computation node communication means. A program characterized by causing a reverse shift communication process with a mask to be executed, which is communicated to a corresponding computation node and reflected in a corresponding array element arranged on another computation node. The masked reverse shift communication process is:
A parallelization reference access pattern analysis process for recognizing a parallel loop nest that is parallelized based on a reference access pattern of a parallel reference array that is a target of reverse shift communication with a mask;
Data mapping that analyzes the data mapping of each array appearing in the parallel loop nest for each parallel loop nest of the reverse shift communication target with mask, and extracts the array having the same mapping as the reference array for parallelization Analysis process,
For each occurrence of the array in the parallel loop nest, an access pattern analysis process for selecting the masked reverse shift communication target array, access pattern and target dimension;
Reverse shift vector analysis processing for calculating the reverse shift communication direction and width required for the masked reverse shift communication target access pattern, and the reverse shift communication buffer width;
Inverse shift target index analysis processing for calculating an index for reverse shift communication target with mask,
Extending the allocation range of the masked reverse shift communication target array by the reverse shift communication buffer width, and immediately before the parallel loop nest of the masked reverse shift communication target, from the array element corresponding to the reverse shift communication buffer, Generate a shift communication command to the reverse shift communication buffer, and immediately after the parallel loop nest of the masked reverse shift communication target, from the element corresponding to the masked reverse shift communication target index of the reverse shift communication buffer, The program according to claim 15, further comprising a masked reverse shift communication generation process for generating a reverse shift communication command to an array element to be processed. In the parallel reference access pattern analysis process,
For each parallel loop nest, in each distributed dimension of the parallel reference array, check whether the subscript of the reference access pattern satisfies the predetermined condition, and mask only the parallel loop nest satisfying the predetermined condition The program according to claim 16, wherein the program is selected as a parallel loop nest for reverse shift communication. In the access pattern analysis process,
For each occurrence in the parallel loop nest of each array having the same mapping as the parallel reference array extracted in the data mapping analysis process, a subscript of each dimension corresponding to the distributed dimension of the parallel reference array is The program according to claim 16 or 17, wherein an access pattern that satisfies a predetermined condition is selected as an access pattern for masked reverse shift communication. In the inverse shift vector analysis process,
For each parallel loop nest of the reverse shift communication target with mask selected in the parallelization reference access pattern analysis process, the subscript of the reference access pattern in the distributed dimension of the reference array for parallelization and the access pattern analysis process selected A reverse shift vector is calculated for each corresponding combination of subscripts in the target dimension of masked reverse shift communication for each masked reverse shift communication target access pattern,
Corresponding to the masked reverse shift communication target array selected in the access pattern analysis process, the masked reverse shift of all occurrences that are the target access patterns of the masked reverse shift communication selected in the access pattern analysis process Calculates the maximum positive value and the minimum negative value in the set of reverse shift vectors of the communication target dimension, and reverses the absolute value of the maximum positive value and the minimum negative value with a mask. The program according to any one of claims 16 to 18, wherein an upper reverse shift communication buffer width and a lower reverse shift communication buffer width of the dimension of the shift communication target array are set. In the reverse shift target index analysis process,
For each target parallel loop nest of masked reverse shift communication selected in the parallelization reference access pattern analysis process, the masked inverse of the target access pattern of each masked reverse shift communication selected in the access pattern analysis process The program according to any one of claims 16 to 19, wherein a value satisfying a predetermined condition among subscripts of a target dimension of shift communication is calculated as a reverse shift target index. In the masked reverse shift communication generation process,
For the reverse shift communication with mask from the computation node in which the array element corresponding to the buffer for reverse shift communication with mask is arranged for the buffer for reverse shift communication with mask of the target array for reverse shift communication with mask Generate an instruction to perform shift communication via the inter-computation node communication means to another computation node in which the buffer is arranged before executing the parallel loop nest,
For each masked reverse shift communication target access pattern, a corresponding array element is arranged from a calculation node in which the reverse shift communication buffer corresponding to the reverse shift target index determined in the reverse shift target index analysis processing is arranged. The program according to any one of claims 16 to 20, wherein an instruction for performing reverse shift communication via a communication means between calculation nodes to a calculation node after execution of parallel loop nest is generated.

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