JP2009290704A - Differential amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential amplifier circuit capable of achieving high-speed operation for differential signals while ensuring a sufficient phase margin for common-mode signals. <P>SOLUTION: A differential amplifier circuit includes a differential input stage for amplifying a differential input signal applied across an input terminal, a first single-phase output stage coupled to a first output terminal of the differential input stage, a second single-phase output stage coupled to a second output terminal of the differential input stage, a first capacitor for coupling between the first output terminal and the output of the first single-phase output stage, a second capacitor for coupling between the second output terminal and the output of the second single-phase output stage, a third capacitor for coupling between the first output terminal and the output of the second single-phase output stage, and a fourth capacitor for coupling between the second output terminal and the output of the first single-phase output stage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present disclosure generally relates to amplifier circuits, and more particularly to differential amplifier circuits.

  In a fully differential operational amplifier, a common mode voltage is controlled by feeding back an in-phase signal from an output to an input. Further, by providing a feedback capacitor between the differential input stage and the output stage, phase compensation is performed for both the in-phase signal and the differential signal.

  FIG. 1 is a diagram illustrating an example of a configuration of common mode feedback for a fully differential operational amplifier. An amplifier whose amplification factor is determined by the resistance values of the resistors R5 and R6 on the input terminal side and the resistance values of the resistors R1 and R2 by negatively feeding back the differential signal output of the operational amplifier 10 through the resistors R1 and R2, respectively. Is configured. The first differential signal output (+ side) of the operational amplifier 10 is supplied to the inverting input of the comparator 11 via the capacitor C1 and the resistor R5 connected in parallel. Further, the second differential signal output (− side) of the operational amplifier 10 is supplied to the inverting input of the comparator 11 via the capacitor C2 and the resistor R6 connected in parallel. The resistance values of the resistors R5 and R6 are equal, and an intermediate potential between the potential of the first differential signal output and the potential of the second differential signal output is applied to the inverting input of the comparator 11. Further, the capacitor C1 and the capacitor C2 absorb the fluctuation of the differential signal output current of the operational amplifier 10 at a high frequency, so that the inverting input of the comparator 11 has the potential of the first differential signal output and the second differential signal output. The time average of the intermediate potential with the potential of the differential signal output is applied. The comparator 11 compares the averaged intermediate potential with the reference potential VREF, and supplies a voltage signal indicating the comparison result to the operational amplifier 10 as common mode feedback.

  FIG. 2 is a diagram illustrating an example of the configuration of the operational amplifier 10. The operational amplifier 10 shown in FIG. 2 includes PMOS transistors 21 to 25, NMOS transistors 26 to 29, a resistor R7, a resistor R8, a capacitor C3, and a capacitor C4. A bypass voltage BP is applied to the gates of the PMOS transistors 21 and 23, and a bypass common voltage BPC is applied to the gate of the PMOS transistor 22. The PMOS transistor 22, the PMOS transistors 24 and 25, and the NMOS transistors 28 and 29 constitute a differential input stage of the operational amplifier 10. A common feedback signal CM applied in common to the gates of the NMOS transistors 28 and 29 is an output signal of the comparator 11 shown in FIG. By adjusting the common feedback signal CM by the comparator 11, an intermediate potential between the average voltage of the first differential signal output OUT_PLUS and the average voltage of the second differential signal output OUT_MINUS of the operational amplifier 10 becomes the reference potential VREF. Controlled to be equal.

  The first differential signal input IN_PLUS is applied to the gate of the PMOS transistor 25 in the differential input stage. The second differential signal input IN_MINUS is applied to the gate of the PMOS transistor 24 in the differential input stage. The drain ends of the PMOS transistors 24 and 25 are the outputs of the differential input stage, and are applied to the gates of the NMOS transistors 26 and 27, respectively.

  The NMOS transistor 27 and the PMOS transistor 23 constitute a first single-phase output stage of the operational amplifier 10. The drain end of the NMOS transistor 27 becomes the output of the first single-phase output stage, that is, the first differential signal output of the operational amplifier 10. That is, the first differential signal OUT_PLUS is output from the drain end of the NMOS transistor 27.

  The NMOS transistor 26 and the PMOS transistor 21 constitute a second single-phase output stage of the operational amplifier 10. The drain end of the NMOS transistor 26 becomes the output of the second single-phase output stage, that is, the second differential signal output of the operational amplifier 10. That is, the second differential signal OUT_MINUS is output from the drain end of the NMOS transistor 26.

  In the operational amplifier 10, feedback capacitors C3 and C4 are provided for phase compensation between the in-phase signal and the differential signal. Specifically, the output and the input of the first single-phase output stage are connected by a capacitor C4 and a resistor R8 connected in series. That is, the drain end and the gate end of the NMOS transistor 27 are connected by the capacitor C4 and the resistor R8 connected in series. Further, the output and the input of the second single-phase output stage are connected by the series-connected capacitor C3 and the resistor R7. That is, the drain end and the gate end of the NMOS transistor 26 are connected by the capacitor C3 and the resistor R7 connected in series.

  The feedback capacitors C4 and C3 reduce the gain in the high frequency region of the first and second single-phase output stages. Thereby, phase compensation is performed, and stable operation without oscillation can be realized in a configuration in which negative feedback is applied to both the in-phase signal and the differential signal as shown in FIG.

In general, it is desirable that an operational amplifier operates at high speed with respect to a differential signal. In order to operate at high speed, it is necessary to increase the gain in the high frequency region, and the phase compensation capacitance is adjusted so that the unity gain frequency (frequency where the gain is 1) for the differential signal is increased. However, if the phase compensation capacitors C3 and C4 in FIG. 2 are reduced to increase the unity gain frequency for the differential signal, the unity gain frequency for the in-phase signal also increases, and sufficient phase margin for the in-phase signal is secured. There is a problem that it cannot be done. Conversely, if the phase compensation capacitance is adjusted so as to ensure a sufficient phase margin for the in-phase signal, the unity gain frequency for the differential signal is lowered, and high-speed operation cannot be realized.
JP 2000-151305 A JP 2000-201038 A

  In view of the above, a differential amplifier circuit capable of realizing a high-speed operation for a differential signal while ensuring a sufficient phase margin for the in-phase signal is desired.

  A differential amplifier circuit according to a first configuration includes a differential input stage for amplifying a differential input signal applied to an input terminal, and a first single phase coupled to a first output terminal of the differential input stage. Coupling between an output stage, a second single-phase output stage coupled to a second output terminal of the differential input stage, and an output of the first output terminal and the first single-phase output stage A first capacitor, a second capacitor coupling between the second output terminal and the output of the second single-phase output stage, the first output terminal and the second single-phase output. And a third capacitor coupled between the output of the stage and a fourth capacitor coupled between the output of the second output terminal and the output of the first single-phase output stage. .

  The differential amplifier circuit according to the second configuration includes a differential input stage that amplifies a differential input signal applied to an input terminal, and a first single unit coupled to the first output terminal of the differential input stage. A phase output stage, a second single-phase output stage coupled to a second output terminal of the differential input stage, and a feedback circuit that switches connection of a feedback path by capacitive coupling according to a switching signal, A feedback circuit is provided between the first output terminal and the output of the first single-phase output stage in the first state of the switching signal and between the second output terminal and the second single-phase output stage. And outputs between the first output terminal and the output of the second single-phase output stage in the second state of the switching signal, and the second output terminal, respectively. The outputs of the first single-phase output stage are respectively coupled via capacitors.

  For the first single-phase output stage, the sum of the first capacitor and the fourth capacitor becomes the feedback capacitor for the in-phase signal, and the difference between the first capacitor and the fourth capacitor is the feedback capacitor for the differential signal. It becomes. Similarly, for the second single-phase output stage, the sum of the second capacitor and the third capacitor becomes the feedback capacitor for the in-phase signal, and the difference between the second capacitor and the third capacitor is the differential. This is the feedback capacity for the signal. In this way, while reducing the feedback capacity for the differential signal and increasing the operation speed of the differential signal, it is possible to increase the feedback capacity for the in-phase signal and sufficiently secure the phase margin of the in-phase signal.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 is a diagram illustrating an example of the configuration of the operational amplifier 30. The operational amplifier 30 shown in FIG. 3 can be used in a configuration in which negative feedback is applied to both the in-phase signal and the differential signal as shown in FIG.

  It includes PMOS transistors 31 to 35, NMOS transistors 36 to 39, resistors R10 to R13, and capacitors C10 to C13. A bypass voltage BP is applied to the gates of the PMOS transistors 31 and 33, and a bypass common voltage BPC is applied to the gate of the PMOS transistor 32. The PMOS transistor 32, the PMOS transistors 34 and 35, and the NMOS transistors 38 and 39 constitute a differential input stage of the operational amplifier 30. The common feedback signal CM applied in common to the gates of the NMOS transistors 38 and 39 is an output signal of the comparator 11 when the operational amplifier 10 is replaced with the operational amplifier 30 in the configuration shown in FIG. By adjusting the common feedback signal CM by the comparator 11, an intermediate potential between the average voltage of the first differential signal output OUT_PLUS and the average voltage of the second differential signal output OUT_MINUS of the operational amplifier 30 becomes the reference potential VREF. Controlled to be equal.

  The first differential signal input IN_PLUS is applied to the gate of the PMOS transistor 35 in the differential input stage. The second differential signal input IN_MINUS is applied to the gate of the PMOS transistor 34 in the differential input stage. The drain ends of the PMOS transistors 34 and 35 are the outputs of the differential input stage, and are applied to the gates of the NMOS transistors 36 and 37, respectively.

  The NMOS transistor 37 and the PMOS transistor 33 constitute a first single-phase output stage of the operational amplifier 30. The drain end of the NMOS transistor 37 becomes the output of the first single-phase output stage, that is, the first differential signal output of the operational amplifier 30. That is, the first differential signal OUT_PLUS is output from the drain end of the NMOS transistor 37.

  The NMOS transistor 36 and the PMOS transistor 31 constitute a second single-phase output stage of the operational amplifier 30. The drain end of the NMOS transistor 36 becomes the output of the second single-phase output stage, that is, the second differential signal output of the operational amplifier 30. That is, the second differential signal OUT_MINUS is output from the drain end of the NMOS transistor 36.

  In this way, the differential input stage amplifies the differential input signals (IN_PLUS and IN_MINUS) applied to the input ends (the gate ends of the PMOS transistors 35 and 34), and the first output end and the second output. The amplified signal is output from the end. A first single-phase output stage including an NMOS transistor 37 and a PMOS transistor 33 is coupled to the drain of the PMOS transistor 35 which is the first output terminal of the differential input stage. A second single-phase output stage including the NMOS transistor 36 and the PMOS transistor 31 is coupled to the drain of the PMOS transistor 34 which is the second output terminal of the differential input stage.

  In the operational amplifier 30, feedback capacitors C10 and C11 are provided for phase compensation between the in-phase signal and the differential signal. Specifically, the output and input of the first single-phase output stage are connected by a capacitor C11 and a resistor R11 connected in series. That is, the drain end and the gate end of the NMOS transistor 37 are connected by the capacitor C11 and the resistor R11 connected in series. In addition, the output and the input of the second single-phase output stage are connected by the capacitor C10 and the resistor R10 connected in series. That is, the drain end and the gate end of the NMOS transistor 36 are connected by the capacitor C10 and the resistor R10 connected in series.

  Further, in the operational amplifier 30, feedback capacitors C12 and C13 are provided in order to compensate for the phase margin of the in-phase signal while increasing the operation speed for the differential signal. Specifically, the capacitor C13 and the resistor R13 connected in series connect the output of the first single-phase output stage and the second output of the differential input stage. That is, the drain end of the NMOS transistor 37 and the drain end of the PMOS transistor 34 are connected by the capacitor C13 and the resistor R13 connected in series. The output of the second single-phase output stage and the first output of the differential input stage are connected by the capacitor C12 and the resistor R12 connected in series. That is, the drain end of the NMOS transistor 36 and the drain end of the PMOS transistor 35 are connected by the capacitor C12 and the resistor R12 connected in series.

  In this way, the first capacitor C11 couples between the first output terminal (the drain terminal of the PMOS transistor 35) and the output of the first single-phase output stage (the drain terminal of the NMOS transistor 37). The second capacitor C10 couples between the second output terminal (the drain terminal of the PMOS transistor 34) and the output of the second single-phase output stage (the drain terminal of the NMOS transistor 36). The third capacitor C12 couples between the first output terminal (the drain terminal of the PMOS transistor 35) and the output of the second single-phase output stage (the drain terminal of the NMOS transistor 36). Further, the fourth capacitor C13 couples between the second output terminal (the drain terminal of the PMOS transistor 34) and the output of the first single-phase output stage (the drain terminal of the NMOS transistor 37).

  FIG. 4 is a diagram for explaining feedback of the in-phase signal component in the differential amplifier circuit of FIG. 4, the same components as those in FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.

  A voltage waveform 41 shows an in-phase signal component of the voltage applied to the gate terminal of the NMOS transistor 37. The voltage waveform 42 represents the in-phase signal component of the voltage applied to the gate terminal of the NMOS transistor 36. A voltage waveform 43 represents an in-phase signal component of the operational amplifier output voltage OUT_PLUS that appears at the drain terminal of the NMOS transistor 37. Further, the voltage waveform 44 shows the in-phase signal component of the operational amplifier output voltage OUT_MINUS appearing at the drain terminal of the NMOS transistor 36. Since the in-phase signal component is shown, the voltage waveforms on the positive side and the negative side are the same waveform in phase.

A current fed back from the drain end to the gate end of the NMOS transistor 37 by the capacitor C11 is shown as a current I1. Further, a current fed back from the drain end of the NMOS transistor 36 to the gate end of the NMOS transistor 37 by the capacitor C12 is shown as a current I2. The waveform of the current I1 becomes a current waveform 45, and the waveform of the current I2 becomes a current waveform 46. The current waveform 47 is obtained by adding the current waveform 45 and the current waveform 46, and indicates the sum of the current I1 and the current I2. Here, assuming that the common-mode signal component of the output voltage OUT_PLUS and the common-mode signal component of the output voltage OUT_MINUS are the voltage V0,
I1 = V0 · jωC11
I2 = V0 · jωC12
Can be considered. In this case, the sum of I1 and I2 is
I1 + I2 = V0 · jω (C11 + C12)
It becomes. That is, the sum C11 + C12 of the capacitance value of C11 and the capacitance value of C12 becomes the feedback capacitance for the in-phase signal.

  FIG. 5 is a diagram for explaining feedback of differential signal components in the differential amplifier circuit of FIG. 5, the same components as those in FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.

  A voltage waveform 51 indicates a differential signal component of a voltage applied to the gate terminal of the NMOS transistor 37. A voltage waveform 52 represents a differential signal component of a voltage applied to the gate terminal of the NMOS transistor 36. A voltage waveform 53 indicates a differential signal component of the operational amplifier output voltage OUT_PLUS that appears at the drain terminal of the NMOS transistor 37. Further, the voltage waveform 54 shows a differential signal component of the operational amplifier output voltage OUT_MINUS appearing at the drain terminal of the NMOS transistor 36. Since the differential signal component is shown, the voltage waveforms on the positive side and the negative side have the same shape and have opposite phases.

A current fed back from the drain end to the gate end of the NMOS transistor 37 by the capacitor C11 is shown as a current I1. Further, a current fed back from the drain end of the NMOS transistor 36 to the gate end of the NMOS transistor 37 by the capacitor C12 is shown as a current I2. The waveform of the current I1 becomes a current waveform 55, and the waveform of the current I2 becomes a current waveform 56. The current waveform 57 is obtained by adding the current waveform 55 and the current waveform 56, and indicates the sum of the current I1 and the current I2. Here, when the differential signal component of the output voltage OUT_PLUS is a voltage V0 and the differential signal component of the output voltage OUT_MINUS is a voltage −V0,
I1 = V0 · jωC11
I2 = −V0 · jωC12
Can be considered. In this case, the sum of I1 and I2 is
I1 + I2 = V0 · jω (C11-C12)
It becomes. That is, the difference C11−C12 between the capacitance value of C11 and the capacitance value of C12 is a feedback capacitance for the differential signal.

  As described above, for the first single-phase output stage, C11 + C12 is a feedback capacitor for the in-phase signal, and C11-C12 is a feedback capacitor for the differential signal. Similarly, for the second single-phase output stage, C10 + C13 is a feedback capacitor for the in-phase signal, and C10-C13 is a feedback capacitor for the differential signal. By providing the capacitors C12 and C13 as feedback capacitors in this way, the feedback capacitance for the differential signal is reduced to increase the operation speed of the differential signal, while the feedback capacitance for the common signal is increased to increase the phase of the common signal. A sufficient margin can be secured.

  FIG. 6 is a diagram illustrating an example of a configuration of a low-pass filter using a fully differential operational amplifier. The differential signal output of the operational amplifier 30A is negatively fed back to the input through the resistors 83 and 84 having the resistance value R2, respectively, so that the resistance value R1 of the resistors 81 and 82 on the input terminal side and the resistance value R2 of the negative feedback are obtained. An amplifier whose amplification factor is determined is configured. Further, a negative feedback path via the variable capacitor 60 is provided by connecting the variable capacitor 60 in parallel to the resistor 83. Further, a negative feedback path through the variable capacitor 70 is provided by connecting the variable capacitor 70 in parallel to the resistor 84. These feedback capacitors realize low-pass filter characteristics.

  The variable capacitor 60 includes capacitors 61 to 63 and switches 64 and 65. The capacitance values of the capacitors 61, 62, and 63 are Cfc0, Cfc1, and Cfc2, respectively. The switches 64 and 65 are controlled by control signals FC_SW1 and FC_SW2, respectively. Each switch becomes conductive when the control signal is 1, and becomes non-conductive when the control signal is 0. Similarly, the variable capacitor 70 includes capacitors 71 to 73 and switches 74 and 75. The capacitance values of the capacitors 71, 72, and 73 are Cfc0, Cfc1, and Cfc2, respectively. The switches 74 and 75 are controlled by control signals FC_SW1 and FC_SW2, respectively. Each switch becomes conductive when the control signal is 1, and becomes non-conductive when the control signal is 0. The capacitance values of the variable capacitor 60 and the variable capacitor 70 are the same and use the same control signal, and the variable capacitance value of the variable capacitor 60 and the variable capacitance value of the variable capacitor 70 are the same.

  The first differential signal output (+ side) of the operational amplifier 30A is supplied to the inverting input of the comparator 90 via the capacitor 87 and the resistor 85 connected in parallel. Further, the second differential signal output (− side) of the operational amplifier 30 </ b> A is supplied to the inverting input of the comparator 90 through the capacitor 88 and the resistor 86 connected in parallel. The resistance values of the resistor 85 and the resistor 86 are equal, and an intermediate potential between the potential of the first differential signal output and the potential of the second differential signal output is applied to the inverting input of the comparator 90. Further, the capacitor 87 and the capacitor 88 absorb the fluctuation of the differential signal output current of the operational amplifier 30A at a high frequency, so that the potential of the first differential signal output and the second differential signal output are supplied to the inverting input of the comparator 90. The time average of the intermediate potential with the potential of the differential signal output is applied. The comparator 90 compares the averaged intermediate potential with the reference potential VREF, and supplies a voltage signal indicating the comparison result to the operational amplifier 30A as common mode feedback.

  In the low-pass filter shown in FIG. 6, the cutoff frequency can be adjusted to be low by increasing the capacitance values (cut-off capacitances) of the variable capacitors 60 and 70. Further, the cutoff frequency can be adjusted to be high by reducing the capacitance values (cutoff capacitances) of the variable capacitors 60 and 70. At this time, when the cutoff frequency is high, it is necessary to increase the unity gain frequency of the operational amplifier 30A with respect to the differential signal. When the cut-off frequency is low, the unity gain frequency of the operational amplifier 30A may be low with respect to the differential signal. Therefore, it is necessary to control the internal feedback capacitance of the operational amplifier 30A in conjunction with the control of the capacitance values of the variable capacitors 60 and 70.

  FIG. 7 is a diagram illustrating an example of the configuration of the operational amplifier 30A in FIG. In FIG. 7, the same components as those of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.

  In the operational amplifier 30A in FIG. 7, capacitors 101 to 106 and resistors 111 to 116 are provided in place of the capacitors C10 to C13 and resistors R10 to R13 with respect to the operational amplifier 30 in FIG. Switches 121 to 124 are provided.

  The output of the first single-phase output stage and the input are fixedly connected by the capacitor 106 and the resistor 116 connected in series. That is, the drain end and gate end of the NMOS transistor 37 are connected by the capacitor 106 and the resistor 116 connected in series. In addition, the output and the input of the second single-phase output stage are fixedly connected by the capacitor 105 and the resistor 115 connected in series. That is, the drain end and the gate end of the NMOS transistor 36 are connected by the capacitor 105 and the resistor 115 connected in series. Here, the capacitance values of the capacitors 105 and 106 are C3.

  Further, the capacitor 102, the resistor 112, and the switch 122 connected in series connect the output of the first single-phase output stage and the first or second output of the differential input stage in a switchable manner. The connection state of the switch 122 is controlled by a switching signal SW1. When the switching signal SW1 is 0, the drain end of the NMOS transistor 37 and the drain end of the PMOS transistor 35 are connected via the capacitor 102 and the resistor 112. When the switching signal SW1 is 1, the drain end of the NMOS transistor 37 and the drain end of the PMOS transistor 34 are connected via the capacitor 102 and the resistor 112. Here, the capacitance value of the capacitor 102 is C1.

  Further, the capacitor 101, the resistor 111, and the switch 121 connected in series connect the output of the second single-phase output stage and the first or second output of the differential input stage in a switchable manner. Similarly to the switch 122, the connection state of the switch 121 is controlled by the switching signal SW1. When the switching signal SW1 is 0, the drain end of the NMOS transistor 36 and the drain end of the PMOS transistor 34 are connected via the capacitor 101 and the resistor 111. When the switching signal SW1 is 1, the drain end of the NMOS transistor 36 and the drain end of the PMOS transistor 35 are connected via the capacitor 101 and the resistor 111. Here, the capacitance value of the capacitor 101 is C1.

  In addition, the capacitor 104, the resistor 114, and the switch 124 connected in series connect the output of the first single-phase output stage and the first or second output of the differential input stage in a switchable manner. The connection state of the switch 124 is controlled by a switching signal SW2. When the switching signal SW2 is 0, the drain end of the NMOS transistor 37 and the drain end of the PMOS transistor 35 are connected via the capacitor 104 and the resistor 114. When the switching signal SW2 is 1, the drain end of the NMOS transistor 37 and the drain end of the PMOS transistor 34 are connected via the capacitor 104 and the resistor 114. Here, the capacitance value of the capacitor 104 is C2.

  Further, the capacitor 103, the resistor 113, and the switch 123 connected in series connect the output of the second single-phase output stage and the first or second output of the differential input stage in a switchable manner. The connection state of the switch 123 is controlled by the switching signal SW2 similarly to the switch 124. When the switching signal SW2 is 0, the drain end of the NMOS transistor 36 and the drain end of the PMOS transistor 34 are connected via the capacitor 103 and the resistor 113. When the switching signal SW2 is 1, the drain end of the NMOS transistor 36 and the drain end of the PMOS transistor 35 are connected via the capacitor 103 and the resistor 113. Here, the capacitance value of the capacitor 103 is C2.

  FIG. 8 is a table showing the relationship between the capacitance value of the cutoff capacitance, the differential capacitance value, and the common-mode capacitance value in the circuits shown in FIGS. 6 and 7. When the control signals FC_SW1 and FC_SW2 shown in FIG. 6 are both 0, the capacitance values (cut-off capacitances) of the variable capacitor 60 and the variable capacitor 70 are Cfc0. This state is shown in the row indicated as fc1 in the table of FIG. Here, fc1 means a cut-off frequency, and fc1 = 1 / (2π · R2 · Cfc0). In this case, the cut-off frequency corresponds to a high one among high, medium, and low, so it is necessary to realize a high-speed operation for the differential signal by sufficiently reducing the differential capacitance value that is the feedback capacitance for the differential signal. There is. In the example shown in FIG. 8, the switching signals SW1 and SW2 shown in FIG. 7 are set to 0 and 1, respectively, with respect to the cutoff frequency fc1. As a result, the differential capacitance value becomes C1-C2 + C3 = Co. It is assumed that Co is designed so that C1 = Co and C2 = C3 = 2Co, where Co is the basic capacitance value.

  When the control signals FC_SW1 and FC_SW2 shown in FIG. 6 are set to 1 and 0, respectively, the capacitance values (cutoff capacitances) of the variable capacitor 60 and the variable capacitor 70 are Cfc0 + Cfc1. This state is shown in the row indicated as fc2 in the table of FIG. Here, fc2 means a cut-off frequency, and fc2 = 1 / (2π · R2 · (Cfc0 + Cfc1)). In this case, since the cut-off frequency corresponds to one of high, medium, and low, it is necessary to reduce the differential capacitance value, which is the feedback capacitance for the differential signal, to some extent to realize high-speed operation for the differential signal. is there. In the example illustrated in FIG. 8, the switching signals SW1 and SW2 illustrated in FIG. 7 are set to 1 and 0, respectively, with respect to the cutoff frequency fc2. As a result, the differential capacitance value becomes −C1 + C2 + C3 = 3Co.

  When both the control signals FC_SW1 and FC_SW2 shown in FIG. 6 are set to 1, the capacitance values (cut-off capacitances) of the variable capacitor 60 and the variable capacitor 70 are Cfc0 + Cfc1 + Cfc2. This state is shown in the row indicated as fc3 in the table of FIG. Here, fc3 means a cut-off frequency, and fc3 = 1 / (2π · R2 · (Cfc0 + Cfc1 + Cfc2)). In this case, since the cut-off frequency corresponds to the low of high, medium, and low, high-speed operation for differential signals is not particularly required, but the phase delay in the high frequency band is large due to the large cut-off capacity. The phase margin becomes insufficient. Therefore, it is necessary to increase the differential capacitance value in order to ensure the phase margin. In the example shown in FIG. 8, both the switching signals SW1 and SW2 shown in FIG. 7 are set to 0 with respect to the cutoff frequency fc3. As a result, the differential capacitance value becomes C1 + C2 + C3 = 5Co.

  As described above, the differential capacitance value (the value of the feedback capacitance with respect to the differential signal) can be set to Co, 3Co, and 5Co for the high, medium, and low cutoff frequencies in the low-pass filter of FIG. . That is, the value of the feedback capacitance for the differential signal can be adjusted according to the degree to which high-speed operation for the differential signal is required. As can be seen from FIG. 8, the in-phase capacitance value (the value of the feedback capacitance for the in-phase signal) is constant at 5Co regardless of the value of the cutoff frequency. Therefore, even if the value of the feedback capacitance for the differential signal is adjusted, a constant and sufficient phase margin can always be secured for the in-phase signal.

  In the configuration shown in FIG. 7, the gap between the first output terminal of the differential input stage (the drain terminal of the PMOS transistor 35) and the output of the first single-phase output stage (the drain terminal of the NMOS transistor 37) is fixed. Capacitive coupling. In addition, the second output terminal of the differential input stage (the drain terminal of the PMOS transistor 34) and the output of the second single-phase output stage (the drain terminal of the NMOS transistor 36) are fixedly capacitively coupled. In addition to these fixed capacitive couplings, a feedback circuit is provided that switches the connection of feedback paths by capacitive coupling in accordance with the switching signal SW1. In the first state (0) of the switching signal SW1, the feedback circuit is provided between the first output terminal and the output of the first single-phase output stage, and between the second output terminal and the second single-phase. The output of the output stage is coupled via a capacitor 102 and a capacitor 101, respectively. Further, in the second state (1) of the switching signal SW1, between the first output terminal and the output of the second single-phase output stage and between the second output terminal and the output of the first single-phase output stage. They are coupled via a capacitor 101 and a capacitor 102, respectively. In addition to this feedback circuit, a second feedback circuit for switching the connection of the feedback path by capacitive coupling according to the second switching signal SW2 is further provided. In the first state (0) of the switching signal SW2, the second feedback circuit is provided between the first output terminal and the output of the first single-phase output stage, and between the second output terminal and the second output terminal. And the output of the single-phase output stage are coupled via a capacitor 104 and a capacitor 103, respectively. Further, in the second state (1) of the switching signal SW2, between the first output terminal and the output of the second single-phase output stage and between the second output terminal and the output of the first single-phase output stage. These are coupled through a capacitor 103 and a capacitor 104, respectively.

  In the above configuration, it is not necessary to provide both the first feedback circuit and the second feedback circuit, and only one of them may be provided. Furthermore, one or more feedback circuits such as a third feedback circuit may be additionally provided. Similarly, the feedback path by fixed capacitive coupling by the capacitors 105 and 106 may be configured to be switchable.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a figure which shows an example of a structure of the common mode feedback with respect to a fully differential operational amplifier. It is a figure which shows an example of a structure of an operational amplifier. It is a figure which shows an example of a structure of an operational amplifier. It is a figure for demonstrating the feedback of the in-phase signal component in the differential amplifier circuit of FIG. It is a figure for demonstrating the feedback of the differential signal component in the differential amplifier circuit of FIG. It is a figure which shows an example of a structure of the low-pass filter using a fully differential operational amplifier. It is a figure which shows an example of a structure of the operational amplifier of FIG. FIG. 8 is a table showing a relationship among a capacitance value of a cutoff capacitance, a differential capacitance value, and an in-phase capacitance value in the circuits shown in FIGS. 6 and 7. FIG.

Explanation of symbols

31 to 35 PMOS transistors 36 to 39 NMOS transistors R10 to R13 Resistors C10 to C13 Capacitance

Claims (7)

A differential input stage for amplifying a differential input signal applied to the input end;
A first single-phase output stage coupled to a first output of the differential input stage;
A second single-phase output stage coupled to the second output of the differential input stage;
A first capacitor for coupling between the first output terminal and the output of the first single-phase output stage;
A second capacitor for coupling between the second output terminal and the output of the second single-phase output stage;
A third capacitor for coupling between the first output terminal and the output of the second single-phase output stage;
A differential amplifier circuit comprising: a fourth capacitor coupling between the second output terminal and the output of the first single-phase output stage.   2. The differential amplifier circuit according to claim 1, wherein the values of the first to fourth capacitors are variably configured.   A path for negatively feeding back the output of the first single-phase output stage and the output of the second single-phase output stage to the input terminal of the differential input stage via a feedback capacitor; 3. The differential amplifier circuit according to claim 2, wherein values of the first to fourth capacitors are changed according to the value. A differential input stage for amplifying a differential input signal applied to the input end;
A first single-phase output stage coupled to a first output of the differential input stage;
A second single-phase output stage coupled to the second output of the differential input stage;
A feedback circuit that switches connection of a feedback path by capacitive coupling according to a switching signal, wherein the feedback circuit is configured to connect the first output terminal and the first single-phase output stage in a first state of the switching signal. And the second output terminal and the output of the second single-phase output stage are respectively coupled via capacitors, and in the second state of the switching signal, the first output terminal Differential amplification characterized by coupling the output of the second single-phase output stage and the output of the second output terminal and the output of the first single-phase output stage through capacitors, respectively. circuit.   A second feedback circuit that is provided separately from the feedback circuit and switches connection of a second feedback path by capacitive coupling in response to a second switching signal, wherein the second feedback circuit includes the second feedback circuit; In the first state of the switching signal, between the first output terminal and the output of the first single-phase output stage and between the second output terminal and the output of the second single-phase output stage. The second switching signal is coupled between the first output terminal and the output of the second single-phase output stage in the second state of the second switching signal, and the second output terminal and the first 5. The differential amplifier circuit according to claim 4, wherein the outputs of one single-phase output stage are coupled via capacitors.   A path for negatively feeding back the output of the first single-phase output stage and the output of the second single-phase output stage to the input terminal of the differential input stage via a feedback capacitor; 6. The differential amplifier circuit according to claim 5, wherein the switching signal is controlled according to a value. A capacitor for fixedly coupling between the first output terminal and the output of the first single-phase output stage;
The difference according to any one of claims 4 to 6, further comprising a capacitor for fixedly coupling between the second output terminal and the output of the second single-phase output stage. Dynamic amplification circuit.

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