JP2009283771A - Laminate printed circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminate printed circuit board which allows improvement in efficiency of inductance per area by forming a coil into one body to raise a winding density of the coil. <P>SOLUTION: A plurality of printed circuit boards 1A to 1C are put one over another, and a plurality of parallel outer upper wiring patterns 1 are formed on a first layer surface (principal surface) a, and a plurality of parallel outer lower wiring patterns 8 are formed on a fourth layer surface (back surface) d, and both ends of these wiring patterns are connected to each other by outer conduction holes 3 to constitute an outer coil 10A, and a plurality of parallel inner upper wiring patterns 4 are formed on a second layer surface (inner layer surface) b, and a plurality of inner lower wiring patterns 6 are formed on a third layer surface (inner layer surface) c, and both ends of these wiring patterns are connected to each other by inner conduction holes 5 to constitute an inner coil 10B, and one end part of the outer coil and one end part of the inner coil are connected by a connection path R to obtain a structure of one electrically connected coil K. Coils are laminated and integrally formed in a perpendicular direction of the laminate printed circuit board, whereby time and effort for coil attachment and the number of components can be reduced and a component mounting area can be effectively used. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a laminated printed board in which a coil structure is integrally formed.

  In order to mount a coil on a printed circuit board on which a circuit based on a wiring pattern is formed, a coil component manufactured separately is generally soldered to the printed circuit board. However, even when a special standard coil is mounted on a printed circuit board having a circuit that requires a very small amount of demand, the coil must be designed and manufactured each time.

  Therefore, the efficiency of the operation of providing the coil on the printed circuit board is poor. Therefore, for example, the invention disclosed in [Patent Document 1] has been provided. According to this invention, it is described that when a coil is provided on a substrate, it is not necessary to prepare a coil component, and the work of providing a coil on the substrate is improved.

In the invention, a plurality of printed wiring patterns are provided on both sides of a substrate by a known printed wiring pattern forming method. Further, a through hole with a conductive layer such as a through hole print wiring system, formed by a known wiring scheme for electrically connecting the substrate both sides of the printed wiring pattern directly on a printed circuit board, the n-number of coils It comes to form.
JP 2000-223316 A

  According to [Patent Document 1], both ends of a wiring pattern formed on both surfaces of a substrate and through holes, which are through holes provided through the substrate, are sequentially connected to form a coil directly on the substrate. It is possible. However, a single substrate is used, and a single-phase coil is formed using both surfaces and the plate thickness.

  By the way, ultra-miniaturization of information gathering devices and communication devices in recent years is being realized, and miniaturization of coils and transformers used in oscillators, receiving circuits, electromagnetic wave detection sensors and the like incorporated in these devices is becoming more and more compact. Desired. On the other hand, there is a tendency to use a printed circuit board in which a plurality of printed circuit boards provided with these electronic components are stacked and stacked.

  However, even if the technique of [Patent Document 1] is simply applied and a single printed circuit board is replaced with a multilayer printed circuit board, wiring patterns are basically formed on the main surface (front surface) and the back surface of the multilayer printed circuit board. It is only done. The through holes connecting these wiring patterns are also provided penetrating from the front surface to the back surface of the multilayer printed board.

  As a result, only a single-phase winding coil in which the conductor can be wound only once can be formed, and a large inductance cannot be obtained with a limited area. Furthermore, since the conductor pattern is formed on the main surface or the back surface of the multilayer printed board, the mounting area for the electronic component to be mounted is reduced accordingly.

  The present invention has been made on the basis of the above circumstances, and the object of the present invention is to integrally form a multi-phase coil to increase the winding density of the coil and to improve the efficiency of inductance per area. A multilayer printed circuit board shall be provided.

  Furthermore, it is intended to provide a multilayer printed circuit board in which a coil is integrally formed on a printed circuit board, labor and time required for attaching the coil, and the number of parts can be reduced, and an area of an outer layer surface on which an electronic component is mounted can be used effectively.

  In order to satisfy the above object, the multilayer printed circuit board of the present invention allows a plurality of printed circuit boards to be overlapped, and a wiring pattern can be formed on the main surface, the back surface opposite to the main surface, and the mating surface of the printed circuit boards. A plurality of parallel wiring patterns formed on the main surface and a plurality of parallel wiring patterns formed on the back surface, and both ends of the wiring patterns from the main surface to the back surface. A plurality of parallel lines formed on the inner layer surface between the main surface and the back surface are configured by communicating with a through hole (hereinafter the same) that is a through hole having a conductive layer on the inner wall surface provided over the inner wall surface. A wiring pattern and a plurality of parallel wiring patterns formed on an inner layer surface different from the inner layer surface by connecting both ends of the wiring patterns with each other through a conduction hole provided across the inner layer surface. Configure the coil And forms a single coil structure communicating with one end portion of the one end portion and the inner coil of the outer coil.

  Therefore, the inner coil and the outer coil are integrally formed on the multilayer printed board, and the outer and inner coils are communicated with each other through the communication path, so that the coil having a multiphase winding is integrally formed. In particular, it is not necessary to manufacture and mount a coil component, so that labor can be reduced and the winding density of the coil can be increased by forming the conductor in a multi-phase winding form.

  Further, in the multilayer printed circuit board, the inner coil as well as the outer coil communicate with each other through a conduction hole provided with a conductive layer on the inner wall surface provided from the main surface to the back surface, and one end of the outer coil and one end of the inner coil are communicated with each other. To form a single coil structure.

  There is no need to provide a conduction hole corresponding to each of the outer coil and the inner coil, and it is only necessary to provide a conduction hole penetrating from the main surface to the back surface. There is no change in the coil structure obtained, and the labor can be reduced.

  Further, in the multilayer printed circuit board, a plurality of parallel wiring patterns formed on the inner layer surface between the main surface and the back surface, and a plurality of parallel wiring patterns formed on the inner layer surface different from the inner layer surface Are connected by a conduction hole provided between the inner layer surfaces of each other to form one coil structure, and the main surface and the back surface are used as a mounting space for electronic components and a space for forming other wiring patterns.

  While integrally forming on the inner layer surface of the projected area of the mounting part (electronic component and mounting wiring pattern) of the electronic component in the thickness direction, a space for mounting the required electronic component on the outer layer surface is secured, The area can be effectively used as a component mounting space.

  Also, in the multilayer printed circuit board, the outer conductive holes provided from the main surface to the back surface of the plurality of parallel wiring patterns formed on the main surface and the end portions of the plurality of parallel wiring patterns formed on the back surface. A plurality of parallel wiring patterns formed on the inner layer surface between the main surface and the back surface, and a plurality of parallel wiring patterns formed on an inner layer surface different from the inner layer surface, forming an outer coil by communicating with each other The inner coil was configured by communicating both ends of each other with an inner conduction hole provided across the inner layer surfaces.

  A transformer can be configured by forming an outer coil and an inner coil that are independent from each other, one of which is a primary winding and the other is assigned to a secondary winding. Furthermore, by integrally forming the primary winding and the secondary winding within the same projected area in the thickness direction of the multilayer printed circuit board, it is possible to reduce the labor and time required for mounting the manufactured coil.

  In addition, in the multilayer printed circuit board, the mutual ends of the plurality of parallel wiring patterns formed on the main surface and the plurality of parallel wiring patterns formed on the inner layer surface between the main surface and the back surface are arranged from the main surface. A plurality of parallel wiring patterns formed on the inner layer surface different from the inner layer surface and a plurality of parallel wiring patterns formed on the rear surface constitute the first coil by communicating with the first conduction hole provided over the layer surface. The second coil was configured by communicating both end portions of the parallel wiring patterns through a second conduction hole provided from the inner layer surface to the back surface.

  A plurality of coils that are independent of each other in the thickness direction can be laminated and integrally formed, so that it is not necessary to separately manufacture a coil, and it is possible to reduce the labor for attaching the manufactured coil and reduce the number of parts. Also, coils with different characteristics can be integrally formed by varying the number of turns and the conductor spacing.

  According to the present invention, a coil is directly formed on a printed circuit board, the winding density of the coil is increased, and the efficiency of inductance per area can be improved. In addition, there are effects such as reduction of labor for attaching the coil and reduction in the number of components, and effective use of the outer layer surface on which the electronic component is mounted as a component mounting space.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 3 show a first embodiment, FIG. 1 is a perspective view of a multilayer printed board P, FIG. 2A is a perspective view schematically showing an outer coil 10A, and FIG. FIG. 3A is a schematic perspective view of the first layer surface a, FIG. 3B is a schematic perspective view of the second layer surface b, and FIG. 3C is a third perspective view schematically showing the inner coil 10B. It is a schematic perspective view of the layer surface c.

In the figure, reference numeral 1 denotes a laminated printed circuit board. Here, three printed circuit boards 1A to 1C are superimposed and integrally formed, but more printed circuit boards may be stacked.
The upper surface of the uppermost printed circuit board 1A is the first layer surface a, the mating surface of the uppermost printed circuit board 1A and the middle printed circuit board 1B is the second layer surface b, and the mating surface of the middle printed circuit board 1B and the lowermost printed circuit board 1C is the third. The layer surface c and the lower surface of the lowermost printed circuit board 1C are defined as a fourth layer surface d.

  Therefore, as the multilayer printed board P, the first layer surface a is the main surface, and the fourth layer surface d is the back surface opposite to the main surface. The second layer surface b and the third layer surface c between the main surface (first layer surface a) and the back surface (fourth layer surface d) are inner layer surfaces. In any of the layer surfaces a to d, a wiring pattern can be formed.

  Actually, the middle printed circuit board 1B is merely an intermediate plate material in which only a through hole is provided and no wiring pattern is formed. With the intermediate plate material 1B in between, the uppermost printed circuit board 1A is superimposed on the upper surface of the intermediate plate material 1B, and the lowermost printed circuit board 1C is integrated on the lower surface.

  A wiring pattern to be described later is formed on the first layer surface a that is the upper surface of the uppermost printed circuit board 1A and the second layer surface b that is the lower surface. And the wiring pattern mentioned later is formed in the 4th layer surface d which is the 3rd layer surface c which is the upper surface of 1C of the lowest stage printed circuit boards. Further, all printed circuit boards 1A to 1C are provided with conduction holes made of through holes to be described later.

  As shown in FIG. 3A, on the first layer surface a, a plurality (three in this case) of outer upper wiring patterns 1 are provided in parallel with each other with a predetermined insulation interval and one jumping pattern. 2 is provided.

  The outer upper wiring pattern 1 is provided obliquely with respect to the longitudinal direction of the printed circuit board 1A, and both ends thereof are provided from the first layer surface a to the second layer surface b and are through holes that form the outer coil 10A. Connected to the outer conduction hole 3. That is, the outer conduction holes 3 are provided in two rows with respect to the width direction of the printed circuit board 1A, with a predetermined insulation interval along the longitudinal direction.

  From the shape of the outer upper wiring pattern 1, the outer upper wiring pattern 1 is not provided in the outer conduction hole 3 e (see FIGS. 1, 2 and 3) on one side (front side) on the rightmost side. One end of the jumping pattern 2 is connected. Further, the other end portion of the jumping pattern 2 is connected to the outer conduction hole 3f on the other (back) side in the leftmost portion.

  The jumping pattern 2 is provided in parallel to the outermost upper wiring pattern 1 on the right side from the outer conductive hole 3e on one side, and is bent at a portion near the edge in the width direction of the printed board 1A. Then, it extends along the other side outer conduction hole 3 and the longitudinal edge of the printed circuit board 1A, and is connected to the other side outer conduction hole 3f on the leftmost side.

As shown in FIG. 3B, a plurality (three in this case) of the inner upper wiring patterns 4 are provided on the second layer surface b with a predetermined insulation interval between them, and the second layer surface b to the third layer surface b. An inner conduction hole 5 and an outer conduction hole 3, which are through holes forming the inner coil 10B, are provided over the layer surface c.
The outer conduction hole 3 (including 3e and 3f, hereinafter the same) is provided at a position communicating with the outer conduction hole 3 described above with reference to FIG. Therefore, the outer conduction hole 3 is penetrated from the first layer surface a to the third layer surface c through the second layer surface b so far.

The inner upper wiring pattern 4 is provided obliquely with respect to the longitudinal direction of the printed circuit board 1B. The inclination direction is the same as that of the outer upper wiring pattern 1, but the inclination angle is larger than that of the outer upper wiring pattern 1.
The inclination of the inner upper wiring pattern 4 may be arbitrarily formed while maintaining a predetermined insulation interval of the wiring pattern (conductor) based on the coil characteristics (for example, inductance and winding density).

  Both end portions of these inner upper wiring patterns 4 are connected to the inner conduction holes 5 which are through holes provided from the second layer surface b to the third layer surface c. That is, the inner conduction holes 5 are provided in two rows facing the width direction of the printed circuit board 1B, with a predetermined insulation interval along the longitudinal direction.

  Both the outer upper wiring pattern 1 that forms the outer coil 10A and the inner upper wiring pattern 4 that forms the inner coil 10B both extend from the center position in the width direction of the printed boards 1A and 1B in the width direction (from the front to the rear in FIG. 1). The length is equally distributed along the left and right. As a matter of course, the mutual distance between the inner conductive holes 5 which is the entire length of the inner upper wiring pattern 4 is shorter than the mutual distance between the outer conductive holes 3 which is the entire length of the outer upper wiring pattern 1.

  As shown in FIG. 3C, a plurality (two in this case) of inner lower wiring patterns 6 are provided at predetermined insulation intervals on the third layer surface c, and one guide pattern 7 is formed. Is done. Further, a plurality of outer conduction holes 3 and one inner conduction hole 5f which are through holes are provided from the third layer surface c to the fourth layer surface d.

The outer conduction hole 3 is provided at a position communicating with the outer conduction hole 3 described with reference to FIGS. 3 (A) and 3 (B). Therefore, the outer conduction hole 3 penetrates from the first layer surface a to the fourth layer surface d through the second layer surface b and the third layer surface c.
In the present embodiment, only the outer conduction hole 3e on one side of the rightmost side is provided only from the first layer surface a to the third layer surface c via the second layer surface b, and is formed on the fourth layer surface d. Does not penetrate.

The inner lower wiring pattern 6 on the third layer surface c is provided in an oblique direction opposite to the inner upper wiring pattern 4 on the second layer surface b. The both end portions are connected to the inner conduction hole 5 provided from the second layer surface b to the third layer surface c.
As described above, the inner conduction hole 5 is connected to both end portions of the inner upper wiring pattern 4, but only the inner conduction hole 5f on one side of the leftmost portion extends from the third layer surface c to the fourth layer surface d. Provided. In other words, the other inner conduction hole 5 except the inner conduction hole 5f on one side on the leftmost side is provided only from the second layer surface b to the third layer surface c, and the upper and lower end portions are blocked from here. The

  One end portion of the guide pattern 7 provided on the third layer surface c is connected to the outer conduction hole 3 on one side at the rightmost portion provided on the third layer surface c through the second layer surface b from the first layer surface a. The other end is connected to the inner conduction hole 5 on the other side on the rightmost side. Therefore, the guide pattern 7 is provided across the outer conduction hole 3 e and the inner conduction hole 5.

Further, on the fourth layer surface d shown in FIG. 3C, a plurality of outer lower wiring patterns 8 are provided with predetermined insulation intervals as shown by broken lines, and the first terminal pattern 9a and the second terminal pattern 9 The terminal pattern 9b is formed.
The outer lower wiring pattern 8 is inclined in a direction opposite to the outer upper wiring pattern 1 formed on the first layer surface a, and both end portions thereof are connected to the outer conductive hole 3.

One end portion of the first terminal pattern 9a is connected to the inner conduction hole 5f on one side at the leftmost portion provided from the third layer surface c to the fourth layer surface d, and is provided in the longitudinal direction of the printed circuit board 1C. It is done.
One end portion of the second terminal pattern 9b provided at the winding start portion and the terminal portion of the coil to be formed is provided so as to penetrate from the first layer surface a to the fourth layer surface d. It is connected to the conduction hole 3 and is provided in the longitudinal direction of the printed circuit board 1C opposite to the first terminal pattern 9a.

Note that the wiring directions of these terminal patterns 9a and 9b are appropriately changed according to the mounting wiring pattern of an electronic component (not shown), and are not limited to the above shapes.
In this manner, a plurality of types of wiring patterns are formed across the first layer surface a to the fourth layer surface d, and the outer conduction hole 3 and the inner conduction hole 5 are provided. By superimposing these three printed circuit boards 1A to 1C, an outer coil 10A shown in FIG. 2A and an inner coil 10B shown in FIG. 2B are formed.

First, from the inner coil 10B of FIG. 2B, the first terminal pattern 9a formed on the fourth layer surface d rises to the second layer surface b through the inner conduction holes 5f, 5 and is formed most here. It communicates with the inner upper wiring pattern 4 on the left side.
The inner upper wiring pattern 4 is lowered to the third layer surface c by the inner conduction hole 5 on the other side and communicates with the inner lower wiring pattern 6. The second layer surface is communicated with the inner conduction hole 5 on the one side from the inner lower wiring pattern 6. It goes up to b and communicates with the inner upper wiring pattern 4.

  Further, the inner upper wiring pattern 4 is lowered to the third layer surface c by the inner conductive hole 5 on the other side, communicates with the inner lower wiring pattern 6, and is raised to the second layer surface b by the inner conductive hole 5 on the one side. It communicates with the upper wiring pattern 4. Hereinafter, by sequentially repeating this configuration, the inner coil 10 </ b> B having a corner portion but wound in a substantially spiral shape is formed.

Finally, the inner coil 10B descends to the third layer surface c at the inner conduction hole 5 on the other rightmost side and is connected to the guide pattern 7 formed here. The guide pattern 7 communicates with the jumping pattern 2 formed on the first layer surface a through the outer conductive hole 3e on one side, and is further connected to the outer coil 10A shown in FIG.
That is, the guide pattern 7, the outer conduction hole 3, and the jumping pattern 2 constitute a communication path R that communicates the inner coil 10B and the outer coil 10A.

As shown in FIG. 2A, the jumping pattern 2 is parallel to the outermost upper wiring pattern 1 on the rightmost side and between the outer conductive hole 3 on the other side and the edge along the longitudinal direction of the printed board 1A. Provided on the leftmost side and communicated with the outer conduction hole 3f on the other end side.
The outer conduction hole 3f drops from the first layer surface a to the fourth layer surface d through the second layer surface b and the third layer surface c, and communicates with the outermost lower wiring pattern 8 formed in the leftmost portion. The outer lower wiring pattern 8 goes up to the first layer surface a through the outer conductive hole 3 on one side and communicates with the outer upper wiring pattern 1 formed here.

  Then, the outer upper wiring pattern 1 is lowered to the fourth layer surface d through the outer conductive hole 3 on the other side and communicates with the outer lower wiring pattern 8. The outer lower wiring pattern 8 goes up to the first layer surface a through the outer conductive hole 3 on one side, communicates with the outer upper wiring pattern 1 and goes down to the fourth layer surface d through the outer conductive hole 3 on the other side.

Hereinafter, by repeating the above state a plurality of times, the outer coil 10 </ b> A having a corner but a substantially spiral shape is formed. Finally, the outer coil 10A is lowered to the fourth layer surface d at the rightmost outer conductive hole 3 on the rightmost side, and is connected to the second terminal pattern 9b formed here.
As shown in FIG. 1, an inner coil 10B and an outer coil 10A are integrally formed with each other on the multilayer printed circuit board P, and the outer and inner coils 10A and 10B are communicated with each other via a communication path R, so that a multiphase winding is formed. The coil K having the following structure is integrally formed.

By integrally forming the coil K electrically connected to the multilayer printed circuit board P, it is not necessary to manufacture and mount a coil component in particular, and the labor can be reduced, and the conductor is in a two-phase winding form. As a result, the winding density of the coil K can be increased, and the inductance efficiency per area is improved.
Further, this embodiment is suitable for increasing the number of turns by closely contacting the longitudinal pitches of the wiring patterns 1, 4, 6, and 8 of the integrally formed coil K.

4 and 5A and 5B show a modification of the first embodiment. FIG. 4 is a perspective view of the multilayer printed board P, and FIG. 5A is a schematic view of the outer coil 10A. FIG. 5B is a perspective view schematically showing the inner coil 10B.
As described above, the multilayer printed circuit board P itself is configured by superimposing the three printed circuit boards 1A, 1B, and 1C. The top surface of the uppermost printed circuit board 1A is the first layer surface a, and the uppermost printed circuit board 1A and the middle circuit board are stacked. The mating surface with the printed circuit board 1B is referred to as the second layer surface b, the mating surface between the middle printed circuit board 1B and the lowermost printed circuit board 1C is referred to as the third layer surface c, and the lower surface of the lowermost printed circuit board 1C is referred to as the fourth layer surface d. There is no change.

  Therefore, as the multilayer printed board P, the first layer surface a is the main surface, and the fourth layer surface d is the back surface opposite to the main surface. The second layer surface b and the third layer surface c between the main surface (first layer surface a) and the back surface (fourth layer surface d) are inner layer surfaces. In any of the layer surfaces a to d, a wiring pattern can be formed.

  The outer upper wiring pattern 1 and the jumping pattern 2 are formed on the first layer surface a, and the inner upper wiring pattern 4 is formed on the second layer surface b. The inner lower wiring pattern 6 is formed on the third layer surface c, and the outer lower wiring pattern 8, the first terminal pattern 9a, and the second terminal pattern 9b are formed on the fourth layer surface d.

  Here, all the outer conduction holes 3 and the inner conduction holes 5 are provided so as to penetrate from the first layer surface a to the fourth layer surface d through the second layer surface b and the third layer surface c. That is, in the embodiment described above, the upper ends and / or the lower ends of some of the outer conduction holes 3 and all of the inner conduction holes 5 are in a closed state.

  Therefore, before the three printed circuit boards 1A to 1C are overlapped, through-hole processing is not performed on the outer conductive hole 3 for forming the outer coil 10A or the inner conductive hole 5 for forming the inner coil 10B at a necessary portion. Don't be. Since this processing is performed separately from the processing for the outer conduction hole 3 penetrating from the first layer surface a to the fourth layer surface d, it takes time and labor.

  On the other hand, as shown in FIGS. 4 and 5B, all the inner conduction holes 5 including the outer conduction holes 3 connected to the guide pattern 7 and the jumping pattern 2 are second to second layers from the first layer surface a. Through the layer surface b and the third layer surface c to the fourth layer surface d, it becomes a through hole penetrating the three printed circuit boards 1A to 1C.

  In other words, after the three printed boards 1 </ b> A to 1 </ b> C are overlapped to form the multilayer printed board P, through holes for all the outer conductive holes 3 and the inner conductive holes 5 can be processed. As in the embodiment described above, there is no need to make different processing for one outer conduction hole 3 and all inner conduction holes 5, and the labor can be reduced.

The completed outer coil 10A is exactly the same as the outer coil 10A structure previously described with reference to FIG. 2A, and the completed inner coil 10B itself is the same as the inner coil shape 10B previously described with reference to FIG. Is exactly the same. There is no change in the multilayer printed circuit board P being integrally formed with the electrically connected outer coil 10A, inner coil 10B, and coil K composed of the communication path R.
Therefore, the coil K structure shown in FIG. 4 is not different from the coil K structure described with reference to FIG. 1, and the same effect can be obtained. Furthermore, it is possible to increase the number of winding phases of the integrally formed coil K by increasing the number of stacked printed circuit boards from three.

6 is a perspective view of the multilayer printed board P showing the second embodiment, FIG. 7A is a schematic perspective view of the first layer surface a, and FIG. 7B is a schematic perspective view of the second layer surface b. 7 (C) is a schematic perspective view of the third layer surface c.
Three printed circuit boards 1A to 1C are overlapped to form a laminated printed circuit board P. The upper surface of the uppermost printed circuit board 1A is the first layer surface a, and the mating surface of the uppermost printed circuit board 1A and the intermediate printed circuit board 1B is the second. The layer surface b, the mating surface of the middle printed circuit board 1B and the lowermost printed circuit board 1C is the third layer surface c, and the lower surface of the lowermost printed circuit board 1C is the fourth layer surface d.

  Therefore, as the multilayer printed board P, the first layer surface a is the main surface, and the fourth layer surface d is the back surface opposite to the main surface. The second layer surface b and the third layer surface c between the main surface (first layer surface a) and the back surface (fourth layer surface d) are inner layer surfaces. In any of the layer surfaces a to d, a wiring pattern can be formed.

As shown in FIG. 7A, an electronic component D such as a semiconductor element is mounted on the first layer surface a, and a wiring pattern (not shown) connected to the electronic component D and a coil terminal pattern 12a, 12b is formed.
As shown in FIG. 7B, on the second layer surface b, a plurality (here, three) of upper wiring patterns 11 are provided in parallel with a predetermined insulation interval, and the terminal patterns 12a, 12b. A through hole 13 which is a through hole communicating with the first layer a is formed from the first layer a to the second layer b.

  The upper wiring pattern 11 is provided obliquely with respect to the longitudinal direction of the printed circuit board 1B, and both ends thereof are connected to conduction holes 13 that are through holes provided from the second layer surface b to the third layer surface c. . That is, the conduction holes 13 are provided in two rows facing the width direction of the printed circuit board 1B, with a predetermined insulation interval along the longitudinal direction.

From the shape of the upper wiring pattern 11, the upper wiring pattern 11 is not connected to the conduction hole 13 on the one side (front side) on the leftmost side, and the winding end of the coil communicating with the first terminal pattern 12 a (Start point or end point) is provided.
In addition, the upper wiring pattern 11 is not connected to the conduction hole 13 on the other (back) side in the rightmost part, and a coil winding end (end point or starting point) communicating with the second terminal pattern 12b is provided. It has been.

As shown in FIG. 7C, on the third layer surface c, a plurality (four in this case) of lower wiring patterns 14 are provided in parallel with each other with a predetermined insulation interval. In other words, the leftmost lower wiring pattern 14 communicates with the first terminal pattern 12a on the first layer surface a through the conduction hole 13 on one side of the second layer surface b on the leftmost portion.
Further, the lowermost wiring pattern 14 on the rightmost side communicates with the second terminal pattern 12b on the first layer surface a through the conduction hole 13 on the other side of the second layer surface b on the rightmost side.

In this way, the upper and lower wiring patterns 11 and 14 and the conduction holes 13 are provided on the second layer surface b and the third layer surface c which are inner layer surfaces, and the three printed circuit boards 1A to 1C are overlapped to form the laminated printed circuit board P. By configuring, a coil Ka structure as shown in FIG. 6 can be obtained.
That is, the first terminal pattern 12a formed on the first layer surface a is lowered to the third layer surface c through the one conduction hole 13 and connected to the lower wiring pattern 14 formed here. The lower wiring pattern 14 goes up to the second layer surface b through the conductive hole 13 on the other side, and communicates with the upper wiring pattern 11 formed here.

Further, the upper wiring pattern 11 is lowered to the third layer surface c through the conduction hole 13 on one side and communicates with the lower wiring pattern 14, and is raised to the second layer surface b through the conduction hole 13 on the other side and communicates with the upper wiring pattern 11.
Hereinafter, by repeating this configuration sequentially, a coil Ka having a corner portion but having a substantially spiral shape is formed. Finally, the coil Ka rises to the first layer surface a through the other conduction hole 13 and is connected to the second terminal pattern 12b.

  After all, in this embodiment, the coil Ka using only the second layer surface b and the third layer surface c which are inner layer surfaces is obtained integrally. The first layer surface a which is the outer layer surface is provided with the conduction holes 13 and the terminal patterns 12a and 12b, but the wiring patterns 11 and 14 and the conduction holes 13 are not provided on the fourth layer surface d.

The terminal patterns 12a and 12b may be formed on the third layer surface d so that they can communicate with each other through the conduction hole 13.
In other words, while the electrically connected coil Ka is integrally formed on the inner layer surface of the projection area of the mounting portion (electronic component D and mounting wiring pattern) of the electronic component D in the thickness direction of the multilayer printed board P, the outer layer surface Thus, a space for mounting the necessary electronic component D on the first layer surface a and the fourth layer surface d can be secured, and the area of the outer layer surface can be effectively used as the component mounting space.
Furthermore, in order to increase the winding density of the coil Ka and improve the efficiency of inductance per area, another printed circuit board is laminated on the fourth layer surface d, and the wiring pattern is formed as described above. Good.

  8 to 10 show the third embodiment, FIG. 8 is a perspective view of the multilayer printed board P, FIG. 9A is a perspective view schematically showing the outer coil 30A, and FIG. FIG. 10A is a schematic perspective view of the first layer surface a, FIG. 10B is a schematic perspective view of the second layer surface b, and FIG. 10C is the third perspective view schematically showing the inner coil 30B. It is a schematic perspective view of the layer surface c.

  Three printed circuit boards 1A to 1C are overlapped to form a laminated printed circuit board P. The upper surface of the uppermost printed circuit board 1A is the first layer surface a, and the combined surface of the uppermost printed circuit board 1A and the intermediate printed circuit board 1B is the second layer surface. b. It is not changed that the mating surface of the middle printed board 1B and the lowermost printed board 1C is the third layer surface c and the lower surface of the lowermost printed board 1C is the fourth layer surface d.

  Therefore, as the multilayer printed board P, the first layer surface a is the main surface, and the fourth layer surface d is the back surface opposite to the main surface. The second layer surface b and the third layer surface c between the main surface (first layer surface a) and the back surface (fourth layer surface d) are inner layer surfaces. In any of the layer surfaces a to d, a wiring pattern can be formed.

  As shown in FIG. 10 (A), on the first layer surface a, outer upper wiring patterns 22 forming a plurality (here, two) of outer coils 30A are provided in parallel with each other with a predetermined insulation interval. In addition, a first outer terminal pattern 23a and a second outer terminal pattern 23b are provided.

  The outer upper wiring pattern 22 is provided obliquely with respect to the longitudinal direction of the printed circuit board 1A, and both end portions thereof are through holes that form an outer coil 30A provided from the first layer surface a to the second layer surface b. Connected to the outer conduction hole 24. That is, the outer conduction holes 24 are provided in two rows facing the width direction of the printed circuit board 1A, with a predetermined insulation interval along the longitudinal direction of the printed circuit board 1A.

  From the shape of the outer upper wiring pattern 22, the outer upper wiring pattern 22 is not provided in the outer conduction hole 24 on the leftmost side (front side), and the first outer terminal pattern 23 a is connected. . The first outer terminal pattern 23a is formed substantially in parallel with the outermost upper wiring pattern 22 on the leftmost side, and is bent in the vicinity of the outer conduction hole 24 on the other (back) side. It is provided in the longitudinal direction.

  The second outer terminal pattern 23b is connected to the outer conductive hole 24 on the other rightmost side. The second outer terminal pattern 23b is substantially parallel to the outermost upper wiring pattern 22 on the rightmost side, and is bent at a portion near the outer conduction hole 24 on one side. The first outer terminal pattern 23a is It is provided in the longitudinal direction of the printed circuit board 1A on the opposite side.

The wiring directions of these terminal patterns 23a and 23b are appropriately changed according to a mounting wiring pattern (not shown) of an electronic component (not shown), and are not limited to the above shape.
As shown in FIG. 10B, on the second layer surface b, inner upper wiring patterns 25 forming a plurality (three in this case) of inner coils 30B are provided in parallel with each other at a predetermined insulating interval. One first inner terminal pattern 26a and second inner terminal pattern 26b are provided.

The first and second inner terminal patterns 23a and 23b may be provided on the first layer surface a or the third layer surface d through the outer conduction holes 24 (for example, 26aa and 26bb in FIG. 10C). reference).
The wiring directions of these terminal patterns 23a and 23b are appropriately changed according to a mounting wiring pattern (not shown) of an electronic component (not shown) mounted on the first layer surface a or the third layer surface d. The shape is not limited to the above.

  Furthermore, an inner conduction hole 27 and a plurality of outer conduction holes 24 which are through holes forming the plurality of inner coils 30B are provided from the second layer b to the third layer c. The inner conduction holes 27 are provided in two rows facing the width direction of the printed circuit board 1B, with a predetermined insulation interval along the longitudinal direction.

The outer conduction hole 24 is provided at a position communicating with the outer conduction hole 24 described above with reference to FIG. 10A. Therefore, the outer conduction hole 24 is thus far from the first layer surface a to the second layer surface b. It will be provided over the 3rd layer surface c via.
The inner upper wiring pattern 25 is provided obliquely with respect to the longitudinal direction of the printed circuit board 1B, and the inclination direction is the same as the outer upper wiring pattern 22, but the inclination angle is larger than that of the outer upper wiring pattern 22. Is done. Both end portions of the inner upper wiring pattern 25 are connected to the inner conduction hole 27.

  Due to the shape of the inner upper wiring pattern 25, the inner upper wiring pattern 25 is not provided in the inner conduction hole 27 on one side on the leftmost side, and the first inner terminal pattern 26a is connected instead. The first inner terminal pattern 26a is provided in the longitudinal direction of the printed circuit board 1B.

  The inner upper wiring pattern 25 is not provided in the inner conduction hole 27 on the other rightmost side, and the second inner terminal pattern 26b is connected instead. The second inner terminal pattern 26b is provided in the longitudinal direction of the printed circuit board 1B opposite to the first inner terminal pattern 26a.

  Both the outer upper wiring pattern 22 and the inner upper wiring pattern 25 have lengths equally distributed to the left and right along the width direction from the center position in the width direction of the printed circuit boards 1A and 1B. Needless to say, the distance between the inner conductive holes 27 that is the entire length of the inner upper wiring pattern 25 is shorter than the distance between the outer conductive holes 24 that is the entire length of the outer upper wiring pattern 22.

As shown in FIG. 10C, a plurality of inner lower wiring patterns 28 are provided in parallel on the third layer surface c with a predetermined insulation interval, and extend from the third layer surface c to the fourth layer surface d. A plurality of outer conduction holes 24 which are through holes are provided.
The outer conduction hole 24 is provided at a position communicating with the outer conduction hole 24 described with reference to FIGS. 10 (A) and 10 (B). Therefore, all the outer conduction holes 24 are provided to penetrate from the first layer surface a to the fourth layer surface d through the second layer surface b and the third layer surface c.

The inner lower wiring pattern 28 on the third layer surface c is provided in an oblique direction opposite to the inner upper wiring pattern 25 provided on the second layer surface b. The both end portions are connected to the inner conduction holes 27 provided at both end portions of the inner upper wiring pattern 25 from the second layer surface b to the third layer surface c.
As described above, all the outer conduction holes 24 are provided from the first layer surface a to the fourth layer surface d, whereas all the inner conduction holes 27 are provided only from the second layer surface b to the third layer surface c. It is not provided, and the upper and lower ends are closed from here.

  Furthermore, a plurality of outer lower wiring patterns 29 are formed on the fourth layer surface d shown in FIG. The outer lower wiring pattern 29 is provided in an oblique direction opposite to the outer upper wiring pattern 22 formed on the first layer surface a, and both end portions thereof are connected to the outer conductive hole 24.

  In this way, a plurality of types of wiring patterns are formed on each of the first layer surface a to the fourth layer surface d, and the inner and outer conductive holes 27 and 24 are provided. By laminating these three printed circuit boards 1A to 1C to form a laminated printed circuit board P, an outer coil 30A shown in FIG. 9A and an inner coil 30B shown in FIG. 9B are integrally formed. .

First, from the outer coil 30A of FIG. 9A, the leftmost left side formed on the first layer terminal pattern 23a formed on the first layer surface a falls from the first outer terminal pattern 23a to the fourth layer surface d through the outer conduction hole 24. It communicates with the outer lower wiring pattern 29 of the part.
The outer lower wiring pattern 29 goes up to the first layer surface a through the outer conductive hole 24 on the other side, communicates with the outer upper wiring pattern 22, and goes down to the fourth layer surface d through the outer conductive hole 24 on one side. It communicates with the pattern 29 and communicates with the outer upper wiring pattern 22 on the first layer surface a through the outer conduction hole 24 on the other side.

  Hereinafter, by sequentially repeating this configuration, an outer coil 30A having corner portions but wound in a substantially spiral shape is formed. Finally, the outer coil 30A rises to the first layer surface a at the other-side outer conduction hole 24 at the rightmost portion and is connected to the second outer terminal pattern 23b. In this way, the outer coil 30A is integrally formed independently on the multilayer printed board P using the first layer surface a and the fourth layer surface d.

  Next, the inner coil 30B of FIG. 9B will be described. The first inner terminal pattern 26a formed on the second layer surface b is lowered to the third layer surface c by the inner conduction hole 27, and the inner left lowermost portion is lowered. It communicates with the wiring pattern 28. The inner lower wiring pattern 28 rises to the second layer surface b through the other inner conduction hole 27 and communicates with the inner upper wiring pattern 25.

  From the inner upper wiring pattern 25, the inner conductive hole 27 on one side descends to the third layer surface c and communicates with the inner lower wiring pattern 28. The inner lower wiring pattern 28 rises to the second layer surface b through the other inner conduction hole 27 and communicates with the inner upper wiring pattern 25. Hereinafter, by sequentially repeating this configuration, an inner coil 30B having a corner portion but wound in a substantially spiral shape is formed.

  Finally, the inner coil 30B is connected to the second inner terminal pattern 26b via the other-side inner conduction hole 27 in the rightmost part. That is, the inner coil 30b is integrally formed independently on the multilayer printed board P using the second layer surface B and the third layer surface C.

As shown in FIG. 8, an outer coil 30 </ b> A and an inner coil 30 </ b> B that are electrically connected independently of each other are formed on the multilayer printed board P. Therefore, a transformer (transformer) can be formed by assigning one of the primary windings and assigning the other to the secondary winding.
Further, by integrally forming the coils of the primary winding and the secondary winding within the same projected area in the thickness direction of the multilayer printed board P, it is possible to reduce the labor for attaching the manufactured coil and reduce the number of parts.

  11 to 13 show a fourth embodiment, FIG. 11 is a perspective view of the multilayer printed board P, FIG. 12A is a perspective view schematically showing the first coil 40A, and FIG. (B) is a perspective view schematically showing the second coil 40B, FIG. 13 (A) is a schematic perspective view of the first layer surface a, FIG. 13 (B) is a schematic perspective view of the second layer surface b, FIG. (C) is a schematic perspective view of the third layer surface c.

  Three printed circuit boards 1A to 1C are overlapped to form a laminated printed circuit board P. The upper surface of the uppermost printed circuit board 1A is the first layer surface a, and the combined surface of the uppermost printed circuit board 1A and the intermediate printed circuit board 1B is the second layer surface. b. It is not changed that the mating surface of the middle printed board 1B and the lowermost printed board 1C is the third layer surface c and the lower surface of the lowermost printed board 1C is the fourth layer surface d.

  Therefore, as the multilayer printed board P, the first layer surface a is the main surface, and the fourth layer surface d is the back surface opposite to the main surface. The second layer surface b and the third layer surface c between the main surface (first layer surface a) and the back surface (fourth layer surface d) are inner layer surfaces. In any of the layer surfaces a to d, a wiring pattern can be formed.

As shown in FIG. 13A, on the first layer surface a, a plurality of (here, three) first upper wiring patterns 31 are provided in parallel with each other with a predetermined insulation interval, and one upper A A terminal pattern 32a and an upper B terminal pattern 32b are provided.
The first upper wiring pattern 31 is provided obliquely with respect to the longitudinal direction of the printed circuit board 1A, and both end portions thereof are first conduction holes 33 which are through holes provided from the first layer surface a to the second layer surface b. Connected to. Therefore, the first conduction holes 33 are provided in two rows in the width direction of the printed circuit board 1 </ b> A and with a predetermined insulating interval along the longitudinal direction.

  Due to the shape of the first upper wiring pattern 31, the first upper wiring pattern 31 is not provided in the first conduction hole 33 on the one side (near side) on the leftmost side, and instead the upper A terminal pattern 32a. Is connected. The upper A terminal pattern 32a is provided from the first conduction hole 33 in the longitudinal direction of the printed circuit board 1A.

Also, the first upper wiring pattern 31 is not provided in the first conduction hole 33 on the other rightmost side, and the upper B terminal pattern 32b is connected instead. The upper B terminal pattern 32b is provided in the longitudinal direction of the printed board 1A opposite to the upper A terminal pattern 32a.
The wiring directions of these terminal patterns 32a and 32b are appropriately changed according to a mounting wiring pattern (not shown) of an electronic component (not shown), and are not limited to the above shape.

  As shown in FIG. 13B, a plurality (four in this case) of first lower wiring patterns 34 are provided in parallel on the second layer surface b with a predetermined insulation interval therebetween. These first lower wiring patterns 34 are provided in an oblique direction opposite to the first upper wiring pattern 31, and both end portions thereof are provided from the first layer surface a to the second layer surface b. Connected to the conduction hole 33.

  From the shape of the first lower wiring pattern 34, one (front) end of the first lower wiring pattern 34 formed on the leftmost side is connected to the upper A terminal pattern 32 a via the first conduction hole 33. Communicate. The other (back) end of the first lower wiring pattern 34 formed on the rightmost side communicates with the upper b terminal pattern 32 b via the first conduction hole 33.

As shown in FIG. 13C, the third layer surface c is provided with a plurality of (four in this case) second upper wiring patterns 35 in parallel with each other with a predetermined insulation interval, and the third layer surface c. A plurality of second conduction holes 36 that are through holes are provided from the first layer surface to the fourth layer surface d.
The second upper wiring pattern 35 is provided in an oblique direction opposite to the first lower wiring pattern 34 on the second layer surface b, and both end portions thereof are connected to the second conduction hole 36. Accordingly, the second conduction holes 36 are provided in two rows along the width direction of the printed circuit board 1 </ b> C, with a predetermined insulation interval in the longitudinal direction.

  Further, on the fourth layer surface d shown in FIG. 13C, a plurality of (here, four) second lower wiring patterns 37 are provided in parallel with each other with a predetermined insulation interval, as indicated by a broken line, One lower A terminal pattern 38a and one lower B terminal pattern 38b are provided. The second lower wiring pattern 37 is provided in an oblique direction opposite to the second upper wiring pattern 35, and both end portions are connected to the second conduction hole 36.

The lower A terminal pattern 38a is connected to the second conductive hole 36 at the other end on the leftmost side, and is provided to the edge in the longitudinal direction of the printed circuit board 1C. The lower A terminal pattern 38 a communicates with the leftmost second upper wiring pattern 35 through the second conduction hole 36.
The lower B terminal pattern 38b is connected to the second conduction hole 36 at the other end on the rightmost side, and is provided across the edge of the printed board 1C in the direction opposite to the lower A terminal pattern 38a. The lower B terminal pattern 38 b communicates with the second upper wiring pattern 35 on the rightmost side via the second conduction hole 36.

  Thus, a plurality of types of wiring patterns are formed on each of the first layer surface a to the fourth layer surface d, and the first conduction hole 33 and the second conduction hole 36 are provided. By forming the laminated printed board P by superimposing the three printed boards 1A to 1C, the first coil 40A shown in FIG. 12A and the second coil 40B shown in FIG. 12B are formed. Is done.

  First, the first coil 40A in FIG. 12A will be described. The upper A terminal pattern 32a formed on the first layer surface a is lowered to the second layer surface b by the first conduction hole 33, and is most formed on the first layer surface a. It communicates with the first lower wiring pattern 34 on the left side. Further, the first upper wiring pattern 31 rises from the first lower wiring pattern 34 to the first layer surface a through the first conductive hole 33 on the other side.

  From the first upper wiring pattern 31, the first conductive hole 33 on one side descends to the second layer surface b, communicates with the first lower wiring pattern 34, and the first conductive hole 33 on the other side rises to the first layer surface a. The first upper wiring pattern 31 communicates. Hereinafter, by sequentially repeating this configuration, the first coil 40A having a corner portion but wound in a substantially spiral shape is formed.

  Finally, the first coil 40A rises from the first conductive hole 33 on the rightmost side to the first layer surface a and is connected to the upper B terminal pattern 32b. That is, the first coil 40A is integrally formed independently on the multilayer printed board P using the first layer surface a and the second layer surface b.

  Next, the second coil 40B in FIG. 12B will be described. From the lower A terminal pattern 38a formed on the fourth layer surface d to the third layer surface c through the second conduction hole 36, the leftmost portion of the second coil 40B is shown. 2 communicates with the upper wiring pattern 35. Furthermore, the second upper wiring pattern 35 is lowered to the fourth layer surface d through the second conductive hole 36 on the other side, and communicates with the second lower wiring pattern 37.

  From the second lower wiring pattern 37, the second conductive hole 36 on one side goes up to the third layer surface c, communicates with the second upper wiring pattern 35, and the second conductive hole 36 on the other side from the second upper wiring pattern 35. And goes down to the fourth layer surface d and communicates with the second lower wiring pattern 37. Hereinafter, by sequentially repeating this configuration, the second coil 40 </ b> B having a corner portion but wound in a substantially spiral shape is formed.

Finally, the second coil 40B is lowered from the second conductive hole 36 on the rightmost side to the fourth layer surface d and connected to the lower B terminal pattern 38b. That is, the second coil 40B is integrally formed independently on the multilayer printed board P using the third layer surface c and the fourth layer surface d.
As shown in FIG. 13, a plurality of (first and second) coils 40 </ b> A and 40 </ b> B that are electrically connected to the multilayer printed board P independently of each other can be integrally formed. That is, the first coil 40 </ b> A and the second coil 40 </ b> B are formed by laminating one of the occupied areas within a projected area range projected in the thickness direction of the multilayer printed board P.

  Furthermore, coils having the same inductance characteristic made of the same wiring pattern can be stacked and formed, and coils having different inductance characteristics can be formed by varying the number of turns and the conductor (parallel wiring pattern) interval. Therefore, it is not necessary to manufacture a coil separately, and it is possible to reduce the labor for attaching the manufactured coil and reduce the number of parts.

  Note that the number of wiring patterns and the inclination angle and direction of the wiring patterns in the above-described embodiment are not limited, and can be set as needed. That is, in the implementation stage, the constituent elements can be modified and embodied without departing from the spirit of the invention, and various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments.

1 is a perspective view of a multilayer printed circuit board according to a first embodiment of the present invention. The perspective view which represented typically the outer side coil and inner side coil based on the embodiment. The schematic perspective view of a 1st layer surface, the schematic perspective view of a 2nd layer surface, and the schematic perspective view of a 3rd layer surface based on the embodiment. The perspective view of the lamination printed circuit board concerning the modification of the embodiment. The perspective view which represented typically the outer side coil and inner side coil based on the modification. The perspective view of the multilayer printed circuit board based on 2nd Embodiment in this invention. The schematic perspective view of a 1st layer surface, the schematic perspective view of a 2nd layer surface, and the schematic perspective view of a 3rd layer surface based on the embodiment. The perspective view of the multilayer printed circuit board based on 3rd Embodiment in this invention. The perspective view which represented typically the outer side coil and inner side coil based on the embodiment. The schematic perspective view of a 1st layer surface, the schematic perspective view of a 2nd layer surface, and the schematic perspective view of a 3rd layer surface based on the embodiment. The perspective view of the multilayer printed circuit board based on 4th Embodiment in this invention. The perspective view which represented typically the 1st coil and 2nd coil based on the embodiment. The schematic perspective view of a 1st layer surface, the schematic perspective view of a 2nd layer surface, and the schematic perspective view of a 3rd layer surface based on the embodiment.

Explanation of symbols

  1A, 1B, 1C ... printed circuit board, a ... first layer surface (main surface), d ... fourth layer surface (back surface), b ... second layer surface (inner layer surface), c ... third layer surface (inner layer surface), P ... Multilayer printed circuit board, 1 ... outer upper wiring pattern, 3 ... outer conduction hole (through hole), 4 ... inner upper wiring pattern, 5 ... inner conduction hole (through hole), 6 ... inner lower wiring pattern, 8 ... outer lower wiring Pattern: 10A: outer coil, 10B: inner coil, R: communication path, K: coil, 11: upper wiring pattern, 12a, 12b: terminal pattern, 13: conduction hole (through hole), 14: lower wiring pattern, Ka ... Coil, D ... Semiconductor element (electronic component), 22 ... Outer upper wiring pattern, 24 ... Outer conduction hole (through hole), 25 ... Inner upper wiring pattern, 27 ... Inner conduction hole (through hole), 28 ... Lower inside Wiring pattern, 29 Outer lower wiring pattern, 30A ... outer coil, 30B ... inner coil, 31 ... first upper wiring pattern, 33 ... first conduction hole, 34 ... first lower wiring pattern, 35 ... second upper wiring pattern, 36 ... second Conduction hole (through hole), 37 ... second lower wiring pattern, 40A ... first coil, 40B ... second coil.

Claims (13)

A multilayer printed circuit board having a plurality of layer surfaces that allow a plurality of printed circuit boards to be superimposed, a main surface, a back surface opposite to the main surface, and a mating surface between the printed circuit boards to be capable of forming a wiring pattern,
A plurality of parallel wiring patterns formed on the main surface, a plurality of parallel wiring patterns formed on the back surface, and outer conductive holes provided at both ends of the wiring patterns from the main surface to the back surface. Configure the outer coil by communicating,
A plurality of parallel wiring patterns formed on the inner layer surface between the main surface and the back surface, a plurality of parallel wiring patterns formed on an inner layer surface different from the inner layer surface, and both ends of these wiring patterns Configure the inner coil by communicating with the inner conduction hole,
A laminated printed board characterized in that one end of the outer coil and one end of the inner coil communicate with each other to form one coil structure.   The multilayer printed circuit board according to claim 1, wherein the inner conduction hole is formed across the inner layer surfaces of each other.   The multilayer printed circuit board according to claim 1, wherein the inner conduction hole is formed so as to penetrate from the main surface to the back surface.   The inner coil has an inner layer surface of the multilayer printed circuit board within a projected area range in which an occupation area of the outer coil formed over the outer layer surface of the main surface and the rear surface is projected in the thickness direction of the printed circuit board. The multilayer printed circuit board according to any one of claims 1 to 3, wherein the multilayer printed circuit board is formed.   5. The two-phase wound coil structure according to claim 1, wherein the outer coil formed over the outer layer surface of the multilayer printed circuit board and the inner coil formed on the inner layer surface communicate with each other to form a two-phase coil structure. A laminated printed board according to any one of the above. A multilayer printed circuit board having a plurality of layer surfaces that allow a plurality of printed circuit boards to be superimposed, a main surface, a back surface opposite to the main surface, and a mating surface between the printed circuit boards to be capable of forming a wiring pattern,
A plurality of parallel wiring patterns formed on an inner layer surface between the main surface and the back surface, a plurality of parallel wiring patterns formed on an inner layer surface different from the inner layer surface, and both ends of these wiring patterns One coil structure is formed by communicating with each other through a conduction hole provided between the inner layer surfaces of each other,
The multilayer printed circuit board, wherein the main surface and the back surface are a space for mounting electronic components and a space for forming other wiring patterns.   Forming a terminal pattern of the coil on the main surface or the back surface of the multilayer printed circuit board through conduction holes at both ends of a plurality of parallel wiring patterns of the coil formed on the inner layer surface of the printed circuit board; The multilayer printed circuit board according to claim 6, wherein: A multilayer printed circuit board having a plurality of layer surfaces that allow a plurality of printed circuit boards to be superimposed, a main surface, a back surface opposite to the main surface, and a mating surface between the printed circuit boards to be capable of forming a wiring pattern,
A plurality of parallel wiring patterns formed on the main surface, a plurality of parallel wiring patterns formed on the back surface, and outer conductive holes provided at both ends of the wiring patterns from the main surface to the back surface. Configure the outer coil by communicating,
A plurality of parallel wiring patterns formed on the inner layer surface between the main surface and the back surface, a plurality of parallel wiring patterns formed on an inner layer surface different from the inner layer surface, and both ends of these wiring patterns A multilayer printed circuit board comprising an inner coil by communicating with inner conduction holes provided between inner layer surfaces of each other, wherein the outer coil and the inner coil are independent of each other.   The inner coil has an area occupied by the outer coil formed over the outer layer surface of the main surface and the back surface, and the printed circuit board is electrically and independently within a projected area range projected in the thickness direction of the printed circuit board. The multilayer printed circuit board according to claim 8, wherein the multilayer printed circuit board is formed on an inner layer surface of the substrate.   The outer coil and the inner coil formed independently of each other on the printed circuit board are configured such that one of them is a primary winding and the other is assigned to a secondary winding to constitute a transformer. Item 10. The multilayer printed circuit board according to any one of items 8 and 9. A multilayer printed circuit board having a plurality of layer surfaces that allow a plurality of printed circuit boards to be superimposed, a main surface, a back surface opposite to the main surface, and a mating surface between the printed circuit boards to be capable of forming a wiring pattern,
A plurality of parallel wiring patterns formed on the main surface, a plurality of parallel wiring patterns formed on an inner layer surface between the main surface and the back surface, and both ends of the wiring patterns from the main surface The first coil is configured by communicating with the first conduction hole provided over the layer surface,
A plurality of parallel wiring patterns formed on an inner layer surface different from the inner layer surface, a plurality of parallel wiring patterns formed on the back surface, and both ends of these wiring patterns are provided from the inner layer surface to the back surface. A laminated printed board characterized in that a second coil is formed by communicating with a second conduction hole formed, and a plurality of independent coils are formed.   The first coil and the second coil are laminated within a projected area range in which one of the occupied areas is projected in the thickness direction of the printed circuit board, and are formed electrically independent of each other. The multilayer printed circuit board according to claim 11.   The multilayer printed circuit board according to claim 11, wherein the first coil and the second coil have equal inductance or different inductance characteristics.

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