JP2009283762A - Method for manufacturing nitride compound semiconductor led - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing more uniformly forming ruggedness on a light take-out surface and stably mass-producing a nitride compound semiconductor LED which improves light take-out efficiency. <P>SOLUTION: The method for manufacturing a nitride compound semiconductor LED includes the steps of: forming a nitride semiconductor laminate containing Ga by crystal-growing at least a first conductive type semiconductor layer 4, a light emitting layer 5 and a second conductive type semiconductor layers 6, 7 on an epitaxial substrate 1 in this order; forming a reflection electrode layer on a surface of the nitride semiconductor laminate at a side of the second conductive type semiconductor layer; releasing the epitaxial substrate; producing ruggedness on the nitride semiconductor laminate by etching the surface of the nitride semiconductor laminate from which the epitaxial substrate is released; and performing O<SB>2</SB>plasma treatment or O<SB>3</SB>ashing treatment on the nitride semiconductor laminate to which dry etching is applied. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nitride-based compound semiconductor LED having a step of manufacturing by peeling an epitaxial substrate.

  A nitride-based compound semiconductor LED produced by laminating an epitaxial substrate with a laser beam by laminating a conductive support can produce an electrode structure in the vertical direction. The area can be reduced, (ii) excellent mass productivity, and (iii) a heat-dissipating support can be produced, which is expected as an effective production method for producing a large current type LED.

  The nitride-based compound semiconductor LED manufactured by this manufacturing method can improve the light output by making the light extraction surface an uneven structure, suppressing total reflection of light at the interface between the light extraction surface and air. it can. Therefore, as a method for providing the light extraction surface with a concavo-convex structure, for example, Patent Document 1 discloses a method of performing dry etching on a crystal surface of a light extraction surface using a reactive ion etching apparatus (hereinafter referred to as “RIE apparatus”). Is listed. Below, the manufacturing method of the nitride type compound semiconductor LED of a prior art example is demonstrated roughly, referring FIGS.

  First, as shown in FIG. 22, on a sapphire substrate 101, a GaN buffer layer 102 having a thickness of 250 nm, an undoped GaN layer 103 having a thickness of 1 μm, an n-type GaN layer 104 having a thickness of 4 μm, and a barrier made of GaN. A 100 nm thick light-emitting layer 105 including an InGaN well layer and an InGaN well layer, a 30 nm thick p-type AlGaN layer 106, and a 200 nm thick p-type GaN layer 107 are formed by metal organic chemical vapor deposition (MOCVD method). The Pd layer 108 having a thickness of 15 mm is vapor-deposited on the stacked body, and the Ag—Nd layer 109 having a thickness of 300 nm and the Ni—Ti layer having a thickness of 3.3 nm are formed thereon. 110 is formed by sputtering, and then heat treatment is performed in a vacuum at 500 ° C. to alloy the Pd layer 108 and the p-type GaN layer 107.

Next, as shown in FIG. 23, a part of the Ag—Nd layer 109 and a part of the Ni—Ti layer 110 are removed by wet etching in a pattern of 260 μmφ by photolithography, and then a SiO ₂ film having a thickness of 0.3 μm. The film 111 is deposited by plasma CVD. Then, a mask is prepared by photolithography to form a 90 μmφ opening in a portion of the SiO ₂ film 111 located on the Ni—Ti layer 110, and wet etching is performed until the Ni—Ti layer 110 is exposed. A part of the _two films 111 is removed, and a Ti layer 112 with a thickness of 100 nm, a Pt layer 113 with a thickness of 120 nm, and an Au layer 114 with a thickness of 3 μm are deposited.

Next, as shown in FIG. 24, on the Si substrate 115, a Ti layer 116 having a thickness of 100 nm, a Pt layer 117 having a thickness of 120 nm, an Au layer 118 having a thickness of 500 nm, and an Au—Sn layer having a thickness of 3 μm. 119 are deposited in this order. Next, the eutectic bonding method is used to bond the Au layer 114 of the wafer on which the sapphire substrate 101 to the Au layer 114 are laminated and the Au—Sn layer 119 of the wafer on which the Si substrate 115 to the Au—Sn layer 119 are laminated. And bonded at a temperature of 300 ° C. and a pressure of 300 N / cm ^{2 in} a vacuum atmosphere.

  Next, YAG-THG laser light having a wavelength of 355 nm is irradiated from a surface different from the light emitting layer 105 when viewed from the sapphire substrate 101, and the GaN buffer layer 102 and the undoped GaN layer 103 in contact with the sapphire substrate 101 are thermally decomposed to produce the sapphire. The substrate 101 is removed. Then, the surface of the n-type GaN layer 104 exposed is subjected to dry etching using an RIE apparatus as shown in Patent Document 1, thereby forming irregularities on the surface of the n-type GaN layer 104. The unevenness on the surface of the n-type GaN 104 improves the light extraction efficiency of the nitride compound semiconductor LED.

Finally, as shown in FIG. 25, two layers of Ti having a thickness of 150 mm and Au having a thickness of 500 nm are formed in the center of the surface of the n-type GaN layer 104 having the unevenness using a photoresist process and a lift-off process. The layer 120 (hereinafter referred to as “Au layer”) is formed in this order. Further, a nitride-based compound semiconductor obtained by forming a layer 121 (hereinafter referred to as “Al layer”) 121 composed of three layers of Ti having a thickness of 150 mm, Al having a thickness of 150 nm, and Ti having a thickness of 150 mm on the Si substrate 115. An LED wafer is divided into 350 μm pitch chips using a diamond scribe method to obtain a nitride-based compound semiconductor LED.
JP 2003-69075 A

  However, in the manufacture of the nitride-based compound semiconductor LED of the conventional example, the surface state of the n-type GaN layer 104 exposed after the sapphire substrate 101 is peeled is unstable, so that even if dry etching is simply performed using an RIE apparatus. The distribution and shape of the irregularities on the surface of the n-type GaN layer 104 cannot be made stable, and in extreme cases, the irregularities can hardly be produced. For this reason, nitride-based compound semiconductor LEDs with high light extraction efficiency are mass-produced where the unevenness is formed on the surface, while the light extraction efficiency is high, while the unevenness is not formed on the surface where the unevenness is not formed. I couldn't.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method capable of uniformly forming irregularities formed on a light extraction surface and stably mass-producing a nitride compound semiconductor LED having high light extraction efficiency.

The present invention includes a step of forming a nitride semiconductor laminate containing Ga by crystal growth of at least a first conductive semiconductor layer, a light emitting layer, and a second conductive semiconductor layer in this order on an epitaxial substrate; Forming a reflective electrode layer on the surface of the nitride semiconductor multilayer body on the second conductivity type semiconductor layer side, exfoliating the epitaxial substrate, and exfoliating the epitaxial substrate of the nitride semiconductor multilayer body And a step of producing a concavo-convex shape in the nitride semiconductor laminate by dry etching a surface, and a step of performing O ₂ plasma treatment or O ₃ ashing treatment on the dry-etched nitride semiconductor laminate. This is a method for manufacturing a nitride-based compound semiconductor LED.

  Therefore, the step of peeling off the epitaxial substrate is preferably performed by irradiating a laser beam from the epitaxial substrate side as viewed from the first conductivity type semiconductor layer and thermally decomposing a part of the nitride semiconductor multilayer body.

  Further, it is preferable to remove Ga from the nitride semiconductor multilayer body by a wet etching method before the step of dry etching the nitride semiconductor multilayer body, and an etching solution used for the wet etching method is a hydrochloric acid type. It is preferable.

The dry etching preferably uses Cl ₂ and SiCl ₄ material gases, and preferably includes a step of O ₂ plasma treatment or O ₃ ashing treatment between the dry etchings. The flow rate of Cl ₂ is preferably larger than the flow rate of SiCl ₄ .

Further, it is preferable that the surface of the nitride semiconductor multilayer body is not exposed to the air between the dry etching step and the O ₂ plasma treatment or O ₃ ashing step. According to the said manufacturing method, the uneven | corrugated shape on a 1st conductivity type semiconductor layer does not form a flat part, but can produce nitride compound semiconductor LED with favorable light output stably.

  According to the present invention, the unevenness on the light extraction surface can be formed more uniformly, and a nitride-based compound semiconductor LED with high light extraction efficiency can be stably mass-produced.

  Hereinafter, preferred embodiments 1 and 2 of the present invention will be described. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts, and the present invention is not limited to the following first and second embodiments.

(Embodiment 1)
In Embodiment 1, nitride system compound semiconductor LED is manufactured by setting it as process 1-13 mentioned below. Hereinafter, steps 1 to 13 that are the features of the first embodiment will be described with reference to FIGS.

(Process 1)
First, as shown in FIG. 1, a buffer layer 2, an undoped layer 3, a first conductivity type semiconductor layer 4, a light emitting layer 5, and second conductivity type semiconductor layers 6 and 7 are formed on an epitaxial substrate 1. Are grown in this order by using a metal organic chemical vapor deposition method (MOCVD method). Thereby, an example of the nitride semiconductor laminated body containing Ga can be formed on the epitaxial substrate 1.

  Here, as a material used for the epitaxial substrate 1, conventionally known materials can be employed, and examples thereof include sapphire, spinel, lithium niobate, and neodymium gallate.

  As a material used for the buffer layer 2 and the undoped layer 3, for example, a GaN material can be used. The thickness of the buffer layer 2 is not specifically limited, The thickness normally used in the said field | area can be employ | adopted, for example, can be about 10-500 nm. Moreover, the thickness of the undoped layer 3 is not specifically limited, The thickness normally used in the said field | area can be employ | adopted, For example, it can be set as about 0.1-50 micrometers.

  The material used for the first conductivity type semiconductor layer 4 can be n-type GaN. The thickness of the 1st conductivity type semiconductor layer 4 is not specifically limited, For example, it can be set as 2-10 micrometers.

The light-emitting layer 5, can be used as the structure including the well layer comprising a barrier layer made of GaN and _{In q Ga 1-q N (} 0 <q <1). The thicknesses of the barrier layer and the well layer are not particularly limited, and can be 3 to 30 nm and 0.5 to 5 nm, for example.

  The second conductive semiconductor layers 6 and 7 are composed of two layers, a p-type AlGaN layer and a p-type GaN layer. The thicknesses of the p-type AlGaN layer and the p-type GaN layer are not particularly limited, and can be, for example, 10 to 100 nm and 50 to 1000 nm, respectively.

(Process 2)
Next, as shown in FIG. 2, a p-type ohmic electrode 8, a reflective electrode layer 9, and a cover layer 10 are formed in this order on the surfaces of the second conductive semiconductor layers 6 and 7, and then heat-treated. The p-type ohmic electrode 8 and the p-type GaN layer of the second conductivity type semiconductor layer 7 are alloyed.

  Here, as a material used for the p-type ohmic electrode 8, a conventionally well-known thing can be employ | adopted, for example, Pd etc. can be mentioned. Moreover, the thickness of the p-type ohmic electrode 8 is not specifically limited, The thickness normally used in the said field | area can be employ | adopted, for example, can be about 1-1000 mm. The p-type ohmic electrode 8 is preferably formed by vapor deposition.

  As the reflective electrode layer 9, a conventionally known one can be adopted, and for example, Ag—Nd can be mentioned. Further, the thickness of the reflective electrode layer 9 is not particularly limited, and a thickness usually used in the field can be adopted, and for example, can be about 1 to 1000 nm.

  Examples of the cover layer 10 include Ni—Ti. Moreover, the thickness of the cover layer 10 is not specifically limited, The thickness normally used in the said field | area can be employ | adopted, for example, can be about 0.1-100 nm. The reflective electrode layer 9 and the cover layer 10 can be formed by sputtering, for example.

  The above heat treatment is not particularly limited as long as the p-type ohmic electrode 8 and the p-type GaN layer of the second conductivity type semiconductor layer 7 can be alloyed. It is possible to process in vacuum.

(Process 3)
Next, as shown in FIG. 3, a part of the reflective electrode layer 9 and the cover layer 10 is removed, and a part of the p-type ohmic electrode 8 is exposed. Thereby, a pattern composed of the p-type ohmic electrode 8 and the cover layer 10 is produced on the surface opposite to the epitaxial substrate 1 when viewed from the p-type ohmic electrode 8.

  Here, as a method of removing the reflective electrode layer 9 and the cover layer 10, for example, a method using photolithography and etching can be used. When a method using photolithography and etching is used, the pattern of the p-type ohmic electrode 8 and the cover layer 10 can be about 1 to 500 μmφ. For example, when the portion not covered with the resist is wet etched, The electrode layer 9 and the cover layer 10 can be removed.

(Process 4)
Next, as shown in FIG. 4, the exposed surface of the p-type ohmic electrode 8, the exposed surface of the cover layer 10, and the side surface of the laminate of the reflective electrode layer 9 and the cover layer 10. An insulating protective film 11 is deposited on the substrate. The material used for the insulating protective film 11 may be any material as long as it has insulating properties. For example, SiO ₂ , SiN, Si ₃ N ₄ , HfO ₂ , TiO ₂ , Al ₂ O ₃ , HfLaO , HfAlO, LaAlO, and the like. Of these, SiO ₂ and SiN are preferably used because of good controllability of film formation. The insulating protective film 11 is not limited to a single layer, and may have a multilayer structure.

  The thickness of the insulating protective film 11 is not specifically limited, The thickness normally used in the said field | area can be employ | adopted, for example, it can also be set as about 0.1-30 micrometers. As a method for forming the insulating protective film 11, for example, a plasma CVD method can be used.

(Process 5)
Next, as shown in FIG. 5, after removing a part of the insulating protective film 11 and exposing a part of the surface of the cover layer 10, the adhesion layer 12 is formed on the insulating protective film 11 and the exposed cover layer 10. Then, the diffusion preventing layer 13 and the first bonding metal layer 14 are formed. Note that the adhesion layer 12 and the diffusion prevention layer 13 are not necessarily required, and the first bonding metal layer 14 may be a layer having these functions.

  Here, as a method of removing a part of the insulating protective film 11, for example, a method using photolithography and etching can be used. That is, a mask is formed on the surface of the insulating protective film 11, and the insulating protective film 11 is wet etched until the cover layer 10 is exposed. In the case of producing a pattern by this photolithography, the opening of the insulating protective film 11 can be, for example, about 10 to 300 μmφ.

  As the metal or alloy constituting the adhesion layer 12 and the diffusion prevention layer 13, conventionally known ones can be employed, for example, NiTi, Ti, Ni, W, TiW, Pt, Mo, Nb, Ta, etc. Can be mentioned. The thickness of the adhesion layer 12 and the diffusion prevention layer 13 is not particularly limited, and a thickness usually used in this field can be adopted, and can be, for example, about 1 to 1000 nm. As a method for forming the adhesion layer 12 and the diffusion prevention layer 13, for example, vapor deposition can be used.

  As the metal or alloy used for the first bonding metal layer 14, a conventionally known metal can be used, and examples thereof include Au, AuSn, AuGe, AuSi, an alloy of Ag, Pd, and Cu. be able to. The thickness of the first bonding metal layer 14 is not particularly limited, and a thickness usually used in the field can be adopted, and for example, can be about 0.1 to 30 μm. . As a method of forming the first bonding metal layer 14, for example, vapor deposition can be used.

(Step 6)
Next, as shown in FIG. 6, a first ohmic layer 16, a diffusion prevention layer 17, a bonding layer 18, and a second bonding metal layer 19 are formed in this order on the conductive substrate 15.

  Here, as a material used for the conductive substrate 15, a conventionally known material can be employed, and examples thereof include Si. Moreover, as a material used for the 1st ohmic layer 16, a conventionally well-known thing can be employ | adopted, for example, Ti etc. can be mentioned. The thickness of the first ohmic layer 16 is not particularly limited, and a thickness usually used in the field can be employed, and can be, for example, about 1 to 1000 nm.

  Further, as the diffusion preventing layer 17, a conventionally known one can be employed, and examples thereof include Pt. Further, the thickness of the diffusion preventing layer 17 is not particularly limited, and a thickness usually used in the field can be adopted, and for example, can be about 1 to 1000 nm.

  As the bonding layer 18, a conventionally known one can be employed, and examples thereof include Au. Moreover, the thickness of the joining layer 18 is not specifically limited, The thickness normally used in the said field | area can be employ | adopted, for example, can be about 10-3000 nm.

  Also, as the second bonding metal layer 19, a conventionally known one can be employed, and examples thereof include AuSn. Further, the thickness of the second bonding metal layer 19 is not particularly limited, and a thickness usually used in the field can be adopted, for example, about 0.1 to 100 μm. it can.

(Step 7)
Next, as shown in FIG. 7, the first adhesive metal layer 14 of the wafer in which the layers from the epitaxial substrate 1 produced in Steps 1 to 5 to the first adhesive metal layer 14 are laminated and the conductive produced in Step 6 are used. The second adhesive metal layer 19 of the wafer laminated with the conductive substrate 15 to the second adhesive metal layer 19 is bonded together.

Here, as a method of bonding the wafers, for example, a eutectic bonding method can be used. When the eutectic bonding method is used, the temperature is preferably 100 to 500 ° C. and the pressure is preferably 10 to 1000 N / cm ² , and is preferably performed in a vacuum atmosphere.

(Process 8)
Next, as shown in FIG. 8, a laser layer is irradiated from a surface different from the light emitting layer 5 when viewed from the epitaxial substrate 1, and a buffer layer 2 (not shown) in contact with the epitaxial substrate 1 (not shown). The epitaxial substrate 1 is removed by thermally decomposing a part of the undoped layer 3.

Here, for example, a YAG-THG laser beam is preferable as the laser beam used for peeling off the epitaxial substrate 1, and the wavelength of the laser beam is preferably 355 nm.
In addition, it is considered that Ga droplets are generated on the surface of the undoped layer 3 after thermally decomposing a part of the undoped layer 3 with laser light, and this Ga droplet is obstructed from being etched uniformly in Step 10. it seems to do. In addition, it is thought that Ga droplet contains Ga.

(Step 9)
Therefore, as shown in FIG. 9, wet etching is performed to remove the Ga droplets, and the surface of the undoped layer 3 is cleaned.

  Here, the etching solution used for wet etching is preferably a hydrochloric acid-based solution, and more preferably an aqueous solution of hydrochloric acid. In the case of an aqueous hydrochloric acid solution, for example, a 35% aqueous hydrochloric acid solution can be used. It is considered that Ga on the surface of the undoped layer 3 is removed or washed by this wet etching so that it can be uniformly etched in the next step 10.

(Process 10)
Next, as shown in FIG. 10, an active Ga layer having a certain regularity on the surface of the undoped layer 3 is produced by etching the surface of the undoped layer 3. In FIG. 10, the case where the surface of the undoped layer 3 is etched is described. However, in the present invention, the surface of the first conductivity type semiconductor layer 4 may be etched together with the undoped layer 3. When is not formed, only the surface of the first conductivity type semiconductor layer 4 may be etched.

Here, the etching of the surface of the undoped layer 3 and / or the first conductivity type semiconductor layer 4 is preferably dry etching, and more preferably dry etching using an RIE apparatus. In the case of dry etching using an RIE apparatus, dry etching is preferably performed using a material gas such as Cl ₂ or SiCl ₄ . When using the above material gas, it is preferable flow rate of Cl ₂ is greater than the flow rate of SiCl _4, further the ratio of the flow rate of Cl ₂ flow rate and the SiCl ₄ is 2: is preferably about 1.

  The regularity that can be formed on the surface of the undoped layer 3 and / or the first conductive type semiconductor layer 4 by the above-described etching may be, for example, an uneven shape. The depth is preferably about 5000 nm and the depth is about 0.01 to 1 μm.

(Step 11)
Next, as shown in FIG. 11, a Ga oxide film 24 is formed on the surface of the undoped layer 3 by oxidizing the active Ga layer.

Examples of the method for oxidizing the active Ga layer include a method of performing O ₂ plasma treatment and a method of performing O ₃ ashing treatment. Here, examples of the O ₂ plasma treatment include a treatment in which the active Ga layer is oxidized to the Ga oxide film 24 by exciting O _{2 in} a vacuum to bring it into a plasma state and bringing it into contact with the active Ga layer. Can do. Further, as the O ₃ ashing process, for example, a process of oxidizing the active Ga layer to the Ga oxide film 24 by bringing high concentration ozone into contact with the active Ga layer can be exemplified. Here, the material gas used for the O ₂ plasma treatment only needs to contain O ₂ , and not all of it is necessarily O ₂ . Here, the material gas used for the O ₃ ashing process only needs to contain O ₃ and does not necessarily have to be all O ₃ .

(Step 12)
Next, as shown in FIG. 12, the active Ga layer is oxidized and then etched again, whereby irregularities are formed on the first conductivity type semiconductor layer 4 with good reproducibility.

  The etching in this step 12 is preferably performed until the undoped layer 3 (not shown) is removed, and the etching is preferably performed under the same conditions and method as the etching used in step 10. Further, it is preferable that the surface of the undoped layer 3 (not shown), the active Ga layer, and the Ga oxide film 24 is not exposed to the atmosphere from the start of etching in the step 10 until the etching in the step 12 is completed.

(Step 13)
Next, as shown in FIG. 13, an n-type ohmic electrode 20 is formed in the center of the first conductive semiconductor layer 4 on the uneven side, and the first ohmic layer 16 of the conductive substrate 15 is An ohmic electrode 21 is formed on the opposite surface.

  Here, a conventionally well-known thing can be employ | adopted as the n-type ohmic electrode 20, For example, Ti, Au etc. can be mentioned. The n-type ohmic electrode 20 can have either a single-layer structure or a multilayer structure of metal. The thickness of the n-type ohmic electrode 20 is not specifically limited, The thickness normally used in the said field | area can be employ | adopted, for example, can be about 1-1000 nm. In the case of a multilayer structure, the thickness of each layer may be smaller than 1 nm. The n-type ohmic electrode 20 can be provided by using a photoresist process and a lift-off process, but is not limited to these methods. The n-type ohmic electrode 20 is desirably provided in the center of the first conductivity type semiconductor layer 4.

  Furthermore, as the ohmic electrode 21, a conventionally known one can be adopted, and examples thereof include Ti and Al. The ohmic electrode 21 can have either a metal single layer structure or a multilayer structure. The thickness of the ohmic electrode 21 is not particularly limited, and a thickness usually used in the field can be adopted. For example, the thickness can be about 1 to 1000 nm. The thickness of each layer may be smaller than 1 nm.

  Finally, the nitride compound semiconductor LED wafer obtained in the above step 13 is divided into chips of, for example, 350 μm pitch using, for example, a diamond scribe method, a laser scribe method, or a dicing method. A physical compound semiconductor LED is obtained.

(Embodiment 2)
In the second embodiment, a nitride compound semiconductor LED is manufactured by replacing the steps 5 to 13 of the first embodiment with steps 14 to 21 described later. A specific feature of the second embodiment is that the conductive substrate 15 of the first embodiment is changed to a plating support layer 23. Therefore, hereinafter, steps 14 to 21 which are features of the second embodiment will be described with reference to FIGS. Since steps 1 to 4 are the same as those in the first embodiment, description thereof is omitted here.

(Step 14)
After step 4 of the first embodiment, as shown in FIG. 14, after removing a part of the insulating protective film 11 and exposing the cover layer 10, the insulating protective film 11 and the exposed cover layer 10 are exposed. Then, the adhesion layer 12, the diffusion preventing layer 13, and the plating seed layer 22 are formed. The method for removing a part of the insulating protective film 11 and the method for forming the adhesion layer 12 and the diffusion prevention layer 13 are the same as those in the step 5 of the first embodiment, but after that, the first bonding metal The difference from the first embodiment is that a plating seed layer 22 is provided instead of the layer 14.

  Here, as a metal or an alloy used for the plating seed layer 22, a conventionally known metal can be employed, for example, Au. The thickness of the plating seed layer 22 is not particularly limited, and a thickness usually used in the field can be adopted, and can be, for example, about 10 to 5000 nm.

  As a method of forming the adhesion layer 12, the diffusion prevention layer 13, and the plating seed layer 22 on the insulating protective film 11 and the exposed cover layer 10, for example, vapor deposition can be used.

(Step 15)
Next, as shown in FIG. 15, a plating support layer 23 is formed on the surface opposite to the diffusion prevention layer 13 when viewed from the plating seed layer 22. Here, a conventionally well-known thing can be employ | adopted as a metal used for the plating support layer 23, For example, Cu can be mentioned.

(Step 16)
Next, as shown in FIG. 16, laser light is irradiated from a surface different from the light emitting layer 5 when viewed from the epitaxial substrate 1, and a part of the buffer layer 2 and the undoped layer 3 in contact with the epitaxial substrate 1 are thermally decomposed. Thus, the epitaxial substrate 1 is removed.

(Step 17)
Next, as shown in FIG. 17, wet etching is performed to remove the Ga droplets, and the surface of the undoped layer 3 is cleaned.

(Step 18)
Next, as shown in FIG. 18, the surface of the undoped layer 3 is etched to produce an active Ga layer having a certain regularity on the surface of the undoped layer 3. In FIG. 18, the case where the surface of the undoped layer 3 is etched is described. However, in the present invention, the surface of the first conductivity type semiconductor layer 4 may be etched together with the undoped layer 3. When is not formed, only the surface of the first conductivity type semiconductor layer 4 may be etched.

(Step 19)
Next, as shown in FIG. 19, a Ga oxide film 24 is formed on the surface of the undoped layer 3 by oxidizing the active Ga layer.

(Step 20)
Next, as shown in FIG. 20, the active Ga layer is oxidized and then etched again, thereby forming irregularities on the first conductivity type semiconductor layer 4 with good reproducibility. Here, in step 20, for example, by etching the surface of the Ga oxide film 24 and the undoped layer 3 and / or the first conductivity type semiconductor layer 4 in the same manner as in step 12, the Ga oxide film 24 and the undoped layer are etched. 3 can be removed.

(Step 21)
Next, as shown in FIG. 21, an n-type ohmic electrode 20 is formed at the center of the first conductive semiconductor layer 4 on the uneven side, and the first ohmic layer 16 of the conductive substrate 15 is An ohmic electrode 21 is formed on the opposite surface.
Thereafter, the chip is divided into chips by the same method as in the first embodiment, and the nitride-based compound semiconductor LED in the second embodiment is obtained.

  Since the nitride-based compound semiconductor LED manufactured as described above can be manufactured with high reproducibility of the unevenness of the light extraction surface, the nitride-based compound semiconductor LED with higher light output can be stably mass-produced.

  In the first and second embodiments, the epitaxial substrate 1 is peeled off on the conductive substrate 15 and the plating layer. However, the epitaxial substrate 1 is peeled off after being mounted directly on the circuit board without forming the support substrate. However, the same effect can be obtained. Therefore, the present invention is not limited to the case where the epitaxial substrate 1 is peeled after the support base is formed, and includes a step of peeling the epitaxial substrate 1 after being mounted directly on the circuit board.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the present invention, the surface unevenness of the light extraction surface can be produced with good reproducibility, and a nitride compound semiconductor LED having a high light output can be stably mass-produced.

6 is a schematic cross-sectional view showing a manufacturing process 1 of the nitride-based compound semiconductor LED of Embodiment 1. FIG. FIG. 6 is a schematic cross-sectional view showing a manufacturing process 2 of the nitride-based compound semiconductor LED according to the first embodiment. 6 is a schematic cross-sectional view showing a manufacturing process 3 of the nitride-based compound semiconductor LED of Embodiment 1. FIG. FIG. 6 is a schematic cross-sectional view showing a manufacturing process 4 of the nitride-based compound semiconductor LED according to the first embodiment. 6 is a schematic cross-sectional view showing a manufacturing process 5 of the nitride-based compound semiconductor LED of Embodiment 1. FIG. FIG. 6 is a schematic cross-sectional view showing a manufacturing process 6 of the nitride-based compound semiconductor LED of the first embodiment. FIG. 6 is a schematic cross-sectional view showing a manufacturing process 7 for the nitride-based compound semiconductor LED of the first embodiment. It is typical sectional drawing which shows the manufacturing process 8 of the nitride type compound semiconductor LED of this Embodiment 1. FIG. It is typical sectional drawing which shows the manufacturing process 9 of the nitride type compound semiconductor LED of this Embodiment 1. FIG. It is typical sectional drawing which shows the manufacturing process 10 of the nitride type compound semiconductor LED of this Embodiment 1. FIG. It is typical sectional drawing which shows the manufacturing process 11 of the nitride type compound semiconductor LED of this Embodiment 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing step 12 of the nitride-based compound semiconductor LED of the first embodiment. FIG. FIG. 5 is a schematic cross-sectional view showing a manufacturing step 13 for the nitride-based compound semiconductor LED of the first embodiment. It is typical sectional drawing which shows the manufacturing process 14 of the nitride type compound semiconductor LED of this Embodiment 2. FIG. It is typical sectional drawing which shows the manufacturing process 15 of the nitride type compound semiconductor LED of this Embodiment 2. FIG. It is typical sectional drawing which shows the manufacturing process 16 of the nitride type compound semiconductor LED of this Embodiment 2. FIG. It is typical sectional drawing which shows the manufacturing process 17 of the nitride type compound semiconductor LED of this Embodiment 2. FIG. It is typical sectional drawing which shows the manufacturing process 18 of the nitride type compound semiconductor LED of this Embodiment 2. FIG. It is typical sectional drawing which shows the manufacturing process 19 of the nitride type compound semiconductor LED of this Embodiment 2. FIG. It is typical sectional drawing which shows the manufacturing process 20 of the nitride type compound semiconductor LED of this Embodiment 2. FIG. It is typical sectional drawing which shows the manufacturing process 21 of the nitride type compound semiconductor LED of this Embodiment 2. FIG. It is typical sectional drawing which shows the manufacturing process of the conventional nitride type compound semiconductor LED. It is typical sectional drawing which shows the manufacturing process of the conventional nitride type compound semiconductor LED. It is typical sectional drawing which shows the manufacturing process of the conventional nitride type compound semiconductor LED. It is typical sectional drawing which shows the manufacturing process of the conventional nitride type compound semiconductor LED.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Epitaxial substrate, 2 Buffer layer, 3 Undoped layer, 4 1st conductivity type semiconductor layer, 5,105 Light emitting layer, 6,7 2nd conductivity type semiconductor layer, 8 p-type ohmic electrode, 9 Reflective electrode layer, 10 Cover 11, protective layer, 12 adhesion layer, 13 diffusion prevention layer, 14 first adhesion metal layer, 15 conductive substrate, 16 first ohmic layer, 17 diffusion prevention layer, 18 bonding layer, 19 second layer Adhesive metal layer, 20 n-type ohmic electrode, 21 ohmic electrode, 22 plating seed layer, 23 plating support layer, 24 Ga oxide film, 101 sapphire substrate, 102 GaN buffer layer, 103 undoped GaN layer, 104 n-type GaN layer 106 p-type AlGaN layer, 107 p-type GaN layer, 108 Pd layer, 109 Ag-Nd layer, 110 Ni-Ti layer, 111 SiO ₂ film, 112 , 116 Ti layer, 113, 117 Pt layer, 114, 118, 120 Au layer, 115 Si substrate, 119 Au—Sn layer, 121 Al layer.

Claims (9)

Forming a nitride semiconductor laminate containing Ga by crystal growth of at least a first conductive semiconductor layer, a light emitting layer, and a second conductive semiconductor layer in this order on an epitaxial substrate;
Forming a reflective electrode layer on the surface of the nitride semiconductor multilayer body on the second conductivity type semiconductor layer side;
Peeling the epitaxial substrate;
A step of dry-etching the surface of the nitride semiconductor laminate from which the epitaxial substrate has been peeled to produce a concavo-convex shape in the nitride semiconductor laminate; and
And a step of subjecting the dry-etched nitride semiconductor laminate to O ₂ plasma treatment or O ₃ ashing treatment.   The step of peeling off the epitaxial substrate is performed by irradiating a laser beam from the epitaxial substrate side as seen from the first conductive type semiconductor layer and thermally decomposing a part of the nitride semiconductor stacked body. The method for producing a nitride-based compound semiconductor LED according to claim 1.   3. The nitride-based compound semiconductor according to claim 1, wherein Ga in the nitride semiconductor multilayer body is removed by a wet etching method before performing the dry etching of the nitride semiconductor multilayer body. LED manufacturing method.     The method of manufacturing a nitride-based compound semiconductor LED according to claim 3, wherein an etching solution used in the wet etching method is a hydrochloric acid type. 5. The method of manufacturing a nitride-based compound semiconductor LED according to claim 1, wherein the dry etching uses a material gas of Cl ₂ and SiCl ₄ . In the dry etching, a dry etching process using Cl ₂ and SiCl ₄ material gases is performed, followed by an O ₂ plasma process or an O ₃ ashing process, and again using Cl ₂ and SiCl ₄ material gases. The method for producing a nitride compound semiconductor LED according to claim 1, wherein a dry etching step is performed. The material gas in the dry etching, nitride-based compound semiconductor LED manufacturing method according to claim 1, the flow rate of the Cl ₂ being greater than the flow rate of SiCl _4. The surface of the nitride semiconductor multilayer body is not exposed to the air between the dry etching step and the O ₂ plasma treatment or the O ₃ ashing step. Manufacturing method of nitride-based compound semiconductor LED.   9. The nitride-based compound semiconductor LED manufactured by the manufacturing method according to claim 1, wherein the uneven shape on the first conductivity type semiconductor layer is not formed with a flat portion.

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