JP2009282678A - Flash memory module and storage system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a storage controller to perform control in consideration of a storage area of a flash memory. <P>SOLUTION: The storage controller manages address conversion information representing a correspondence relation between a logical address and a physical address of a storage area (e.g. physical block) in the flash memory. The storage controller uses the address conversion information to identify a physical address corresponding to a logical address designated by an I/O request from a higher-order apparatus, and transmits an I/O command having I/O destination information based on the identified physical address to a memory controller in a flash memory module. The memory controller performs I/O to a storage area in the flash memory identified from the I/O destination information included in the I/O command from the storage controller. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a flash memory module including a memory controller and a flash memory, and a storage system including the flash memory module.

  For example, there is a storage system disclosed in Patent Document 1 as a storage system including a flash memory module. According to Patent Document 1, a memory controller in a flash memory module performs wear leveling processing and reclamation processing.

US Patent Application Publication No. 2006/0288153

  The storage system includes a plurality of flash memory modules and a host controller (hereinafter referred to as “storage controller”) that manages the plurality of flash memory modules. For example, the storage controller receives an I / O request from a higher-level device (for example, a host computer or other storage system), and sends it to one or more flash memory modules among a plurality of flash memory modules according to the I / O request. to access.

  As a flash memory module, an SSD (Solid State Device) is generally known. For example, a NAND flash memory is mounted on the SSD. In the NAND flash memory, data reading and writing are performed in page units, and data erasing is performed in block units. In the NAND flash memory, it becomes unusable in units of blocks.

  Management of the flash memory is performed by a memory controller in the SSD. For this reason, the storage controller above the SSD cannot perform control in consideration of the block of the flash memory.

  The SSD is compatible with a hard disk drive (HDD) interface, but there is no interface for communication between SSDs.

  Accordingly, an object of the present invention is to enable a storage controller to perform control in consideration of a storage area of a flash memory.

  Another object of the present invention is to enable data exchange between flash memory modules.

  Other objects of the present invention will become clear from the following description.

  A storage controller manages address conversion information indicating a correspondence relationship between a logical address and a physical address of a storage area (for example, a physical block) in the flash memory. The storage controller specifies the physical address corresponding to the logical address specified by the I / O request from the higher-level device using the address conversion information, and has the I / O destination information based on the specified physical address. The / O command is transmitted to the memory controller in the flash memory module. The memory controller performs I / O with respect to the storage area in the flash memory specified from the I / O destination information included in the I / O command from the storage controller.

  In a preferred embodiment, in addition to the first switch mechanism to which both the storage controller and the plurality of flash memory modules are connected, the second switch mechanism to which the plurality of flash memory modules are connected but the storage controller is not connected. Is provided. Data transfer between the flash memory modules is performed via the second switch mechanism.

  Hereinafter, several embodiments of the present invention will be described with reference to the drawings.

  FIG. 20 shows the configuration of the storage system according to the first embodiment of the present invention.

  The storage system 2000 includes a plurality of flash memory modules 2003 and a storage controller that is above the plurality of flash memory modules.

  Each flash memory module 2003 includes, for example, a plurality of NAND flash memory chips and a flash memory control unit 301 (see, for example, FIG. 3). Accordingly, data is written to and read from the flash memory module 2003 in units of pages, and data is erased in units of blocks. In the following description, data stored in one page is referred to as “data element”, and data stored in one block including a plurality of pages is referred to as “data element group”. In addition, a block identified from an address specified by an I / O request received from a host computer 2009 as a host device of the storage system may be referred to as a “logical block”. A physical block assigned to a logical block may be referred to as an “original block”. When the first data element stored in the first physical page in the original block is updated to the second data element, the second data element is in another physical block assigned to the original block. The first physical page in the original block is referred to as the “original page”, the first data element is referred to as the “original data element”, and the other physical block is referred to as the second physical page. It may be called “update block”, the second physical page in the update block may be called “update page”, and the second data element may be called “update data element”. The latest data element corresponding to the logical page in the logical block is referred to as “valid data element”. If the original data element is not updated, the valid data element is the original data element. If the update data element corresponding to the original data element exists in the update block, the valid data element is the update data element. is there.

  A RAID group is constituted by two or more flash memory modules 2003 of the plurality of flash memory modules 2003 (RAID is an abbreviation for Redundant Array of Independent (or Inexpensive) Disks). The RAID group is sometimes called a parity group. A plurality of logical volumes are formed by logically dividing one or a plurality of storage spaces provided by one or a plurality of RAID groups. At least one of the plurality of logical volumes is provided to the host computer 2009 as a host device of the storage system 2000. The storage controller receives an I / O request (write request or read request) designating a logical volume from the host computer 2009, and is designated by the I / O request (write request) in response to the I / O request. The write target data is written to the logical volume being read, or the read target data is read from the logical volume specified by the I / O request (read request). Writing the write target data to the logical volume means that the data element that is the basis of the write target data is written to one or a plurality of pages corresponding to the logical address representing the write destination. . Also, reading the read target data from the logical volume means that the valid data element that is the basis of the read target data is read from one or more pages corresponding to the logical address representing the read source. That is.

  The storage controller includes, for example, a host adapter 2004, a cache memory 2005, and a processor 2006. The host adapter 2004, the cache memory 2005, and the processor 2006 are multiplexed (for example, duplexed). A host adapter 2004, a cache memory 2005, a processor 2006, and a plurality of flash memory modules 2003 are connected to the first switch mechanism 2001.

  The first switch mechanism 2001 includes one or a plurality of switch devices. Through the first switch mechanism 2001, the flash memory module 2003, the host adapter 2004, the cache memory 2005, and the processor 2006 communicate with each other.

  The cache memory 2005 temporarily stores write target data written to the logical volume and read target data read from the logical volume. The cache memory 2005 is accessible from multiplexed processors 2006 (that is, a plurality of processors 2006). Information relating to a plurality of flash memories in the plurality of flash memory modules 2003 (hereinafter referred to as “flash management information”) is stored in a cache area 2201, which is a partial storage area of the cache memory 2005. In the I / O request received by the host adapter 2004 from the host computer 2009, the address of the logical block (logical address range) of the logical volume is specified, so the data element corresponding to the logical address range is stored in which page. However, the flash management information includes address conversion information indicating the correspondence between the logical address range and the physical address. The processor 2006 can access a desired page or block in the flash memory using the address translation information. The address conversion information includes, for example, a first management table shown in FIG. 21 and a second management table shown in FIG. The first management table manages the correspondence between the logical address range and the rough physical address, and the second management table manages the correspondence between the rough physical address and the detailed physical address. .

  Specifically, as shown in FIG. 21, a rough physical address is associated with the first management table for each logical address range. The rough physical address includes, for example, a flash memory control unit address, a block number, an update page map, and an update block address. A logical address range is an address of a logical block. In order to identify the original block corresponding to the logical block, the number of the original block is associated with the address of the flash memory control unit that can access the original block. The block number includes an address of the flash memory chip including the original block, which can be designated by the flash memory control unit that can access the original block. The updated page map is a map (for example, a bitmap) indicating the position of the original page (that is, the updated page) in the original block. The update block address is the address of the update block assigned to the original block corresponding to the logical block identified from the logical address range. The update block address includes, for example, a flash memory control unit address and a block number.

  In the second management table, as shown in FIG. 22, write position information and original page information are recorded for each update block address. The write position information is information indicating up to which page of the update block is an update page (whether it is a page in which an update data element is written). The original page information is information for identifying the original page, and is information associated with each updated page. The original page information includes, for example, a page number corresponding to the original page, the number of the original block having the original page, and the address of the flash memory control unit that accesses the original block.

  From the above, the address conversion information configured by the first and second management tables is information indicating the location of a physical page in which valid data elements corresponding to the logical page in the logical block are stored. Can do. For example, the processor 2006 stores the original page information related to the original page corresponding to a certain logical page in the original page if it is not associated with the update block allocated to the original block including the original page. It can be seen that the data element is a valid data element corresponding to the certain logical page. On the other hand, if the original page information is associated with the update block, the processor 2006 is stored in the update page with the last address among one or more update pages associated with the original page information. It can be seen that the updated data element is a valid data element corresponding to the certain logical page. For example, when reading a valid data element corresponding to the certain logical page, the processor 2006 creates a read command for each page having I / O destination information representing an original page or an updated page storing the valid data element. Then, the read command is transmitted to the flash memory control unit (see FIG. 3) in the flash memory module 2003 having the original page or the updated page. As a result, a single page read operation described later with reference to FIG. 4 is executed by the flash memory control unit. As described above, since the I / O command transmitted from the processor 2006 to the flash memory module 2003 includes I / O destination information indicating the physical page that is the I / O destination, the logical address is stored in the flash memory module 2003. There is no need to hold information indicating the correspondence between the physical address and the physical address. For this reason, the flash memory control unit to be described later does not have to have an address conversion function of specifying a physical address from a logical address.

  Refer to FIG. 20 again. The host adapter 2004 receives an I / O request from the host computer 2009 and transfers the I / O request to the processor 2006 through the first switch mechanism 2001. In addition, when the received I / O request is a write request, the host adapter 2004 writes the write target data in the cache memory 2005. If the received I / O request is a read request, the host adapter 2004 reads the read target data stored in the cache memory 2005 from the cache memory 2005 and transmits the read read target data to the host computer 2009. To do. In addition to the host computer 2009, a management terminal 2007 is connected to the host adapter 2004 as shown. On the display screen 2008 of the management terminal 2007, for example, the status regarding a large number of flash memory chips in the plurality of flash memory modules 2003 is displayed. Information indicating the status (hereinafter referred to as “flash memory status information”) is stored in, for example, a predetermined storage resource (for example, the cache memory 2005). The processor 2006 transmits flash memory status information to the management terminal 2007 via the host adapter 2004, and the management terminal 2007 displays the status represented by the information. The displayed status includes, for example, a status specified from the first management table and / or the second management table, and which flash memory chip in which flash memory module has a defective block.

  The processor 2006 processes an I / O request from the host adapter 2004. Specifically, a physical address described later corresponding to a logical address specified from the I / O request is specified, and an I / O command having I / O destination information based on the physical address is specified as the I / O command. The data is transmitted to the flash memory control unit 301 (see, for example, FIG. 3) that can access the flash memory chip having the storage area specified from the previous information. Further, the processor 2006 creates and issues a reclamation command to be described in detail later. To create an I / O command or a reclamation command, a copy of a necessary part of the first and second management tables (see FIGS. 21 and 22) described above is used. A copy of the necessary part is stored in, for example, a local memory 2202 included in the processor 2006. The I / O destination storage area is a physical page. This is because reading and writing are performed in units of pages. Therefore, the I / O destination information included in the I / O command includes, for example, the page number of the physical page corresponding to the I / O destination area, the number of the physical block including the physical page, and the physical block. The address of the accessible flash memory control unit 301 is included. That is, the I / O command is issued for each page. On the other hand, the erasure command is issued from the processor 2006 in units of blocks. The erase command has the number of the physical block to be erased.

  The storage system 2000 includes a second switch mechanism 2002 in addition to the first switch mechanism 2001. The second switch mechanism 2002 includes one or a plurality of switch devices. A plurality of flash memory modules 2003 are connected to the second switch mechanism 2002, but the host adapter 2004, the cache memory 2005, and the processor 2006 are not connected. That is, the second switch mechanism 2002 is a dedicated switch mechanism for communication between the flash memory modules 2003. By connecting the flash memory module 2003 to the second switch mechanism 2002, the flash memory module 2003 can be expanded in a tree shape.

  FIG. 3 shows the configuration of the flash memory module 2003.

  The flash memory module 2003 is a module including a flash memory control unit 301 as a memory controller and a plurality (or one) of flash memory chips 315 that are flash memories connected to the flash memory control unit 301.

  The flash memory chip 315 is composed of a plurality of physical blocks 316. One physical block 316 includes a plurality of (for example, 64) physical pages 317.

  A plurality of flash memory chips 315 sharing a data bus 319 and a control signal line 318 are connected to the flash memory control unit 301. The data bus 319 is a bus through which data elements flow. The control signal line 318 is a line through which a control signal flows.

  In addition to the control signal line 318, the line 320 connecting the flash memory control unit 301 and each flash memory chip 315 includes a line 320 through which a chip selection signal flows and a line 321 through which a busy signal flows. The lines 320 and 321 are wired independently for each flash memory chip 315.

  The flash memory control unit 301 includes a command interpretation unit 302, a flash command generation unit 303, a first block buffer 305, a sequence / timing control unit 304, a first page buffer 306, a second page buffer 307, and a chip selection unit 308. And a busy signal monitoring unit 309. The flash memory control unit 301 is connected to the first switch mechanism 2001 (see FIG. 20) via the first data bus 312. Although not shown in FIG. 3, as shown in FIGS. 9 and 10, the flash memory control unit 301 further includes a second block buffer 903 (in FIGS. 9 and 10, the transfer source and the transfer destination). Are described as 903A and 903B). The flash memory control unit 301 is connected to the second switch mechanism 2002 (see FIG. 20) via the second data bus 904. Examples of signals that the flash memory control unit 301 receives from the processor 2006 include a command 310 and an activation signal 313. Examples of signals that the flash memory control unit 301 transmits to the processor 2006 include a status 311 and a status signal 314. The activation signal 313 is a signal for activating the flash memory control unit 301. The status signal 314 is a signal indicating the status of the flash memory control unit 301 (for example, in operation or operation end).

  The command interpretation unit 302 interprets the command 310 from the processor 2006 and transmits the interpretation result to the flash command generation unit 303. In addition, the command interpretation unit 302 transmits a status 311 to the processor 2006.

  The flash command generation unit 303 generates a command for the flash memory chip 315 (hereinafter referred to as “flash command”) based on the result of interpretation by the command interpretation unit 302. The flash command is transmitted to the target flash memory chip 315 via the control signal line 318, for example. There are three types of flash commands, for example, read, write, and erase. The read and write flash commands are issued in units of pages, and the erase flash command is issued in units of blocks. Data elements following the read and write flash commands pass through the data bus 319.

  The first block buffer 305 is a buffer used when reclaiming in the flash memory module 2003 having the buffer 305. The first block buffer 305 reads the valid data element read from the update page in the update block and the original page in the N original blocks (N is a natural number) allocated to the update block. The valid data elements that have been recorded are stored. Therefore, the storage capacity of the first block buffer 305 is required to be at least N blocks.

  The sequence / timing controller 304 controls the operation sequence of the flash memory controller 301 and the timing of each signal. The sequence / timing control unit 304 receives the activation signal 313 from the processor 2006 and activates the flash memory control unit 301 or transmits the status signal 314 to the processor 2006.

  The first page buffer 306 is a buffer used when data elements are written to the physical page 317. Specifically, the first page buffer 306 stores data elements to be written to the physical page 317. The storage capacity of the first page buffer 306 is a storage capacity for one physical page.

  The second page buffer 307 is a buffer used when a data element is read from the physical page 317. Specifically, the data element read from the physical page 317 is stored in the second page buffer 306. The storage capacity of the second page buffer 307 is also a storage capacity for one physical page.

  The chip selection unit 308 selects the flash memory chip 315 that is the transmission destination of the flash command based on the flash command.

  The busy signal monitoring unit 309 monitors the presence / absence of a busy signal from the flash memory chip 315.

  The second block buffer 903 shown in FIG. 9 is a buffer used when reclaiming between the flash memory module 2003 having the buffer 903 and another flash memory module 2003. The second block buffer 903 reads the valid data element read from the update page in the update block and the original page in the M original blocks (M is a natural number) allocated to the update block. Valid data elements are stored. Accordingly, the storage capacity of the second block buffer 903 is required to be at least M blocks. The value of M and the value of N described above may be the same or different. That is, the number of original blocks allocated to a certain update block and the number of original blocks allocated to another update block may be the same or different. The effective data element group stored in the second block buffer 903 is sent to the flash memory control in another flash memory module 2003 via the second data bus 904 and the second switch mechanism 2002 (see FIG. 20). Transferred to the unit 301. The valid data element group received from the flash memory control unit 301 in another flash memory module 2003 via the second data bus 904 and the second switch mechanism 2002 (see FIG. 20) It is written in the block buffer 903.

  FIG. 2 shows a configuration of the flash memory chip 315.

  The flash memory chip 315 includes a memory cell array 202 and an internal buffer 205 having a storage capacity for one or two physical pages. In page units, data elements are transferred between the memory cell array 202 and the internal buffer 205, and writing and reading are performed. For controlling the flash memory chip 315, a chip selection signal 206, a plurality of control signals 207 for identifying information on the data bus 319, a busy signal 208 indicating that an internal operation is in progress, and the like are used.

  The memory cell array 202 is divided into a plurality of physical blocks 316. Each physical block 316 is composed of a plurality of physical pages 317.

  For example, FIG. 1 shows a part of the memory cell array 202. FIG. 1 is a diagram showing an example in which 16896 memory cells are arranged in the horizontal direction and 16 memory cells are arranged in the vertical direction. A page, which is a unit of writing and reading, is configured by a group of memory cells that constitute one column in the horizontal direction. In one vertical column, 16 FETs (Field Effect Transistors) each having a floating gate are connected in series. When the vertical direction of the memory cell is a bit line and the horizontal direction is a word line, a page is composed of memory cells selected by one word line. In FIG. 1, 16 pages of memory cells are shown. By combining four memory cell array portions shown in FIG. 1, one physical block which is an erase unit is configured. That is, according to the example of FIG. 1, the physical block is composed of 64 physical pages. Access to the NAND flash memory is performed by giving addresses in the order of command, column address, and row address. A row address is composed of a block address and a page address. A block is specified on the upper side, and a page is specified on the lower side.

  Hereinafter, various processes performed in the present embodiment will be described.

  First, a single page read operation will be described with reference to FIG.

The processor 2006 transmits an activation signal 313 to the transmission destination flash memory control unit 301 of the read command designating the read source physical page, and transmits the read command 310 to the flash memory control unit 301. The command interpretation unit 302 receives the command 310 and specifies that the command 310 is a read command. The flash command generation unit 303 creates a read flash command corresponding to the read command 310. The read flash command includes address information including the following (4-1) to (4-3),
(4-1) The number of the physical page 401 of the read source,
(4-2) the number of the physical block containing the physical page 401,
(4-3) the number of the flash memory chip containing the physical block,
It is included. The read flash command created by the flash command generation unit 303 is transmitted to the flash memory chip specified from (4-3) above. In response to this, a data element is read from the read-source physical page 401, and the read data element is transferred to the second page buffer 307. Then, the data element is transferred from the second page buffer 307 to the processor 2006 via the first data bus 312. A status signal 314 indicating the end of reading is transmitted from the sequence / timing control unit 304 to the processor 2006.

  Next, a single page write operation will be described with reference to FIG.

  The processor 2006 transmits the activation signal 313 to the transmission destination flash memory control unit 301 of the write command designating the write destination physical page, and the write command 310 and the write target data element are transmitted to the flash memory control unit. 301.

  The data element to be written is stored in the first page buffer 306 via the first data bus 312.

The command interpreter 302 receives the command 310 and specifies that the command 310 is a write command. The flash command generation unit 303 creates a write flash command corresponding to the write command 310. The write flash command includes address information including the following (5-1) to (5-3),
(5-1) The number of the physical page 501 at the write destination,
(5-2) the number of the physical block containing the physical page 501;
(5-3) the number of the flash memory chip containing the physical block,
It is included. The write flash command created by the flash command generation unit 303 is transmitted to the flash memory chip identified from (5-3) above. Further, the write target data element stored in the first page buffer 306 is transmitted to the flash memory chip. As a result, the write target data element is written to the write-destination physical page 501. A status signal 314 indicating the end of the single page write operation is transmitted from the sequence / timing controller 304 to the processor 2006.

  With reference to FIG. 6, the process performed when the valid data element in the original block is updated will be described.

  It is assumed that valid data elements are stored in all original pages of the original block 601. Further, it is assumed that an update block (erased block) 602 in which no valid data element is stored is assigned to the original block 601. In this case, when a valid data element stored in a certain original page in the original block 601 needs to be updated to an updated data element, the updated data element is not the certain original page in the original block 601. In the update block 602, the page with the smallest page address is written among the pages in which no valid data element is written. That is, update data elements are written in ascending order of page addresses.

  Specifically, for example, when a valid data element stored in the original page 603 needs to be updated to an update data element, the processor 2006 uses the physical page 604 in the update block 602 as a write destination of the update data element. Is transmitted to the flash memory control unit 301 in the flash memory module 2003 having the update block 602. The physical page 604 is a page in which no valid data element is written in the update block 602 and has the lowest page address (the first page according to FIG. 6). The update data element is written to the physical page 604 by performing the single page write operation described with reference to FIG. 5 according to the write command.

  In this case, for example, a status signal 314 indicating completion of writing is transmitted from the flash memory control unit 301 to the processor 2006. For example, in response to receiving the status signal 314, the processor 2006 updates the update page map corresponding to the logical block to which the original block 601 is assigned in the first management table (see FIG. 21). Specifically, since the original page 603 is the third physical page in the original block 601, the bit corresponding to the third physical page is updated in the update page map.

  Further, the processor 2006 updates the write position information corresponding to the update block 602 in the second management table (see FIG. 22) to information indicating that the update data element has been written up to the first update page. .

  Further, the processor 2006 updates the original page information corresponding to the first page of the update block 602 in the second management table (see FIG. 22) to information representing the third page 603 of the original block 601.

  Hereinafter, the description of the update of the first and second management tables is omitted or simplified, but such an update is performed by the processor 2006 each time an update data element is written in the update block 602.

  If the processor 2006 refers to the updated first and second management tables, the valid data element corresponding to the third logical page in the logical block to which the original block 601 is allocated is the original data element in the original block 601. It can be known that it exists in the update page 604 in the update block 602 instead of the page 603.

  Now, when the valid data element stored in the original page 605 in the original block 601 needs to be updated to the update data element, the processor 2006 updates the update data element in the update block 602 as the write destination of the update data element. A write command designating page 606 (update page next to update page 604) is transmitted to flash memory control unit 301. As a result, the update data element is written in the update page 606. The first and second management tables are also updated by the same method as described above.

  Thereafter, when the same original page 605 needs to be updated again, the processor 2006 flashes a write command designating the update page 607 (update page next to the update page 606) as the write destination of the update data element. It transmits to the memory control unit 301. As a result, the update data element is written in the update page 607. The first and second management tables are also updated by the same method as described above. As a result, in the second management table, the original page information respectively corresponding to the second and third update pages 606 and 607 in the update block 602 becomes information representing the first original page 605 of the original block 601. ing. By referring to the second management table, the processor 2006 corresponds to the first logical page in the logical block to which the original block 601 is assigned, with the data element stored in the update page 607 on the rear side. It is possible to know that it is a valid data element.

  Hereinafter, the reclamation process will be described.

  Reclamation processing means that when valid data elements corresponding to one logical block are distributed in a plurality of physical blocks, the valid data elements distributed in the plurality of physical blocks are converted into one physical block. It is a process to consolidate. The reclamation process is executed, for example, when the processor 2006 detects that there is no empty update page in the update block assigned to the original block. The fact that there is no empty update page means that the write position information (see FIG. 22) corresponding to the update block represents the last update page of the update block.

  In this embodiment, a reclamation command that is a command dedicated to reclamation is supported. Reclamation processing is executed in accordance with a reclamation command issued from the processor 2006 to the flash memory control unit 301. Thereby, it is possible to suppress a decrease in performance for processing an I / O request from the host computer 2009.

  That is, in the reclamation process, data elements are read in units of pages and data elements are written in units of pages. For example, if one physical block is composed of 64 pages, It is considered that the processor 2006 will issue 64 read commands and 64 write commands. As a result, the processor 2006 becomes heavily loaded, and therefore the performance of processing an I / O request from the host computer 2009 may be reduced. In the present embodiment, as described above, a reclamation command that is a dedicated command for instructing reclamation processing is supported. This eliminates the need for the processor 2006 to issue a read command and a write command on a page basis for reclamation processing, thereby suppressing a decrease in performance of processing an I / O request from the host computer 2009.

  The reclamation process performed in the present embodiment can be broadly classified into two types: an intra-module reclamation process and an inter-module reclamation process.

  According to the intra-module reclamation process, valid data elements corresponding to one logical block are arranged in the first block buffer 305 in ascending order of logical page addresses in one flash memory module 2003. The sorted valid data elements are written into the erased physical block in the module 2003.

  According to the inter-module reclamation process, an effective data element corresponding to one logical block is stored in the second block buffer 903 in the transfer source flash memory module (hereinafter referred to as “transfer source module”) 2003. The logical page addresses are arranged in ascending order. The arranged valid data element groups are transferred from the transfer source module 2003 to the transfer destination flash memory module (hereinafter referred to as “transfer destination module”) 2003 via the second switch mechanism 2002 (see FIG. 20). . The received valid data element group is once written in the second block buffer 903 in the transfer destination module 2003 and then written in the erased physical block from the second block buffer 903.

  Hereinafter, various reclamation processes will be described in detail.

  <In-module reclamation process>.

  The first in-module reclamation process will be described with reference to FIG.

  In the first intra-module reclamation process, a plurality of physical blocks 611 and 612 in which valid data elements corresponding to one logical block are stored, and a physical block 613 to which valid data elements are aggregated are one Present in the flash memory chip 614. The physical block 611 is an original block assigned to one logical block, and the physical block 612 is an update block assigned to the original block. According to the example of FIG. 7, since the number of original blocks 611 assigned to one update block 612 is one, the storage capacity of the first block buffer 305 is at least one physical block. Storage capacity is required.

  As shown in FIG. 7, when the number of original blocks 611 assigned to the update block 612 is one, the processor 2006 uses the reclamation command 1300 shown in FIG. 13 based on the first and second management tables. To create. The reclamation command 1300 shown in FIG. 13 includes a read command 1301, a page list 1302, an erase command 1304, a block number 1305, a write command 1306, and a block number 1307 in order from the top.

  The page list 1302 is a parameter subsequent to the read command 1301 and includes a block number and a page number representing each reading source page. Each reading source page is a physical page corresponding to each logical page constituting one logical block and having valid data elements. As described above, which physical block has which valid data element exists in which physical block is determined by the processor 2006 in the first and second management tables (strictly, in the first memory stored in the local memory in the processor 2006). It can be specified by referring to a copy of a necessary part in the first and second management tables. In the example of FIG. 7, the block number and page number in the first row in the page list 1302 represent the third update page of the update block 612, and the block number and page number in the second row are the original block. 611 represents the second original page of 611, and the block number and page number in the third row represent the first update page of the update block 612.

  The block number 1305 is a parameter subsequent to the erase command 1304 and represents the number of the physical block 613 to be erased. A block number 1307 is a parameter subsequent to the write command 1306 and represents a physical block 613 from which the data element group is erased.

  When the flash memory control unit 301 receives the reclamation command 1300 as described above, the following processing is performed.

  That is, the command interpretation unit 302 specifies that the received command 1300 is a reclamation command. As shown in FIG. 15, the flash command generation unit 303 generates a plurality of read flash commands 1500 corresponding to a plurality of read source pages based on the page list 1302 in response to the read command 1301 in the reclamation command 1300. To do. Each generated read flash command 1500 is transmitted to the flash memory chip having the read source page specified by the command 1500. One read flash command 1500 includes, for example, two page read commands 1504 and 1507, and a column address 1505 and a row address 1506 that are parameters sandwiched between the commands 1504 and 1507. The column address 1505 and the row address 1506 are calculated using the block number and page number in the page list 1302. In response to the read flash command 1500, a valid data element is read from the read source page specified by the command 1500. The read valid data element is written into the first block buffer 305. On the first block buffer 305, the read valid data elements are arranged in ascending order of logical page addresses.

  Next, in response to the erase command 1304 in the reclamation command 1300, the flash memory control unit 301 erases the data element group in the physical block 613 specified from the block number 1305. Specifically, the flash command generation unit 303 creates an erase flash command for erasing the data element group in the physical block 613. The created erase flash command is transmitted to the flash memory chip having the physical block 613. As a result, the data element group stored in the physical block 613 is deleted.

  Next, in response to the write command 1306 in the reclamation command 1300, the flash memory control unit 301 stores the valid data element group stored in the first block buffer 305 in the physical block 613 identified from the block number 1307. Write. Specifically, the flash command generation unit 303 creates a plurality of write flash commands in units of pages for writing a plurality of valid data elements constituting the valid data element group to a plurality of physical pages in the physical block 613, respectively. To do. The created write flash command is transmitted to the flash memory chip having the physical block 613. As a result, a plurality of valid data elements stored in the first block buffer 305 are written into the physical block 613. Since the valid data elements are arranged in the first block buffer 305 in ascending order of the logical page addresses, the top of the aggregation-destination physical block 613 starts from the top valid data element of the first block buffer 305. Valid data elements are written sequentially from the page.

  When the flash memory control unit 301 finishes writing the valid data element group stored in the first block buffer 305 in the physical block 613, the flash memory control unit 301 sends a status signal 314 indicating the end of the processing of the reclamation command 1300 to the processor 2006. Send. As a result, the processor 2006 can know that the reclamation process has ended.

  The first in-module reclamation process is completed by the series of processes described above. In the modification example of the first in-module reclamation process, the aggregation-destination physical block 613 may exist in a flash memory chip different from the flash memory chip 614, or the original block 611 or the update block 612 may be The flash memory chip 614 may exist in a different flash memory chip. That is, in a modification of the first in-module reclamation process, reclamation may be performed between a plurality of flash memory chips.

  Since one flash memory control unit 301 controls a plurality of flash memory chips, processes that can be processed in parallel by the flash memory chips can be performed in parallel. The reclamation process is performed for each block which is an erasing unit, but the command issued to the flash memory chip is a flash command for each page. Accordingly, during the reclamation process, it is possible to interrupt a page unit I / O command from the processor 2006 based on an I / O request from the host computer 2009.

  The second in-module reclamation process will be described with reference to FIG.

  In the second in-module reclamation process, a plurality of physical blocks 801 to 803 in which valid data elements corresponding to two logical blocks are stored, and two aggregation destinations respectively corresponding to two logical blocks are stored. Physical blocks 804 and 805 exist on different flash memory chips 811 and 812. Specifically, a first source block 801 corresponding to the first logical block, an update block 803, and a second aggregation destination block 805 corresponding to the second logical block are included in the first flash memory chip 811. Exists. In addition, a second original block 802 corresponding to the second logical block and a first aggregation destination block 804 corresponding to the first logical block exist in the second flash memory chip 812. According to the example of FIG. 8, two original blocks 801 and 802 are allocated to one update block 803. Therefore, the storage capacity of the first block buffer 305 is equivalent to two physical blocks. Storage capacity is required.

As shown in FIG. 8, when two (or more) original blocks are assigned to one update block, the processor 2006 executes the reclamation command 1400 shown in FIG. Created based on the second management table. According to the reclamation command 1400 shown in FIG. 14, the following four points are different from the reclamation command 1300 shown in FIG.
(14-1) In the page list 1402, information representing a large number of read source pages respectively corresponding to a large number of logical pages constituting two logical blocks is recorded (the first half of the page list 1402 is Corresponds to one logical block, and the second half of the page list 1402 corresponds to the second logical block).
(14-2) The number of block numbers 1405 following the erase command 1404 is two,
(14-3) The number of block numbers 1407 following the write command 1406 is two,
(14-4) The point that the address of the flash memory chip is included in any block number of the page list 1402, block number 1405, and block number 1407 (that is, the block under management of the flash memory control unit 301 is uniquely specified Information that can be done is included in the block number),
There is.

  Based on the first half of the page list 1402 in the reclamation command 1400 of FIG. 14, each valid data element corresponding to the first logical block is transferred from the original block 801 and the update block 803 to the first half of the first block buffer 305. Read out. Each valid data element corresponding to the first logical block is arranged in ascending order of the logical page address in the first half of the first block buffer 305. Similarly, each valid data element corresponding to the second logical block is read from the original block 802 and the update block 803 to the latter half of the first block buffer 305 based on the latter half of the page list 1402. The valid data elements corresponding to the second logical block are arranged in ascending order of logical page addresses in the second half of the first block buffer 305.

  Next, in response to the erase command 1404 in the reclamation command 1400, the flash memory control unit 301 erases the data element groups in the two physical blocks 804 and 805 respectively identified from the two block numbers 1405. .

  Next, in response to the write command 1406 in the reclamation command 1400, the flash memory control unit 301 assigns the first block buffer 305 to the two physical blocks 804 and 805 identified from the two block numbers 1407, respectively. Are written in the two valid data element groups. Specifically, the valid data element group stored in the first half of the first block buffer 305 is written into the first aggregation destination block 804 and stored in the second half of the first block buffer 305. The valid data element group is written in the second aggregation destination block 805.

  The second in-module reclamation process is completed by the series of processes described above. Note that, in a modification of the second intra-module reclamation process, the second original block 802 and the first aggregation destination physical block 804 may exist in the flash memory chip 811. That is, in the modification example of the second in-module reclamation process, data elements may be rearranged in a single flash memory chip.

  <Inter-module reclamation process>.

  The first inter-module reclamation process will be described with reference to FIGS. 9 and 10. 9 shows a first flash memory module (hereinafter referred to as “transfer source module”) 2003A, and FIG. 10 shows a second flash memory module (hereinafter referred to as “transfer destination module”) 2003B.

  According to the example of FIG. 9, there are an original block 901 corresponding to one logical block and an update block 902 assigned to the original block 901 in one flash memory chip 871 of the transfer source module 2003A. The number of original blocks 901 assigned to the update block 902 is one. The original block 901 or the update block 902 may exist in another flash memory chip.

  On the other hand, according to the example of FIG. 10, the transfer destination module 2003B includes a physical block 1002 that is an aggregation destination.

  According to the example of the first inter-module reclamation process shown in FIG. 9 and FIG. 10, since the number of original blocks 901 assigned to one update block 902 is one, valid data elements between modules The storage capacity of the second block buffer 903 used when the group is transferred may be a storage capacity for one physical block.

  In the first inter-module reclamation process, the processor 2006 shows the transfer source reclamation command 1600 shown in FIG. 16 and FIG. 18 based on the first and second management tables (see FIG. 21 and FIG. 22). A transfer destination reclamation command 1800 is created. The processor 2006 transmits a transfer source reclamation command 1600 to the flash memory control unit 301A in the transfer source module 2003A, and transmits a transfer destination reclamation command 1800 to the flash memory control unit 301B in the transfer destination module 2003B. To do.

  According to the transfer source reclamation command 1600 shown in FIG. 16, the read command 1601 and the page list 1602 are included as common points with the reclamation command 1300 shown in FIG. Instead of the command 1304, the block number 1305, the write command 1306, and the block number 1307, a transfer command 1604 and a transfer destination flash memory control unit address 1605 are included. The transfer command 1604 is a command for transferring a valid data element group read based on the page list 1603 and arranged in ascending order of logical page addresses to the transfer destination module 2003B. The transfer destination flash memory control unit address 1605 is a parameter subsequent to the transfer command 1604 and represents the address of the flash memory control unit 301B in the transfer destination module 2003B.

  According to the transfer destination reclamation command 1800 shown in FIG. 18, as a common point with the reclamation command 1300 shown in FIG. 13, an erase command 1801, a block number 1802 following the erase command 1801, a write command 1803, and a write command The block number 1805 corresponding to 1803 is included. The difference is that the read command 1301 and the page list 1302 are not included, and the transfer source flash memory control unit address 1804 is included for the write command 1803. There is in point. The transfer source flash memory control unit address 1804 represents the address of the flash memory control unit 301A in the transfer source module 2003A.

  Upon receiving the transfer source confirmation command 1600, the transfer source flash memory control unit 301A performs the following processing.

  That is, as shown in FIG. 9, the command interpretation unit 302A specifies that the received command 1600 is a transfer source reclamation command. As shown in FIG. 9, the flash command generation unit 303A generates a plurality of read flash commands respectively corresponding to a plurality of read source pages based on the read command 1601 and the page list 1602 in the transfer source reclamation command 1600. The read flash command is transmitted to the flash memory chip having the read source page. As a result, a plurality of valid data elements corresponding to a plurality of logical pages constituting the logical block are read, and the read valid data elements are written in the second block buffer 903A. The plurality of valid data elements are arranged in the second block buffer 903A in ascending order of logical page addresses.

  Next, in response to the transfer command 1604 in the transfer source reclamation command 1600, the flash memory control unit 301A transfers the flash memory control unit 301B indicated by the transfer destination flash memory control unit address 1605 to the second block buffer 903A. The stored valid data element group is transferred through the second data bus 904. Specifically, for example, when the command interpretation unit 302A interprets the transfer command 1604, the sequence / timing control unit 304A converts the valid data element group stored in the second block buffer 903A to the second data buffer group 903A. Transfer through the data bus 904. At this time, if the transfer destination flash memory control unit 301B is busy, the fact that it is busy is transmitted from the sequence / timing control unit in the flash memory control unit 301B to the processor 2006, and the processor 2006 receives the transfer destination flash memory. Unless the interruption command is transmitted to the control unit 301B, the transfer-destination flash memory control unit 301B waits until a valid data element group is received from the transfer-source flash memory control unit 301A.

  When the flash memory control unit 301A has finished transferring the valid data element group stored in the second block buffer 903A to the flash memory control unit 301B (for example, a predetermined response is received from the transfer destination flash memory control unit 301B). If received), a status signal 314A indicating the end of processing of the transfer source reclamation command 1600 is transmitted to the processor 2006. Accordingly, the processor 2006 can know that the transfer of the valid data element group has been completed from the transfer source module 2003A.

  The transferred valid data element group passes through the second switch mechanism 2002 (see FIG. 20) and, as shown in FIG. 10, through the second data bus 904, the second data in the flash memory control unit 301B. Stored in the block buffer 903B.

  In response to the erase command 1801 in the transfer destination reclamation command 1800, the transfer destination flash memory control unit 301B erases the data element group in the physical block 1002 identified from the block number 1802.

  Next, in response to the write command 1803 in the transfer destination reclamation command 1800, the flash memory control unit 301B sends the flash memory control unit 301A that is the source of the valid data element group stored in the second block buffer 903B. Is a flash memory control unit specified from the transfer source flash memory control unit address 1804. If the determination result is affirmative, the flash memory control unit 301B writes the valid data element group stored in the second block buffer 903B to the physical block 1002 identified from the block number 1805. At that time, valid data elements are read from the second block buffer 903B in ascending order of addresses, and the read valid data elements are written in ascending order of page addresses of the physical block 1002 at the aggregation destination. .

  When the flash memory control unit 301B finishes writing the valid data element group stored in the second block buffer 903B in the physical block 1002, the status signal 314B indicating the end of the processing of the transfer destination reclamation command 1800 is displayed. To the processor 2006. As a result, the processor 2006 can know that the writing of the valid data element group has been completed in the transfer destination module 2003B.

  The first inter-module reclamation process is completed by the series of processes described above. If the buffer 903B is empty, the transfer destination flash memory control unit 301B receives the transferred valid data element. At this time, the flash memory control unit 301B indicated by the transfer source flash memory control unit address 1804 When it is confirmed that the transfer source flash memory control unit 301A matches, the valid data element group stored in the buffer 903B is written into the designated block (block represented by the block number 1805).

  The transfer destination reclamation command 1800 may be transmitted from the transfer destination flash memory control unit 301A to the flash memory control unit 301B instead of the processor 2006. However, as described above, not only the transfer source reclamation command 1600 but also the transfer destination reclamation command 1800 is transmitted from the processor 2006, so that the processor 2006 can change the transfer source module 2003A and the transfer destination module 2003B. Can receive status signals and status from both. For this reason, the processor 2006 can know whether the operation is reliably performed in each of the transfer source module 2003A and the transfer destination module 2003B.

  Similar to the intra-module reclamation process, the second inter-module reclamation process in which a plurality of original blocks are assigned to one update block can also be performed. That is, a plurality of original blocks 901 respectively assigned to a plurality of logical blocks may be assigned to the update block 902 existing in the transfer source module 2003A, and a plurality of logical blocks may be assigned to the transfer destination module 2003B. There may be a plurality of aggregation-destination physical blocks 1002 corresponding to each.

  In this case, as the storage capacities of the second block buffers 903A and 903B, a storage capacity for a plurality of original blocks allocated to the update block 902 is required.

  In this case, the transfer source reclamation command 1700 shown in FIG. 17 is transmitted to the transfer source module 2003A instead of the transfer source reclamation command 1600 shown in FIG. On the other hand, instead of the transfer destination reclamation command 1800 shown in FIG. 18, the transfer destination reclamation command 1900 shown in FIG. 19 is transmitted to the transfer destination module 2003B.

According to the transfer source reclamation command 1700 shown in FIG. 17, the following two points are different from the transfer source reclamation command 1600 shown in FIG.
(17-1) Information representing a large number of read source pages respectively corresponding to a large number of logical pages constituting a plurality of logical blocks is recorded in the page list 1702;
(17-2) The block number in the page list 1702 includes the address of the flash memory chip,
There is. Upon receiving this transfer source reclamation command 1700, the transfer source flash memory control unit 301A reads valid data elements from a plurality of original blocks 901 based on the page list 1702 and writes them in the second block buffer 903A. As a result, a plurality of valid data element groups corresponding to the plurality of logical blocks are stored in the second block buffer 903A. A plurality of valid data element groups are transmitted from the second block buffer 903A to the flash memory control unit 301B and written to the second block buffer 903B in the flash memory control unit 301B.

Further, according to the transfer destination reclamation command 1900 shown in FIG. 19, the following three points are different from the transfer destination reclamation command 1800 shown in FIG.
There is.
(19-1) The fact that there are a plurality of block numbers 1902 following the erase command 1901,
(19-2) A plurality of block numbers 1905 corresponding to the write command 1903 exist.
(19-3) The flash memory chip address is included in any of the block numbers 1902 and 1905,
There is. Upon receiving the transfer destination reclamation command 1900, the transfer destination flash memory control unit 301B deletes the data element group in the plurality of aggregation destination blocks 1002 identified from the plurality of block numbers 1902. Then, the transfer destination flash memory control unit 301B writes the plurality of valid data element groups stored in the second block buffer 903B to the plurality of aggregation destination blocks 1002 specified from the plurality of block numbers 1905.

  As described above, according to the first embodiment described above, the storage controller can centrally manage a plurality of flash memories.

  Further, according to the first embodiment, when the storage controller issues a reclamation command to the flash memory control unit, the flash memory control unit reads and writes in units of pages in response to the reclamation command. Execute reclamation that occurs. For this reason, the storage controller does not have to issue a read command and a write command in units of pages, so that a decrease in performance for processing an I / O request from the host computer 2009 can be suppressed.

  Further, according to the first embodiment, the valid data element group is transferred between the flash memory modules 2003 via the second switch mechanism 2002 to which the storage controller is not connected. In other words, in the transfer of the valid data element group between the flash memory modules 2003, the first switch mechanism 2001 connecting the storage controller and the flash memory module 2003 is not passed. For this reason, the path through which the data to be written or the data to be read according to the I / O request from the host computer 2009 is not compressed, so that it is possible to suppress a decrease in the performance of processing the I / O request from the host computer 2009. .

  Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 11 and 12.

  As shown in FIG. 12, in the second embodiment, a flash memory module 2003 ′ having a unified IF flash memory control unit is adopted instead of the flash memory module 2003 (“IF” is an abbreviation of interface). ).

  As shown in FIG. 11, the unified IF flash memory control unit 1106 includes IF protocol conversion units 1103 and 1104 in addition to the flash memory control unit 301. The IF protocol conversion units 1103 and 1104 are circuits that perform protocol conversion for high-speed serial communication. The IF protocol conversion unit 1103 exists between the second switch mechanism 2002 and the second block buffer 903. The IF protocol conversion unit 1104 exists between the first switch mechanism 2001, the command interpretation unit 302, the first data bus 312, and the sequence / timing control unit 304.

  The IF protocol conversion units 1103 and 1104 unify the communication IF via the second switch mechanism 2002 and the communication IF via the first switch mechanism 2001.

  As mentioned above, although several suitable embodiment of this invention was described, these are the illustrations for description of this invention, Comprising: It is not the meaning which limits the scope of the present invention only to these embodiment. The present invention can be implemented in various other forms. For example, in the above-described embodiment, the reclamation process is taken as an example of the data rearrangement process, but the present invention can be applied to other data rearrangement processes such as a wear leveling process.

1 is a schematic diagram of a part of a memory cell array of a NAND flash memory. 2 shows an example of the configuration of a flash memory chip. 2 shows a configuration example of a flash memory module. It is explanatory drawing of a single page read-out operation | movement. It is explanatory drawing of a single page write operation. It is explanatory drawing of the process performed when an update generate | occur | produces in the effective data element in an original block. It is explanatory drawing of the 1st in-module reclamation process. It is explanatory drawing of the 2nd in-module reclamation process. The transfer source flash memory module in the first inter-module reclamation process is shown. A transfer destination flash memory module in the first inter-module reclamation process is shown. The structural example of the storage system which concerns on 2nd embodiment of this invention is shown. The structural example of the unified IF flash memory control part with which the flash memory module in 2nd embodiment of this invention is equipped is shown. The reclamation command issued in the 1st in-module reclamation process is shown. The reclamation command issued in the second in-module reclamation process is shown. It is explanatory drawing that a read flash command is produced based on a read command and a page list. A transfer source reclamation command issued in the first inter-module reclamation process is shown. A transfer source reclamation command issued in the second inter-module reclamation process is shown. The transfer destination reclamation command issued in the first inter-module reclamation process is shown. The transfer destination reclamation command issued in the second inter-module reclamation process is shown. 1 shows a configuration example of a storage system according to a first embodiment of the present invention. The structural example of a 1st management table is shown. The structural example of a 2nd management table is shown.

Explanation of symbols

2000 ... Storage system 2001 ... First switch mechanism 2002 ... Second switch mechanism 2003 ... Flash memory module 2004 ... Host adapter 2005 ... Cache memory 2006 ... Processor 2007 ... Management terminal 2009 ... Host computer

Claims (25)

A storage system that accepts an I / O request (input / output request) specifying a logical address of a storage area in a logical storage resource based on flash memory from a host device,
A flash memory module;
A storage controller that receives the I / O request from the host device and accesses the flash memory module in response to the I / O request;
The storage controller is
A storage resource for storing address conversion information representing a correspondence relationship between a logical address and a physical address of a storage area in the flash memory;
A physical address corresponding to a logical address designated by the received I / O request is specified using the address conversion information, and an I / O command having I / O destination information based on the specified physical address is A processor for transmitting to the memory controller,
The flash memory module is
Flash memory,
A memory controller that receives the I / O command and performs I / O to a storage area in the flash memory that is specified from I / O destination information included in the I / O command.
Storage system. The flash memory has a plurality of physical blocks composed of a plurality of physical pages, and a data element stored in a physical page in the first physical block is updated to an update data element A memory in which the update data element is written to a physical page in a second physical block that is an erased physical block assigned to the first physical block;
The address conversion information is information indicating the location of each valid data element corresponding to the logical block to which the storage area corresponding to the logical address belongs, and is assigned to the first physical block corresponding to the first logical block. Information that is updated by the processor when an update data element is written to a physical page in the second physical block being
The processor creates a reclamation command and sends the reclamation command to the memory controller of the flash memory module;
The reclamation command is
A plurality of page information elements representing a plurality of read source physical pages each storing a plurality of valid data elements constituting a valid data element group corresponding to the first logical block, and using the address conversion information Page list created
Erase block information representing erase blocks, which are physical blocks from which data elements are erased, and
Write destination block information representing the erase block to be the write destination of the valid data element group,
The plurality of read source physical pages exist in the first physical block and / or the second physical block,
The memory controller has a first buffer and executes the following (3-1) to (3-3).
(3-1) The plurality of valid data elements are read from the plurality of read source physical pages specified from the page list, and the valid data elements are arranged in the order of logical addresses corresponding to the first logical block. Writing the plurality of valid data elements into a first buffer;
(3-2) erasing a data element group in the erase block specified from the erase block information;
(3-3) Write a plurality of valid data elements stored in the first buffer to the erase block identified from the write destination block information.
The storage system according to claim 1. The reclamation command further includes a read command having the page list, an erase command having the erase block information, and a write command having the write destination block information,
The memory controller executes (3-1) in response to the read command included in the reclamation command, and executes (3-2) in response to the erase command included in the reclamation command. , Executing (3-3) in response to the write command of the reclamation command,
The storage system according to claim 2. The flash memory has a plurality of flash memory chips,
Each flash memory chip has a plurality of physical blocks,
A plurality of the first physical blocks are assigned to the second physical block;
Each page information element constituting the page list includes information representing the physical page of the read source, and information representing the physical block having the physical page of the read source,
The information representing the physical block having the physical page of the read source, the erase block information, and the write destination block information each include information representing the flash memory chip including the physical block. ,
The storage system according to claim 2 or 3. The flash memory has a plurality of flash memory chips,
Each flash memory chip has a plurality of physical blocks,
The physical block having the plurality of read source physical pages and the erase block exist in different flash memory chips,
The storage system according to any one of claims 2 to 4. A plurality of the first physical blocks are assigned to the second physical block;
The storage capacity of the first buffer is the storage capacity of the plurality of first physical blocks;
The storage system according to any one of claims 2 to 5. The flash memory has a plurality of physical blocks composed of a plurality of physical pages, and a data element stored in a physical page in the first physical block is updated to an update data element A memory in which the update data element is written to a physical page in a second physical block that is an erased physical block assigned to the first physical block;
The address conversion information is information indicating the location of each valid data element corresponding to the logical block to which the storage area corresponding to the logical address belongs, and is assigned to the first physical block corresponding to the first logical block. Information that is updated by the processor when an update data element is written to a physical page in the second physical block being
The plurality of flash memory modules include first and second flash memory modules,
The flash memory in the first flash memory module includes the first physical block and the second physical block,
The flash memory in the second flash memory module includes an erase block that is a physical block from which a data element group is erased,
The processor creates a first reclamation command, sends the first reclamation command to the first memory controller of the first flash memory module,
The first reclamation command has at least (7-A) and (7-B) among the following (7-A) to (7-D):
(7-A) A plurality of page information elements representing a plurality of read source physical pages each storing a plurality of valid data elements constituting a valid data element group corresponding to the first logical block, A page list created using address translation information,
(7-B) Information representing a second memory controller included in the second flash memory module;
(7-C) Erase block information representing an erase block which is a physical block from which the data element group is erased,
(7-D) Write destination block information indicating the erase block to be a write destination of the valid data element group,
The plurality of read source physical pages exist in the first physical block and / or the second physical block,
The first memory controller has a second buffer A, executes the following (7-1) and (7-2),
(7-1) A plurality of valid data elements are read from the plurality of read source physical pages specified from the information of (7-A), and valid data elements are in order of logical addresses corresponding to the first logical block. Write the plurality of valid data elements in the second buffer A so that
(7-2) transferring a plurality of valid data elements stored in the second buffer A to the second memory controller identified from the information of (7-B);
The information of (7-C) and (7-D) is transmitted from the first memory controller or the processor to the second memory controller,
The second memory controller has a second buffer B and executes the following (7-3) to (7-5).
(7-3) Write the plurality of valid data element groups transferred from the first memory controller to the second buffer B.
(7-4) erasing the data element group in the erase block identified from the information of (7-C),
(7-5) Write a plurality of valid data elements stored in the second buffer B to the erase block identified from the information of (7-D).
The storage system according to any one of claims 1 to 6. The processor creates a second reclamation command and sends the second reclamation command to the second memory controller;
The information of (7-C) and (7-D) is not included in the first reclamation command,
The second reclamation command includes the information (7-C) and (7-D).
The storage system according to claim 7. The first reclamation command further includes a read command having the information (7-A) and a transfer command having the information (7-B),
The second reclamation command further includes an erase command having the information (7-C) and a write command having the information (7-D),
The first memory controller executes (7-1) in response to the read command included in the first reclamation command, and (7) in response to the transfer command included in the reclamation command. -2)
The second memory controller executes the (7-4) in response to the erase command included in the reclamation command, and the (7-5) in response to the write command included in the reclamation command. Run the
The storage system according to claim 8. In addition to the first switch mechanism to which both the storage controller and the plurality of flash memory modules are connected, the storage controller and the second flash memory module among the plurality of flash memory modules are connected to the second switch mechanism. With a switch mechanism
The transfer of the plurality of valid data elements from the first flash memory module to the second flash memory module is performed via the second switch mechanism.
The storage system according to any one of claims 7 to 9. The flash memory has a plurality of flash memory chips,
Each flash memory chip has a plurality of physical blocks,
A plurality of the first physical blocks are assigned to the second physical block;
Each page information element constituting the page list includes information representing the physical page of the read source, and information representing the physical block having the physical page of the read source,
The information representing the physical block having the physical page of the read source, the erase block information, and the write destination block information each include information representing the flash memory chip including the physical block. ,
The storage system according to any one of claims 7 to 10. A plurality of the first physical blocks are assigned to the second physical block;
The storage capacities of the second buffers A and B are the storage capacities of the plurality of first physical blocks, respectively.
The storage system according to any one of claims 7 to 11. The processor creates a data rearrangement command and sends the data rearrangement command to the memory controller included in the flash memory module;
The data rearrangement command is:
A page list that is a plurality of page information elements representing a plurality of read source physical pages of a plurality of data elements constituting a data element group corresponding to the first logical block;
Erase block information representing erase blocks, which are physical blocks from which data elements are erased, and
Write block information representing the erase block to be written to, and
The memory controller has a first buffer and executes the following (13-1) to (13-3).
(13-1) Reading a plurality of data elements from the plurality of read source physical pages specified from the page list, and writing the plurality of data elements into the first buffer.
(13-2) erasing a data element group in the erase block specified from the erase block information;
(13-3) Write a plurality of data elements stored in the first buffer to the erase block specified from the write destination block information.
The storage system according to claim 1. The plurality of flash memory modules include first and second flash memory modules,
The flash memory in the first flash memory module includes one or a plurality of physical blocks having a plurality of read source physical pages of a plurality of data elements constituting a data element group corresponding to the first logical block. And
The flash memory in the second flash memory module includes an erase block that is a physical block from which a data element group is erased,
The processor creates a first data rearrangement command, sends the first data rearrangement command to the first memory controller of the first flash memory module,
The first data rearrangement command has at least (14-A) and (14-B) among the following (14-A) to (14-D):
(14-A) a page list which is a plurality of page information elements representing the plurality of read source physical pages;
(14-B) Information representing a second memory controller included in the second flash memory module;
(14-C) erase block information representing an erase block which is a physical block from which the data element group is erased;
(14-D) Write destination block information representing the erase block to be a write destination of the data element group,
The first memory controller has a second buffer A and executes the following (14-1) and (14-2):
(14-1) Reading a plurality of data elements from the plurality of read source physical pages specified from the information of (14-A), and writing the plurality of data elements to the second buffer A,
(14-2) transferring a plurality of data elements stored in the second buffer A to the second memory controller identified from the information of (14-B);
The information of (14-C) and (14-D) is transmitted from the first memory controller or the processor to the second memory controller,
The second memory controller has a second buffer B, and executes the following (14-3) to (14-5).
(14-3) Write the plurality of data element groups transferred from the first memory controller to the second buffer B.
(14-4) erasing the data element group in the erase block identified from the information of (14-C),
(14-5) Write a plurality of data elements stored in the second buffer B to the erase block identified from the information of (14-D).
The storage system according to claim 1 or 13. The processor creates a second data relocation command and sends the second data relocation command to the second memory controller;
The information of (14-C) and (14-D) is not included in the first data rearrangement command,
The second data rearrangement command includes the information (14-C) and (14-D).
The storage system according to claim 14. In addition to the first switch mechanism to which both the storage controller and the plurality of flash memory modules are connected, the storage controller and the second flash memory module among the plurality of flash memory modules are connected to the second switch mechanism. With a switch mechanism
Transfer of the plurality of data elements from the first flash memory module to the second flash memory module is performed via the second switch mechanism.
The storage system according to claim 14 or 15. The memory controller has a unified interface unit that unifies communication interfaces via the first switch mechanism and communication via the second switch mechanism.
The storage system according to claim 16. Flash memory,
A memory controller that controls I / O (input / output) to the flash memory,
The memory controller is
A command interpreter that interprets commands received from outside;
When the command interpreted by the command interpreter is a data relocation command, the physical address information included in the data relocation command is used to create a read command and / or a write command related to data relocation, A command generation unit that transmits the created read command and / or write command to the flash memory,
Flash memory module. The flash memory has a plurality of physical blocks composed of a plurality of physical pages,
The data rearrangement command has the following physical address information (19-A) to (19-C):
(19-A) A page list which is a plurality of page information elements representing a plurality of read source physical pages each storing a plurality of data elements constituting a data element group corresponding to the first logical block.
(19-B) Erase block information representing an erase block which is a physical block from which a data element group is erased,
(19-C) Write destination block information indicating the erase block to be a write destination of the data element group,
Have
The memory controller further includes a first buffer;
The memory controller executes the following (19-1) to (19-4).
(19-1) The command generation unit creates a plurality of read commands in units of pages for reading a plurality of data elements from the plurality of read source physical pages specified from the page list, and the plurality of reads Send a command to the flash memory,
(19-2) The first buffer stores the plurality of data elements read in response to the plurality of read commands in page units.
(19-3) The command generation unit transmits an erase command for erasing a data element group in the erase block specified from the erase block information to the flash memory.
(19-4) A plurality of page-by-page write commands for writing a plurality of data elements stored in the first buffer to a plurality of physical pages in the erase block specified from the write destination block information Send to the flash memory,
The flash memory module according to claim 18. The data rearrangement command further includes a read command having the information (19-A), an erase command having the information (19-B), and a write command having the information (19-C). Have
The command generation unit executes (19-1) in response to the read command included in the data rearrangement command, and (19-3) in response to the erase command included in the data rearrangement command. And (19-4) is executed in response to the write command included in the data rearrangement.
The flash memory module according to claim 19. The flash memory has a plurality of flash memory chips, and when the data element stored in the physical page in the first physical block is updated to the update data element, the flash memory has the first physical block. A memory in which the updated data element is written to a physical page in a second physical block that is an allocated erased physical block;
Each flash memory chip has a plurality of physical blocks,
A plurality of the first physical blocks are assigned to the second physical block;
Each page information element constituting the page list includes information representing the physical page of the read source, and information representing the physical block having the physical page of the read source,
The information representing the physical block having the physical page of the read source, the erase block information, and the write destination block information each include information representing the flash memory chip including the physical block. ,
The flash memory module according to claim 19 or 20. The flash memory has a plurality of flash memory chips,
Each flash memory chip has a plurality of physical blocks,
The physical block having the plurality of read source physical pages and the erase block exist in different flash memory chips,
The flash memory module according to any one of claims 19 to 21. The flash memory is an erased physical block assigned to the first physical block when a data element stored in a physical page in the first physical block is updated to an updated data element. A memory in which the update data element is written to a physical page in a second physical block;
A plurality of the first physical blocks are assigned to the second physical block;
The storage capacity of the first buffer is the storage capacity of the plurality of first physical blocks;
The flash memory module according to any one of claims 19 to 22. The flash memory has a plurality of physical blocks composed of a plurality of physical pages,
The memory controller has a second buffer;
The data rearrangement command is a first data rearrangement command having the following (24-A) and (24-B):
(24-A) A plurality of page information elements representing a plurality of read source physical pages each storing a plurality of data elements constituting a data element group corresponding to the first logical block, wherein the address conversion A page list created using information,
(24-B) Information representing a second memory controller included in the second flash memory module;
When the command interpreted by the command interpreter is the first data rearrangement command, the memory controller executes the following (24-1) to (24-3).
(24-1) The command generation unit flushes a plurality of read commands in units of pages for reading a plurality of data elements from the plurality of read source physical pages specified from the information of (24-A). Send to memory,
(24-2) The second buffer stores the plurality of data elements read in response to the plurality of read commands in page units.
(24-3) transferring a plurality of data elements stored in the second buffer to another memory controller identified from the information of (24-B);
24. The flash memory module according to any one of claims 18 to 23. The flash memory has a plurality of physical blocks composed of a plurality of physical pages,
The memory controller has a second buffer;
The data rearrangement command is a second data rearrangement command having the following (25-A) and (25-B):
(25-A) erase block information representing an erase block which is a physical block from which the data element group is erased,
(25-B) write destination block information representing the erase block that is the write destination of the data element group;
The memory controller executes the following (25-1) to (25-3).
(25-1) The second buffer writes a plurality of data element groups transferred from another memory controller to the second buffer.
(25-2) The command generation unit transmits an erase command for erasing a data element group in the erase block specified from the information of (25-A) to the flash memory.
(25-3) The command generation unit writes a plurality of data elements stored in the second buffer to a plurality of physical pages in the erase block specified from the information of (25-B), respectively. Transmitting a plurality of page-by-page write commands to the flash memory,
The flash memory module according to any one of claims 18 to 24.

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