JP2009277007A - Computer device and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance execution performance of an application program, in a computer device loaded with a plurality of processors. <P>SOLUTION: A processor device trying to start execution of the application program needing exclusive use of external devices 117-120 shared by the plurality of processor devices 100-102 transmits an inter-processor interrupt signal to the other processor devices. The other processor devices receiving the inter-processor interrupt signal stop access operation to the external devices to make the processor executing the application program needing the exclusive use of the external devices exclusively use the external devices, so that the execution performance of the application program can be enhanced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a conflict avoidance technique when a plurality of processor devices (hereinafter also referred to as processors) access a shared resource.

As a case where a plurality of processors use a shared resource, for example, there is a technique described in Non-Patent Document 1.
In Non-Patent Document 1, a plurality of processors share an external bus and are connected to an external device via the external bus. One processor or several processors are grouped as one unit, and each of these units is united. In a computer in which a plurality of operating systems operate simultaneously, each operating system executes an operation of an external device via a shared bus based on a request from an application program (hereinafter also simply referred to as an application).

Moreover, there is a technique described in Patent Document 1 as a contention avoidance technique when a shared resource is accessed by a plurality of processors.
In Patent Document 1, in a shared memory type multiprocessor computer system in which a plurality of processors share a main memory, a lock granularity is calculated every time a resource shared by a plurality of processors is locked, and the calculated lock granularity is calculated. It is disclosed that the lock granularity statistical information of a resource is updated based on the above, and when the lock wait for the resource occurs, the lock waiting method is determined based on the lock granularity statistical information of the resource.
JP 2001-84235 A “RENESAS EDGE No. 17”, Renesas Technology Corp., April 2007, Volume 5, No. 1, P02-P03

  In the prior arts including the techniques of Patent Document 1 and Non-Patent Document 1 described above, in a plurality of operating systems operating on a plurality of processors, an external device that is a shared resource while another operating system uses the shared bus There is a problem that the execution performance of the application is lowered because the execution of the application that performs the above operation is awaited.

  One of the main objects of the present invention is to solve the above-described problems, and in a computer device equipped with a plurality of processor devices, execution of an application program that requires exclusive use of shared resources is started. The main purpose is to improve the execution performance of an application program by allowing a processor device to be used exclusively to use shared resources.

The computer apparatus according to the present invention is:
A computer device including a plurality of processor devices and a shared resource shared by the plurality of processor devices,
Each of the plurality of processor devices accesses the shared resource to execute an application program,
The execution start processor device which is going to start execution of the application program transmits an exclusive operation request signal requesting exclusive use of the shared resource to another processor device,
The processor device that has received the exclusive operation request signal from the execution start processor device stops the access operation to the shared resource for a predetermined time.

  According to the present invention, a processor device that attempts to start execution of an application program that requires exclusive use of a shared resource transmits an exclusive operation request signal, and another processor device that has received the exclusive operation request signal transmits to the shared resource. Since the access operation is stopped, the shared resource can be exclusively used by the processor device that executes the application program that requires exclusive use of the shared resource, and the execution performance of the application program can be improved.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration example of a computer apparatus 10 according to the present embodiment.
The computer apparatus 10 shown in FIG. 1 is equipped with three processor devices and one operating system operates.
FIG. 2 is a flowchart showing an operation example of the processor device when the dispatch processing unit 107 of the operating system 106 is executed.
FIG. 3 is a flowchart showing an operation example of the processor device when the exclusive operation request transmission processing unit 108 of the operating system 106 is executed.
FIG. 4 is a flowchart showing an operation example of the processor device when the exclusive operation request reception processing unit 109 of the operating system 106 is executed.

As shown in FIG. 1, the computer apparatus 10 according to the present embodiment includes a plurality of processors 100 to 102 (three in this case), an operating system 106 and a storage unit 111 common to each processor, and a plurality of external devices 117. 120 (four in this case) and a shared bus 116 for connecting the processor and external devices.
As will be described later, the external devices 117 to 120 are shared by the plurality of processors 100 to 102 and are examples of shared resources.

  The processors 100 to 102 are arithmetic processing devices that execute applications assigned by the dispatch processing unit 107 of the operating system 106.

The storage unit 111 is connected to the processors 100 to 102, and includes an application program (AP) group 112 that is a plurality of applications executed on the processor, application information 113 (also referred to as AP information) that is information for each application program, The shared storage unit 114 is a storage area for storing information shared by all processors. The shared storage unit 114 is an example of a shared storage device.
The shared storage unit 114 will be described in the second and subsequent embodiments.

  The shared bus 116 is a bus that connects the processors 100 to 102 and the external devices 117 to 120.

  The inter-processor interrupt mechanisms 103 to 105 are present in the processors 100 to 102, respectively, and transmit inter-processor interrupt signals to other processors and receive inter-processor interrupt signals from other processors.

The application information 113 stores exclusive operation request information 115 that is information related to the exclusive operation request.
The exclusive operation request information 115 stores an exclusive operation request flag indicating the presence or absence of an exclusive operation request.

In the operating system 106, the exclusive operation request transmission processing unit 108 is a process of operating the inter-processor interrupt mechanisms 103 to 105 and transmitting inter-processor interrupt signals to other processors.
The exclusive operation request reception processing unit 109 is a process that operates when the inter-processor interrupt mechanisms 103 to 105 each receive an inter-processor interrupt.
The timer 110 is a time measuring unit that operates based on a set timeout value and detects that a timeout has occurred.
Note that the entities of the dispatch processing unit 107, the exclusive operation request transmission processing unit 108, the exclusive operation request reception processing unit 109, and the timer 110, which are components of the operating system 106, are code blocks for realizing the respective processes. The processor reads and executes these code blocks to realize the intended function.

Next, the operation will be described.
First, the operation of the processor when executing the dispatch processing unit 107 will be described.
FIG. 2 is a flowchart showing an example of the operation of the processor when the dispatch processing unit 107 of the operating system 106 is executed.
In the following description, it is assumed that the processor (execution start processor device) that starts executing the application is the processor 100.

By executing the dispatch processing unit 107, the processor 100 selects an application to be allocated to the processor 100 next from the application group 112 in S200.
Next, in S201, the processor 100 checks the exclusive operation request flag of the exclusive operation request information 115 corresponding to the application selected in S200.
As a result of examining the exclusive operation request flag, if the application does not request an exclusive operation (NO in S202), the process proceeds to S204.
If the application requests an exclusive operation (YES in S202), the process proceeds to S203, and the processor 100 executes the exclusive operation request transmission processing unit.
In S204, the application selected in S200 is assigned to the processor 100, and the execution of the dispatch processing unit 107 is terminated.

Next, an operation example of the processor when executing the exclusive operation request transmission processing unit 108 will be described.
FIG. 3 is a flowchart showing an operation example of the processor when the exclusive operation request transmission processing unit 108 of the operating system 106 is executed.
By executing the exclusive operation request transmission processing unit 108, the processor 100 transmits an inter-processor interrupt signal to another processor in S300, and thereafter ends the execution of the exclusive operation request transmission processing unit 108.
The inter-processor interrupt signal is a signal for requesting exclusive use of the external devices 117 to 120 that are shared resources to other processors, and is an example of an exclusive operation request signal.

Next, the operation of the processor when the exclusive operation request reception processing unit 109 is executed will be described.
FIG. 4 is a flowchart showing an operation example of the processor when the exclusive operation request reception processing unit 109 of the operating system 106 is executed.

When receiving the inter-processor interrupt signal from the processor 100, the processors 101 and 102 execute the exclusive operation request reception processing unit 109.
When executing the exclusive operation request reception processing unit 109, the processors 101 and 102 temporarily stop the operations of the processors 101 and 102 in S400. Note that the operation to temporarily stop here is an access operation to the external devices 117 to 120, and operations other than the access operation to the external devices 117 to 120 can be continued.
Next, the processors 101 and 102 set a timeout value to the timer 110 in S401, and start a timer operation in S402.
If no timeout has occurred in S403, S403 is repeated.
If a timeout has occurred in S403, the process proceeds to S404, where the processors 101 and 102 resume their operations and end. That is, the processors 101 and 102 can start an access operation to the external devices 117 to 120.

  As described above, by suspending other processor operations in the computer at the time of executing the application that requests the exclusive operation, the application is not affected by the operations of the other processors in the computer for a certain period of time. It is possible to operate exclusively in the computer.

As described above, in the present embodiment, a plurality of processors are operated, interprocessor interrupts are connected to each processor, and each processor has a shared resource.
The application has an exclusive operation request flag indicating whether it is necessary to monopolize and execute the shared resource (exclusive operation)
When the application is dispatched to the processor, if it is determined that the exclusive operation is required by the exclusive operation request flag, the exclusive operation request transmission processing unit that transmits the exclusive operation request to another processor;
A computer apparatus having an operating system including an exclusive operation request reception processing unit that temporarily stops a processor when an exclusive operation request is received has been described.

  In this embodiment, it has been described that one operating system operates on a plurality of processors.

  Further, in the present embodiment, it has been described that the exclusive operation request uses an inter-processor interrupt.

  Further, in the present embodiment, it has been described that the period during which the exclusive operation request reception processing unit pauses the processor is a predetermined fixed period.

Embodiment 2. FIG.
In the first embodiment described above, the suspension period (timeout value) is fixed. Next, an embodiment in which a timeout value can be designated for each application will be described.

  The overall configuration is the same as in the first embodiment. However, in the first embodiment, the exclusive operation request information 115 stores an exclusive operation request flag indicating the presence or absence of an exclusive operation request. However, in the second embodiment, the exclusive operation request flag and the application operate exclusively. Information (stop time information) indicating the stop time (time-out value) during which another processor stops the access operation to the shared resource.

Next, the operation will be described.
The operation of the processor at the time of execution of the dispatch processing unit 107 is the same as that of the first embodiment.

Next, the operation of the processor when the exclusive operation request transmission processing unit 108 is executed will be described.
FIG. 5 is a flowchart showing an operation example of the processor when the exclusive operation request transmission processing unit 108 of the operating system 106 is executed.
Also in the present embodiment, description will be made assuming that the processor 100 starts executing an application.
By executing the exclusive operation request transmission processing unit 108, the processor 100 reads the timeout value from the exclusive operation request information 115 of the application selected during the operation of the dispatch processing unit 107 in S500.
Then, the processor 100 writes the read timeout value in the shared storage unit 114 (S501).
Next, the processor 100 transmits an inter-processor interrupt signal to another processor in S502, and ends the execution of the exclusive operation request transmission processing unit.

Next, the operation of the processor when the exclusive operation request reception processing unit 109 is executed will be described.
FIG. 6 is a flowchart showing an operation example of the processor when the exclusive operation request reception processing unit 109 of the operating system is executed.
When receiving the interprocessor interrupt signal from the processor 100, the processors 101 and 102 execute the exclusive operation request reception processing unit 109.
The processors 101 and 102 execute the exclusive operation request reception processing unit 109, thereby temporarily stopping the access operations of the processors 101 and 102 to the external devices 117 to 120 in S600, respectively.
Next, the processors 101 and 102 read the timeout value from the shared storage unit 114 in S601.
Next, the processors 101 and 102 set a timeout value to the timer 110 in S602, and start a timer operation in S603.
Next, when no timeout has occurred in S604, the processors 101 and 102 repeat S604.
If a timeout has occurred in S604, the process proceeds to S605, the operations of the processors 101 and 102 are resumed, and the process ends.

  As described above, the timeout value can be specified for each application that makes an exclusive operation request. Therefore, the minimum necessary timeout value can be set for each application, and the processor that receives the exclusive operation request temporarily The stop period can be shortened, and the processing capacity of the entire computer can be improved accordingly.

  As described above, in the present embodiment, the exclusive operation request transmission processing unit transmits an inter-processor interrupt and requests a period for suspension, and the exclusive operation request reception processing unit performs an exclusive operation request during the period for pausing the processor. It has been described that the period is requested from the transmission processing unit.

Embodiment 3 FIG.
In the first embodiment described above, the exclusive operation request reception processing unit that has received the exclusive operation request has always suspended the processor operation. However, according to the priority of the application being executed by the processor, the processor operation is suspended. An embodiment for determining availability is shown.

The overall configuration is the same as in the first embodiment.
However, in the first embodiment, the exclusive operation request information 115 stores an exclusive operation request flag indicating the presence / absence of an exclusive operation request, but in the third embodiment, the exclusive operation request flag is unique within the computer apparatus 10 and the exclusive operation request flag. The priority of the application is stored.

  Next, the operation will be described.

  The operation of the processor at the time of execution of the dispatch processing unit 107 is the same as that of the first embodiment.

Next, the operation of the processor when the exclusive operation request transmission processing unit 108 is executed will be described.
FIG. 7 is a flowchart showing an operation example of the processor when the exclusive operation request transmission processing unit 108 of the operating system 106 is executed.
Also in the present embodiment, description will be made assuming that the processor 100 starts executing an application.
By executing the exclusive operation request transmission processing unit 108, the processor 100 reads priority information indicating the priority of the application from the exclusive operation request information 115 of the application selected when the dispatch processing unit 107 is executed in S700.
Next, the processor 100 writes the read priority information to the shared storage unit 114 (S701).
Next, the processor 100 transmits an inter-processor interrupt signal to another processor in S702, and ends the execution of the exclusive operation request transmission processing unit.

Next, the operation of the processor when the exclusive operation request reception processing unit 109 is executed will be described.
FIG. 8 is a flowchart showing an operation example of the processor when the exclusive operation request reception processing unit 109 of the operating system 106 is executed.
When receiving the interprocessor interrupt signal from the processor 100, the processors 101 and 102 execute the exclusive operation request reception processing unit 109.
By executing the exclusive operation request reception processing unit 109, the processors 101 and 102 read the priority of the application being executed by the processors 101 and 102 in S800.
Next, the processors 101 and 102 read priority information from the shared storage unit 114 in S801.
Next, the processors 101 and 102 compare the priorities in S802, and when the priority stored in the shared storage unit 114 is lower (NO in S802), the exclusive operation request reception processing unit 109. The execution of is terminated. That is, in this case, the processors 101 and 102 do not restrict the access operation to the external devices 117 to 120 even if the application that the processor 100 starts executing requests exclusive use of the external devices 117 to 120.
If the priority stored in the shared storage unit 114 in S802 is higher (YES in S802), the processors 101 and 102 proceed to S803 and access the external devices 117 to 120 of the processors 101 and 102. Pauses operation.
Next, the processors 101 and 102 set a timeout value to the timer 110 in S804, and start the timer operation in S805.
If no timeout has occurred in S806, S806 is repeated.
If a timeout has occurred in S806, the processors 101 and 102 proceed to S807 to resume the operations of the processors 101 and 102 and end the execution of the exclusive operation request reception processing unit 109.

  As described above, since priority can be specified for each application that makes an exclusive operation request, if the running application has a higher priority than the application that made the exclusive operation request, the process is suspended. It is possible to continue without

As described above, in the present embodiment, the application has priority information that is unique within the computer together with the exclusive operation request flag,
The exclusive operation request transmission processing unit transmits an inter-processor interrupt and notifies priority information,
The exclusive control request reception processing unit compares the priority information of the application being executed on the processor with the priority information notified from the exclusive operation request transmission processing unit, and if its own priority is higher, Explained that it will not stop.

Embodiment 4 FIG.
FIG. 9 shows a configuration example of the computer apparatus 10 according to the present embodiment.
In the computer apparatus 10 shown in FIG. 9, two processors are mounted.
In Embodiments 1 to 3 described above, one operating system operates on a plurality of processors. In Embodiment 4, a plurality of operating systems are operated on a plurality of processors (two in this case). The system (in this case, a total of two for each processor) operates.

  The computer apparatus 10 according to this embodiment includes a plurality of processors 900 and 901 (two in this case), operating systems 916 and 917 for each processor, storage units 902 and 903 for each processor, and shared storage shared between the processors. 926, a plurality of external devices 913 to 915 (three in this case), and a shared bus 912 for connecting the processor and the external devices.

The storage units 902 and 903 are connected to the processors 900 and 901, respectively, and store application groups 904 and 905 composed of a plurality of applications executed by the processors, and application information 906 and 907 that are information corresponding to each application. To do.
The processors 900 and 901 are arithmetic processing devices that execute applications dispatched (assigned) by the operating systems 916 and 917.
The application information 906 and 907 stores exclusive operation request information 908 and 909 that are information related to the exclusive operation request.
The exclusive operation request information 908 and 909 stores an exclusive operation request flag indicating whether or not there is an exclusive operation request.
Inter-processor interrupt mechanisms 910 and 911 exist in the processors 900 and 901, respectively, and transmit inter-processor interrupt signals to other processors and receive inter-processor interrupt signals from other processors.
The shared storage unit 926 is a storage unit shared between the processors 900 and 901.
The shared bus 912 is a bus that connects the processors 900 and 901 and the external devices 913 to 915.

The dispatch processing units 918 and 919 are processes for assigning an application selected from the application groups 904 and 905 to the processors 900 and 901.
The exclusive operation request transmission processing unit 920 is a process of operating the interprocessor interrupt mechanism 910 and transmitting an interprocessor interrupt signal to another processor.
The exclusive operation request reception processing unit 921 is a process that operates when the inter-processor interrupt mechanism 911 receives an inter-processor interrupt signal.
The timer 922 is a time measuring unit that operates based on a set timeout value and detects that a timeout has occurred.
The operating system 916 includes only a dispatch processing unit 918 and an exclusive operation request transmission processing unit 920, and the operating system 917 includes only a dispatch processing unit 919, an exclusive operation request reception processing unit 921, and a timer 922.
Therefore, the processor 900 that executes the operating system 916 can execute only the dispatch processing unit 918 and the exclusive operation request transmission processing unit 920, and the processor 901 that executes the operating system 917 includes the dispatch processing unit 919, the exclusive operation request, and the like. Only the reception processing unit 921 and the timer 922 can be executed.
In the configuration of FIG. 9, the operating system 916 is an example of a first operating system, and the operating system 917 is an example of a second operating system.

Next, the operation will be described.
The operation is the same as the operation shown in the first to third embodiments.
That is, when the processor 900 starts executing the application, the dispatch processing unit 918 and the exclusive operation request transmission processing unit 920 are executed as in the first to third embodiments, and the execution target application needs the exclusive operation. If it is an application, an inter-processor interrupt signal is transmitted to another processor 901.
Then, the processor 901 that has received the inter-processor interrupt signal from the processor 900 executes the exclusive operation request reception processing unit 921, and temporarily stops the access operation to the external devices 913 to 915 for a predetermined time.

  As described above, when an application that requests an exclusive operation is executed, the other processor operation is suspended in the computer so that the application is not affected by the operation of the other processor in the computer for a certain period of time. It is possible to operate exclusively in the computer.

  As described above, in the present embodiment, it has been described that a certain operating system has only the exclusive operation request transmission processing unit, and the other operating systems have only the exclusive operation request receiving unit.

Embodiment 5 FIG.
FIG. 10 shows a configuration example of the computer apparatus 10 according to the present embodiment.
In the computer apparatus 10 shown in FIG. 10, two processors are mounted.
In Embodiment 4 above, the processor on which the exclusive operation request transmission processing unit operates and the other processors are independent. However, in Embodiment 5, the exclusive operation request transmission processing unit and exclusive processing are performed on each processor. The operation request receiving unit operates.

  The computer apparatus 10 according to this embodiment includes a plurality of processors 1000 and 1001 (two in this case), operating systems 1016 and 1017 for each processor, storage units 1002 and 1003 for each processor, and shared storage shared between the processors. Unit 1026, a plurality of external devices 1013 to 1015 (three in this case), and a shared bus 1012 for connecting the processor and the external devices.

In this embodiment, a plurality of processors are classified into a plurality of groups, and a different operating system is executed for each group. Processors belonging to the same group execute a common operating system.
FIG. 10 shows an example in which there are two processors, each processor belongs to a different group, and each processor uses a different operating system. Instead of this, for example, 2n (n ≧ 2) processors are installed in the computer apparatus 10 and are classified into two groups of n machines, and the processors belonging to one group commonly use the operating system 1016. The processors belonging to the other group may use the operating system 1017 in common. Further, it may be classified into three or more groups and three or more operating systems may be prepared.

The storage units 1002 and 1003 are connected to the processors 1000 and 1001, respectively, and store application groups 1004 and 1005 composed of a plurality of applications executed by the processors, and application information 1006 and 1007, which are information corresponding to each application. To do.
The processors 1000 and 1001 are arithmetic processing devices that execute applications dispatched (assigned) by the operating systems 1016 and 1017.
The application information 1006 and 1007 store exclusive operation request information 1008 and 1009 that are information related to the exclusive operation request.
The exclusive operation request information 1008 and 1009 stores an exclusive operation request flag indicating whether or not there is an exclusive operation request.
The inter-processor interrupt mechanisms 1010 and 1011 are mechanisms that exist in the processors 1000 and 1001, respectively, that transmit inter-processor interrupt signals to other processors and receive inter-processor interrupt signals from other processors.
The shared storage unit 1026 is a storage unit shared between the processors 1000 and 1001.
The shared bus 1012 is a bus that connects the processors 1000 and 1001 and the external devices 1013 to 1015.
The dispatch processing units 1018 and 1019 allocate the applications selected from the application groups 1004 and 1005 to the processors 1000 and 1001.
Exclusive operation request transmission processing units 1020 and 1021 are processes for operating inter-processor interrupt mechanisms 1010 and 1011 to transmit inter-processor interrupt signals to other processors, respectively.
The exclusive operation request reception processing units 1022 and 1023 are processes that operate when the inter-processor interrupt mechanisms 1010 and 1011 respectively receive an inter-processor interrupt.
The timers 1024 and 1025 are time measuring means that operate based on a set timeout value and detect that a timeout occurs.

The operation is the same as that shown in the first to third embodiments.
As described above, in the fourth embodiment, only one processor executes the exclusive operation request transmission processing unit and only the other processor executes the exclusive operation request reception processing. In the embodiment, each processor executes an exclusive operation request transmission processing unit and an exclusive operation request reception process.

  As described above, when an application that requests an exclusive operation is executed, the other processor operation is suspended in the computer so that the application is not affected by the operation of the other processor in the computer for a certain period of time. It is possible to operate exclusively in the computer.

  As described above, in the present embodiment, it has been described that a plurality of operating systems operate on a plurality of processors, and each processor executes an exclusive operation request transmission processing unit and an exclusive operation request reception process.

Finally, a hardware configuration example of the computer apparatus 10 shown in the first to fifth embodiments will be described.
Note that the configuration described below is merely an example of the hardware configuration of the computer apparatus 10, and the hardware configuration of the computer apparatus 10 may be another configuration.

As described above, the computer apparatus 10 includes a processor device that executes a program, and, for example, via a shared bus, for example, a ROM (Read Only Memory), a RAM (Random Access Memory), a communication board, a display device, It is connected to a keyboard, mouse, magnetic disk device, etc., and controls these hardware devices.
Further, the processor device may be connected to an FDD (Flexible Disk Drive), a compact disk device (CDD), a printer device, and a scanner device. Further, instead of the magnetic disk device, a storage device such as a flash memory, an optical disk device, or a memory card (registered trademark) read / write device may be used.
At least some of these hardware devices are external devices that are shared resources.

The RAM is an example of a volatile memory. The ROM, FDD, CDD, and magnetic disk device storage media are examples of non-volatile memories. These are examples of the storage device.
A communication board, a keyboard, a mouse, a scanner device, an FDD, and the like are examples of an input device.
Communication boards, display devices, printer devices, and the like are examples of output devices.

  The communication board may be connected to, for example, a LAN (local area network), the Internet, a WAN (wide area network), or the like.

For example, the magnetic disk device stores a file group such as an operating system (OS), a window system, an application program group, and application information.
The programs of the application program group are executed by the processor using an operating system and a window system.

The RAM temporarily stores at least part of an operating system program and application programs to be executed by the processor.
The RAM stores various data necessary for processing by the processor.

The ROM stores a BIOS (Basic Input Output System) program, and the magnetic disk device stores a boot program.
When the computer apparatus 10 is activated, a BIOS program in the ROM and a boot program for the magnetic disk apparatus are executed, and an operating system is activated by the BIOS program and the boot program.

  The program group stores a program for executing the function described as “˜unit” in the description of the first to fifth embodiments. The program is read and executed by the processor.

In the description of Embodiments 1 to 5, the file group includes “determination of”, “calculation of”, “comparison of”, “execution of”, “update of”, and “setting of”. , Information, data, signal values, variable values, and parameters indicating the results of the processing described as “registration of”, “selection of”, etc. are stored as items of “˜file” and “˜database”. Has been.
The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory. Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the processor via a read / write circuit, and extracted, searched, referenced, compared, and calculated. Used for processor operations such as calculation, processing, editing, output, printing, and display.
Information, data, signal values, variable values, and parameters are stored in the main memory, registers, cache memory, and buffers during the processor operations of extraction, search, reference, comparison, operation, calculation, processing, editing, output, printing, and display. It is temporarily stored in a memory or the like.
The arrows in the flowcharts described in the first to fifth embodiments mainly indicate input / output of data and signals. The data and signal values are RAM memory, FDD flexible disk, CDD compact disk, magnetic Recording is performed on a recording medium such as a magnetic disk of the disk device, other optical disks, mini disks, and DVDs. Data and signals are transmitted on-line via buses, signal lines, cables, and other transmission media.

  In addition, what is described as “to part” in the description of the first to fifth embodiments may be “to step”, “to procedure”, and “to process”. Also, what is described as “˜unit” may be realized by firmware stored in the ROM. Alternatively, it may be implemented only by software, only hardware such as elements, devices, substrates, wirings, etc., or a combination of software and hardware, and further a combination of firmware. Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD. The program is read by the processor and executed by the processor.

FIG. 3 is a diagram illustrating a configuration example of a computer apparatus according to the first embodiment. FIG. 4 is a flowchart showing an operation example when the dispatch processing unit according to the first embodiment is executed. FIG. 6 is a flowchart showing an operation example at the time of execution of the exclusive operation request transmission processing unit according to the first embodiment. FIG. 6 is a flowchart showing an operation example when the exclusive operation request reception processing unit according to the first embodiment is executed. FIG. 9 is a flowchart showing an operation example at the time of execution of the exclusive operation request transmission processing unit according to the second embodiment. FIG. 9 is a flowchart showing an operation example at the time of execution of the exclusive operation request reception processing unit according to the second embodiment. FIG. 10 is a flowchart showing an operation example when an exclusive operation request transmission processing unit according to the third embodiment is executed. FIG. 10 is a flowchart showing an operation example at the time of execution of the exclusive operation request reception processing unit according to the third embodiment. FIG. 10 is a diagram illustrating a configuration example of a computer apparatus according to a fourth embodiment. FIG. 10 is a diagram illustrating a configuration example of a computer apparatus according to a fifth embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Computer apparatus, 100 Processor apparatus, 101 Processor apparatus, 102 Processor apparatus, 103 Interprocessor interrupt mechanism, 104 Interprocessor interrupt mechanism, 105 Interprocessor interrupt mechanism, 106 Operating system, 107 Dispatch processing part, 108 Exclusive operation request transmission process part 109, exclusive operation request reception processing unit, 110 timer, 111 storage unit, 112 application program group, 113 application program information, 114 shared storage unit, 115 exclusive operation request information, 116 shared bus, 117 external device, 118 external device, 119 External device, 120 external device, 900 processor device, 901 processor device, 902 storage unit, 903 storage unit, 904 application program Group, 905 application program group, 906 application program information, 907 application program information, 908 exclusive operation request information, 909 exclusive operation request information, 910 interprocessor interrupt mechanism, 911 interprocessor interrupt mechanism, 912 shared bus, 913 external device, 914 external device, 915 external device, 916 operating system, 917 operating system, 918 dispatch processing unit, 919 dispatch processing unit, 920 exclusive operation request transmission processing unit, 921 exclusive operation request reception processing unit, 922 timer, 926 shared storage unit, 1000 processor unit, 1001 processor unit, 1002 storage unit, 1003 storage unit, 1004 application program group, 10 5 Application program group, 1006 Application program information, 1007 Application program information, 1008 Exclusive operation request information, 1009 Exclusive operation request information, 1010 Interprocessor interrupt mechanism, 1011 Interprocessor interrupt mechanism, 1012 Shared bus, 1013 External device, 1014 External device 1015 External device 1016 Operating system 1017 Operating system 1018 Dispatch processing unit 1019 Dispatch processing unit 1020 Exclusive operation request transmission processing unit 1021 Exclusive operation request transmission processing unit 1022 Exclusive operation request reception processing unit 1023 Exclusive operation Request reception processing unit, 1024 timer, 1025 timer, 1026 shared storage unit.

Claims (9)

A computer device including a plurality of processor devices and a shared resource shared by the plurality of processor devices,
Each of the plurality of processor devices accesses the shared resource to execute an application program,
The execution start processor device which is going to start execution of the application program transmits an exclusive operation request signal requesting exclusive use of the shared resource to another processor device,
The computer apparatus, wherein the processor apparatus that has received the exclusive operation request signal from the execution start processor apparatus stops an access operation to the shared resource for a predetermined time. The computer device further includes:
A shared storage device shared by the plurality of processor devices is included,
The execution start processor device writes stop time information indicating a time during which another processor device stops an access operation to the shared resource to the shared storage device, and sends the exclusive operation request signal to the other processor device. Send
The processor device that has received the exclusive operation request signal from the execution start processor device reads the stop time information from the shared storage device, and performs an access operation to the shared resource for the time indicated in the stop time information. The computer apparatus according to claim 1, wherein the computer apparatus is stopped. The computer device further includes:
A shared storage device shared by the plurality of processor devices is included,
Each of the plurality of processor devices, while executing the application program, manages the priority of the application program being executed,
The execution start processor device writes priority information indicating the priority of an application program to start execution to the shared storage device, and transmits the exclusive operation request signal to another processor device.
The processor device that has received the exclusive operation request signal from the execution start processor device reads the priority information from the shared storage device, and the priority indicated in the priority information is an application program being executed by the own device. If the priority is higher than the priority of the application program, the access operation to the shared resource is stopped for a predetermined time, and the priority indicated in the priority information is the priority of the application program being executed by the own device. 3. The computer apparatus according to claim 1, wherein the access operation to the shared resource is not stopped when the value is not higher than 3. Each of the plurality of processor devices includes:
An exclusive operation request transmission process for transmitting the exclusive operation request signal and an exclusive operation request reception process for stopping an access operation to the shared resource for a predetermined time when the exclusive operation request signal is received are described. Running the operating system
If applicable to the execution start processor device, send the exclusive operation request signal to another processor device,
4. The computer according to claim 1, wherein when the exclusive operation request signal is received from the execution start processor device, the access operation to the shared resource is stopped for a predetermined time. apparatus. Each of the plurality of processor devices includes:
5. The computer apparatus according to claim 4, wherein a common operating system is executed. The plurality of processor devices are classified into a plurality of groups,
Each of the processor devices that fall into the same group
5. The computer apparatus according to claim 4, wherein a common operating system is executed. The processor device of any of the plurality of processor devices is
Executing a first operating system describing an exclusive operation request transmission process for transmitting the exclusive operation request signal;
The remaining processor devices of the plurality of processor devices are:
Executing a second operating system describing an exclusive operation request receiving process for stopping an access operation to the shared resource for a predetermined time when the exclusive operation request signal is received;
When the processor device that executes the first operating system corresponds to the execution start processor device, the processor device that transmits the exclusive operation request signal to the processor device that executes the second operating system,
When the processor device executing the second operating system receives the exclusive operation request signal from the processor device executing the first operating system, the processor device performs an access operation to the shared resource for a predetermined time. The computer apparatus according to claim 1, wherein the computer apparatus is stopped.   The execution start processor device determines whether or not exclusive use of the shared resource is necessary for execution of an application program to start execution, and when exclusive use of the shared resource is necessary, The computer apparatus according to claim 1, wherein the exclusive operation request signal is transmitted to a processor apparatus. A plurality of processor devices and shared resources shared by the plurality of processor devices are included, and each of the plurality of processor devices is a computer device that accesses the shared resources and executes an application program.
Exclusive operation request transmission processing for transmitting an exclusive operation request signal for requesting exclusive use of the shared resource to another processor device to an execution start processor device that is to start execution of the application program;
A program that causes a processor device that has received the exclusive operation request signal from the execution start processor device to execute an exclusive operation request reception process for stopping an access operation to the shared resource for a predetermined time.

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