JP2009266871A - Silicon carbide semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: when a source region of a high-concentration impurity is formed by implanting phosphorus into a source region, only a surface of the source region undergoes enhanced oxidation to cause formation of a step between surfaces of a well region and of the source region, resulting in an increase in channel resistance. <P>SOLUTION: An insulating gate semiconductor device is made of silicon carbide, and a sacrificial layer 14 having an equal concentration profile of phosphorus is formed at least on the well region 3 and the surface of the source region 4. Consequently, when a gate insulating film is formed, enhanced oxidation is uniformly caused on the surfaces of the well region 3 and of source region 4, so that no step is formed between the surface of the well region 3 and the surface of the source region 4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a silicon carbide semiconductor substrate, and more particularly to a method for manufacturing a silicon carbide semiconductor power device used for a large current.

  A power device is a semiconductor element that allows a large current to flow, and is desired to have a high breakdown voltage and low loss. Conventionally, power devices using silicon (Si) semiconductors have been mainstream, but in recent years, power devices using silicon carbide (SiC) semiconductors have attracted attention and are being developed. Since a silicon carbide semiconductor has a dielectric breakdown electric field that is an order of magnitude higher than that of silicon, a reverse breakdown voltage can be maintained even if a depletion layer of a PN junction or a Schottky junction is thinned. Therefore, since the device thickness can be reduced and the doping concentration can be increased, silicon carbide is expected to be a material for power devices with low on-resistance, high breakdown voltage, and low loss.

  FIG. 17 is a cross-sectional view showing a structure of a double injection MOSFET as an example of a conventional silicon carbide semiconductor device. As shown in FIG. 17, in a conventional silicon carbide semiconductor device, drift layer 102 having a higher resistance than that of substrate 101 is epitaxially grown on substrate 101 made of low resistance silicon carbide. A p-type well region 103 is formed in the surface layer of the drift layer 102 by selective ion implantation, and a high-concentration n-type source region 105 and a region surrounded by the source region 105 are positioned therein by ion implantation. P-type p + contact region 104 is provided.

  A gate insulating film 106 made of a thermal oxide film is formed from above the drift layer 102 sandwiched between the two well regions 103 to the end of the source region 105 in the two well regions 103. A gate electrode 109 is formed on the gate insulating film 106. A source electrode 108 that is in ohmic contact with the contact region 104 is provided on the end of the source region 105 located on both ends of the p + contact region 104. Furthermore, a drain electrode 107 that is in ohmic contact with the substrate 101 is provided on the entire back surface of the substrate 101.

  An interlayer insulating film 110 is deposited on the drift layer 102, the p-type well region 103, the p + contact region 104 and the source region 105. The interlayer insulating film 110 is provided with contact holes that reach the source electrode 108 and the gate electrode 109, respectively. The interlayer insulating film 110 is made of aluminum having a thickness of 2 μm and fills the contact holes. A wiring 111 and a gate electrode upper wiring 112 are provided. Such a structure is disclosed in, for example, Patent Document 1.

The breakdown of the on-resistance of such a power MOSFET is that the source contact resistance of the source electrode and the source region, the source region resistance, the channel resistance of the channel formed under the gate electrode, and the current are in the JFET region (between adjacent well regions). JFET resistance when flowing through the substrate, drift resistance when current flows through the drift layer below the JFET, substrate resistance when current flows through the substrate, and drain contact resistance. Various developments have been made with the aim of further reducing the on-resistance, and as one of them, the source contact resistance and the source resistance are reduced by increasing the concentration of the source region.
Japanese Patent No. 3759145

The inventors of the present application investigated the contact resistance of the source region and the dependency on the concentration of the source region and the implanted species. The result is shown in FIG. Conventionally, nitrogen ion implantation has been used to form the source region, but it has been found that even if the implantation dose is increased to 1 × 10 ²⁰ cm ⁻³ or more, the contact resistance does not decrease but rises. . However, in the case of phosphorus ion implantation, the contact resistance can be reduced with increasing doping concentration even in the region of 1 × 10 ²⁰ cm ⁻³ or more. Furthermore, it was found that even when the concentration was increased to 4 × 10 ²⁰ cm ⁻³ or more, the contact resistance uniformly decreased, and the contact resistance could be reduced by an order of magnitude compared to nitrogen implantation. Non-patent document 1 also reports that there is a limit in reducing contact resistance even if the doping concentration of nitrogen is increased, which is caused by the low solid solution limit of nitrogen in silicon carbide.

  However, the inventors of the present application have found that when the source region formed by phosphorous implantation is thermally oxidized, the oxidation rate is about twice that of the non-implanted substrate, the nitrogen implanted region, and the aluminum implanted region. FIG. 13 shows the result of evaluating the thickness of the surface thermal oxide film with a spectroscopic ellipsometer when silicon carbide is thermally oxidized in a dry oxygen atmosphere at 1200 ° C. for 3 hours. Whereas the non-implanted n-type 4H—SiC silicon carbide substrate, the nitrogen-implanted surface of the non-doped silicon carbide epitaxial layer, and the aluminum-implanted surface have a constant film thickness of about 80 nm regardless of the impurity concentration. In the phosphorus implantation layer, the surface oxide film thickness increases depending on the impurity concentration.

For example, even when the surface impurity concentration is 1 × 10 ²⁰ cm ⁻³ , the oxide film thickness is about 100 nm and is thicker than that of the nitrogen implantation region or the aluminum implantation region, but as the impurity concentration increases, the film thickness further increases. At × 10 ²⁰ cm ⁻³ , the thickness is about 160 nm, which is twice the thickness of the nitrogen implantation region and the aluminum implantation region.

  Therefore, when a double injection type MOSFET is manufactured by applying phosphorus implantation to the source region formation, the following problems occur. Hereinafter, description will be given with reference to the drawings. 14 to 16 are cross-sectional process diagrams of the double-injection type MOSFET when the source region is formed by implanting phosphorus.

  First, the drift layer 2 made of silicon carbide containing impurities at a lower concentration than the substrate is epitaxially grown on the silicon carbide substrate 1 (FIG. 14A).

  Next, an unillustrated implantation mask (for example, made of SiO 2 or the like) is formed on the surface, the substrate temperature is kept at a high temperature of about 500 ° C., and aluminum is implanted as a p-type impurity, thereby forming the P-type well region 3 on the surface. (FIG. 14B).

Similarly, an implantation mask (not shown) (not shown) is formed on the surface, phosphorus is implanted as an n-type impurity while maintaining the substrate temperature at a high temperature of about 500 ° C., and the n-type source region 4 is formed. It is formed on a part of the surface in the well region. In order to obtain a low contact resistance, the impurity concentration in the phosphorus implantation region is preferably higher than 1 × 10 ²⁰ cm ⁻³ , more preferably 4 × 10 ²⁰ cm ⁻³ . The implantation conditions are, for example, energy 30 keV, dose amount 1.1 × 10 ¹⁵ cm ⁻² , energy 80 keV, dose amount 2.2 × 10 ¹⁵ cm ⁻² , energy 180 keV, dose amount 5.0 × 10 ¹⁵ cm ^−2. For example, an implantation profile as shown in FIG. 7 is obtained, and an average concentration of 4 × 10 ²⁰ cm ⁻³ can be realized in the source region (FIG. 14C).

Next, an implantation mask (not shown) (for example, made of SiO) is formed on the surface, the substrate temperature is kept at a high temperature of about 500 ° C., and aluminum is implanted as a p-type impurity, leading to the well region 3. The contact region 5 is formed in the source region. The contact region 5 has a higher concentration than the well region 3 in order to achieve ohmic contact with the source electrode. For example, it is about 1 × 10 ²⁰ cm ⁻³ . In order to prevent the p-type impurity in the contact region from being compensated by the n-type impurity region in the source region and reducing the substantial p-type impurity concentration, the n-type source region and the p-type contact region do not overlap as much as possible. Thus, an implantation mask is formed (FIG. 14D).

  After removing the implantation mask, activation annealing is performed at a high temperature of about 1700 ° C. in an inert gas such as argon.

Thereafter, the gate insulating film 6 is formed on the surface by a known thermal oxidation method (for example, heating to 1200 ° C. in dry oxygen). The phosphorus-implanted source region 4 has a higher thermal oxidation rate than the drift region 2, the well region 3 into which aluminum is implanted, and the contact region 5, and the gate insulating film 6 a on the surface of the source region has a gate insulation in the region other than the source region. The film thickness is about twice as large as that of the film 6b. Therefore, there is a step on the surface between the source region 4 and other regions. If SiC having a thickness t is thermally oxidized to form a thermal oxide film (SiO ₂ ) having a thickness t ′, the relationship between t and t ′ is obtained as follows. The density of _SiC is d _SiC and the density of _{SiO 2} is d _{SiO 2} . If the molecular weights are M _sic and M _{sio 2} , the number of silicon atoms contained in SiC per unit area of thickness t and the number of silicon atoms contained in SiO 2 of thickness t ′ after thermal oxidation are as follows: Since they are equal, the following equation holds.

Here, if d _SiC = 3.2, d _SiO2 = 2.6, M _sic = 40.1, and M _sio2 = 60.1, t = 0.5 × t ′. That is, SiC having a thickness t of about 50% of the thickness t ′ of the thermal oxide film is consumed. For example, when a gate oxide film having a thickness of 80 nm is formed, SiC having a depth of about 40 nm from the surface is consumed. When a gate oxide film having a thickness of 160 nm is formed, SiC having a depth of about 80 nm from the surface is consumed. Therefore, the step T between the phosphorus implantation region and the other region is 80-40 = 40 nm. When generalized, a step of 1/2 of the difference in thickness of the oxide film thickness is formed.

  At this time, silicon carbide of about 50% of the thickness of the thermal oxide film is consumed from the difference between the density of the thermal oxide film and the density of silicon carbide to become a thermal oxide film. That is, the amount of silicon carbide consumed in the source region 4 is larger than that in the other regions, and therefore the surface of the source region is lower than that in the other regions, and the source region has a recessed shape. A thermal oxide film 7 is also formed on the back surface of the substrate 1 (FIG. 14E).

  Next, for example, polycrystalline silicon containing n-type impurities is deposited on the gate insulating film 6, a resist mask (not shown) is formed, and patterning is performed by dry etching to form the gate electrode 8 (FIG. 15A). ).

  Further, an interlayer insulating film 9 is formed on the gate electrode 8. The interlayer insulating film 9 is, for example, silicon oxide (FIG. 15B).

  In order to form a source electrode, a contact hole 10 connected to the source region 4 and the contact region 5 is formed in the formed interlayer insulating film 9 by dry etching (FIG. 15C).

  In order to form the source electrode, for example, nickel is deposited on the surface having a thickness of 100 nm, and the source electrode 11 is formed by patterning. Thereafter, heat treatment is performed at about 950 ° C. in an inert gas atmosphere such as nitrogen in order to obtain ohmic characteristics. The substrate back electrode has a three-layer structure of titanium 12a, nickel 12b, and silver 12c (FIG. 16A).

  The double injection MOSFET thus produced has the following problems.

  When a gate voltage is applied to the gate electrode, a channel through which carriers flow is formed on the surface of the well region sandwiched between the source region and the drain region.

  Electrons injected from the source electrode travel through this channel through the source region. However, a step is formed between the source region and the well region due to gate oxidation, and carriers are subjected to geometrical scattering here, so that the channel mobility is lowered. That is, the channel resistance is increased and the on-resistance of the MOSFET is increased.

  This step T does not disappear in the depth region where the SiC surface is thermally oxidized as long as a region where phosphorus is implanted and a region where phosphorus is not implanted are mixed in the wafer surface.

  In view of the above problems, the present invention forms a source region by high-concentration phosphorus implantation and suppresses the contact resistance of the source electrode and the sheet resistance of the source region, while reducing the step on the channel surface and reducing the channel mobility. An object is to provide a silicon MOSFET.

The silicon carbide semiconductor device of the present invention is
A semiconductor substrate;
A drift layer made of silicon carbide containing impurities at a lower concentration than the substrate formed on the semiconductor substrate;
A p-type well region formed on the surface of the drift layer;
An n-type source region formed in the well region;
A gate insulating film formed on the surface so as to straddle the well region and the source region;
A gate electrode formed on the gate insulating film;
A source electrode formed on at least a part of the source region;
A semiconductor device comprising silicon carbide containing
The concentration of phosphorus on the surface of the source region is 1 × 10 ²⁰ cm ⁻³ or more,
The carbonization characterized in that the difference in the substrate thickness direction between the interface between the well region and the gate insulating film and the interface between the source region and the gate insulating film is less than ½ of the thickness of the gate insulating film. It is a silicon semiconductor device.

  In a preferred embodiment, the well region surface preferably contains phosphorus.

  Since the source region is formed by injecting phosphorus, the solid solution limit in silicon carbide is higher than that of nitrogen, and a source region with a high impurity concentration can be realized, thereby reducing the source region contact resistance and sheet resistance. it can.

The concentration of phosphorus in the source region is more preferably 4 × 10 ²⁰ cm ⁻³ or more.
In the case of phosphorus implantation, the contact resistance of the source region uniformly decreases with an increase in the doping concentration of the source region even at such high concentration implantation.

The method for manufacturing the silicon carbide semiconductor device is as follows:
A step (a) of epitaxially growing a drift layer made of silicon carbide containing impurities at a lower concentration than the substrate on a silicon carbide substrate;
(B) forming a p-type well region by ion-implanting p-type impurities into the drift layer surface;
(C) forming a source region by ion-implanting phosphorus into the well region;
A step (d) of forming a sacrificial layer containing phosphorus having a substantially uniform concentration profile over the entire surface of the drift layer over the in-plane direction;
An annealing step (e) for activating the p-type impurity and the phosphorus implanted after the steps (b), (c) and (d);
(F) forming a gate insulating film by thermally oxidizing at least the surface layer including the sacrificial layer after the activation annealing;
And a step (g) of forming a source electrode in at least a part of the source region.

  Here, the sacrificial layer is a SiC surface layer in the depth range consumed by gate oxidation, and the phosphorus concentration difference is kept within a certain range within the surface in the sacrificial layer.

  By doing so, the speed-up oxidation at the time of thermal oxidation is uniformly performed in the plane, so that there is no step between the source region and the well region.

  In a preferred embodiment, the ion implantation of the source region is a multi-stage implantation, and the concentration peak position on the surface side with respect to the most drift layer by the ion implantation of the source region is deeper than the formation position of the sacrificial layer. It is preferable.

  By doing so, it is possible to prevent the phosphorus concentration in the sacrificial layer on the surface of the source region from significantly increasing due to the profile of the source region implantation.

  In a preferred embodiment, the step (g) is a step of depositing metal on at least a part of the surface of the source region and performing heat treatment to form a metal silicide to be a source electrode. preferable.

In a preferred embodiment, the concentration of phosphorus in the sacrificial layer is 1 × 10 ¹⁹ cm ⁻³ or more within the depth range of the silicon carbide surface layer consumed by thermal oxidation in the step (f). It is preferable.

The method for manufacturing the silicon carbide semiconductor device is as follows:
A step (h) of epitaxially growing a drift layer made of silicon carbide containing impurities at a lower concentration than the substrate on the silicon carbide substrate;
(I) forming a p-type well region by ion-implanting p-type impurities into the drift layer surface;
A step (j) of forming a source region by ion implantation of phosphorus into the well region; and an annealing step (k) for activating the p-type impurity and the phosphorus implanted after the steps (i) and (j). When,
Forming a gate insulating film by thermal oxidation after the activation annealing (l);
A step (m) of forming a source electrode in at least a part of the source region, and the implantation concentration of phosphorus in the step (j) is the same as that of the silicon carbide surface layer consumed by thermal oxidation in the step (l). Within the depth range, it is preferably 1 × 10 ¹⁹ cm ⁻³ or less.

  With such a concentration, the rate of accelerated oxidation of the sacrificial layer is small, and even if an in-plane distribution occurs in the phosphorus concentration profile of the sacrificial layer, the step between the source region surface and the well region surface can be kept small.

  In a preferred embodiment, the step (m) is a step of depositing metal on at least a part of the surface of the source region and performing heat treatment to form a metal silicide to serve as a source electrode. preferable.

  According to the present invention, since the source region is formed by phosphorus implantation, the concentration of the source region can be increased as compared with nitrogen implantation, and the source contact resistance can be reduced. In addition, since the phosphorous injection layer is present only on the surface of the source region in the related art, the oxidation rate is significantly increased only in the source region. As a result, there is a step between the surface of the well region and the surface of the source region. Since a sacrificial layer having a uniform phosphorus concentration profile within the surface is formed on the entire surface including the well region and the source region up to the depth consumed by gate oxidation, uniform accelerated oxidation occurs over the entire wafer surface. The step difference between the source region surface and the well region surface can be reduced.

(First embodiment)
Hereinafter, a double injection type MOSFET which is an example of a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the drawings. 1 to 3 are sectional views showing a process flow of an inversion type double injection type MOSFET according to an embodiment of the present invention.

First, in the step shown in FIG. 1A, a drift layer 2 made of silicon carbide is epitaxially grown on a silicon carbide substrate 1. Silicon carbide substrate 1 has a main surface that is turned off, for example, by 8 ° from the (0001) plane in the <11-20> direction, and an n-type doping concentration of 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁹ cm. ^-3 . Next, thermal CVD is performed using, for example, silane (SiH ₄ ) and propane (C ₃ H ₈ ) as source gases, hydrogen (H ₂ ) as a carrier gas, and nitrogen (N ₂ ) gas as a dopant gas. Thus, drift layer 2 having a lower doping concentration than silicon carbide substrate 1 is epitaxially grown. For example, if a MOSFET with a withstand voltage of 600 V is manufactured, it is desirable that the doping concentration of the semiconductor layer 2 is 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ and the thickness is 10 μm or more.

Next, in the step shown in FIG. 1B, an ion implantation mask (not shown) is formed on the surface of the drift layer 2, and the well region 3 is formed by ion implantation. For the implantation mask, for example, silicon oxide is deposited by CVD, and patterning is performed by photolithography and dry etching. In order to reduce implantation defects, a p-type well region 3 is formed on the semiconductor layer 2 by ion implantation of aluminum or boron while maintaining the substrate at a high temperature of, for example, 500 ° C. or higher. The doping concentration of the well region 3 is usually in the range from about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and the depth is about 1 μm so as not to pinch off. Thereafter, the implantation mask is removed with hydrofluoric acid.

Further, in the step shown in FIG. 1C, an ion implantation mask (not shown) is formed on the surface of the drift layer 2, and the source region 3 is formed by ion implantation. For the implantation mask, for example, silicon oxide is deposited by CVD, and patterning is performed by photolithography and dry etching. In order to reduce implantation defects, the source region 4 is formed inside the well region 3 by implanting phosphorus ions while maintaining the substrate at a high temperature of, for example, 500 ° C. or higher. The doping concentration of the source region 4 is usually in the range from about 5 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the depth is about 0.3 μm. At this time, by adjusting the implantation conditions, the sacrificial layer 14 is formed on the surface of the source region 4 so that the phosphorus concentration is kept below a certain concentration.

If the phosphorus concentration in the sacrificial layer is set to a certain concentration or less, formation of a step can be suppressed. According to the phosphorus implantation data shown in FIG. 13, the thickness of the thermal oxide film on the surface of the implantation region decreases as the phosphorus implantation concentration decreases. If the data is extrapolated, it can be inferred that the concentration should be about 5 × 10 ¹⁹ cm ⁻³ or less in order to make the film thickness comparable to that of the aluminum implantation region, nitrogen implantation region, or bare substrate without implantation. More preferably, if the concentration is 1 × 10 ¹⁹ cm ⁻³ or less, the film thickness can be the same as that of an aluminum implantation region, a nitrogen implantation region, or a bare substrate without implantation. Therefore, the phosphorus concentration in the sacrificial layer may be set to 1 × 10 ¹⁹ cm ⁻³ or less. The thickness of the sacrificial layer is about 50% or more of the thickness of the gate oxide film to be formed in a later step. This is because the thickness of the silicon carbide consumed in forming the thermal oxide film is about 50% of the thickness of the thermal oxide film because of the relationship between the density of the thermal oxide film and the density of silicon carbide. In this embodiment, since the thickness of the gate insulating film is set to 80 nm, the thickness of the sacrificial layer is about 40 nm.

However, in order to reduce the contact resistance of the source electrode, the phosphorus implantation concentration at the interface between the source electrode and the source region is preferably 1 × 10 ²⁰ cm ⁻³ or more, more preferably 4 × 10 ²⁰ cm ^{−. 3} or more.

  As an n-type ohmic electrode of silicon carbide, nickel is generally deposited and then heat-treated at about 900 ° C. to form nickel silicide. When heat treatment is performed, nickel reacts with silicon carbide and enters silicon carbide. Therefore, the inventor has found that the interface between the electrode and silicon carbide is deeper than the initial silicon carbide surface and is about 75% to 150% of the initial nickel thickness.

In this embodiment mode, nickel having a thickness of 100 nm is deposited as a source electrode, and heat treatment at 950 ° C. is performed. Accordingly, the interface between the source electrode and the silicon carbide is formed to a depth of 75 nm to 150 nm from the surface of the silicon carbide formed by the thermal oxidation. That is, it is necessary that the implantation concentration of phosphorus be 1 × 10 ²⁰ cm ⁻³ or more in this range from 115 nm to 190 nm from the silicon carbide surface at the beginning of implantation.

The phosphorus implantation concentration profile as described above can be realized by setting the phosphorus implantation conditions to, for example, an energy of 240 keV and a dose of 1.0 × 10 ¹⁶ cm ⁻² . FIG. 8 shows an injection profile under this injection condition. In the sacrificial layer having a depth of 40 nm from the surface as shown in FIG. 8, the concentration of phosphorus is 1 × 10 ¹⁹ cm ⁻³ or less, and the concentration of phosphorus at a depth of 115 nm to 190 nm at which an electrode can penetrate and become an interface is 1 × 10 9. It can be set to ²⁰ cm ⁻³ or more.

  After the implantation, the implantation mask is removed with hydrofluoric acid.

Further, in the step shown in FIG. 1D, an ion implantation mask (not shown) is formed on the surface of the drift layer 2, and the contact region 5 is formed by ion implantation. For the implantation mask, for example, silicon oxide is deposited by CVD, and patterning is performed by photolithography and dry etching. In order to reduce implantation defects, p-type contact regions 5 are formed on the semiconductor layer 2 by ion implantation of aluminum or boron while maintaining the substrate at a high temperature of, for example, 500 ° C. or higher. The doping concentration of the contact region 5 is usually in the range from about 5 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the depth is about 0.3 μm. Thereafter, the implantation mask is removed with hydrofluoric acid. A sacrificial layer having a phosphorus concentration of 1 × 10 ¹⁹ cm ⁻³ or less is also formed on the surface of the contact region. Through the steps shown in FIGS. 1B to 1D, the concentration of phosphorus becomes 1 × 10 ¹⁹ cm ⁻³ or less over the entire surface of the drift region 2, the well region surface 3, the source region 4 surface, and the contact region 5 surface. A sacrificial layer 14 is formed.

  Thereafter, activation annealing is performed at 1700 ° C. for 30 minutes in an inert gas atmosphere such as argon.

Next, a gate oxide film 6 is formed on the surface of the drift layer 2 in the step shown in FIG. The thickness of the gate oxide film is, for example, about 80 nm. The wafer is held in a quartz tube, and dry oxygen is introduced at a flow rate of 2.5 SLM (l / s) while maintaining the temperature in the quartz tube at 1200 ° C., and thermal oxidation is performed for 3 hours. Thereby, a silicon oxide film having a thickness of about 80 nm is grown on the surface of the semiconductor layer 2 as the gate insulating film 6. At this time, about 40 nm of the surface of the drift layer sandwiched between the well region 3, the source region 4, the contact region 5, and the two adjacent well regions 3 is consumed to form a gate oxide film. The region from the surface to a depth of 40 nm is the sacrificial layer 14, and the surface of the well region 3, the source region 4, the contact region 5 and the drift layer 2 contains phosphorus only in a concentration of 1 × 10 ¹⁹ cm ^−3. Therefore, the thermal oxide films on the surfaces thereof have substantially the same thickness, so that the step between the surface of the source region 4 and the surface of the well region 3 can be reduced.

Next, the gate electrode 8 is formed in the step shown in FIG. As a material for the gate electrode 8, polycrystalline silicon having heat resistance and conductivity is preferable. The melting point of polycrystalline silicon is 1420 ° C., which is sufficiently higher than the heat treatment temperature of the electrode. Polycrystalline silicon is deposited by a low pressure CVD method. Silane and phosphine are used as the source gas, and maintained at a growth temperature of 550 ° C. for 8 hours at a pressure of 95 Pa. For example, polycrystalline silicon having an n-type doping concentration of about 7 × 10 ²⁰ cm ⁻³ and a thickness of 500 nm is formed as a gate oxide film. 6 is deposited. Patterning is performed by photolithography and dry etching.

  Next, an interlayer insulating film 9 is deposited on the surfaces of the gate oxide film 6 and the gate electrode 8 in the step shown in FIG. As the interlayer insulating film 9, silicon oxide having a high dielectric breakdown voltage and easy deposition is formed by, for example, atmospheric pressure CVD. The thickness is 1 μm, for example.

Next, in the step shown in FIG. 2 (d), a contact hole 10 reaching the contact region 5 and the source region 4 on the surface of the drift layer 2 is opened in the interlayer insulating film 9. For the opening of the contact hole 10, known photolithography and dry etching are used. For dry etching, for example, RIE using CHF ₃ or CF ₄ may be performed. At this time, not only the interlayer insulating film but also the underlying gate oxide film is removed, and the silicon carbide surface of the drift layer 2 is exposed.

  Next, in the step shown in FIG. 3, the source electrode 11 is formed so as to fill the contact hole 10. As the source electrode 11, for example, nickel is deposited with a thickness of 100 nm by a vacuum evaporation method or a sputtering method. Then, after patterning by well-known photolithography and etching, heat treatment is performed, and nickel and silicon carbide are reacted to form nickel silicide. For example, the heat treatment is performed at 950 ° C. for 1 minute in an inert atmosphere such as nitrogen. By this heat treatment, nickel reacts with silicon carbide and enters the silicon carbide. The penetration depth from the surface is about 75% to 150% of the initial nickel thickness. That is, it penetrates about 75 to 150 nm. Accordingly, a sacrificial layer having a low phosphorus concentration is formed in FIG. 1C, and even if there is a low implantation concentration region on the surface of the source region 4 after gate oxidation, the source electrode penetrates into the high implantation concentration region. It is possible to make it.

  Subsequently, the back electrode 12 is formed. The back electrode 12 is a laminated film in which titanium is deposited as a first electrode 12a in contact with the back surface of the substrate at 0.3 μm, nickel is deposited as a second electrode 12b at 1 μm, and silver is deposited as a third electrode 12c at 1 μm. Heat treatment is performed at 950 ° C. for 1 minute.

  Finally, the upper wiring 13 for connecting the source electrode 11 is formed on the surface. The upper wiring is formed by depositing aluminum with a thickness of 3 μm by a vacuum vapor deposition method or a sputtering method, and patterning by well-known photolithography and etching.

In the silicon carbide double-implanted MOSFET manufactured in this way, the source region is formed using phosphorus implantation. Therefore, a source region having a higher concentration can be formed compared to nitrogen implantation, and the source contact resistance can be reduced. It can be reduced to about 1 × 10 ⁻⁵ Ω · cm ² . Further, there is almost no step in the substrate thickness direction at the interface between the source region 4 and the gate insulating film and the interface between the well region 3 and the gate insulating film, and at least the step is less than ½ of the thickness of the gate insulating film. Therefore, the channel resistance does not increase.

In this embodiment, nickel is deposited as a source electrode and an ohmic electrode is formed by performing heat treatment at 950 ° C. However, when the concentration of the surface of the source region is set to a high concentration, for example, 4 × 10 ²⁰ cm ⁻³ or more. Although the contact resistance is high, ohmic contact can be obtained without heat treatment.

  In this embodiment, an example of a vertical MOSFET has been described. However, the present invention can also be applied to a lateral MOSFET having source and drain regions on the surface. That is, as long as the source and drain regions are formed by ion implantation of phosphorus, a similar problem occurs even in the lateral MOSFET, and this problem can be solved.

(Second Embodiment)
Hereinafter, a double injection type MOSFET which is an example of a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the drawings. 4 to 6 are sectional views showing a process flow of the inversion type double injection MOSFET according to the embodiment of the present invention.

In the first embodiment, by adjusting the energy of source implantation, phosphorus is not implanted into the surface of the source region 4, so that phosphorus is implanted into the surfaces of the well region 3, the source region 4, the contact region 5, and the drift region 2. A sacrificial layer having a concentration of 1 × 10 ¹⁹ cm ⁻³ or less was formed.

  In the present embodiment, conversely, phosphorus is injected into the surface of the well region 3, the source region 4, the contact region 5, and the drift region 2, so that the phosphorus concentration is substantially uniform in the plane. A layer is formed.

First, in the step shown in FIG. 4A, a drift layer 2 also made of silicon carbide is epitaxially grown on the silicon carbide substrate 1. Silicon carbide substrate 1 has a main surface that is turned off, for example, by 8 ° from the (0001) plane in the <11-20> direction, and an n-type doping concentration of 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁹ cm. ^-3 . Next, thermal CVD is performed using, for example, silane (SiH ₄ ) and propane (C ₃ H ₈ ) as source gases, hydrogen (H ₂ ) as a carrier gas, and nitrogen (N ₂ ) gas as a dopant gas. Thus, drift layer 2 having a lower doping concentration than silicon carbide substrate 1 is epitaxially grown. For example, if a MOSFET with a withstand voltage of 600 V is manufactured, it is desirable that the doping concentration of the semiconductor layer 2 is 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ and the thickness is 10 μm or more.

Next, in the step shown in FIG. 4B, an ion implantation mask (not shown) is formed on the surface of the drift layer 2, and the well region 3 is formed by ion implantation. For the implantation mask, for example, silicon oxide is deposited by CVD, and patterning is performed by photolithography and dry etching. In order to reduce implantation defects, a p-type well region 3 is formed on the semiconductor layer 2 by ion implantation of aluminum or boron while maintaining the substrate at a high temperature of, for example, 500 ° C. or higher. The doping concentration of the well region 3 is usually in the range from about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and the depth is about 1 μm so as not to pinch off. Thereafter, the implantation mask is removed with hydrofluoric acid.

4C, an ion implantation mask (not shown) is formed on the surface of the drift layer 2, and the source region 4 is formed by ion implantation. For the implantation mask, for example, silicon oxide is deposited by CVD, and patterning is performed by photolithography and dry etching. In order to reduce implantation defects, the source region 4 is formed inside the well region 3 by maintaining the substrate at a high temperature of, for example, 500 ° C. or more and implanting phosphorus ions in multiple stages. The implantation conditions are, for example, two-stage implantation with an energy of 80 keV, a dose of 2.5 × 10 ¹⁵ cm ⁻² , an energy of 180 keV, and a dose of 6.0 × 10 ¹⁵ cm ⁻² . FIG. 9 shows an injection profile under this condition.

  Thereafter, the implantation mask is removed with hydrofluoric acid.

4D, an ion implantation mask (not shown) is formed on the surface of the drift layer 2, and the contact region 5 is formed by ion implantation. For the implantation mask, for example, silicon oxide is deposited by CVD, and patterning is performed by photolithography and dry etching. In order to reduce implantation defects, p-type contact regions 5 are formed on the semiconductor layer 2 by ion implantation of aluminum or boron while maintaining the substrate at a high temperature of, for example, 500 ° C. or higher. The doping concentration of the contact region 5 is usually in the range from about 5 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the depth is about 0.3 μm. Thereafter, the implantation mask is removed with hydrofluoric acid.

Subsequently, in the step shown in FIG. 5A, phosphorus is uniformly implanted over the surface of the drift region 2, the surface of the well region 3, the surface of the source region 4, and the surface of the contact region 5. This process is called sacrificial layer implantation. The sacrificial layer implantation uniformly forms in-plane phosphorus into the layer consumed by surface gate oxidation. For example, the energy is 30 keV and the dose is 6.0 × 10 ¹⁵ cm ⁻² . FIG. 10 shows an implantation profile of phosphorus by this sacrificial layer implantation. The implantation profile of the source region is a superposition of the previous source implantation and sacrificial layer implantation. FIG. 11 shows a phosphorus implantation profile of the source region in this embodiment. In the case of a sacrificial layer formed by implanting phosphorus, since the implantation profile has a tail, thermal oxidation until the phosphorus on the surface of the well region is completely removed exposes a high concentration of phosphorus by source implantation only on the surface of the source region. Since accelerated oxidation may occur, it is better to leave some phosphorus in the sacrificial layer. In this case, the well region surface contains phosphorus.

As a result, a sacrificial layer 14 having a substantially uniform concentration profile of phosphorus concentration in the in-plane direction is formed on the surface. The implantation conditions are, for example, an implantation energy of 30 keV and a dose of about 3 × 10 ¹³ cm ⁻² , for example. According to this implantation condition, a profile with a peak depth of about 40 nm and a phosphorus peak concentration of about 1 × 10 ¹⁹ cm ⁻³ is obtained. Thereafter, activation annealing is performed at 1700 ° C. for 30 minutes in an inert gas atmosphere such as argon.

  Next, a gate oxide film 6 is formed on the surface of the drift layer 2 in the step shown in FIG. The thickness of the gate oxide film is, for example, about 80 nm. The wafer is held in a quartz tube, and dry oxygen is introduced at a flow rate of 2.5 SLM (l / s) while maintaining the temperature in the quartz tube at 1200 ° C., and thermal oxidation is performed for 3 hours. As a result, a silicon oxide film having a thickness of about 100 nm is grown as the gate insulating film 6 on the surface of the semiconductor layer 2. At this time, about 40 nm of the surface of the drift layer sandwiched between the well region 3, the source region 4, the contact region 5, and the two adjacent well regions 3 is consumed to form a gate oxide film. The region from this surface to a depth of 40 nm is the sacrificial layer 14, and since the surface of the well region 3, the source region 4, the contact region 5 and the drift layer 2 contains phosphorus at the same level, Thus, the thermal oxide film on the surface of the surface has substantially the same thickness, so that the step between the surface of the source region 4 and the surface of the well region 3 can be reduced.

Next, the gate electrode 8 is formed in the step shown in FIG. As a material for the gate electrode 8, polycrystalline silicon having heat resistance and conductivity is preferable. The melting point of polycrystalline silicon is 1420 ° C., which is sufficiently higher than the heat treatment temperature of the electrode. Polycrystalline silicon is deposited by a low pressure CVD method. Silane and phosphine are used as the source gas, and maintained at a growth temperature of 550 ° C. for 8 hours at a pressure of 95 Pa. For example, polycrystalline silicon having an n-type doping concentration of about 7 × 10 ²⁰ cm ⁻³ and a thickness of 500 nm is formed as a gate oxide film. 6 is deposited. Patterning is performed by photolithography and dry etching.

  Next, an interlayer insulating film 9 is deposited on the surfaces of the gate oxide film 6 and the gate electrode 8 in the step shown in FIG. As the interlayer insulating film 9, silicon oxide having a high dielectric breakdown voltage and easy deposition is formed by, for example, atmospheric pressure CVD. The thickness is 1 μm, for example.

Next, in the step shown in FIG. 6A, a contact hole 10 reaching the contact region 5 and the source region 4 on the surface of the drift layer 2 is opened in the interlayer insulating film 11. For the opening of the contact hole 10, known photolithography and dry etching are used. For dry etching, for example, RIE using CHF ₃ or CF ₄ may be performed. At this time, not only the interlayer insulating film but also the underlying gate oxide film is removed, and the silicon carbide surface of the drift layer 2 is exposed.

  Next, in the step shown in FIG. 6B, the source electrode 14 is formed so as to fill the contact hole 10. As the source electrode 14, for example, nickel is deposited with a thickness of 100 nm by a vacuum evaporation method or a sputtering method. Then, after patterning by well-known photolithography and etching, heat treatment is performed, and nickel and silicon carbide are reacted to form nickel silicide. The heat treatment is performed at, for example, 950 ° C. for 1 minute in an inert atmosphere such as nitrogen. By this heat treatment, nickel reacts with silicon carbide and enters the silicon carbide. The penetration depth from the surface is about 75% to 150% of the initial nickel thickness. That is, it penetrates about 75 to 150 nm. Therefore, even if there is a region with a low implantation concentration on the surface of the source region 4 after gate oxidation, it is possible to penetrate the source electrode to a region with a high implantation concentration.

  Subsequently, the back electrode 12 is formed. The back electrode 12 is a laminated film in which titanium is deposited as a first electrode 12a in contact with the back surface of the substrate at 0.3 μm, nickel is deposited as a second electrode 12b at 1 μm, and silver is deposited as a third electrode 12c at 1 μm. Heat treatment is performed at 950 ° C. for 1 minute.

  Finally, the upper wiring 13 for connecting the source electrode 11 is formed on the surface. The upper wiring is formed by depositing aluminum with a thickness of 3 μm by a vacuum vapor deposition method or a sputtering method, and patterning by well-known photolithography and etching.

  As described above, in this embodiment, the influence of accelerated oxidation due to high concentration implantation of phosphorus is suppressed without introducing expensive epitaxial growth at a manufacturing cost, and the interface between the well region and the gate insulating film, the source region, and the gate. Steps in the substrate thickness direction at the interface with the insulating film can be almost eliminated and at least less than ½ of the thickness of the gate insulating film, so that the channel resistance is not increased.

In this embodiment, nickel is deposited as a source electrode and an ohmic electrode is formed by performing heat treatment at 950 ° C. However, when the concentration of the surface of the source region is set to a high concentration, for example, 4 × 10 ²⁰ cm ⁻³ or more. Although the contact resistance is high, ohmic contact can be obtained without heat treatment.

  In this embodiment, an example of a vertical MOSFET has been described. However, the present invention can also be applied to a lateral MOSFET having source and drain regions on the surface. That is, as long as the source and drain regions are formed by ion implantation of phosphorus, a similar problem occurs even in the lateral MOSFET, and this problem can be solved.

  According to the present invention, in the silicon carbide semiconductor device, a silicon carbide semiconductor device having a low contact resistance in the source region and a low on-resistance can be realized, and the step difference between the well region surface and the source region surface can be reduced, so that the channel mobility is reduced. Can be prevented. Therefore, it can be utilized for realizing a low on-resistance silicon carbide semiconductor device.

Process sectional drawing which shows the manufacturing method of the double injection type MOSFET which concerns on 1st embodiment of this invention Process sectional drawing which shows the manufacturing method of the double injection type MOSFET which concerns on 1st embodiment of this invention following FIG. Process sectional drawing which shows the manufacturing method of the double injection type MOSFET which concerns on 1st embodiment of this invention following FIG. Process sectional drawing which shows the manufacturing method of the double injection type MOSFET which concerns on 2nd embodiment of this invention Process sectional drawing which shows the manufacturing method of the double injection type MOSFET which concerns on 2nd embodiment of this invention following FIG. Process sectional drawing which shows the manufacturing method of the double injection type MOSFET which concerns on 2nd embodiment of this invention following FIG. The figure which shows the implantation profile of the phosphorus of the source implantation in the manufacturing method of the conventional double implantation type MOSFET The figure which shows the implantation profile of the phosphorus of a source injection in the manufacturing method of the double injection type MOSFET which concerns on 1st embodiment of this invention. The figure which shows the implantation profile of the phosphorus of a source injection in the manufacturing method of the double injection type MOSFET which concerns on 2nd embodiment of this invention. The figure which shows the injection | pouring profile of phosphorus of sacrificial layer injection | pouring in the manufacturing method of the double injection type MOSFET which concerns on 2nd embodiment of this invention. The figure which shows the implantation profile of the phosphorus of the source region by superimposition of source implantation and sacrificial layer implantation in the manufacturing method of the double implantation MOSFET according to the second embodiment of the present invention. Correlation diagram of impurity concentration and source contact resistance at interface between source region and source electrode Correlation diagram of surface concentration of each implantation type and thermal oxide film thickness in implantation region Process sectional drawing which shows the manufacturing method of the conventional double injection type MOSFET which inject | poured phosphorus and formed the source region FIG. 14 is a cross-sectional flow diagram showing a conventional method of manufacturing a double injection MOSFET, following FIG. FIG. 15 is a cross-sectional flow diagram illustrating a conventional method of manufacturing a double injection MOSFET, following FIG. Sectional view showing the structure of a conventional double injection MOSFET

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon carbide substrate 2 Drift layer 3 Well region 4 Source region 5 Contact region 6 Gate insulating film 6a Gate insulating film on the surface of source region 6b Gate insulating film on the surface other than the source region 7 Back surface thermal oxide film 8 Gate electrode 9 Interlayer Insulating film 10 Contact hole 11 Source electrode 12 Back electrode 12a First back electrode 12b Second back electrode 12c Third back electrode 13 Upper wiring 14 Sacrificial layer

Claims (9)

A semiconductor substrate;
A drift layer made of silicon carbide containing impurities at a lower concentration than the substrate formed on the semiconductor substrate;
A p-type well region formed on the surface of the drift layer;
An n-type source region formed in the well region;
A gate insulating film formed on the surface so as to straddle the well region and the source region;
A gate electrode formed on the gate insulating film;
A semiconductor device comprising silicon carbide including a source electrode formed on at least a part of the source region,
The concentration of phosphorus on the surface of the source region is 1 × 10 ²⁰ cm ⁻³ or more,
The carbonization characterized in that the difference in the substrate thickness direction between the interface between the well region and the gate insulating film and the interface between the source region and the gate insulating film is less than ½ of the thickness of the gate insulating film. Silicon semiconductor device. The silicon carbide semiconductor device according to claim 1, wherein phosphorus is included in a surface of the well region. 3. The silicon carbide semiconductor device according to claim 1, wherein a concentration of phosphorus on a surface of the source region is 4 × 10 ²⁰ cm ⁻³ or more. A step (a) of epitaxially growing a drift layer made of silicon carbide containing impurities at a lower concentration than the substrate on a silicon carbide substrate;
(B) forming a p-type well region by ion-implanting p-type impurities into the drift layer surface;
(C) forming a source region by ion implantation of phosphorus into the well region, and (d) forming a sacrificial layer containing phosphorus having a substantially uniform concentration profile over the entire surface of the drift layer over the in-plane direction. ,
An annealing step (e) for activating the p-type impurity and the phosphorus implanted after the steps (b), (c) and (d);
(F) forming a gate insulating film by thermally oxidizing at least the surface layer including the sacrificial layer after the activation annealing;
And (g) forming a source electrode in at least a part of the source region. 5. The step (g) is a step of forming a metal silicide to form a source electrode by depositing a metal on at least a part of the surface of the source region and performing a heat treatment. A method for manufacturing a silicon carbide semiconductor device. 6. The method of manufacturing a silicon carbide semiconductor device according to claim 5, wherein the concentration peak position on the surface side with respect to the drift layer most deeply by ion implantation of the source region is deeper than the formation position of the sacrificial layer. 6. The phosphorus concentration in the sacrificial layer is 1 × 10 ¹⁹ cm ⁻³ or more within a depth range of the silicon carbide surface layer consumed by thermal oxidation in the step (f). 6. A method for manufacturing a silicon carbide semiconductor device according to 6. A step (h) of epitaxially growing a drift layer made of silicon carbide containing impurities at a lower concentration than the substrate on the silicon carbide substrate;
(I) forming a p-type well region by ion-implanting p-type impurities into the drift layer surface;
(J) forming a source region by implanting phosphorus into the well region;
An annealing step (k) for activating the p-type impurity and the phosphorus implanted after the steps (i) and (j);
Forming a gate insulating film by thermal oxidation after the activation annealing (l);
Forming a source electrode in at least a part of the source region (m),
The phosphorus implantation concentration in the step (j) is 1 × 10 ¹⁹ cm ⁻³ or less within the depth range of the silicon carbide surface layer consumed by thermal oxidation in the step (l). A method for manufacturing a silicon carbide semiconductor device. 9. The step (m) is a step of forming a metal silicide to form a source electrode by depositing a metal on at least a part of the surface of the source region and performing a heat treatment. A method for manufacturing a silicon carbide semiconductor device.

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