JP2009260882A - Decoding device and in-house equipment in optical communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by partially or entirely stopping function of error correction code decoding processing at a receiving side when a bit error rate of a transmission line is small. <P>SOLUTION: A decoding device mounted in a receiving device includes a plurality of FEC decoding parts 32 which perform error correction of respective frames with error correction code, the frames being input to the receiving device and arranged in a parallel state each other; and a FEC decoding controller 34 which switches setting of valid/invalid of the error correction processing for each of the FEC decoding parts 32 based on a bit error rate estimate of the transmission line. The FEC decoding parts 32 performs error correcting operation when receiving indication of the valid from the FEC decoding controller 34, and stops error correcting operation when receiving indication of the invalid. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a decoding apparatus mounted on a receiver and used when decoding a frame with an error correction code (FEC).

  Using the optical data communication network between the station side equipment OLT (Optical Line Terminal: optical subscriber line terminal equipment) and a plurality of home side equipment ONU (Optical Network Unit: optical subscriber line termination equipment) Systems that communicate in the direction are known.

  In particular, a single star network configuration in which the station-side device OLT and each home-side device ONU are connected radially with a single optical fiber has been put into practical use. This network configuration simplifies the system and equipment configuration, but if one home-side device ONU occupies one optical fiber and there are N home-side device ONUs, it is directly connected from the station-side device OLT. N optical fibers are required, and it is difficult to reduce the cost of the system.

  Therefore, a PON (Passive Optical Network) communication system in which one optical fiber drawn from the station side device OLT is shared by a plurality of home side devices ONU has been put into practical use. The PON optical communication system is one of low-cost access methods for optical subscribers that have been applied to FTTx such as FTTH (Fiber To The Home) and FTTB (Fiber To The Building).

  In the PON optical communication system, one station side is passed through a passive optical branching device (optical coupler) that splits and multiplexes the signal passively from the input signal without the need for external power supply. The device OLT and a plurality of home-side devices ONU are connected by an optical transmission line. The station-side apparatus OLT and the N-station home-side apparatus ONU are based on 1-to-N transmission connected via an optical fiber SMF and an optical coupler OC. Thereby, many home side apparatuses ONU can be allocated with respect to one station side apparatus OLT, and the whole installation cost can be held down.

  In the optical communication system, an optical signal transmitted between the station side device OLT and the home side device ONU is configured by an FEC (Forward Error Collection) frame including a parity for error correction.

Each of the station side device OLT and the home side device ONU performs error correction / decoding of the data of the FEC frame in units of FEC frames using the error correction parity included in the received optical signal.
JP 2007-104571 A

When the transmission distance between the station side device OLT and the home side device ONU is short, or when the number of branches by the optical coupler is small, the received optical power has a sufficient margin for the minimum optical reception sensitivity, and the error correction code is Even if it is not used, the required specifications of the system (bit error rate 10 ^-12 or less, etc.) may be satisfied.

  Even though the bit error rate on the transmission line is very low with respect to the required specifications of the system, it is a waste of the power consumption of the receiver to always perform the FEC decoding process on the receiving side.

  Therefore, an object of the present invention is to provide a decoding apparatus that can reduce power consumption by partially or completely stopping the function of FEC decoding processing when the bit error rate is small.

  A decoding apparatus according to the present invention includes a plurality of FEC decoding units that are mounted on a receiver and that perform error correction on frames with error correction codes that are input to the receiver and arranged in parallel with each other, and a bit error rate of a transmission path And an FEC decode control unit that performs setting switching of validity / invalidity of error correction processing for each of the FEC decode units based on the estimated value, and each FEC decode unit receives the valid from the FEC decode control unit. The error correction operation is performed when the instruction is received, and the error correction operation is stopped when the invalid instruction is received.

  In this configuration, the error correction speed is improved by error-correcting frames with error correction codes arranged in parallel (parallel) by a plurality of FEC decoding units. Based on the estimated bit error rate of the transmission path, it is determined whether an error correction process by the FEC decoder is necessary, and based on the determination result, setting of error correction processing is enabled / disabled for each of the FEC decoding units. . As a result, each FEC decoding unit stops the error correction operation when receiving the invalid instruction from the FEC decoding control unit, so that the power consumption of the decoding apparatus can be reduced.

  In particular, when error correction is used for a high-speed transmission rate of 10 Gbps class, an implementation example in which parallel processing is performed by a plurality of FEC encoders and FEC decoders is often employed due to processing performance limitations in digital circuits. The present invention is particularly effective in such a case.

  Each FEC decoding unit has an error correction circuit that performs error correction processing on an input error correction code-added frame and a data holding circuit that holds the frame for a predetermined time corresponding to the operation of the error correction circuit. When the invalid instruction is received, the operation of the error correction circuit is stopped, and the frame held for a predetermined time by the data holding circuit is output from the FEC decoding unit. With this configuration, each FEC decoding unit reduces power consumption by disabling the error correction circuit and operates the data holding circuit to ensure a delay time, and then outputs a frame from the FEC decoding unit. be able to. The power consumption of the data holding circuit is usually lower than that of the error correction circuit.

  Each of the FEC decoding units may further include an error position / size calculation circuit and stop the operation of the error position / size calculation circuit when receiving the invalid instruction. Since the position / size calculation circuit does not need to be operated without error correction, the power consumption can be reduced by disabling this. Note that the power consumption of the data holding circuit is usually lower than that of the position / size calculation circuit.

  The decoding apparatus according to the present invention includes a bit error rate estimator that receives information on the number of errors of an error correction symbol for a frame with an error correction code from the error position / size calculation circuit and estimates a bit error rate of a transmission path. It is also possible to have more. With this configuration, the error position / size calculation circuit can calculate the number of symbol errors in a frame with an error correction code, and this can be used to estimate the bit error rate of the transmission path.

  The decoding apparatus according to the present invention includes n FEC decoding units (n is an integer equal to or greater than 2), and the FEC decoding control unit determines a bit error rate based on a bit error rate estimation result of the bit error rate estimation unit. May be instructed to invalidate the error correction processing to each of the NM (m is an integer of 1 to less than n) FEC decoding units. Since the instruction to invalidate the error correction processing is issued to each of the n−m (m is an integer of 1 to less than n) FEC decode units, there is always an FEC decode unit that has received a valid instruction. Yes. Therefore, the FEC decoding control unit can acquire the bit error rate estimation value of the transmission path from the bit error rate estimation unit of the FEC decoding unit that has received an instruction to enable error correction processing.

  The FEC decoding control unit obtains a bit error rate estimation value of a transmission path for a frame with an error correction code from the outside of a decoding device, and the number of FEC decoding units is n (n is 2 or more). Integer), and the FEC decode control unit determines an error for each of the n FEC decode units based on the bit error rate estimation result of the bit error rate estimation unit if the bit error rate is equal to or less than a reference value. An instruction to invalidate the correction process may be given. If the estimated bit error rate of the transmission path can be acquired from the outside of the decoding device, even if the bit error rate becomes equal to or less than the reference value, it is not necessary to make use of some FEC decoding units. Therefore, the power consumption of the decoding device can be reduced to the minimum.

  Further, the in-home apparatus of the optical communication system of the present invention is used in the PON optical communication system, and is arranged in parallel with each other, with error rate estimating means for estimating the bit error rate of the transmission path and the station side apparatus receiving from each other. Based on a plurality of FEC decoding units that respectively correct errors in frames with error correction codes and the bit error rate estimation value of the transmission path, the setting of enabling / disabling error correction processing is performed for each of the FEC decoding units. Each FEC decode unit performs an error correction operation when receiving the valid instruction from the FEC decode control unit and performs error correction when receiving the invalid instruction. The FEC decode control unit is configured to give the valid instruction when the in-home device starts up, and the error rate estimation Stage, the during operation of the in-home apparatus, and repeating that causes the setting switching enable / disable the FEC decoding control unit performs bit error estimation of the transmission path.

  According to this in-home device, the level of light received varies depending on the distance of the optical fiber from the station-side device to the home-side device, and it does not know whether it is installed near or far from the station-side device. When it is raised, error correction can be performed with certainty. Further, if there is a margin in the bit error rate of the transmission line during operation, the operation of the FEC decoding circuit can be stopped to save power.

  As described above, according to the present invention, the bit error rate of the transmission path is estimated on the receiving side, and decoding of a part or all of the FEC decoding units is performed when the bit error rate is smaller than the requirement of the communication system. By stopping the function, the power consumption of the receiver can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic diagram illustrating a configuration example of a PON optical communication system.

  In the PON optical communication system, a station side device OLT provided in a station building and a home side device ONU provided in a plurality of subscribers are connected via an optical fiber SMF and an optical coupler OC.

  The home-side apparatus ONU includes a network interface for connecting a terminal for enjoying an optical network service such as a personal computer installed in the subscriber's home.

  The optical coupler OC is composed of a star coupler that passively branches and multiplexes a signal from an input signal without requiring an external power supply.

  The optical fibers connected to the station-side device OLT, the optical coupler OC, the optical coupler OC, and the home-side device ONU are single mode fibers each composed of one optical fiber SMF. That is, one station side device OLT is connected to one optical coupler OC through one trunk optical fiber SMF. One optical coupler OC is connected to M second optical couplers OC (M is a number of 4 in this example) by an optical fiber SMF. The second optical coupler OC is connected to L units (L is a number of 8 or less in this example) of the home-side devices ONU by branch optical fibers SMF. Therefore, a signal transmitted / received by one station-side device OLT is distributed to a maximum of 32 home-side devices ONU by a two-stage optical coupler OC. Note that the numbers of the optical couplers OC and the home-side devices ONU are merely examples.

  The communication system of the embodiment of the present invention incorporates the technology of 10 Gigabit Ethernet (Ethernet is a registered trademark) into the PON optical communication system, and is optical at a baseband speed of 10.3125 Gbps. The 10GE-PON (Gigabit Ethernet-Passive Optical Network) system that realizes fiber access section communication is adopted.

  According to the 10GE-PON system, the communication between the station side device OLT and the home side device ONU is performed in units of variable length frames.

  First, a downlink frame that enters the station side apparatus OLT from the higher level network is subjected to a predetermined bridge process in the station side apparatus OLT, and a logical link to be relayed is specified. Then, it is transmitted to the optical fiber SMF as an optical signal through the station side device OLT. The optical signal transmitted to the optical fiber SMF is branched by the optical coupler OC and transmitted to the home device ONU connected to the optical coupler OC. However, only the home device ONU constituting the logical link transmits a predetermined downlink frame. Capture and relay frame to home network interface.

  On the other hand, the upstream optical signal includes an upstream frame from each home-side apparatus ONU. The upstream optical signal needs to be transmitted so that the optical signals from the respective home devices ONU do not compete with each other in time. For this purpose, the station side device OLT allocates a window (hereinafter simply referred to as a window) during which an upstream optical signal may be transmitted to each home side device ONU, and notifies it as a control frame. The home apparatus ONU to which the window is assigned transmits an upstream optical signal to the assigned window. This upstream optical signal is referred to as a “burst optical signal”. The burst optical signal is a finite-time optical signal sequence which is transmitted from each home-side apparatus ONU and whose light emission state is changed by a 10.3125 Gbps baseband signal.

  Therefore, the competition of the upstream optical signal between each home-side apparatus ONU is avoided. Each home-side apparatus ONU, when given a certain window, may transmit frames continuously as long as it fits in that window.

  The station apparatus OLT can receive a burst optical signal including a series of frame signals from each home apparatus ONU.

  The optical signal waveform and the optical signal intensity received by the station side device OLT and the home side device ONU are, for example, the characteristics of the light emitting elements of the station side device OLT and the home side device ONU, the length of the optical fiber SMF, It depends on the characteristics of the optical transmission line. Therefore, the station side device OLT and the home side device ONU perform predetermined processing on the received optical signal, and then transmit the restored significant frame sequence to the network.

  FIG. 2 is a diagram illustrating a format of a downstream optical signal. This optical signal is composed of continuous FEC frames. The FEC frame is composed of a frame with an error correction code in which parity data for FEC is added to FEC information of a certain length to be sent. The FEC frame is a unit of error correction code encoding processing and decoding processing.

  FIG. 3 is a diagram illustrating the structure of the FEC frame.

  The FEC frame is composed of an FEC information part and an FEC parity part, scrambled data is stored in the FEC information part, and parity data for error correction calculated from the FEC information part is stored in the FEC parity part. Stored. A unit of data included in the FEC information part and the FEC parity part is referred to as a “block”. In the embodiment of the present invention, the 64B / 66B code is used for data transmission, and hence it is referred to as a “66B block”. The 66B block consists of 66 bits, of which 64 bits are transmission data, and 2 bits are a synchronization header SH for synchronization.

  The synchronization header SH of the FEC information part is composed of a code “01” or “10”, and the synchronization header SH of the FEC parity part is composed of a code “11” or “00”. The FEC frame is synchronized by searching for a location where these synchronization header patterns match.

  The FEC information section stores a plurality of 66B blocks sent from the 64B / 66B conversion section 12 (see FIG. 4). The FEC parity part is composed of a plurality of 66B blocks for storing packet data, and this also has a structure in which two bits of the synchronization header SH (SH) are added, like the FEC information part.

  Here, the concept of packet and idle will be described. A packet is a unit of data contained in an optical signal. The length of one packet is variable from 64 bytes to 1522 bytes. When sending multiple packets, there is an idle between the packets. This idle has a minimum of 8 bytes.

  On the other hand, the FEC frame is obtained by dividing a byte sequence composed of a packet and an idle into fixed bytes (every 239 bytes if Reed-Solomon 255: 239). In other words, the FEC frame is a frame in which the transmission data string is cut into pieces at fixed lengths without being aware of the beginning or end of the packet.

  FIG. 4 shows the internal configuration of the optical transmission unit of the station side apparatus OLT and the light of the house side apparatus ONU in the PON optical communication system using the 64B / 66B code from the station side apparatus OLT to the house side device ONU of the present invention. It is the block diagram which simplified and represented the internal structure of the receiving part. Only one home device ONU is depicted.

  The optical transmission unit of the station side apparatus OLT includes a MAC transmission unit 11 that handles 64-bit unit data of the upper layer (MAC layer), and a 64B / 66B conversion unit 12 that receives 64-bit unit data from the MAC transmission unit 11. Prepare. The 64B / 66B conversion unit 12 attaches a 2-bit synchronization header SH (SH) to each 64-bit data, converts it to 66 bits (as described above, this is called a block), and sends it to the scrambler unit 13. . The scrambler unit 13 scrambles the 64-bit data portion. The scrambler unit 13 then sends scrambled 64-bit data and a 2-bit synchronization header SH to the FEC encoding unit 14. These 64-bit data and the synchronization header SH constitute the FEC information section (FIG. 3). The FEC encoding unit 14 calculates the FEC parity, adds the FEC parity unit (FIG. 3) to the FEC information unit, generates an FEC frame, and sends it to the electrical / optical conversion unit 15 (E / O conversion). The electrical / optical converter 15 converts an electrical signal into an optical signal and sends it to an optical fiber.

  Bit errors may occur in electrical signals due to attenuation of light or application of noise on this optical fiber transmission line.

  The optical receiving unit of the home-side apparatus ONU converts an optical signal (which may include a bit error) from an optical fiber into an electric signal by an optical / electrical conversion unit 21 (O / E conversion), and performs FEC decoding. Send to part 22.

  The FEC decoding unit 22 detects the FEC information part of the FEC frame and the synchronization header SH of the parity part and performs processing for synchronizing the FEC frame. After synchronization, the received data is subjected to error correction using the FEC parity for each FEC frame. The contents of the error correction processing are calculation of an error position (in which position of a plurality of symbols there is an error), size (correction value), and correction processing of an erroneous symbol. The error-corrected received data is descrambled by the descrambler unit 23. Thereafter, the 66B / 64B conversion unit 24 performs 64B / 66B decoding processing, removes the 2-bit synchronization header SH, and relays the data to the terminal device via the MAC reception unit 25 as an Ethernet frame.

  FIG. 5 is a block diagram illustrating an example of an internal configuration of the FEC decoding unit 22 of the home-side apparatus ONU.

  The FEC decoding unit 22 is connected in parallel to a switch circuit 31 that cuts FEC frames connected serially from the optical / electrical conversion unit 21 into individual FEC frames, and corrects the error of the FEC frames. And a plurality of FEC decoding units 32. The number of contacts of the switch circuit 31 matches the number of FEC decoding units 32. For example, if eight FEC decoding units 32 are prepared, the number of contacts of the switch circuit 31 is “8”. As a result, the FEC frames connected and supplied in a serial state are supplied one by one to the FEC decoding unit 32, and parallel processing is performed. By performing parallel processing with a plurality of FEC decoding units 32, if the processing capability of error correction of one FEC decoding unit 32 is 1.25 Gbps, error correction processing of 10 Gbps is realized with eight FEC decoding units 32 Can do.

  The FEC decoding unit 22 further includes a bit error rate estimation unit 33 and an FEC decoding control unit 34.

  The bit error rate estimator 33 receives information on the number of error correction symbol errors for the FEC frame from each FEC decoder 32 (each FEC decoder 32 performs symbol error in the FEC frame by performing the error correction process described above. In response, the bit error rate of the transmission path is estimated. The estimated bit error rate is provided to the FEC decode control unit 34.

  The FEC decoding control unit 34 outputs a setting switching signal for enabling / disabling error correction processing to each FEC decoding unit 32 based on the bit error rate estimation result of the transmission path by the bit error rate estimating unit 33.

  Each FEC decoding unit 32, upon receiving the error correction processing valid / invalid setting switching signal, performs error correction processing if the signal indicates “valid”, and the signal indicates “invalid”. If there is, error correction processing is not performed.

  FIG. 6 is a block diagram illustrating an example of an internal configuration of the FEC decoding unit 32. The FEC decoding unit 32 includes an error position / size calculation circuit 32a, an error correction circuit 32b, and a data holding circuit 32c.

  The error position / size calculation circuit 32a calculates the position and size of the symbol error in the FEC frame based on the received data and the received parity data of the FEC frame. For example, in the case of the Reed-Solomon code RS (255, 239), the position of up to 8 symbol errors and the size of the error can be calculated. The error correction circuit 32b corrects the received data by correcting the received data corresponding to the symbol error position by an error size. The data holding circuit 32c is a circuit for holding received data over an error position / size calculation time (usually within one frame). The data holding circuit 32c sends the received data to the error correction circuit 32b in accordance with the end time of the calculation of the error position / size, and the error correction circuit 32b receives the received data indicated by the error position when the received data indicates the error size. Make corrections.

  The FEC decoding unit 32 receives the error correction processing valid / invalid setting switching signal from the FEC decoding control unit 34, and when the error correction processing is set to "invalid", the error position / size calculation circuit The operation of the error correction circuit 32b is stopped, and only a delay process for a predetermined time by the data holding circuit 32c is performed. In this case, the received data is transferred to the descrambler unit 23 as it is.

  In order to stop the operation of the error position / size calculation circuit 32a and the error correction circuit 32b, the supply of the clock pulse signal supplied to the clock terminals of these circuits may be stopped. Alternatively, a reset signal may be supplied to the reset terminal of these circuits.

  Even when the error correction processing in the FEC decoding unit 32 is invalidated, the FEC frame held for a predetermined time in the data holding circuit 32c is output from the FEC decoding unit 32, so the arrangement, order, and delay of each FEC frame are held. Thus, it is possible to maintain a link state such as MPCP (Multi-Point Control Protocol) that is vulnerable to delay variation.

  Hereinafter, the error correction processing of all the FEC decoding units 32 is enabled or the error correction of a part of the FEC decoding units 32 is performed in accordance with the setting of error correction processing validity / invalidity performed by the FEC decoding unit 22. A flow of processing for determining whether to invalidate processing or to invalidate error correction processing of all FEC decoding units 32 will be described with reference to a flowchart (FIG. 7).

After the power-on of the home device ONU, the FEC decode control unit 34 first enables error correction processing of all the FEC decode units 32 (full decode mode; step S1). In the case of a PON optical communication system in which the distance from the station side device to the home side device can be different depending on the home side device, the full decode mode is first received according to the distance of the optical fiber from the station side device to the home side device. This is because the light level is different, and even if it is not installed near the station side device or whether it is installed far away, it can be received with correct error correction at startup. Then, the bit error rate estimation value is fetched from the bit error rate estimation unit 33, the bit error rate is confirmed (step S2), and the bit error rate is compared with a reference value (for example, 10 ^-12 ) which is a system requirement condition (step ¹² ). S3).

  If it is determined in step S3 that the bit error estimated value of the transmission line is higher than the reference value (there are many errors), the full decoding mode is set (step S1), and error correction processing of all the FEC decoding units 32 is performed. Valid.

  When it is determined that the bit error estimated value is equal to or less than the reference value, the FEC decoding unit 22 is set to the power saving mode (step S4). In this power saving mode, an error correction processing invalidity setting signal is sent to some FEC decoding units 32 to invalidate the error correction processing. That is, the invalidated FEC decoding unit 32 receives the error correction processing invalidation setting signal and stops the operation of the error position / size calculation circuit 32a and the error correction circuit 32b. The FEC decoding unit 32 that has received an effective setting signal that does not receive an invalid setting signal for error correction processing performs error correction processing. Of the plurality of FEC decoding units 32, the number of FEC decoding units 32 that receive valid setting signals is a part of all the FEC decoding units 32.

  The reason why the error correction processing of some FEC decoding units 32 is made valid in this way is that if the error correction processing of all the FEC decoding units is stopped, the number of symbol errors in the transmission channel cannot be calculated. This is because the bit error rate cannot be estimated (however, an embodiment in which error correction processing of all FEC decoding units 32 is invalidated will be described later).

  Therefore, the bit error rate confirmation process (step S4 → S2) is performed by the operating FEC decoding unit 32.

  When some of the FEC decoding units 32 are operating, a specific example of the bit error rate confirmation process (step S2) is as follows.

For example, when the configuration of eight FEC decoding units 32 is adopted, the transmission rate is 10 Gbps, and the bit error rate requirement specification of the system is 10 ⁻¹² , for example, only one FEC decoding unit 32 is in a state where error correction processing is effective. Suppose there is. The bit error rate estimator 33 determines that the bit error rate of the transmission path is 10 if no symbol error is detected by the operating FEC decoder 32 for (10 ^{12/10 10} ) × 8 = approximately 800 seconds. ^-12 or less. If even one symbol error is detected within 800 seconds, it is estimated that the bit error rate of the transmission path is greater than 10 ⁻¹² .

If FEC decoding unit 32 that the error correction processing multiple (e.g., m stand), in their multiple FEC decoding section ^{32, (10 12/10 10} ) × (8 / m) = about 800 / m sec If no symbol error is detected by the operating FEC decoding unit 32, the bit error rate of the transmission path is estimated to be 10 ⁻¹² or less.

  In general, when the number of contacts of the switch circuit 31, that is, the number of FEC decoding units 32 installed is n and the number of FEC decoding units performing error correction processing is m, time: {n / (m × transmission speed × system If no symbol error is detected by the operating FEC decoding unit 32 over the bit error rate requirement specification)}, the bit error rate of the transmission path is equal to or less than the bit error rate requirement (reference value) of the system. presume.

  Next, a flow of processing for invalidating error correction processing of all the FEC decoding units 32 when the bit error estimated value is equal to or less than the reference value will be described.

  When the error correction processing of all the FEC decoding units 32 is invalidated, the information on the bit error rate of the transmission path cannot be obtained from the FEC decoding unit 32. Therefore, in this case, the FEC decoding unit 22 must obtain the bit error rate estimation value from the outside. For example, the block error number obtained by the 66B / 64B conversion unit 24 that decodes the transmission line code or the data of the number of FCS errors of the Ethernet packet obtained by the MAC reception unit 25 is acquired, and the bit error rate estimation value is estimated. To do. Based on this estimated value, when the bit error rate of the transmission path is worse than the reference value, error correction processing of all the FEC decoding units 32 is validated.

  As described above, in a state where a plurality of FEC decoding units 32 are installed in a home device as the communication speed increases, if error correction processing of all the FEC decoding units 32 is enabled, power consumption increases. The bit error rate confirmation process (step S2) is repeated at regular time intervals, and when it is determined that the bit error rate of the transmission path is equal to or less than the system request, a part or all of the error correction process is stopped, thereby The power consumption of ONU can be reduced.

  Although the embodiments of the present invention have been described above, the embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.

It is the schematic which shows the structural example of the PON optical communication system which connected between the control station apparatus OLT and several terminal device ONU with the optical fiber via the optical coupler. It is a frame block diagram of the optical signal transmitted from the station side apparatus OLT to the home side apparatus ONU. It is a figure which shows the internal structure of one FEC frame. It is the block diagram showing the structure of the PON optical communication system from the station side apparatus OLT to the house side apparatus ONU. It is a block diagram which shows an example of an internal structure of the FEC decoding part 22 of the home side apparatus ONU. 3 is a block diagram illustrating an example of an internal configuration of an FEC decoding unit 32. FIG. It is a flowchart for demonstrating the state transition of a decoder control part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 MAC transmission part 12 64B / 66B conversion part 13 Scrambler part 14 FEC encoding part 15 Electrical / optical conversion part 21 Optical / electrical conversion part 22 FEC decoding part 23 Descrambler part 24 66B / 64B conversion part 25 MAC reception part 31 Switch Circuit 32 FEC decoding unit 32a Error position / size calculation circuit 32b Error correction circuit 32c Data holding circuit 33 Bit error rate estimation unit 34 FEC decoding control unit

Claims (7)

A decoding device mounted on a receiver,
A plurality of FEC decoding units that respectively perform error correction on frames with error correction codes that are input to the receiver and arranged in parallel with each other;
An FEC decode control unit that performs setting switching of validity / invalidity of error correction processing for each of the FEC decode units based on the estimated bit error rate of the transmission path,
Each of the FEC decoding units performs an error correction operation when receiving the valid instruction from the FEC decode control unit, and stops the error correction operation when receiving the invalid instruction Device. Each FEC decoding unit has an error correction circuit that performs error correction processing on an input error correction code-added frame and a data holding circuit that holds the frame for a predetermined time corresponding to the operation of the error correction circuit. And
2. The decoding device according to claim 1, wherein when the invalidation instruction is received, the operation of the error correction circuit is stopped and the frame held by the data holding circuit for a predetermined time is output from the FEC decoding unit.   3. The decoding device according to claim 2, wherein each FEC decoding unit further includes an error position / size calculation circuit, and stops the operation of the error position / size calculation circuit when receiving the invalid instruction. .   4. The decoding according to claim 3, further comprising a bit error rate estimator that receives information on the number of errors of an error correction symbol for a frame with an error correction code from the error position / size calculation circuit and estimates a bit error rate of a transmission path. Device. There are n FEC decoding units (n is an integer of 2 or more),
If the bit error rate is less than or equal to a reference value based on the bit error rate estimation result of the bit error rate estimator, the FEC decode control unit is nm (m is an integer between 1 and less than n) FECs. The decoding device according to claim 4, wherein an instruction to invalidate the error correction processing is given to each of the decoding units. The FEC decoding control unit obtains a bit error rate estimation value of a transmission path for a frame with an error correction code from outside the decoding device,
There are n FEC decoding units (n is an integer of 2 or more),
If the bit error rate is equal to or less than a reference value based on the bit error rate estimation result of the bit error rate estimation unit, the FEC decode control unit disables error correction processing for each of the n FEC decode units. The decoding device according to any one of claims 1 to 3, wherein the instruction is performed. A home device used in a PON optical communication system in which the distance from the station side device to the home side device can vary depending on the home side device,
An error rate estimating means for estimating a bit error rate of a transmission line;
A plurality of FEC decoding units that respectively perform error correction on frames with error correction codes arranged in parallel with each other received from the station side device;
An FEC decode control unit configured to perform setting switching of validity / invalidity of error correction processing for each of the FEC decode units based on the estimated bit error rate of the transmission path,
Each FEC decoding unit performs an error correction operation when receiving the valid instruction from the FEC decode control unit, and stops the error correction operation when receiving the invalid instruction,
The FEC decode control unit is configured to instruct the validity at the time of startup of the home device,
The home device is characterized in that the error rate estimation means repeatedly performs bit error estimation of a transmission path and causes the FEC decode control unit to switch between valid / invalid setting while the home device is in operation.

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