JP2009250644A - Jitter detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To heighten detection accuracy of jitter included in an inputted clock. <P>SOLUTION: In this jitter detection circuit equipped with a gating circuit 10 for outputting a pulse showing a rising edge timing of the inputted clock, an integration circuit 20 for converting an interval of output pulses of the gating circuit 10 into a voltage level and outputting the result, and a peak detection circuit 40 for displaying a peak voltage of an output voltage value of the integration circuit 20, a high-pass filter 30 is inserted between the integration circuit 20 and the peak detection circuit 40. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a jitter detection circuit that easily detects the magnitude of jitter contained in an input clock.

  FIG. 7 shows a conventional jitter detection circuit (Non-Patent Document 1). The conventional jitter detection circuit includes a gating circuit 10, an integration circuit 20, and a peak detection circuit 40. The gating circuit 10 includes a buffer 11, a delay circuit 12, and an AND circuit 13. The integrating circuit 20 includes a current source 21 of current 4 * I, a current source 22 of current I, a switch SW, and a capacitor C1. In the jitter detection circuit, the output voltage of the integration circuit 20 may be amplified and output, and peak detection may be performed outside the circuit. Here, in order to clearly indicate the problem at the time of jitter detection, the peak detection circuit 40 is provided. Including.

  The operation of the conventional jitter detection circuit will be described with reference to FIG. The gating circuit 10 outputs a pulse having a certain time width when a clock signal as an input signal transitions to an H level. 7 and 8 exemplify a case where a pulse having a time width of T / 4 is output, where T is a clock cycle. Note that Non-Patent Document 1 shows a circuit that outputs a pulse even when a clock signal transits to an L level using exclusive OR, but either can be used.

  In the integrating circuit 20, the switch SW is closed when the input node V0 becomes H level. The integration circuit 20 draws out the charge of the capacitor C1 by the reference current I by the current source 22 while the switch SW is open. However, when the switch SW is closed, the current source 21 causes a current 4 * I that is four times that current to flow. . At this time, the current I out of the current 4 * I flows to the GND through the current source 22, and the remaining current 3 * I charges the capacitor C1.

  Therefore, when a jitter-free clock is input, a current 3 * I flows into the capacitor C1 during the time T / 4 when the pulse that is the output of the gating circuit 10 is output, and the potential of the node V1 is as shown in FIG. As shown in V1 (Adjustment) of (c) of (c), it rises by (3/4) * I * T. During the time 3 * T / 4 when no pulse is output, the current I is discharged from the capacitor C1, and the potential of the node V1 drops by (3/4) * I * T. Therefore, when there is no jitter in the input clock, the potential of the node V1 oscillates with a voltage amplitude (3/4) * I * T and a period T, but a constant potential when time-averaged in a time sufficiently longer than the period T. Keep.

When the input clock has jitter, as shown in FIG. 8A, the timing at which the clock signal transitions to the H level is shifted from the period T by ΔT, not after the period T of the previous transition. At this time, since the discharge time of the integration circuit 20 is (3/4) * T−ΔT, the potential of the node V1 rises by I * ΔT. By holding the maximum value of the potential of the node V1 by the peak detection circuit 40, the jitter amount of the input clock is incremented from the initial value of the jitter display output potential as shown in the jitter display output (adjustment) of FIG. Can be detected.
K. Ichiyama et al., "A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter Measurement", IEEE INTERNATIONAL TEST CONFERENCE 2006, Paper 6.2

  However, in the conventional jitter detection circuit, it is difficult to detect jitter with high accuracy unless the following two values completely match. One of the values is the product of the value of the discharge current I of the integrating circuit 20 and the time obtained by subtracting the delay time (T / 4) of the gating circuit 10 from the period T. The other is the product of the current value obtained by subtracting the discharge current I from the charging current 4 * I of the integrating circuit 20 and the delay time (T / 4) of the gating circuit 10.

  On the other hand, when a conventional circuit is configured by a semiconductor integrated circuit or a hybrid component, these current values and delay values are affected by process variations, temperature, power supply fluctuations, etc., and are desired unless adjusted each time. It is difficult to match the above two values with accuracy.

  For example, when the delay time becomes longer than the target value (T / 4) without adjustment, the potential of the node V1 increases monotonously as indicated by V1 (no adjustment) in FIG. When this potential rise exceeds the potential rise due to jitter, the jitter display output (unadjusted) in FIG. 8 (f) has a problem that the correct jitter amount cannot be displayed.

  An object of the present invention is to provide a jitter detection circuit with improved jitter detection accuracy without being affected by process variations, temperature, power supply fluctuations, and the like.

To achieve the above object, a jitter detection circuit according to a first aspect of the present invention comprises a gating circuit that outputs a pulse indicating at least one edge timing of a rising edge or a falling edge of an input clock signal, and the gating circuit An integration circuit that converts the output pulse interval into a voltage level and outputs the voltage, and an amplification circuit that amplifies the output voltage value of the integration circuit or a peak detection circuit that displays the peak voltage of the output voltage value of the integration circuit In the jitter detection circuit, a high-pass filter is provided between the integration circuit and the amplification circuit or the peak detection circuit.
According to a second aspect of the present invention, in the jitter detection circuit according to the first aspect, when the output voltage of the integrating circuit exceeds a first potential, the output pulse width of the gating circuit is reduced, and the first And delay control means for widening the output pulse width when the second potential is lower than the second potential.
The invention according to claim 3 is the jitter detection circuit according to claim 1, wherein the output current of the current source for charging the capacitance of the integration circuit when the output voltage of the integration circuit exceeds the first potential. And a current control means for increasing the output current when the voltage falls below a second potential lower than the first potential.
According to a fourth aspect of the present invention, in the jitter detection circuit according to the second aspect, a frequency at which the output pulse width of the gating circuit is changed is set lower than a cutoff frequency of the high-pass filter. .
The invention according to claim 5 is the jitter detection circuit according to claim 3, wherein the frequency at which the output current of the current source of the integration circuit is changed is set lower than the cutoff frequency of the high-pass filter. And

According to the first aspect of the present invention, the output voltage drift of the integration circuit caused by process, temperature, power supply fluctuation, etc. is used for jitter detection by the configuration having the high-pass filter between the integration circuit and the amplification circuit or peak detection circuit. This has the effect of reducing the effect on the jitter and greatly improving the jitter detection accuracy.
According to the second aspect of the present invention, the output voltage variation of the integration circuit is fed back to the delay circuit of the gating circuit, so that the output voltage variation of the integration circuit is suppressed to a certain range, and the current source of the integration circuit is determined. Since the current characteristic can be maintained, the change in the output pulse interval of the gating circuit can be converted to the change in the output voltage of the integration circuit with high accuracy, and the jitter detection accuracy can be further improved.
According to the third aspect of the present invention, the output voltage fluctuation of the integration circuit is fed back to the current source of the integration circuit, so that the output voltage fluctuation of the integration circuit is suppressed within a certain range, and the constant current of the current source of the integration circuit is controlled. Therefore, the change of the output pulse interval of the gating circuit can be converted to the change of the output voltage of the integration circuit with high accuracy, and the jitter detection accuracy can be further improved.
According to the fourth and fifth aspects of the present invention, the frequency of the change in the output pulse width of the gating circuit and the frequency of the change in the output current of the integration circuit are set lower than the cutoff frequency of the high-pass filter. The influence of the function of suppressing the output voltage fluctuation within a certain range on the jitter detection can be reduced, and the jitter detection accuracy can be further improved.

  Variations in delay time and current value due to the temperature, power supply voltage, etc. described above occur mainly at a very low frequency. Therefore, in the present invention, a high-pass filter is added to the node V1 so as to eliminate this influence and leave only a potential change caused by jitter having a relatively high frequency. In addition, in order to cope with process variations, a feedback circuit is added so that the above two basic constants match. Furthermore, the time constant of the feedback circuit is set to a long time constant that can sufficiently attenuate the influence by the added high-pass filter. This will be described in detail below.

  FIG. 1 shows a first embodiment of the jitter detection circuit of the present invention. The jitter detection circuit of the first embodiment includes a gating circuit 10, an integration circuit 20, a high-pass filter 30, and a peak detection circuit 40. The gating circuit 10, the integration circuit 20, and the peak detection circuit 40 are the same as those described with reference to FIG.

  The operation of the jitter detection circuit of this embodiment will be described with reference to FIG. The gating circuit 10 outputs a pulse having a certain time width when a clock signal as an input signal transitions to an H level. 1 and 2 exemplify a case where a pulse having a time width of T / 4 is output with a clock period T.

  In the integrating circuit 20, the switch SW is closed when the input node V0 becomes H level. The integrating circuit 20 draws out the electric charge of the capacitor C1 by the current source 22 by the current source 22 while the switch SW is open, but when the switch SW is closed, the current 4 * I that is four times the current flows from the current source 21. At this time, the current I out of the current 4 * I flows to the GND through the current source 22, and the remaining current 3 * I charges the capacitor C1.

  Therefore, when a jitter-free clock is input, a current 3 * I flows into the capacitor C1 during the time T / 4 when the pulse that is the output of the gating circuit 10 is output, and the potential of the node V1 is as shown in FIG. As shown in V1, the voltage increases by (3/4) * I * T. During the time 3 * T / 4 when no pulse is output, the current I is discharged from the capacitor C1, and the potential of the node V1 drops by (3/4) * I * T. Therefore, when there is no jitter in the input clock, the potential of the node V1 oscillates with a voltage amplitude (3/4) * I * T and a period T. keep.

  When the input clock has jitter, as shown in FIG. 2, the timing at which the clock signal transitions to the H level is shifted from the period T by ΔT, not after the period T of the previous transition. At this time, since the discharge time of the integration circuit 20 is (3/4) * T−ΔT, the potential of the node V1 rises by I * ΔT.

  The high-pass filter 30 can be composed of a capacitor C2 having one end connected to the node V1 and the other end connected to the node V2, and a resistor R1 connecting the node V2 and GND. The reciprocal of the product of the resistor R1 and the capacitor C2 is the low-frequency cutoff frequency. This cut-off frequency is set sufficiently high compared to the fluctuation frequency of the potential of the node V1 due to process, temperature, power supply fluctuation, and the like.

  For example, when the frequency of the input clock is 6 GHz and the lower limit frequency of the jitter frequency to be detected is 1 MHz, the cutoff frequency is set to about 10 kHz. Of the frequency components of the V1 output in FIG. 2 (c), the frequency components due to process, temperature, power supply fluctuation, etc. are usually less than 1 kHz, so the output of the node V2 in FIG. The frequency component does not propagate.

  Further, the 6 GHz signal that is the basic component of the clock is cut off at a frequency of approximately 100 MHz that is the reciprocal of the time constant represented by the product of the output resistance of the current source 21 of the integrating circuit 20 and the capacitance C1.

  As a result, only a potential fluctuation of 1 MHz to 100 MHz at the node V1 due to jitter propagates to the node V2. As shown in the jitter display output of FIG. 2 (e), the detection of the jitter is realized by holding the maximum value of the potential of the node V2 by the peak detection circuit 40 or simply amplifying and outputting it. The jitter amount of the input clock can be detected by an increment from the initial value of the jitter display output potential.

  Here, by setting the band of the amplifier circuit or the peak detection circuit 40 to the upper limit of the jitter frequency to be detected (for example, the above 100 MHz), it is not affected by the basic frequency of the clock (for example, the above 6 GHz). The jitter of the frequency to be detected is output to the node V2. Therefore, the fluctuation of the node V1 due to the process, temperature, power supply fluctuation, etc. can be removed, and the maximum value of the potential of the node V2 is held by the peak detection circuit 40 or displayed by the amplifier, thereby easily and accurately performing jitter. Detection is possible.

  FIG. 3 shows a second embodiment of the jitter detection circuit of the present invention. The jitter detection circuit according to the second embodiment is different from the first embodiment in that a delay control circuit 50 is added to the configuration of the first embodiment and that a delay adjusting means is added to the delay circuit 12A constituting the gating circuit 10A. .

  The delay control circuit 50 has a function of receiving the potential of the node V1, detecting a change in the potential of the node V1, and outputting a potential for increasing or decreasing the delay value of the delay circuit 12A to the node V3. The delay circuit 12A constituting the gating circuit 10A increases or decreases the delay value (assuming T / 4 here) according to the potential of the node V3. The increase / decrease in the delay can be realized by an existing technology such as a delay circuit using a varactor.

  As shown in FIG. 4, when the potential of the node V1 rises to a certain value Vth + or more, the delay control circuit 50 changes the potential of the node V3 so as to reduce the delay value of the delay circuit 12A. Further, when the potential of the node V1 falls below a certain value Vth−, the potential of the node V3 is changed so as to increase the delay value of the delay circuit 12A. In FIG. 4B, Δtd is a time for jitter, and t1 is a time for control by the delay control circuit 50. Here, although the determination values are binary values of Vth + and Vth−, it is within the scope of the idea of the present invention to provide a larger number of determination values and to perform continuous feedback.

  When the delay of the delay circuit 12A is reduced by the feedback operation of the delay control circuit 50, the time for the integrating circuit 20 to charge the capacitor C1 via the switch SW is slightly shortened. Since the discharging current increases from the charging current of the capacitor C1, the potential of the node V1 gradually falls after exceeding the Vth + as shown in FIG.

  When the delay of the delay circuit 12A is increased by the feedback operation of the delay control circuit 50, the time for the integrating circuit 20 to charge the capacitor C1 through the switch SW is slightly increased. Since the charge current increases from the current that discharges the capacitor C1, the potential of the node V1 rises gently after falling below Vth− as shown in FIG.

  Therefore, the potential of the node V1, which is the output of the integrating circuit 20, can be held within a potential slightly exceeding Vth + and a potential slightly lower than Vth−. As a result, the output potential can be maintained within a range in which the current source of the integrating circuit 20 can maintain constant current, so that the pulse interval of the node V0 can be converted to the potential change of the node V1 with high accuracy.

  The period of the potential fluctuation of the node V1 by the delay control circuit 50 is designed to be sufficiently long (for example, less than 1 kHz) as compared with the jitter frequency (for example, 1 MHz to 100 MHz), so that the high-pass filter 30 (for example, cutoff) Only a high-frequency potential fluctuation indicating the amount of jitter appears at the output node V2 having a frequency of 10 kHz. Therefore, since the potential fluctuation of the node V1 due to the delay control circuit 50 does not appear in the potential fluctuation of the node V2, the jitter display output can display the jitter amount with high accuracy.

  FIG. 5 shows a third embodiment of the jitter detection circuit of the present invention. The jitter detection circuit of the third embodiment is different from the first embodiment in that a current control circuit 60 is added and a current value adjusting means is added to the charge current source 21A constituting the integration circuit 20A.

  The current control circuit 60 has a function of receiving the potential of the node V1, detecting a change in the potential of the node V1, and outputting a potential for increasing or decreasing the current value of the charge current source 21A to the node V4. The charge current source 21A constituting the integrating circuit 20A increases or decreases the current value (assumed to be 4 * I here) according to the potential of the node V4.

  The charge current source 21A can be realized by a PMOS transistor having a source connected to the power supply, a drain connected to one end of the switch SW, and a gate connected to the node V4 (not shown).

  As shown in FIG. 6, when the potential of the node V1 rises to a certain value Vth + or more, the current control circuit 60 changes the potential of the node V4 so as to reduce the current value of the charge current source 21A. Further, when the potential of the node V1 falls below a certain value Vth−, the potential of the node V4 is changed so as to increase the current value of the charge current source 21A. In FIG. 6B, ΔI is a current for jitter, and I1 is a current for control by the current control circuit 60. Here, the determination values are binary values of Vth + and Vth−, but it is within the scope of the idea of the present invention to perform a larger number of determination values and continuous feedback.

  When the current of the charging current source 21A of the integrating circuit 20A is reduced by the feedback operation of the current control circuit 60, the discharging current increases from the current for charging the capacitor C1, so that as shown in FIG. The potential of the node V1 gradually falls after exceeding Vth +.

  Further, when the current of the charging current source 21A of the integrating circuit 20A is increased by the feedback operation of the current control circuit 60, the charging current increases from the current for discharging the capacitor C1, so that as shown in FIG. The potential of the node V1 rises gently after falling below Vth−.

  Therefore, the potential of the node V1, which is the output of the integrating circuit 20A, can be held within a potential slightly exceeding Vth + and a potential slightly lower than Vth−. As a result, the output potential can be maintained within a range in which the current source of the integrating circuit 20A can maintain constant current, so that the pulse interval of the node V0 can be converted into a change in the potential of the node V1 with high accuracy.

  By designing the period of the potential fluctuation of the node V1 by the current control circuit 60 to be sufficiently longer than the jitter frequency, the node V2 at the output of the high pass filter 30 has only a high-frequency potential fluctuation indicating the jitter amount. appear. Therefore, since the potential fluctuation of the node V1 by the current control circuit 60 does not appear in the potential fluctuation of the node V2, the jitter display output can display the jitter amount with high accuracy.

1 is a circuit diagram showing a configuration of a jitter detection circuit according to a first exemplary embodiment of the present invention. FIG. FIG. 2 is an operation characteristic diagram of the jitter detection circuit of FIG. 1. It is a circuit diagram which shows the structure of the jitter detection circuit of the 2nd Example of this invention. FIG. 4 is an operation characteristic diagram of the jitter detection circuit of FIG. 3. It is a circuit diagram which shows the structure of the jitter detection circuit of the 3rd Example of this invention. FIG. 6 is an operation characteristic diagram of the jitter detection circuit of FIG. 5. It is a circuit diagram which shows the structure of the conventional jitter detection circuit. FIG. 8 is an operation characteristic diagram of the jitter detection circuit of FIG. 7.

Explanation of symbols

10, 10A: Gating circuit, 11: Buffer, 12, 12A: Delay circuit, 13: AND circuit 20, 20A: Integration circuit, 21, 21A, 22: Current source, SW: Switch, C1: Capacitance 30: High pass Filter, C2: Capacitance, R1: Resistance 40: Peak detection circuit (or amplification circuit)
50: Delay control circuit 60: Current control circuit

Claims (5)

A gating circuit that outputs a pulse indicating at least one edge timing of a rising edge or a falling edge of an input clock signal; an integration circuit that converts an interval between output pulses of the gating circuit to a voltage level; and In a jitter detection circuit comprising an amplification circuit that amplifies the output voltage value of the circuit or a peak detection circuit that displays the peak voltage of the output voltage value of the integration circuit,
A jitter detection circuit comprising a high-pass filter between the integration circuit and the amplification circuit or the peak detection circuit. The jitter detection circuit according to claim 1,
The output pulse width of the gating circuit is narrowed when the output voltage of the integrating circuit exceeds the first potential, and the output pulse width is decreased when the output voltage is lower than the second potential lower than the first potential. A jitter detection circuit comprising delay control means for widening. The jitter detection circuit according to claim 1,
When the output voltage of the integration circuit exceeds the first potential, the output current of the current source for charging the capacitance of the integration circuit is reduced and falls below a second potential lower than the first potential. A jitter detection circuit comprising current control means for increasing the output current in some cases. The jitter detection circuit according to claim 2,
A jitter detection circuit, wherein a frequency for changing the output pulse width of the gating circuit is set lower than a cut-off frequency of the high-pass filter. The jitter detection circuit according to claim 3,
A jitter detection circuit, wherein a frequency of changing the output current of the current source of the integration circuit is set lower than a cut-off frequency of the high-pass filter.

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