JP2009232340A - Image pickup element and method for driving image pickup element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image pickup element suitable to control the reading timing of pixel signals by setting a sleep period of reading processing. <P>SOLUTION: The image pickup element 100 includes a read-reset line address generating section 13 for generating a plurality of addresses indicating the position of a line of a sensor cell to be processed on the time division basis during one horizontal scanning period; a driving pulse generator 14 for generating a signal for driving the sensor cell of the selection line: a sensor cell array 15; and a horizontal transfer section 16 for outputting the read data of the image signal per line. The read-reset line address generating section 13 includes the same number of selection line address generating circuits as the number of time-divisions, and can independently control the generating circuits. Further, in a control section 1321, a reading sleep period is set in repeating reading processing of the pixel signal, and the pixel signal is read from a line of an OB region in the reading sleep period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention includes a photoelectric conversion unit in which a plurality of photoelectric conversion elements are arranged in a matrix, and a plurality of times in a time division manner in a horizontal scanning period with respect to a predetermined pixel line constituting the photoelectric conversion elements. The present invention relates to an image sensor that performs a reading process of accumulated charges and a method for driving the image sensor.

  In the CMOS type area sensor, pixels are generally cleared and pixel values are read in units of rows from the top to the bottom (or from the bottom to the top) of the screen. For example, in the case of VGA (640 × 480) resolution, the total number of lines is often about 500 when including a light-shielded OB (Optical Black) region. When the frame rate is 30 [fps], one image is taken every 1/30 seconds. To obtain this image, 500 lines are scanned, and the scanning time for one line is set as the horizontal synchronization signal. In many cases, the acronym for HSYNC is taken as 1H. Simply speaking, the period of 1H is 1/30 seconds divided by 500 lines, that is, 1/15000 seconds, in other words, 1/15 milliseconds (about 67 μsec). In a normal CMOS sensor, readout of pixels and initialization (reset) of accumulated pixel charges are performed during 1H. This is because reading out the charges accumulated in the pixels is a process of taking out the accumulated charges themselves, and therefore a process of initialization is always required after the process of obtaining the amount of accumulated charges. By repeating the process of resetting immediately after reading a certain line in order line by line for all the lines, imaging with a maximum exposure time (500H) can be performed. At this time, if attention is paid to a specific line, reading and resetting from its own line are performed during the 1H period, and reading and resetting from other lines are performed during the remaining 499H period. This is an event that applies to all pixels.

In a normal CMOS sensor, pixel values of accumulated pixels are destroyed when readout is performed. Therefore, images with different exposure times can only capture images with different exposure start times and exposure end times. That is, imaging can be performed only in series.
On the other hand, in a sensor capable of nondestructive readout, the charge stored in the pixel value readout operation is not read out because the index value corresponding to the accumulated charge is read out instead of reading out the charge stored in the pixel itself. Will not be damaged. Therefore, no matter how many times the same pixel is read out, it does not affect the accumulation of electric charges according to the amount of incident light. When this feature is used, it is possible to capture images having the same exposure start time but different exposure times. This means that a plurality of exposure images with different pixel readout times can be captured at the same exposure start time, and a plurality of different exposure images are captured in parallel using the same pixel. It can be said that it can be done.

Using these non-destructive readout features makes control a little complicated, but it is also possible to use high-speed frame rate readout that repeatedly reads only a specific area across multiple lines at high speed while imaging with different exposure times. it can.
As such a technique, for example, there is an image sensor described in Patent Document 1.
Such an image sensor performs non-destructive readout and performs readout three times in a 1H period. In a normal readout sequence, after normal exposure (S image), reset is performed in line units, exposure (N image) is performed immediately after reset, and an image obtained by subtracting N image from S image is output. By performing this subtraction process, fixed pattern noise (FPN) can be greatly reduced. Furthermore, by using the data that is read out only for one specific line every 1H period for automatic focus adjustment (AF) and automatic exposure adjustment (AE), imaging control operations can be performed at high speed without interrupting normal exposure processing. it can.

As described above, by using a technique for performing a plurality of processes in the 1H period, it is possible to simultaneously realize a process of reading and resetting in an interlaced manner.
However, if various processes are performed in the 1H period, the response in the subsequent image processing becomes complicated. The size of the image is fixed when a specific process is started, so this is not a big problem in the subsequent image processing. The display quality may be complicated, and the display image quality may be deteriorated.

Therefore, in order to prevent complication, a mechanism for synchronizing every certain period may be introduced. In image processing, since processing is often controlled in units of frames, the output timing of an image may be adjusted based on the start of a frame of an image. That is, in some images, the timing can be easily adjusted by providing a period (wait period) during which no intentional reading is performed.
JP 2005-269552 A

  However, in the above-described conventional driving method, there are a period in which the read is waited and a period in which the read is not waited. The entire pixel is the same because it is affected uniformly, but when compared with images having the same exposure time, there is a difference in pixel value depending on the presence or absence of each readout period (wait period). In addition, in an image having a short exposure time, an image in which a read weight is executed during exposure and an affected line and an unaffected line are mixed is read. That is, even in a situation where each pixel is irradiated with a uniform amount of incident light, a phenomenon in which the accumulated charge amount of each pixel partially varies depending on the combination of the position of the pixel and the processing content of the reading process. There is a fear.

  Therefore, the present invention has been made paying attention to such an unsolved problem of the conventional technology, and is suitable for controlling the readout timing of the pixel signal by setting a pause period of the readout processing. It aims at providing a simple image pick-up element.

  [Mode 1] In order to achieve the above object, an image pickup device according to mode 1 includes a photoelectric conversion unit and a rolling shutter having a configuration in which a plurality of photoelectric conversion elements that convert received light into electric charges and store them are arranged in a matrix. A position of a line formed by the photoelectric conversion element to be processed corresponding to each divided period of a plurality of divided periods obtained by time-dividing each horizontal scanning period in each frame period Address generating means for generating an address indicating the address, and address decoding for activating the photoelectric conversion element at the line position indicated by the address corresponding to each divided period generated by the address generating means for each divided period And a pixel signal having a level corresponding to the amount of accumulated charge from the photoelectric conversion element activated according to the readout instruction via a common line. Pixel signal reading means for reading out by breakage, reset processing means for performing reset processing, which is processing for emptying the accumulated charge of the photoelectric conversion element that has been activated in response to a reset instruction, and each frame period And a reading pause period setting means for setting a reading pause period, which is a period for temporarily stopping the regular reading process of the pixel signal, and a photoelectric conversion element at a predetermined line position in the set reading pause period. Dummy read control means for causing the address decoding means to be in an active state and for causing the pixel signal reading means to read out the pixel signal from the photoelectric conversion element in the active state.

With this configuration, when the address generation unit generates the address of the line to be processed in each divided period, the address decoding unit converts the photoelectric conversion element at the line position corresponding to the generated address into the divided period. Each is activated sequentially.
When the photoelectric conversion element at the processing target address is in an active state, in the divided period in which the readout instruction is given, the pixel signal reading means nondestructively outputs the pixel signal (the index of the background art described above) from the activated photoelectric conversion element. Is read). Further, during the divided period in which the reset instruction is given, the accumulated charge of the activated photoelectric conversion element is reset by the reset processing means.

  On the other hand, when performing the reading process, the reading suspension period setting means can set a reading suspension period (wait period) in which the reading process normally performed in each frame period is temporarily suspended. When the readout pause period is set, the photoelectric conversion element at a predetermined line position is activated by the dummy readout control means during the set readout pause period, and pixel signal readout processing is executed for the photoelectric conversion element Is done. The pixel signal data is unnecessary for image forming processing (or any processing in the subsequent stage). Therefore, for example, this data is not output to the subsequent processing unit, or is discarded by the subsequent processing unit.

  In other words, the non-destructive readout process of the pixel signal is executed from the photoelectric conversion element at the predetermined line position even in the readout pause period, so that a period in which the readout process of the pixel signal is not performed does not occur. it can. That is, it is possible to prevent a period during which the drive voltage is not applied to the common line used when reading the pixel signal from each photoelectric conversion element. As a result, the driving voltage can be stably applied to the common line serving as the transmission path of the pixel signal, so that an adverse effect such as fluctuation of the accumulated charge amount caused by the uneven application voltage can be suppressed. It is done.

  Here, in the readout pause period, for example, offset readout that gives an offset to the start of readout, thinning readout (including interlaced readout) in which pixel signals are read out while thinning out lines, and partial areas of the photoelectric conversion unit are repeated. This is a wait period inserted in each frame period when pixel signal readout processing is performed by various different readout methods such as repeated readout (high-speed readout). The present embodiment is characterized in that the pixel signal is read from a predetermined line position without stopping the reading of the pixel signal during this period. Hereinafter, the same applies to the driving method of the image pickup device of form 10 and the image pickup device of form 11.

  The regular readout process is a pixel signal readout process performed to acquire data used in subsequent processing such as image formation processing. Hereinafter, the same applies to the driving method of the image pickup device of form 10 and the image pickup device of form 11.

  [Embodiment 2] Further, the imaging device of embodiment 2 is the imaging device according to embodiment 1, wherein the photoelectric conversion unit has an OB (Optical black) region composed of a light-shielded line of the photoelectric conversion device. The photoelectric conversion element at the predetermined line position corresponding to the readout pause period is a photoelectric conversion element that forms a line in the OB region.

With such a configuration, the pixel signal is read from the line in the OB region of the photoelectric conversion unit in the reading suspension period.
That is, since the pixel signal is read out every time from the line at the specific position, the control process becomes simple and the circuit configuration can be simplified.

  [Mode 3] Further, the image pickup device according to mode 3 is the image pickup device according to mode 2, wherein the address generation means controls the address counters at least as many as the number of time divisions and independently controls the operations of the address counters. And an address selection unit that sequentially selects each address counter in a time-sharing manner and outputs the count value of the selected address counter as the address to the address decoding unit. And control information acquisition means for acquiring control information for controlling each of the address counters, and the operation control unit controls each of the address counters independently based on the control information acquired by the control information acquisition means. .

With such a configuration, when the reading process and the reset process are performed in a time division manner, the count operation of at least the same number of address counters as the time division number is controlled independently using the control information. Thus, an appropriate address can be generated, and the address decoding means can decode the address generated at an appropriate timing.
For example, each horizontal scanning period is time-divided into N, and the count operation of each address counter is controlled independently, so that the image sensor can perform N types of readout processing and reset processing in each horizontal scanning period. Addresses can be generated in a time division manner, and the generated addresses can be decoded in a time division manner. This allows the image sensor to read charges from a part of the photoelectric conversion elements of the photoelectric conversion unit at high speed (repetitive reading), and to read charges while skipping an arbitrary number of rows (decimation reading). The effect that it is possible to execute a proper reading process is obtained.

  In addition, since the address counter for read processing and the address counter for reset processing can be controlled independently of each other, there is also an effect that the read timing and the reset timing can be accurately controlled.

  [Mode 4] Furthermore, the image pickup device of mode 4 further includes a reference counter that performs a counting operation based on a counter update clock generated based on a horizontal synchronization signal in the image pickup device according to mode 2 or 3, wherein the control information is The offset value of each address counter, and when the offset value and the count value of the reference counter match, the operation control unit performs a count operation on each address counter using the timing of the match as a trigger. Let it begin.

  In such a configuration, for example, each address counter is based on the count value of a reference counter that performs a count operation using as a trigger the horizontal synchronization signal itself or a sample obtained by re-sampling the horizontal synchronization signal with an internal operation clock. The effect that the start timing of the counting operation can be controlled is obtained.

  [Mode 5] Further, in the image pickup device according to mode 5 or 4, the control information includes a step width value, a start line value, and a line width value of each address counter, and the operation is performed. The control unit sets the step width at the time of the counting operation of each address counter based on the step width value, causes each address counter to count at the set step width, and based on the start line value, The initial value of each address counter is set, the count of each address counter is started from the set initial value, and the maximum count value of each address counter is set based on the line width value, and Each address counter is counted within the range from the set initial value to the set maximum count value. To perform the operation.

  With such a configuration, each address counter can be counted with a step width set by the step width value which is one of the control information, so that a desired step width value is set. By preparing the control information, each address counter can be counted with a desired step width. Thereby, the charge can be read out while thinning out the rows corresponding to the step width, so that an effect that the image pickup element can perform the charge high-speed reading process can be obtained.

  Here, for example, if the step width is “1”, the count value is incremented by 1, 1, 2, 3,..., And if “2”, it is 1, 3, 5,.・ ・ Incremented by 2 (in the case of up-counting and the initial value of the counter is “1”). On the other hand, in the case of down-counting, if the step width is "1", it decreases by 3, 2, 1 and 1; Decrease. That is, if the step width is “n”, in the case of up-counting, 1, 1 + n, 1 + 2n,... Increase by n with respect to the initial value of the counter, and in the case of down-counting, for example, the initial value If X is X, Xn, X-2n, X-3n,...

  Further, since each address counter can start counting from the initial value of the address counter set by the start line value which is one of the control information, control information is prepared so that a desired initial value is set. As a result, each address counter can start counting from a desired initial value. As a result, an effect is obtained in which the image pickup element can start the readout process and the reset process of the accumulated charge from the photoelectric conversion element at an arbitrary position in the photoelectric conversion unit.

  Furthermore, each address counter can be caused to perform a counting operation within a range not exceeding the maximum count value set by the line width value which is one of the control information. Accordingly, the image sensor is subjected to pixel signal readout processing and reset processing only for an area composed of photoelectric conversion elements at line positions corresponding to respective count values from the initial value to the maximum count value in the photoelectric conversion unit. The effect that it can be made is acquired.

  [Mode 6] Further, in the image sensor according to mode 6, in the image sensor according to mode 5, the address counter causes the address counter to continuously and repeatedly perform a counting operation within a range from the initial value to the maximum count value. The repeat mode can be set, and the operation control unit counts the address counter set with the repeat mode within a range from the set initial value to the set maximum count value. The operation is repeated continuously.

  With such a configuration, the pixel signal is continuously and repeatedly read out from the area formed by the photoelectric conversion elements at the line positions corresponding to the respective count values from the initial value to the maximum count value. Reset processing can be performed. Thereby, for example, while the image pickup device sequentially reads out pixel signals line by line from the entire region of the photoelectric conversion unit, the pixel signal is continuously transmitted to the image pickup device from a partial region of the photoelectric conversion unit a plurality of times. Can be read out.

  Furthermore, when the period for repeatedly reading out the pixel signal multiple times in each frame period and the count period (frame period) of the reference counter are shifted, a reading pause period can be set to match both periods, Since the pixel signal is read out from the photoelectric conversion element at a predetermined line position in the readout pause period, it is possible to perform a synchronized readout process while suppressing adverse effects on the accumulated charge amount due to the readout pause period. The effect is obtained.

  [Aspect 7] Further, the imaging element according to Aspect 7 is the imaging element according to Aspect 6, wherein the control information includes a weight value of each address counter, and the reading pause period setting means is based on the weight value. A wait count number that is a count number for the wait of the address counter is set, and the operation control unit finishes each operation of the repeated count operation in the address counter in which the repeat mode is set. Each time, the address counter is caused to count the set wait count number, and while the wait count number is being counted, a control signal for invalidating the count value is output to the address decoding means, The dummy read control means sets a period for counting the wait count number as a read pause period. Then, in the reading suspension period, the photoelectric conversion element at the line position corresponding to the address indicating the predetermined line position is caused to be in an active state by the address decoding unit, and the photoelectric conversion element from the active state is The pixel signal is read by the pixel signal reading means.

  With such a configuration, by setting a weight value that matches the cycle of repeatedly reading out the pixel signal a plurality of times in each frame period and the count cycle (frame cycle) of the reference counter, both cycles can be matched. In addition, since the pixel signal is read from the photoelectric conversion element at the predetermined line position during the readout pause period, an effect that the synchronized readout process can be performed while suppressing the influence of the readout pause period is obtained. It is done.

  [Embodiment 8] Further, in the image pickup device according to Embodiment 8, the image pickup device according to Embodiment 6 or 7 includes a first addition value that is an addition value of the step width value and the count value of the base counter, and the start line. A first comparison means for comparing a value and a second addition value that is an addition value of the base counter count value; a third addition value that is an addition value of the line width value and the base counter count value; And a second comparison means for comparing with the maximum value of the count value of the base counter, wherein the reading suspension period setting means indicates that the comparison result of the first comparison means is obtained when the repetition mode is set. The offset value is equal to the count value of the base counter from the horizontal period in which the first addition value is larger and the comparison result of the second comparison means is larger in the third addition value. The period until the horizontal period is set as the reading pause.

  With such a configuration, it is possible to detect the final end of a plurality of repeated read cycles within the count period from the count value of the reference counter, which is the starting position of the counting operation of the address counter, to the maximum count value. Therefore, compared to the case where a readout pause period (wait) is inserted each time the readout process is performed once on the target area for repeated readout, a readout pause period in which repeated readout of pixel signals can be efficiently performed is provided. The effect that it can be set is obtained.

  In other words, when setting the readout pause period in order to synchronize the cycle in which the pixel signal is repeatedly read a plurality of times and the count cycle (frame cycle) of the reference counter, the readout is repeated as much as possible in each frame period from the viewpoint of reading out information. Since it is desirable that the number of times of performing the above is large, repeated reading is continuously performed until the last minute in each frame period within a range not exceeding this value on the basis of the maximum count value of the reference counter.

  [Mode 9] Further, in the image pickup device according to mode 9, in the image pickup device according to any one of modes 6 to 8, a first addition value that is an addition value of the step width value and the count value of the address counter, A third comparison means for comparing the magnitude of a fourth addition value that is an addition value of the start line value and the line width value; a maximum value of the count value of the base counter; the line width value; and the base counter. And a fourth comparison means for comparing the fourth addition value with the fifth addition value, which is an addition value to the count value, and the read pause period setting means is set to the repeat mode. Sometimes, the comparison result of the third comparison means is greater for the first addition value, and the comparison result of the fourth comparison means is greater than the offset value from a horizontal period in which the fifth addition value is greater. The base Setting the period until the horizontal period count value of the counter and match as the reading pause.

  With such a configuration, a plurality of count periods in the count period from the value of the reference counter that is the start position of the count operation of the address counter of the current frame to the value of the reference counter that is the start position of the operation of the next frame Since the final end of the repeated read cycle can be detected, the pixel signal of the pixel signal is compared with the case where the read pause period (wait) is inserted each time the read process is performed once on the target region of the repeated read. There is an effect that it is possible to set a reading pause period in which repeated reading can be performed efficiently.

In other words, when setting the readout pause period in order to synchronize the cycle in which the pixel signal is repeatedly read a plurality of times and the count cycle (frame cycle) of the reference counter, the readout is repeated as much as possible in each frame period from the viewpoint of reading out information. Since it is desirable that the number of times of performing the above is larger, repeated reading is performed continuously from the start position of the current frame period to the start position of the next frame period with reference to the start position of the address counter count operation. To do.
In particular, when the offset value is a relatively large value, it is possible to set a reading pause period that allows efficient repeated reading.

  [Mode 10] In order to achieve the above object, the imaging device according to mode 10 includes a photoelectric conversion unit having a configuration in which a plurality of photoelectric conversion elements that convert received light into charges and store them in a matrix. In each horizontal scanning period, non-destructive readout processing of accumulated charges and reset of accumulated charges are performed in a time-division manner for a predetermined line among a plurality of lines formed by the photoelectric conversion elements of the photoelectric conversion unit. An imaging device capable of performing processing, wherein the readout pause period setting means for setting a readout pause period, which is a period for temporarily stopping regular readout processing of the pixel signal in each frame period, and the set Dummy readout means for reading out the pixel signal from the photoelectric conversion element at a predetermined line position in the readout suspension period.

  With such a configuration, the reading pause period (wait period) can be set by the reading pause period setting means when the pixel signal is normally read out. When the readout pause period is set, the photoelectric conversion element at a predetermined line position is activated by the dummy readout control means during the set readout pause period, and non-destructive readout of the pixel signal is performed with respect to the photoelectric conversion element. Processing is executed. The pixel signal data becomes dummy data that is unnecessary for the subsequent image forming process (or any process in the subsequent stage). Therefore, for example, this data is not output to the subsequent processing unit, or is discarded by the subsequent processing unit.

  In other words, the non-destructive readout process of the pixel signal is executed from the photoelectric conversion element at the predetermined line position even in the readout pause period, so that a period in which the readout process of the pixel signal is not performed does not occur. it can. That is, it is possible to prevent a period during which the drive voltage is not applied to the common line used when reading the pixel signal from each photoelectric conversion element. As a result, the driving voltage can be stably applied to the common line serving as the transmission path of the pixel signal, so that an adverse effect such as fluctuation of the accumulated charge amount caused by the uneven application voltage can be suppressed. It is done.

  [Mode 11] In order to achieve the above object, the image sensor driving method according to mode 11 is a photoelectric device having a configuration in which a plurality of photoelectric conversion elements for converting received light into electric charges and storing them are arranged in a matrix. A pixel signal having a level corresponding to a plurality of accumulated charge amounts in a time-division manner with respect to a predetermined line in a plurality of lines formed by the photoelectric conversion element of the photoelectric conversion unit in each horizontal scanning period. A method for driving an image sensor capable of performing non-destructive readout processing, wherein a readout suspension period setting step for setting a readout suspension period, which is a period during which the readout processing is suspended in each frame period, and the set readout And a dummy reading step of reading out the pixel signal from the photoelectric conversion element at a predetermined line position in the pause period.

  With such a configuration, operations and effects equivalent to those of the image sensor of aspect 10 can be obtained.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. 1 to 5 are diagrams showing a first embodiment of an imaging device and a driving method of the imaging device according to the present invention.
First, the configuration of the image sensor according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of an image sensor 100 according to the present invention.

  The image sensor 100 is an image sensor that controls the exposure time by a rolling shutter system, and as shown in FIG. 1, a communication unit 10 that transmits and receives data to and from an external system controller (not shown), and a system controller Register 11 for storing various data from, a timing control unit 12 for controlling the operation timing of each unit, and a sensor cell line position to be processed in a stored cell read-out process and a stored charge reset process in a sensor cell array 15 to be described later A read / reset line address generation unit 13 for generating an address indicating the signal and a signal for driving the sensor cell of the selected line are generated based on the selection signal from the read / reset line address generation unit 13 and the control signal from the timing control unit 12 Driving pulse generator 14 and sensor cell array 1 When configured to include a horizontal transfer portion 16 for outputting an image signal data comprised of read from the sensor cells of the selected line charge (analog data) in units of lines.

The communication unit 10 receives control data for controlling the operation of the address counter in the read / reset line address generation unit 13 from a system controller (not shown) and stores it in the register 11.
The timing control unit 12 generates drive signals (pixel clock, horizontal synchronization signal, vertical synchronization signal) for driving the read / reset line address generation unit 13, the drive pulse generator 14, and the horizontal transfer unit 16, and these drive signals. Is output to each of the above-described units.

  Based on the selection signal from the read / reset line address generation unit 13, the drive pulse generator 14 reads out the charge accumulated in the sensor cell selected by the selection signal and empties the charge accumulated in the sensor cell. A drive pulse signal for executing (resetting) a reset process is generated, and the generated drive pulse signal is output to the sensor cell array 15.

  The sensor cell array 15 includes a plurality of sensor cells (pixels) configured using CMOS in a matrix, and address lines, reset lines, and readout lines are commonly connected to the sensor cells for each line. Various drive pulse signals are transmitted to the sensor cells constituting each line via the three control lines. When the address line and the readout line become valid, the accumulated charge is transferred to the horizontal transfer unit 16 through the readout line.

  The horizontal transfer unit 16 stores pixel signal data read from each pixel of the selected line of the sensor cell array 15 in a line memory (not shown) for each pixel line, and outputs the stored pixel signal data. Here, there are as many line memories as there are selection line address generation circuits for readout processing to be described later, and pixel signal data is output using separate line memories for each readout processing performed in each time division.

Next, the internal configuration of the read / reset line address generator 13 will be described with reference to FIGS.
Here, FIG. 2 is a block diagram showing an internal configuration of the read / reset line address generation unit 13. FIG. 3 is a diagram illustrating an operation example of the time division selector.
As shown in FIG. 2, the read / reset line address generation unit 13 includes a counter update clock generation unit 130, a reference counter 131, a selection line address generation unit 132, and an address decoding unit 133.

  Based on the pixel clock (CLK) and horizontal synchronization signal (HSYNC) input from the timing controller 12, the counter update clock generator 130 generates a clock that becomes a scanning cycle of one line of sensor cells in the sensor cell array 15. Are output to each selection line address generation circuit (described later) of the reference counter 131 and the selection line address generation unit 132. For example, the horizontal synchronization signal from the timing control unit 12 may be output as it is, or the horizontal synchronization signal may be resampled with an internal operation clock to newly generate and output a counter update clock. In the present embodiment, the latter method is used.

  The reference counter 131 performs a counting operation based on the counter update clock input from the counter update clock generation unit 130 and the pixel clock and vertical synchronization signal (VSYNC) input from the timing control unit 12. Specifically, the reference counter 131 repeatedly counts the range (20) of “the number of effective pixel lines (for example, 16) + the number of return pixel lines (for example, 4)” for the sensor cell array 15.

  The selection line address generation unit 132 includes the same number of selection line address generation circuits as the number of time divisions in the pixel signal reading process and the stored charge reset process according to the accumulated charge amount in one horizontal scanning period. Each selected line address generation circuit is independently controlled based on the various control data stored in 11, and an address indicating the line position to be processed is generated. In the present embodiment, each horizontal scanning period is equally divided into four periods. Therefore, the selection line address generation unit 132 has a configuration including four circuits, selection line address generation circuits 132a to 132d. Of these four circuits, at least one is a reset processing circuit and the rest is a read processing circuit.

The address decoding unit 133 includes a time division selector 133a and an address decoding circuit 133b.
The time division selector 133a selects the selection line address generation circuits 132a to 132d one by one in time division, and outputs the address (count value) generated by the selected selection line address generation circuit to the address decoding circuit 133b. To do.

Specifically, the selection line address generation circuit to be selected in each of the four periods in each horizontal scanning period is determined in advance, and the time division selector 133a selects the selection line corresponding to each period based on the determined content. The address generation circuit is sequentially selected.
For example, as shown in FIG. 3, when one horizontal scanning period is time-divided into four periods A to D, the selected line address generation circuit 132a is divided into the divided period B in the divided period A formed by the time division. The same 132b is selected in the divided period C, and the same 132c is selected in the divided period D, and the output value (address) of the selected circuit is output to the address decoding circuit 133b. Accordingly, in one horizontal scanning period, four addresses are sequentially output to the address decoding circuit 133b in a time division manner.

Further, when a control signal for invalidating the selection line address is input from the selection line address generation circuits 132a to 132d, the time division selector 133a replaces the address value from the corresponding selection line address generation circuit with a subsequent stage. A specific address value for reading out a dummy pixel signal which is unnecessary in the processing is output to the address decoding circuit 133b.
This specific address value may be an address value of an arbitrary line, but in the present embodiment, the address of a line at a specific position (for example, line number 1) in a light-shielded area (OB area) in the sensor cell array 15. Value.

Note that switching of the time division selector 133a may be controlled using an external synchronization signal. Although not shown, the circuit scale can be reduced by decoding the count value of the reference counter 131 and generating the switching control signal of the time division selector 133a.
When the address (count value) is input from the time division selector 133a, the address decoding circuit 133b generates a selection signal for enabling the sensor cell at the line position indicated by the input address in the sensor cell array 15 as a drive pulse. Output to the generator 14.

Next, the internal configuration of the selected line address generation circuit 132a will be described with reference to FIG.
Here, FIG. 4 is a block diagram showing an internal configuration example of the selected line address generation circuit 132a in the case of up-counting.
As shown in FIG. 4, the selection line address generation circuit 132a includes a comparison circuit A1320, a control unit 1321, an initial value generation circuit 1322, an addition circuit A1323, a selector circuit 1324, an address counter 1325, and an addition circuit B1326. And a comparison circuit B1327.

In the present embodiment, the counter update clock is a clock having one horizontal scanning period as one clock cycle, and the count value in the address counter 1325 is updated at the rising edge of the counter update clock. Therefore, it is not necessary to define a period during which the counter update clock is “High”.
Here, the register 11 stores setting information, an offset value, a start line value, a line width value, a step value, a wait value, and the like for each operation mode as control data for the address counter 1325. These pieces of information are set by the user for each of the selection line address generation circuits 132a to 132d via an input device (not shown) or an external device (such as a system controller). These are used for various controls such as control of the count operation of the address counter 1325 and control of dummy read processing.

In the present embodiment, the operation mode includes a normal mode, a repetition mode, and an initial value addition mode. Details of these will be described later.
The offset value is used to determine the start timing of the count operation of the address counter 1325.
The start line value is a value for setting an initial value of the count value of the address counter 1325 and a count width (range) for counting.

The line width value is a value for setting a count width (range) for the address counter 1325 to count. Specifically, the count width is set from the start line value and the line width value.
The step value is a value for setting the step width when the address counter 1325 counts up.

When the repeat mode or the initial value addition mode is set, the wait value is a wait period between each count operation when repeating the count operation performed within the range from the initial count value to the maximum count value ( This is a value for inserting a reading suspension period.
The comparison circuit A 1320 is a circuit that compares the offset value acquired from the register 11 with the count value of the reference counter 131. When the offset value and the count value match, a signal that notifies this is sent to the control unit 1321. Output.

  The control unit 1321 controls the count operation of the address counter 1325 by controlling the operations of the initial value generation circuit 1322, the addition circuit A 1323, and the selector circuit 1324 based on the comparison results of the comparison circuit A 1320 and the comparison circuit B 1327, and the like. Further, in response to the counting operation of the address counter 1325, a control signal for controlling the validity / invalidity of the selected line address is output to the address decoding unit 133.

Specifically, a selection line address valid / invalid control signal for invalidating the selected address is output to the address decoding unit 133 in a read suspension period or a period in which addition prohibition is set. At other times, a selection line address valid / invalid control signal for validating the selected address is output to the address decoding unit 133.
The initial value generation circuit 1322 outputs the start line value stored in the register 11 to the selector circuit 1324, and also sets the initial value based on the step value stored in the register 11 when the initial value addition mode is set. Is a circuit that generates

The addition circuit A 1323 is a circuit that adds the count value of the address counter and the step value stored in the register 11 and outputs the first addition value A that is the addition result to the comparison circuit B 1327.
The selector circuit 1324 sends either the first addition value A input from the addition circuit A or the value input from the initial value generation circuit 1322 to the address counter 1325 in response to a control signal from the control unit 1321. It is a circuit to output.

The address counter 1325 has a function of outputting the value input from the selector circuit 1324 to the address decoding unit 133 as an address of the selected line, and outputting to the adder circuit A 1323.
The addition circuit B 1326 is a circuit that adds the start line value and the line width value stored in the register 11.

The comparison circuit B1327 compares the first addition value A, which is the addition result of the addition circuit A1323, with the second addition value B, which is the addition result of the addition circuit B1326, and compares “first addition value A ≧ second addition value B”. ”Is a circuit that detects the occurrence of the error and notifies the control unit 1321 of the detection.
Hereinafter, common operations in the normal mode, the repetition mode, and the initial value addition mode will be described.

  First, when the control unit 1321 detects the start of the operation, the control unit 1321 enters a “wait for start” state. In this state, when a signal notifying that the offset value matches the count value of the reference counter 131 is input from the comparison circuit A 1320, the start line value obtained from the register 11 is directly input to the initial value generation circuit 1322. An instruction signal is output so as to be input to the selector circuit 1324.

When the instruction signal is input, the initial value generation circuit 1322 outputs the start line value acquired from the register 11 to the selector circuit 1324 as it is.
Further, the control unit 1321 controls the selector circuit 1324 so that the start line value input from the initial value generation circuit 1322 to the selector circuit 1324 is output to the address counter 1325 as it is. Specifically, when the offset value and the count value match, a signal notifying that is output to the selector circuit 1324.

Thus, the selector circuit 1324 outputs the start line value input from the initial value generation circuit 1322 to the address counter 1325, and the start line value is set as the initial value of the count value in the address counter 1325.
Further, the control unit 1321 outputs a control signal for validating the selected line address to the address decoding unit 133 at the timing of updating (counting up) the address counter 1325 (the rising edge of the counter update clock), Change the state to "count up mode".

When the time division selector 133a in the address decoding unit 133 receives a selection line address valid / invalid control signal for validating the selected line address from the control unit 1321, the address decoding unit 133a decodes the address value from the corresponding selection line address generation circuit. Output to the circuit 133b.
The address decoding circuit 133b performs a decoding process on the address value input from the time division selector 133a. Specifically, the decoding process is a process of outputting a selection signal for enabling the sensor cell at the line position indicated by the input address value to the drive pulse generator 14. Based on the selection signal from the address decoding circuit 133b, the driving pulse generator 14 outputs a driving pulse signal corresponding to a designated process in the reading process or the reset process to the sensor cell array 15.

  When the internal state is changed to “count-up mode”, the adding circuit A 1323 adds the step value acquired from the register 11 to the count value from the address counter 1325, and the result of the addition is the first value. The 1 addition value A is output to the selector circuit 1324 and the comparison circuit B 1327, respectively. However, when there is an instruction “addition prohibition” from the control unit 1321, the count value input from the address counter 1325 is output to the selector circuit 1324 and the comparison circuit B1327 as it is.

On the other hand, the addition circuit B 1326 adds the start line value and the line width value acquired from the register 11, and inputs the second addition value B, which is the addition result, to the comparison circuit B 1327. As a result, the second addition value B becomes “maximum count value (last line address value) +1”.
The comparison circuit B1327 compares the second addition value B input from the addition circuit B1326 with the first addition value A input from the addition circuit A1323, and “first addition value A ≧ second addition value B” is satisfied. When this happens, a signal notifying the controller 1321 of this is output.
Upon receiving the above notification from the comparison circuit B 1327, the control unit 1321 performs an operation according to the setting mode stored in the register 11.

Next, the operation in the normal mode will be described.
The normal mode indicates a state in which neither the repeat mode nor the initial value addition mode is set. Every time the reference counter 131 matches the offset value in the address counter 1325, the above “first addition value A ≧ second addition value”. In this mode, a count-up operation is executed until “B” is detected.

Specifically, when the above-mentioned “first addition value A ≧ second addition value B” is detected, the control unit 1321 returns to the “waiting for start” state again at the rising edge of the counter update clock, and the selected line A control signal for invalidating the address is output to the address decoding unit 133.
When the reference counter 131 and the offset value again match (receives a match notification from the comparison circuit A 1320), the initial value generation circuit 1322 directly receives the start line value input to the initial value generation circuit 1322 as a selector. An instruction signal is output so as to be input to the circuit 1324, and a count-up operation similar to the above is executed until “first addition value A ≧ second addition value B” is detected.

Next, the operation in the repetition mode will be described.
The repeat mode is a mode in which the address counter 1325 continuously repeats the count-up operation until “first addition value A ≧ second addition value B” within the range from the initial value to the maximum count value. It is.
Specifically, when the repeat mode is set, when the control unit 1321 receives a notification of “first addition value A ≧ second addition value B” from the comparison circuit B 1327, first, the control unit 1321 obtains a wait value from the register 11. The counter update clock is counted as many times as the number of wait values, and then the start line value is set in the address counter 1325 via the initial value generation circuit 1322 and the selector circuit 1324 in the same manner as described above. The count operation is executed again from the value.

  The weight value may be set by the user via an input device (not shown) or the like, or based on the step value, the start line value, the line width value, the offset value, etc., for example, in the control unit 1321 or the like. An arithmetic process may be performed to automatically set an appropriate value. Here, the appropriate value is a value such that the repetition cycle and the count cycle of the reference counter 131 are synchronized.

The control unit 1321 outputs a selection line address valid / invalid control signal that invalidates the address of the selected line to the address decoding unit 133 simultaneously with starting the wait operation. When the wait value is “0”, the wait operation is omitted and the initial value is set.
When receiving the control signal for invalidating the selected line address from the control unit 1321, the time division selector 133a in the address decoding unit 133 outputs the address value of a specific line in the OB area to the address decoding circuit 133b.

When the address value of a specific line in the OB area is input from the time division selector 133a, the address decode circuit 133b outputs a control signal for activating the line corresponding to the input address value to the drive pulse generator 14. To do.
On the other hand, when a control signal for activating a specific line in the OB area is input from the address decode circuit 133b, the drive pulse generator 14 activates the specific line in the OB area and also outputs a pixel from the sensor cell of the line. A drive pulse signal for reading the signal is generated, and the generated drive pulse signal is supplied to the sensor cell array 15.

As a result, during the period in which the counter update clock is counted as many times as the number of wait values, the pixel signal is read from a specific line in the OB area.
In addition, when the repeat mode is set, the control unit 1321 receives a notification from the comparison circuit A 1320 indicating that a match between the offset value and the count value of the reference counter 131 is detected only for the first time. Subsequent notifications are invalid.

Next, the operation in the initial value addition mode will be described.
In the initial value addition mode, when the value of the step width is “2” or more, the address counter 1325 is caused to repeatedly perform the counting operation, and the comparison circuit B is operated until the value of the step width matches the number of repetitions. Each time a count-up operation is performed until the comparison result becomes “first addition value A ≧ second addition value B”, “1” is added to the initial value of the current address counter 1325, and the value after the addition This is a mode in which the next counting operation is performed using as a new initial value.

  Specifically, when the initial value addition mode is set, when the control unit 1321 receives a notification of “first addition value A ≧ second addition value B” from the comparison circuit B 1327, the control unit 1321 first waits from the register 11. A value is acquired, the counter update clock is counted for the number of times of the wait value, and then an instruction signal for causing the initial value generation circuit 1322 to execute an initial value addition process is output.

When the instruction signal is input from the control unit 1321, the initial value generation circuit 1322 adds “1” to the current initial value, and outputs the addition result to the selector circuit 1324 as a new initial value.
Further, the control unit 1321 controls the selector circuit 1324 so that a new initial value input from the initial value generation circuit 1322 to the selector circuit 1324 is output to the address counter 1325 as it is.

Thus, the selector circuit 1324 outputs the new initial value input from the initial value generation circuit 1322 to the address counter 1325, and the new initial value is set as the initial value of the count value in the address counter 1325.
The wait operation and the initial value addition operation are repeatedly executed as many times as the step width value. When the repetition count value becomes the same value as the step width value, the control unit 1321 returns the initial value after the addition to the initial initial value before the addition, and again counts the same as the above from the initial value. The operation and the initial value addition operation are executed. For example, when the step width is “4” and the initial initial value before addition is “1”, the initial initial value “1” and a new initial value “2” obtained by incrementing the initial value by one. , “3” and “4” are sequentially counted, and then the initial value “4” in the fourth count operation is returned to the initial initial value “1”, and the same counting operation is repeated again. .

In addition, when down-counting, it changes to the process which subtracts a step value and a line width value, respectively. Specifically, the processing of the adder circuit B 1326 is “start line value−line width value”. Since it is a down count, the operation of the comparison circuit B 1327 is changed to “first addition value A ≦ second addition value B”, and the initial value generation circuit 1322 sets “start line value” as an initial value. After the comparison circuit A 1320 detects the coincidence and notifies the control unit 1321, the control unit 1321 shifts to the down-count mode. Other operations are basically the same as the up-count.
Further, the selection line address generation circuits 132b to 132d have the same configuration as the selection line address generation circuit 132a, and thus description thereof is omitted.

Next, a more specific operation of the present embodiment will be described based on FIG.
Here, FIG. 5A is a diagram illustrating an example of a pixel line configuration, FIG. 5B is a diagram illustrating an example of control data, and FIG. 5C is an example of an output value of each counter. FIG.

Here, the selection line address generation circuit 132a is used for reset processing, and the selection line address generation circuits 132b to 132d are used for read processing.
Further, as shown in FIG. 5A, the effective pixel lines are line numbers 1 to 20, and the pixel lines in the OB area are line numbers 1 to 2 and 19 to 20. Further, among the effective pixel lines, the line numbers 4 to 6 are the high-speed read target pixel lines, and the line numbers 1 to 20 are the normal read target pixel lines. The reference counter 131 is controlled so as to repeatedly perform the counting operation in the range of “0” to “19” with the step width “1”.

First, control data is transmitted from the system controller to the image sensor 100, and the control data is stored in the register 11 via the communication unit 10.
As shown in FIG. 5B, the control data has an offset value (offset in FIG. 5B) of “0” for the selected line address generation circuit 132a and “3” for the circuit 132b. "19" is set (stored) for the circuit 132c and "7" is set for the circuit 132d. The start line value (initial value in FIG. 5B) is set to “1” for the selected line address generation circuits 132a to 132c, and “4” is set to the selected line address generation circuit 132d. Has been. The line width value (width in FIG. 5B) is set to “20” for the selected line address generation circuits 132a to 132c and “3” is set to the selected line address generation circuit 132d. ing. The step value (step in FIG. 5B) is set to “1” for the selected line address generation circuits 132a to 132d, and the wait value (wait in FIG. 5B) is the selected line. “1” is set for the address generation circuit 132d. The repeat mode is set for the selected line address generation circuit 132d, and the normal mode is set for the remaining circuits. Hereinafter, in order to distinguish the selection line address generation circuits 132a to 132d having the same circuit configuration, the components 1320 to 1327 of the selection line address generation circuits 132a to 132d are denoted by a to d after the respective symbols. explain.

When receiving an operation start instruction from the system controller, each of the selected line address generation circuits 132a to 132d of the read / reset line address generation unit 13 shifts to a start waiting state.
Then, as shown in FIG. 5C, when the reference counter 131 (BC in the figure) starts the count operation and the count value becomes “0”, the offset value “0” of the selected line address generation circuit 132a is set. Since they match, the start line value “1” is set as an initial value in the address counter 1325a. Since the step width of the selected line address generation circuit 132a is “1”, the count is incremented by one from the initial value “1” to the count width value (maximum count value) “20” (FIG. 5C). CLS in the middle). Here, the update timing of the reference counter 131 is the same as the update timing of each address counter.

  On the other hand, the reference counter 131 counts up one by one in accordance with the counter update clock, and when the count value becomes “3”, it matches the offset value “3” of the selected line address generation circuit 132b. The value “1” is set as an initial value in the address counter 1325b. Since the step width of the selected line address generation circuit 132b is “1”, the address counter 1325b counts up one by one from the initial value “1” to the count width value (maximum count value) “20” (FIG. 5). (LOAD) in (c)).

  The reference counter 131 counts up one by one in accordance with the counter update clock, and when the count value becomes “7”, it matches the offset value “7” of the selected line address generation circuit 132d. The value “4” is set as an initial value in the address counter 1325d. Since the step width of the selected line address generation circuit 132d is “1”, the address counter 1325d counts up from the initial value “4” to the count width value (maximum count value) “6” by one.

  While the count-up operation is being performed, the adder A1323d adds the count value of the address counter 1325d and the step value, and outputs the first addition value A that is the addition result to the comparator B1327d. Further, in the adding circuit B 1326d, “start line value = 4” and “line width value = 3” are added, and a second addition value B (“7”) as a result of the addition is output to the comparing circuit B 1327d. .

  In the comparison circuit B1327d, the addition result “7” (second addition value B) of the addition circuit B1326d is compared with the addition result (first addition value A) of the addition circuit A1323d, and “first addition value A ≧ second addition” is compared. When the “value B” is detected, a signal notifying that is output to the control unit 1321d. That is, when the count value of the address counter 1325d becomes “6”, the first addition value A of the addition circuit A1323d becomes “7”, and thus “7 ≧ second addition value B (= 7)”. Since the condition is satisfied, this is detected and a notification signal is notified to the control unit 1321d.

  Since the repeat mode is set, the control unit 1321d refers to the wait value stored in the register 11 at the timing of the rising edge of the counter update clock when receiving the above notification. Here, “wait value = 1” Therefore, a selected address valid / invalid control signal (L level signal) indicating invalidity of the selected line address is immediately output to the address decoding unit 133.

  When the selection line address valid / invalid control signal indicating invalidity of the selected line address is input from the control unit 1321d, the address decoding unit 133 receives the OB area instead of the address value from the address counter 1325d in the time division selector 133a. The address of the line (here, “address of line number 1”) is output to the address decoding circuit 133b.

When the address value of the line number “1” is input, the address decoding circuit 133 b outputs a control signal that activates the address value to the drive pulse generator 14.
When the control signal for activating the line having the address value of the line number “1” is input from the address decoding circuit 133b, the drive pulse generator 14 activates the line at the corresponding line position, and the sensor cell of the line. A drive pulse signal for reading out the pixel signal is generated from the signal, and the generated drive pulse signal is supplied to the sensor cell array 15.

As a result, in the divided period D in the period corresponding to one counter update clock, the pixel signal is read from the line of line number 1 in the OB area via the readout line (transferred to the horizontal transfer unit 16).
Further, since the wait value is “1”, the initial value generation circuit 1322d and the selector circuit 1324d are controlled at the timing of the rising edge of the next counter update clock, and the start line value “1” is changed to the address counter 1325d. Set to. At the same time, a control signal indicating the validity of the selected line address is output to the address decoding unit 133.

By repeating the above processing, the output value of the address counter 1325d repeats the counting operation continuously as “4 → 5 → 6 → 7 → 4 → 5 → 6 → 7 →. However, when the count value is “7”, it is a readout suspension period, and during this period, the pixel signal is read from the line of the address (OB area) of the count value “1” (LOAD 3 in FIG. 5C). .
The shaded portion in FIG. 5C is a readout suspension period. When no pixel signal readout processing is performed during this period, the non-selected line affects the accumulated charge due to exposure. May change and cause image quality degradation. On the other hand, in the present embodiment, even during the readout pause period, any line in the regular readout process is always selected by selecting a line in the OB region and reading out the pixel signal from the selected line. Thus, the driving voltage for reading is applied to the common reading line, and it is possible to prevent the occurrence of a factor of image quality degradation such as non-uniformity in the amount of accumulated charge.

  On the other hand, the reference counter 131 counts up one by one in accordance with the counter update clock, and when the count value reaches “19”, it matches the offset value “19” of the selected line address generation circuit 132c. The value “1” is set as an initial value in the address counter 1325c. Since the step width of the selected line address generation circuit 132c is “1”, the address counter 1325c counts up one by one from the initial value “1” to the count width value (maximum count value) “20” (FIG. 5). (C) in LOAD2).

  As described above, the image sensor 100 according to the present embodiment has a configuration in which the selection line address generation circuit is provided for the number of time divisions of the pixel signal readout process and the reset process, and each operation can be controlled independently. Various readout processes such as reading out charges repeatedly from a part of the sensor cells at high speed, reading out charges while skipping an arbitrary number of rows, and performing interlaced reading can be performed.

Furthermore, since each selected line address generation circuit can be controlled independently, only a part of the selected line address generation circuits can be stopped, changed in settings, and operated. It is also possible to switch and output captured images according to the situation.
In addition, since the address counter for read processing and the address counter for reset processing can be controlled independently, the read timing and reset timing can be accurately controlled.

Further, since the output values of the plurality of selection line address generation circuits (132a to 132d) are selected by time division by the time division selector 133a, and the selected output values are output to one address decoding circuit 133b. The circuit configuration can be simplified.
Furthermore, the imaging device 100 of the present embodiment synchronizes the cycle with the count cycle of the reference counter when repeatedly reading out pixel signals at a high speed with respect to some sensor cell lines of the sensor cell array 15. Can be set. Then, based on the set weight value, a reading suspension period corresponding to the weight value can be inserted every time some lines are read. Therefore, by setting the wait value, it is possible to easily synchronize the cycle of repeated reading and the cycle of the reference counter.

Furthermore, since the image sensor 100 of this embodiment can read pixel signals from a predetermined line (in the above embodiment, a line in the OB region) during the readout pause period, stable driving to the readout line is possible. While applying a voltage, it is possible to repeatedly read out pixel signals with a reading pause period in between.
In the said 1st Embodiment, the sensor cell array 15 respond | corresponds to the photoelectric conversion part of any one of form 1, 2, 10 and 11, and a sensor cell is either of form 1, 2, 10 and 11. 1 corresponds to the photoelectric conversion element described in 1.

  In the first embodiment, the read / reset line address generator 13 corresponds to the address generator described in the first or third aspect, and the control data includes the second, third, fourth, fifth, sixth, 7 corresponds to the control information described in any one of 7 and 10, and the comparison circuit A 1320, the control unit 1321, the addition circuit B 1326, and the comparison circuit B 1327 correspond to the operation control unit described in any one of the forms 3 to 7. , The initial value generation circuit 1322, the addition circuit A 1323, the selector circuit 1324, and the address counter 1325 correspond to the address counter described in any one of the forms 3 to 7, and the time division selector 133a includes the selection unit described in the form 3. The address decoding circuit 133b corresponds to the address decoding means described in any one of the forms 1, 3, and 7, and the reference counter 13 Corresponds to the reference counter according to Embodiment 4.

  Further, in the first embodiment, the setting of the wait value in the register 11 and the setting process of the reading suspension period according to the wait value in the control unit 1321 are described in any one of the first, seventh, and tenth embodiments. Corresponding to the read pause period setting means or the read pause period setting step described in the eleventh mode, the process of outputting the selection line address valid / invalid control signal for invalidating the address of the selected line from the control unit 1321 to the time division selector 133a. A process for outputting an address value of a specific line (an OB area line) to the address decoding circuit 133b in response to an invalid selection line address valid / invalid control signal in the time division selector 133a, and a specification for the drive pulse generator 14 The drive line that activates the active line and reads out the pixel signal from the activated line. Processing for generating a scan, the dummy read control means according to Embodiment 8, corresponding to the dummy reading step according to the dummy read means or form 11 according to Embodiment 10.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to the drawings. 6 to 7 are diagrams showing a second embodiment of the imaging device and the driving method of the imaging device according to the present invention.

  In the first embodiment, when the repetitive mode is set, the reading pause period corresponding to the wait value is set every time reading of the pixel signal from the line of a part of the region in the sensor cell array 15 is completed. In this period, dummy pixel signals are read out. In contrast, in the present embodiment, during repeated reading in each frame, pixel signals are read continuously without a reading pause period, and the maximum of the reference counter when the reading is performed continuously is performed. The maximum end position of repeated reading with respect to the count value (end position of the frame period) is detected, and the period from the end position to the offset value of the next frame is set as the wait period.

  For example, when reading is repeated for 3 lines of 4 to 6 lines, “4 → 5 → 6” → “4 → 5 → 6” → “4 → 5 → 6” → “4” in each frame period. → 5 → 6 ”→“ 4 → 5 → 6 ”→ 4... And the partial area“ 4 → 5 → 6 ”are repeatedly read out. In this case, the maximum end position can be repeatedly performed within a period from the offset value of the reference counter to the maximum value of the counter (corresponding to the maximum number of lines of the sensor cell array 15). This is the end position for the maximum number of repetitions.

Further, the image sensor of the present embodiment is different from the image sensor 100 of the first embodiment except that the configuration of the selection line address generation circuit is partially different.
In the following, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted as appropriate, and different parts will be described in detail.
First, the configuration of the selection line address generation circuit 132a of the present embodiment will be described with reference to FIG. FIG. 6 is a block diagram showing a configuration of the selection line address generation circuit 132a according to the present embodiment when up-counting is performed.

  As shown in FIG. 6, the selection line address generation circuit 132a of this embodiment includes a comparison circuit A 1320, a control unit 1321, an initial value generation circuit 1322, an addition circuit A 1323, a selector circuit 1324, and an address counter 1325. An addition circuit B1326, a comparison circuit B1327, a MAX_BC detection circuit 1328, an addition circuit C1329, and a comparison circuit C1330.

That is, the configuration is such that the MAX_BC detection circuit 1328, the addition circuit C1329, and the comparison circuit C1330 are added to the selection line address generation circuit 132a in the first embodiment.
The addition circuit A 1323 is a circuit that adds the count value of the address counter and the step value stored in the register 11 and outputs the first addition value A that is the addition result to the comparison circuit B 1327.

The adder circuit B1326 is a circuit that adds the start line value and the line width value acquired from the register 11, and outputs the second addition value B, which is the addition result, to the comparison circuit B1327. The second addition value B is “maximum count value (last line address value) +1”.
The comparison circuit B1327 compares the second addition value B input from the addition circuit B1326 with the first addition value A input from the addition circuit A1323, and “first addition value A ≧ second addition value B” is satisfied. When this happens, a signal notifying the controller 1321 of this is output.

The MAX_BC detection circuit 1328 detects the maximum value of the reference counter 131 and outputs the detected maximum value to the comparison circuit C.
The adder circuit C1329 adds the line width value and the current count value of the reference counter 131.
The comparison circuit C1330 is a circuit that compares the third addition value C, which is the addition processing result of the addition circuit C1329, with the maximum value (MAX_BC) detected by the MAX_BC detection circuit 1328, and the third addition value C is greater than or equal to the maximum value. When it becomes, the signal which notifies that is output to the control part 1321.

In addition to the operation of the control unit of the first embodiment, the control unit 1321 of the present embodiment controls the address decoding unit 133 based on the comparison result of the comparison circuit B1327 and the comparison result of the comparison circuit C1330. A selection line address valid / invalid control signal for invalidating the selected line address is output, thereby setting a read pause period.
Specifically, a notification from the comparison circuit B 1327 (detection notification of “first addition value A ≧ second addition value B”) and a notification from the comparison circuit C 1330 (detection notification of “third addition value C ≧ MAX_BC”) Based on the above, when these conditions are satisfied simultaneously, the position of the count value of the reference counter at this time is set as the maximum end position of repeated reading, and the offset in the next frame from the next count value of the reference counter 131 In a period until the value matches the count value of the reference counter, a selection line address valid / invalid control signal for invalidating the selected address is output to the address decoding unit 133. In other words, when detecting the maximum end position, the control unit 1321 sets a period from the next count value of the reference counter 131 until the count value and the offset value match in the next frame as a reading suspension period.

  Thus, the repeated reading process is interrupted with the vertical synchronization signal as a reference, and the repeated reading from the start position is continuously performed again, with the period from that point to the count start position of the address counter 1325 determined by the offset value as the read pause period. be able to. The merit of this method is that it is easy to identify and synchronize the head image of consecutive frame images.

Note that the selection line address generation circuits 132b to 132d have the same configuration as the selection line address generation circuit 132a, and thus the description thereof is omitted.
The operations of the address decoding unit 133 and the drive pulse generator 14 are the same as those in the first embodiment, and a description thereof will be omitted.

Next, the operation of this embodiment will be described with reference to FIG.
Here, FIG. 7A is a diagram illustrating an example of a pixel line configuration, FIG. 7B is a diagram illustrating an example of control data, and FIG. 7C is an example of an output value of each counter. FIG.
In FIG. 7, the operations of CLS, LOAD1, and LOAD2 are the same as those in the first embodiment, and therefore, the operation of LOAD3 (selected line address generation circuit 132d) will be mainly described below. In addition, in order to distinguish the selection line address generation circuits 132a to 132d having the same circuit configuration, the components 1320 to 1330 of the selection line address generation circuits 132a to 132d are denoted by a to d after the respective symbols. explain.

  As shown in FIG. 7B, the control data for the selected line address generation circuit 132d is an offset value (offset in FIG. 7B) “6” and a start line value (in FIG. 7B). Initial value) “4”, line width value (width in FIG. 7B) “3”, step value (step in FIG. 7B) “1”, weight value (in FIG. 7B) Wait) “0” is set. Furthermore, a repeat mode is set.

  First, when the imaging device 100 is reset, the MAX_BC detection circuits 1328a to 1328d that hold the maximum value of the reference counter 131 in the selection line address generation circuits 132a to 132d are initialized. Since the control timing of the horizontal synchronization signal (HSYNC) and the vertical synchronization signal (VSYNC) is fixed (stable operation) when the image sensor 100 is in an operating state, the MAX_BC detection circuits 1328a to 1328d find the maximum value of the reference counter 131. Start processing. At the update timing of the reference counter 131, the MAX_BC held inside is compared with the count value of the input reference counter 131, and when the input count value is larger than the held MAX_BC, the hold is held. Updating MAX_BC. Thereby, MAX_BC is determined.

Next, upon receiving an operation start instruction from the system controller, each of the selected line address generation circuits 132a to 132d of the read / reset line address generation unit 13 shifts to a start waiting state.
Then, as shown in FIG. 7C, when the reference counter 131 (BC in the figure) starts the count operation and the count value becomes “6”, the offset value “6” of the selected line address generation circuit 132d is obtained. Since they match, the start line value “4” is set as an initial value in the address counter 1325d. Since the step width of the selected line address generation circuit 132d is “1”, the address counter 1325d counts up from the initial value “4” to the count width value (maximum count value) “6” by one.

  Here, since the wait value is “0”, when the count value becomes “6”, the selector next outputs the initial value “4” generated by the initial value generation circuit 1322d to the address counter 1325d. The circuit 1324d is controlled. Therefore, the count-up operation from the initial value “4” to the maximum value “6” is repeated continuously in order of →→ 4 → 5 → 6 → 4 → 5 → 6 → 4 → 5 → 6 →. Is called.

  While the count-up operation is being performed, the adder A1323d adds the count value of the address counter 1325d and the step value, and outputs the first addition value A that is the addition result to the comparator B1327d. Further, in the adding circuit B 1326d, “start line value = 4” and “line width value = 3” are added, and a second addition value B (“7”) as a result of the addition is output to the comparing circuit B 1327d. . Furthermore, in the addition circuit C1320d, the line width value “3” and the count value of the reference counter 131 are added, and a third addition value C as a result of the addition is output to the comparison circuit C1330d.

The comparison circuit B1327d compares the addition result “7” (second addition value B) of the addition circuit B1326d with the addition result (first addition value A) of the addition circuit A1323d.
The comparison circuit C1330d compares the addition result (third addition value C) of the addition circuit C1329d with the maximum value “19” of the count value of the reference counter 131 input from the MAX_BC detection circuit 1328.

  Then, when “first addition value A ≧ second addition value B” is detected in the comparison circuit B1327d, a signal notifying that is output to the control unit 1321d. That is, when the count value of the address counter 1325d becomes “6”, the first addition value A of the addition circuit A1323d becomes “7”, and thus “7 ≧ second addition value B (= 7)”. Since the condition is satisfied, this is detected and a notification signal is notified to the control unit 1321d. This notification signal is output to the control unit 1321d every time the count value becomes “6”.

  On the other hand, when “the third addition value C ≧ MAX_BC (= 19)” is detected in the comparison circuit C1330d, a signal notifying that is output to the control unit 1321d. That is, when the count value of the reference counter 131 becomes “16”, “third addition value C (= 19) ≧ MAX_BC (= 19)” is satisfied, and this is detected, and the notification signal is sent to the control unit 1321d. Notice. This notification signal is output to the control unit 1321d every time it is counted up until the count value of the reference counter 131 reaches MAX_BC (= 19).

  When “first addition value A ≧ second addition value B” and “third addition value C ≧ MAX_BC (= 19)” are simultaneously established in the same count period, the control unit 1321d In the period from the count value until the offset value of the next frame coincides with the count value of the reference counter 131, a selection address valid / invalid control signal (L level) indicating invalidity of the selected line address to the address decoding unit 133 Signal). The period during which the selected address valid / invalid control signal is at the L level is the read suspension period.

  In the example of FIG. 7C, “first addition value A ≧ second addition value B (7)” and “third addition value C ≧ MAX_BC (= 19)” are satisfied simultaneously. When the count value becomes “18”. That is, when the count value of the reference counter 131 becomes “18”, “first addition value A (= 1 + 6 = 7) ≧ second addition value B (= 7)”, “third addition value C (= 3 + 18 = 21) ) ≧ MAX_BC (= 19) ”. The position where the count value of the reference counter 131 is “18” is the maximum end position of the repeated reading process.

  When the selection line address valid / invalid control signal indicating invalidity of the selected line address is input from the control unit 1321d, the address decoding unit 133 receives the OB area instead of the address value from the address counter 1325d in the time division selector 133a. The address of the line (here, “address of line number 1”) is output to the address decoding circuit 133b.

When the address value of the line number “1” is input, the address decoding circuit 133 b outputs a control signal that activates the address value to the drive pulse generator 14.
When the control signal for activating the line having the address value of the line number “1” is input from the address decoding circuit 133b, the drive pulse generator 14 activates the line at the corresponding line position, and the sensor cell of the line. A drive pulse signal for reading out the pixel signal is generated from the signal, and the generated drive pulse signal is supplied to the sensor cell array 15.

As a result, in the divided period D in the period corresponding to one counter update clock, the pixel signal is read from the line of line number 1 in the OB area via the readout line (transferred to the horizontal transfer unit 16).
In addition, the reading suspension period is a period from the count value “19” of the reference counter of the current frame to “6” in the next frame where the count value of the reference counter 131 matches the offset value. 6 ", the initial value generation circuit 1322d and the selector circuit 1324d are controlled at the timing of the rising edge of the next counter update clock to set the start line value" 4 "in the address counter 1325d. At the same time, a control signal indicating the validity of the selected line address is output to the address decoding unit 133.

By repeating the above processing, the output value of the address counter 1325d becomes “... → 7 → 7 → 7 → 4 → 5 → 6 → 4 → 5 → 6 → 4 → 5 → 6 → 4 → 5 → 6 → 7 → 7 → ... ”, and the counting operation is repeated continuously with a pause period before and after. In the readout suspension period, the pixel signal is read out from the address (OB area) line of the count value “1”.
As a result, it is possible to prevent a series of continuous readings from being performed beyond the time when the vertical synchronization signal is input. Thereby, the division | segmentation for every flame | frame of the data read continuously can be performed easily.

  Here, the shaded portion in FIG. 7C is a readout pause period. If the pixel signal readout process is not performed in this period, the line is the same as described in the first embodiment. The amount of stored charge changes every time, and there is a risk that image quality will deteriorate. On the other hand, in the present embodiment, even during the readout pause period, any line in the regular readout process is always selected by selecting a line in the OB region and reading out the pixel signal from the selected line. Thus, the driving voltage for reading is applied to the common reading line, and it is possible to prevent the occurrence of a factor of image quality degradation such as non-uniformity in the amount of accumulated charge.

  As described above, the image pickup device 100 according to the present embodiment detects the maximum end position of the repeated reading process and efficiently performs the repeated reading of the pixel signal with respect to a part of the sensor cell lines of the sensor cell array 15 at a high speed. It is possible to set a reading pause period that is appropriate for performing repeated reading and that is appropriate for synchronizing the repetition period and the count period of the reference counter (the period of the vertical synchronization signal).

Furthermore, since the image sensor 100 of this embodiment can read pixel signals from a predetermined line (in the above embodiment, a line in the OB region) during the readout pause period, stable driving to the readout line is possible. While applying a voltage, it is possible to repeatedly read out pixel signals with a reading pause period in between.
In the second embodiment, the read pause period setting process in the adder circuit A1323, adder circuit B1326, comparison circuit B1327, MAX_BC detection circuit 1328, adder circuit C1329, comparison circuit C1330, and control unit 1321 is described in the eighth embodiment. Corresponding to the read pause period setting means of the above or the read pause period setting step described in the form 11, the output of the selection line address valid / invalid control signal for invalidating the address of the selected line from the control unit 1321 to the time division selector 133a. The process, the process of outputting the address value of a specific line (OB area line) to the address decoding circuit 133b in response to the invalid selected line address valid / invalid control signal in the time division selector 133a, and the drive pulse generator 14 Activate a particular line and The process of generating the drive pulse for reading out the pixel signal from the active line corresponds to the dummy readout control means described in the eighth aspect, the dummy reading means described in the tenth aspect, or the dummy reading step described in the eleventh aspect.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to the drawings. 8 to 9 are diagrams showing a third embodiment of the imaging device and the driving method of the imaging device according to the present invention.
In the second embodiment, during repeated reading in each frame, pixel signals are read continuously without a reading pause period, and the maximum count value of the reference counter when the reading is continuously performed The maximum end position of repeated reading with respect to (end position of frame period) is detected, and the period from the end position to the offset value of the next frame is set as the wait period. On the other hand, in the present embodiment, the third addition of the addition circuit C1329 is added to the comparison result of the comparison circuit B1327 and the comparison circuit C1330 in order to shorten the period during which reading is not performed by setting the offset value as much as possible. Based on the comparison result between the value and the offset value, the reading suspension period is set so that the maximum number of repeated reading processes that can be performed until the count value of the reference counter 131 matches the offset value are continuously performed. .

Further, the image sensor of the present embodiment is different from the image sensor 100 of the second embodiment except that the configuration of the selection line address generation circuit is partially different.
In the following, the same parts as those in the second embodiment are denoted by the same reference numerals, description thereof will be omitted as appropriate, and different parts will be described in detail.
First, the configuration of the selection line address generation circuit 132a of this embodiment will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration of the selection line address generation circuit 132a according to the present embodiment when up-counting is performed.

  As shown in FIG. 8, the selection line address generation circuit 132a of this embodiment includes a comparison circuit A 1320, a control unit 1321, an initial value generation circuit 1322, an addition circuit A 1323, a selector circuit 1324, and an address counter 1325. An addition circuit B1326, a comparison circuit B1327, a MAX_BC detection circuit 1328, an addition circuit C1329, a comparison circuit C1330, and a comparison circuit D1331.

That is, the comparison circuit D1331 is added to the selection line address generation circuit 132a in the second embodiment.
The comparison circuit D1331 is a circuit that compares the third addition value C, which is the addition processing result of the addition circuit C1329, with the offset value, and notifies the fact when the third addition value C is equal to or greater than the offset value. The signal is output to the control unit 1321.

The control unit 1321 of the present embodiment provides a selection line address valid / invalid control signal for invalidating the selection line address to the address decoding unit 133 based on the comparison results of the comparison circuit B1327, the comparison circuit C1330, and the comparison circuit D1331. Output, thereby setting the read pause period.
Specifically, a detection flag signal (FLAG_C) indicating whether or not “third addition value C ≧ offset value” is detected is set, and first, FLAG_C is initialized to an undetected state (L level). Next, a notification from the comparison circuit B 1327 (detection notification of “first addition value A ≧ second addition value B”), a notification from the comparison circuit C 1330 (detection notification of “third addition value C ≧ MAX_BC”), Based on the above, these states are monitored, and when both are established at the same time, the state of the detection flag C (FLAG_C) is set to the detection state (H level). Furthermore, when FLAG_C is in the detection state, after initialization of the reference counter 131, notification from the comparison circuit B 1327 (detection notification of “first addition value A ≧ second addition value B”) and comparison circuit D 1331 Based on the notification (“third addition value C ≧ offset value”), these states are monitored, and when both of them are established at the same time, the reference counter from the count value next to the count value of the reference counter 131 at this time is used. In a period until the count value of 131 matches the offset value, a selection line address valid / invalid control signal for invalidating the selected line address is output. At this time, FLAG_C is initialized to an undetected state (L level). As a result, it is possible to repeatedly read out to a position that does not exceed the count value that matches the offset value in the next frame.

Note that the selection line address generation circuits 132b to 132d have the same configuration as the selection line address generation circuit 132a, and thus the description thereof is omitted.
The operations of the address decoding unit 133 and the drive pulse generator 14 are the same as those in the first embodiment, and a description thereof will be omitted.

Next, based on FIG. 9, operation | movement of this Embodiment is demonstrated.
Here, FIG. 9A is a diagram illustrating an example of a pixel line configuration, FIG. 9B is a diagram illustrating an example of control data, and FIG. 9C is an example of an output value of each counter. FIG.
In FIG. 9, the operations of CLS, LOAD1, and LOAD2 are the same as those in the first embodiment, and therefore, the operation of LOAD3 (selected line address generation circuit 132d) will be mainly described below. In addition, in order to distinguish the selection line address generation circuits 132a to 132d having the same circuit configuration from each other, the components 1320 to 1331 of the selection line address generation circuits 132a to 132d are denoted by “a” to “d”, respectively. explain.

  For the selected line address generation circuit 132d, as shown in FIG. 9B, the control data includes an offset value (offset in FIG. 9B) “6” and a start line value (in FIG. 9B). Initial value) “4”, line width value (width in FIG. 9B) “3”, step value (step in FIG. 9B) “1”, weight value (in FIG. 9B) Wait) “0” is set. Furthermore, a repeat mode is set.

  First, as in the second embodiment, when the image sensor 100 is reset, the MAX_BC detection circuits 1328a to 1328d of the selection line address generation circuits 132a to 132d are initialized, and MAX_BC is determined by the MAX_BC update process. .

Next, upon receiving an operation start instruction from the system controller, each of the selected line address generation circuits 132a to 132d of the read / reset line address generation unit 13 shifts to a start waiting state.
Then, as shown in FIG. 9C, when the reference counter 131 (BC in the figure) starts the count operation and the count value becomes “6”, the offset value “6” of the selected line address generation circuit 132d is obtained. Since they match, the start line value “4” is set as an initial value in the address counter 1325d. At this time, the control unit 1321d initializes FLAG_C to an undetected state (L level). Since the step width of the selected line address generation circuit 132d is “1”, the address counter 1325d counts up from the initial value “4” to the count width value (maximum count value) “6” by one.

  Here, since the wait value is “0”, when the count value becomes “6”, the selector next outputs the initial value “4” generated by the initial value generation circuit 1322d to the address counter 1325d. The circuit 1324d is controlled. Therefore, the count-up operation from the initial value “4” to the maximum value “6” is repeated continuously in order of →→ 4 → 5 → 6 → 4 → 5 → 6 → 4 → 5 → 6 →. Is called.

  While the count-up operation is being performed, the adder A1323d adds the count value of the address counter 1325d and the step value, and outputs the first addition value A that is the addition result to the comparator B1327d. Further, in the adding circuit B 1326d, “start line value = 4” and “line width value = 3” are added, and a second addition value B (“7”) as a result of the addition is output to the comparing circuit B 1327d. . In addition, in the addition circuit C1320d, the line width value “3” and the count value of the reference counter 131 are added, and a third addition value C as a result of the addition is output to the comparison circuit C1330d and the comparison circuit D1331d, respectively.

The comparison circuit B1327d compares the addition result “7” (second addition value B) of the addition circuit B1326d with the addition result (first addition value A) of the addition circuit A1323d.
The comparison circuit C1330d compares the addition result (third addition value C) of the addition circuit C1329d with the maximum value “19” of the count value of the reference counter 131 input from the MAX_BC detection circuit 1328d.

The comparison circuit D1331d compares the addition result (third addition value C) of the addition circuit C1329d with the offset value “6”.
Then, when “first addition value A ≧ second addition value B” is detected in the comparison circuit B1327d, a signal notifying that is output to the control unit 1321d. That is, when the count value of the address counter 1325d becomes “6”, the first addition value A of the addition circuit A1323d becomes “7”, and thus “7 ≧ second addition value B (= 7)”. Since the condition is satisfied, this is detected and a notification signal is notified to the control unit 1321d. This notification signal is output to the control unit 1321d every time the count value becomes “6”.

  On the other hand, when “the third addition value C ≧ MAX_BC (= 19)” is detected in the comparison circuit C1330d, a signal notifying that is output to the control unit 1321d. That is, when the count value of the reference counter 131 becomes “16”, “third addition value C (= 19) ≧ MAX_BC (= 19)” is satisfied, and this is detected, and the notification signal is sent to the control unit 1321d. Notice. This notification signal is output to the control unit 1321d every time it is counted up until the count value of the reference counter 131 reaches MAX_BC (= 19).

Further, when “the third addition value C ≧ the offset value (= 6)” is detected in the comparison circuit D1331d, a signal notifying that is output to the control unit 1321d. That is, during a period in which the count value of the reference counter 131 is 3 to 19, a notification signal is output to the control unit 1321d every time the count is incremented.
The control unit 1321d detects FLAG_C when “first addition value A ≧ second addition value B” and “third addition value C ≧ MAX_BC (= 19)” are simultaneously established in the same count period ( H level). In this state and after the reference counter 131 is initialized, “first addition value A ≧ second addition value B” and “third addition value C ≧ offset value (= 6)” are simultaneously set in the same counting period. When established, the address decoding unit 133 indicates invalidity of the selected line address in the period from the next count value of the reference counter 131 at this time until the offset value of the next frame matches the count value of the reference counter 131. The selected address valid / invalid control signal (L level signal) is output. The period during which the selected address valid / invalid control signal is at the L level is the read suspension period.

  In the example of FIG. 9C, “first addition value A ≧ second addition value B (7)” and “third addition value C ≧ MAX_BC (= 19)” are satisfied at the same time. When the count value becomes “18”. That is, when the count value of the reference counter 131 becomes “18”, “first addition value A (= 1 + 6 = 7) ≧ second addition value B (= 7)”, “third addition value C (= 3 + 18 = 21) ) ≧ MAX_BC (= 19) ”. Thereby, FLAG_C enters a detection state. Thereafter, the count value of the reference counter 131 is initialized to “0” by the vertical synchronization signal, and when the count value is again counted up to “4”, “first addition value A (= 1 + 6 = 7) ≧ Second addition value B (= 7) ”and“ third addition value C (= 3 + 4 = 7) ≧ offset value (= 6) ”, so that both are established simultaneously.

As shown in FIG. 9C, the reading pause period is a period in which the count value of the reference counter 131 is 5-6.
When the selection line address valid / invalid control signal indicating invalidity of the selected line address is input from the control unit 1321d, the address decoding unit 133 receives the OB area instead of the address value from the address counter 1325d in the time division selector 133a. The address of the line (here, “address of line number 1”) is output to the address decoding circuit 133b.

When the address value of the line number “1” is input, the address decoding circuit 133 b outputs a control signal that activates the address value to the drive pulse generator 14.
When the control signal for activating the line having the address value of the line number “1” is input from the address decoding circuit 133b, the drive pulse generator 14 activates the line at the corresponding line position, and the sensor cell of the line. A drive pulse signal for reading out the pixel signal is generated from the signal, and the generated drive pulse signal is supplied to the sensor cell array 15.

As a result, in the divided period D in the period corresponding to one counter update clock, the pixel signal is read from the line of line number 1 in the OB area via the readout line (transferred to the horizontal transfer unit 16).
In addition, since the reading suspension period is a period of the count value “5 to 6” of the reference counter, when the count value becomes “6”, the initial value generation circuit 1322d and the counter value at the rising edge timing of the next counter update clock The selector circuit 1324d is controlled to set the start line value “4” in the address counter 1325d. At the same time, a control signal indicating the validity of the selected line address is output to the address decoding unit 133.

  By repeating the above processing, the output value of the address counter 1325d is changed to “4... 5 → 6 → 4 → 5 → 6 → 7 → 7 → 4 → 5 → 6 → 4 → 5 → 6 → 4 → 5 → 6 → 4 → 5 → 6 → 4 → 5 → 6 →... ”Every time seven consecutive readings are repeated, a rest period of 2 counts (the count value“ 7 ” (Period). In the readout pause period, pixel signals are read out from the lines in the OB area.

Thereby, since continuous reading can be performed with a minimum reading pause period, more information can be obtained from the line of the target region.
Here, the shaded portion in FIG. 9C is a readout suspension period. If the pixel signal readout processing is not performed in this period, the line is the same as described in the first embodiment. The amount of stored charge changes every time, and there is a risk that image quality will deteriorate. On the other hand, in the present embodiment, even during the readout pause period, by selecting a line in the OB area and reading out the pixel signal from the selected line, it is always possible during the regular readout process. Such a line is selected and a driving voltage for reading is applied to the common reading line, so that it is possible to prevent the occurrence of image quality degradation factors such as non-uniformity in the amount of accumulated charge.

As described above, when the image sensor 100 according to the present embodiment repeatedly reads out pixel signals at a high speed for a part of sensor cell lines in the sensor cell array 15, the number of repeated readings is based on the count start position of the address counter. It is possible to set a reading suspension period in which is maximized.
Furthermore, since the image sensor 100 of this embodiment can read pixel signals from a predetermined line (in the above embodiment, a line in the OB region) during the readout pause period, stable driving to the readout line is possible. While applying a voltage, it is possible to repeatedly read out pixel signals with a reading pause period in between.

  In the third embodiment, the read pause period setting process in the adder circuit A1323, adder circuit B1326, comparison circuit B1327, MAX_BC detection circuit 1328, adder circuit C1329, comparison circuit C1330, and control unit 1321 is described in the ninth embodiment. Corresponding to the read pause period setting means of the above or the read pause period setting step described in the form 11, the output of the selection line address valid / invalid control signal for invalidating the address of the selected line from the control unit 1321 to the time division selector 133a. The process, the process of outputting the address value of a specific line (OB area line) to the address decoding circuit 133b in response to the invalid selected line address valid / invalid control signal in the time division selector 133a, and the drive pulse generator 14 Activate a particular line and The process of generating the drive pulse for reading out the pixel signal from the active line corresponds to the dummy readout control means described in the ninth aspect, the dummy reading means described in the tenth aspect, or the dummy reading step described in the eleventh aspect.

In the first to third embodiments, the pixel signal is read from the line in the OB region in the reading suspension period. However, the present invention is not limited to this, and if reading is performed in the reading suspension period, A configuration may be adopted in which pixel signals are read from lines in other regions.
In the first to third embodiments, the read / reset line address generation unit 13 includes four selection line address generation circuits, that is, selection line address generation circuits 132a to 132d. Not limited to this, a configuration having three or fewer or five or more selected line address generation circuits may be used depending on the application.

  In the first to third embodiments, the read / reset line address generation unit 13 is configured by hardware. However, possible functions of each function may be realized by software. For example, the circuit function for controlling the counter operation of the address configured by the comparison circuit A 1320, the control unit 1321, the addition circuit B 1326, and the comparison circuit B 1327 is realized by software.

  In the first to third embodiments, the operation of the image sensor 100 has been described for the normal mode, the repetition mode, and the initial value addition mode. However, the operation is not limited to these operations, and the control is performed. Depending on the method, various other operations can be performed.

It is a block diagram which shows the structure of the image pick-up element 100 which concerns on this invention. 3 is a block diagram showing an internal configuration of a read / reset line address generation unit 13. FIG. It is a figure which shows the operation example of a time division selector. FIG. 3 is a block diagram illustrating an internal configuration example of a selection line address generation circuit 132a according to the first embodiment. (A)-(c) is a figure for demonstrating operation | movement of the selection line address generation circuit 132a in 1st Embodiment. It is a block diagram which shows the example of an internal structure of the selection line address generation circuit 132a in 2nd Embodiment. (A)-(c) is a figure for demonstrating operation | movement of the selection line address generation circuit 132a in 2nd Embodiment. It is a block diagram which shows the example of an internal structure of the selection line address generation circuit 132a in 3rd Embodiment. (A)-(c) is a figure for demonstrating operation | movement of the selection line address generation circuit 132a in 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Imaging device, 10 ... Communication part, 11 ... Register, 12 ... Timing control part, 13 ... Read / reset line address generation part, 14 ... Drive pulse generator, 15 ... Sensor cell array, 16 ... Horizontal transfer part, 130 ... Counter update clock generator, 130 ... reference counter, 132 ... selected line address generator, 133 ... address decoder, 132a to 132d ... selected line address generator, 133a ... time division selector, 133b ... address decoder, 1320 (1320a) To 1320d) ... Comparator A, 1321 (1321a to 1321d) ... Control unit, 1322 (1322a to 1322d) ... Initial value generator, 1323 (1323a to 1323d) ... Adder A, 1324 (1324a to 1324d) ... Selector circuit , 1325 (1325a To 1325d) Address counter, 1326 (1326a to 1326d) Addition circuit B, 1327 (1327a to 1327d) Comparison circuit B, 1328 (1328a to 1328d) MAX_BC detection circuit, 1329 (1329a to 1329d) Addition circuit C , 1330 (1330a to 1330d) ... comparison circuit C, 1331 (1331a to 1331d) ... comparison circuit D

Claims (11)

An imaging device having a photoelectric conversion unit having a configuration in which a plurality of photoelectric conversion elements that convert received light into electric charges and store them in a matrix and a rolling shutter function,
Address generating means for generating an address indicating a position of a line formed by the photoelectric conversion element to be processed corresponding to each divided period of a plurality of divided periods obtained by time-dividing each horizontal scanning period in each frame period;
Address decoding means for activating the photoelectric conversion elements at the line positions indicated by the addresses corresponding to the divided periods generated by the address generating means for each of the divided periods;
Pixel signal reading means for non-destructively reading out a pixel signal of a level corresponding to the amount of accumulated charge from a photoelectric conversion element that has been activated in response to a reading instruction via a common line;
A reset processing means for performing a reset process, which is a process of emptying the accumulated charge, for the photoelectric conversion element that has been activated in response to a reset instruction;
Read pause period setting means for setting a read pause period, which is a period of temporarily pausing regular readout processing of the pixel signal in each frame period;
In the set readout pause period, the photoelectric conversion element at a predetermined line position is made active by the address decoding means, and the pixel signal is read from the active photoelectric conversion element by the pixel signal reading means. An image pickup device comprising: a dummy read control means for reading the image data. The photoelectric conversion unit has an OB (Optical black) region composed of a line of the photoelectric conversion element shielded from light,
2. The image sensor according to claim 1, wherein the photoelectric conversion element at the predetermined line position corresponding to the readout pause period is a photoelectric conversion element that forms a line of the OB region. The address generation means sequentially selects at least the same number of address counters as the number of time divisions, an operation control unit for independently controlling the operation of the address counters, and the address counters in a time division manner, and selects the selected addresses. An address selection unit that outputs a count value of a counter to the address decoding unit as the address;
Comprising control information acquisition means for acquiring control information for controlling each address counter;
The imaging device according to claim 1, wherein the operation control unit independently controls each address counter based on the control information acquired by the control information acquisition unit. A reference counter that performs a counting operation based on a counter update clock generated based on a horizontal synchronization signal is provided.
The control information includes an offset value of each address counter,
4. The operation control unit according to claim 3, wherein when the offset value and the count value of the reference counter coincide with each other, the address counter is caused to start a count operation using the coincidence timing as a trigger. The imaging device described. The control information includes a step width value, a start line value, and a line width value of each address counter,
The operation control unit sets a step width at the time of the count operation of each address counter based on the step width value, and causes each address counter to count at the set step width, thereby obtaining the start line value. Based on the initial value of each address counter, the count of each address counter is started from the set initial value, and the maximum count value of each address counter is set based on the line width value. 5. The image pickup device according to claim 3, wherein each address counter is caused to perform a counting operation within a range from the set initial value to the set maximum count value. 6. In the address counter, it is possible to set a repeat mode in which a count operation performed in a range from the initial value to the maximum count value is continuously repeated.
The operation control unit causes the address counter set with the repetition mode to continuously and repeatedly perform a counting operation performed within a range from the set initial value to the set maximum count value. The imaging device according to claim 5. The control information includes a weight value of each address counter,
The read suspension period setting means sets a wait count number that is a count number for the wait of the address counter based on the wait value,
The operation control unit causes the address counter to count the set wait count every time the repeated count operation is completed in the address counter in which the repeat mode is set. While the wait count is being counted, a control signal for invalidating the count value is output to the address decoding means,
The dummy read control means sets a period during which the number of wait counts are counted as a read pause period, and in the read pause period, a photoelectric conversion element at a line position corresponding to an address indicating the predetermined line position is used as the address decode means. The image pickup device according to claim 6, wherein the image pickup device is activated, and the pixel signal reading unit reads the pixel signal from the activated photoelectric conversion device. A first addition value that is an addition value of the step width value and the count value of the base counter is compared with a second addition value that is an addition value of the start line value and the count value of the base counter. A comparison means;
A second comparison means for comparing a third addition value, which is an addition value of the line width value and the count value of the base counter, and a maximum value of the count value of the base counter;
When the repetition mode is set, the reading suspension period setting means has a larger comparison result of the first comparison means than the first addition value, and a comparison result of the second comparison means 7. A period from a horizontal period in which the third added value becomes larger to a horizontal period in which the offset value and the count value of the base counter coincide with each other is set as the read pause period. 8. The imaging device according to 7. A third comparison is made between the first addition value, which is the addition value of the step width value and the count value of the address counter, and the fourth addition value, which is the addition value of the start line value and the line width value. A comparison means;
A fourth comparison means for comparing a fifth addition value, which is an addition value of the maximum count value of the base counter, the line width value, and the count value of the base counter, and the fourth addition value; Prepared,
When the repetition mode is set, the reading suspension period setting means has a larger comparison result of the third comparison means than the first addition value, and a comparison result of the fourth comparison means The period from the horizontal period in which the fifth added value becomes larger to the horizontal period in which the offset value and the count value of the base counter coincide with each other is set as the reading suspension period. The image pickup device according to any one of 8. A plurality of photoelectric conversion elements configured to convert received light into electric charges and store them in a matrix, and a plurality of photoelectric conversion elements formed by the photoelectric conversion elements of the photoelectric conversion unit in each horizontal scanning period; An imaging element capable of performing non-destructive readout processing of accumulated charges and reset processing of accumulated charges multiple times in a time-sharing manner for a predetermined line of
A readout pause period setting means for setting a readout pause period, which is a period of temporarily pausing regular readout processing of the pixel signal in each frame period;
An image pickup device comprising: dummy read means for reading out the pixel signal from the photoelectric conversion device at a predetermined line position in the set read pause period. A plurality of photoelectric conversion elements configured to convert received light into electric charges and store them in a matrix, and a plurality of photoelectric conversion elements formed by the photoelectric conversion elements of the photoelectric conversion unit in each horizontal scanning period; A method for driving an imaging device capable of performing non-destructive readout processing of accumulated charges and reset processing of accumulated charges multiple times in a time-sharing manner for a predetermined line of
A readout pause period setting step for setting a readout pause period, which is a period of temporarily pausing regular readout processing of the pixel signal in each frame period;
And a dummy readout step of reading out the pixel signal from the photoelectric conversion element at a predetermined line position in the set readout pause period.

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