JP2009217721A - Data synchronization method in multiprocessor system and multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide data sharing that insures data consistency in a multiprocessor system. <P>SOLUTION: The multiprocessor system comprises a plurality of processors and a shared memory, a shared memory area includes a notification memory area allocated to each processor to perform message exchange between the area and the processor, and a data acquisition request is written in the notification memory area when a first processor acquires data in an allocated memory area of a second processor. By monitoring a data acquisition request in the notification memory area, it is possible to confirm that data are requested, and in such a case, data are copied between allocated areas, and a completion notification showing that the copying is completed is written in the notification memory area. A processor of a side for requesting the data performs processing using the acquired data by confirming the completion notification in the notification memory area. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data synchronization technique in a multiprocessor system.

  Computer performance has been improved by improving the frequency clock based on semiconductor miniaturization. However, miniaturization of process rules has a problem of increasing power consumption. Therefore, the introduction of multiprocessor systems that improve the processing capability by utilizing parallelism using a plurality of processors or processors having a plurality of processor cores is in progress.

  In such a multiprocessor system, various data synchronization mechanisms are required to ensure data consistency among a plurality of processors. For example, a lock (semaphore) is used when a processor accesses a shared memory to provide a mechanism in which other processors cannot access data being accessed by a certain processor. Such a locking mechanism has a heavy processing load and impairs the effect of parallel processing (high speed processing).

  Patent Document 1 discloses that job scheduling is divided and executed in parallel processing by Petri nets. The Petri net can realize parallel control of a plurality of processes along the data flow.

Also, in Patent Document 2, a FIFO buffer is provided when data is shared among a plurality of processors, and when one processor updates data, the FIFO buffer is also updated. The data in the buffer is interrupted by another processor. When it becomes possible, it is reflected in the RAM of the processor. In this way, the latest consistent data is always written in the RAM of each processor, and no lock wait or the like occurs in the processor.
JP-A-7-56863 JP 2007-133744 A

  In the method using the Petri net described in Patent Document 1, it is impossible to execute a process in which the data flow and the start of the process are asynchronous.

  In the method of exchanging data via the FIFO buffer described in Patent Document 2, it is necessary to newly provide a circuit such as a FIFO buffer and a controller between the processors.

  In view of the above problems, an object of the present invention is to provide a new and useful data sharing technique that guarantees data consistency in a multiprocessor system.

  The present invention achieves the above object by the following configuration.

One embodiment of the present invention is a data synchronization method in a multiprocessor system including first and second processors and a shared memory that can be accessed by both processors in common. The multiprocessor system in the present invention includes a system including a multicore processor (multicore CPU) in which a plurality of processor cores are provided on the same chip, in addition to a system including a plurality of processors such as CPUs.

  The shared memory has a first memory area assigned to the first processor, a second memory area assigned to the second processor, and a notification memory area. The first and second memory areas are areas that are basically accessed only by the corresponding processor. The notification memory area is an area that is accessed by both the first and second processors, and is an area that is used for notifying a data acquisition request and completion thereof, as will be described later.

  In the present invention, when the first processor requests data in the second memory area allocated to the second processor, the data acquisition request is written in the notification memory area.

  The second processor monitors whether a data acquisition request for requesting data in the second memory area exists in the notification memory area, and if there is a data acquisition request, the second processor stores the requested data in the second memory. Copy from area to first memory area. At the same time, a completion notification for notifying that the copying of the requested data is completed is written in the notification memory area.

  The first processor monitors whether or not the completion notification of the requested data exists in the notification memory area. If the completion notification exists, the first processor performs processing based on the data copied to the first memory area.

  In this way, a part of the shared memory is allocated to each processor, writing to each memory area is performed from a single processor, and notification is given when data is read from a memory area allocated to another processor. By requesting the other processor to copy via the memory area, a consistent data copy can be realized.

  Since the notification of the data acquisition request and the notification of the completion of copying are performed via the notification memory area, the data synchronization of the present invention is executed without providing a new circuit such as a dual port memory or a FIFO buffer. be able to.

  In the present invention, it is preferable that the data acquisition request written in the notification memory area includes a status area for storing the processing status of the data acquisition request process. When the first processor writes a data acquisition request in the notification memory area, a status (flag) indicating a request state is stored in the status area. The completion notification writing process performed when the second processor completes copying the requested data indicates that the status area of the data acquisition request written in the notification memory area by the first processor is copy completion. This can be done by rewriting the status.

  As described above, the completion notification is written by rewriting a part of the data acquisition request in the notification memory area, thereby simplifying the process and reducing the necessary notification memory area.

  In the present invention, it is preferable that the second processor executes a copy of the requested data at a timing at which the data is consistent.

  For example, when the second processor is executing a process that requires atomicity, such as a process of updating a plurality of data, instead of copying the requested data in the middle of the process, a single process is performed. By performing data copying after completion, data consistency can be guaranteed.

  In the present invention, each of the first and second processors executes a plurality of tasks, and the execution code of the task and the data used by the task are stored in a memory area corresponding to the processor executing the task. It is preferable to adopt a configuration stored in an area allocated for each task. In this case, it is preferable that the data acquisition request is executed for each task requesting data, and the requested data copy is executed within the processing of the task corresponding to the data.

  In this way, the processor can perform processing of other tasks while the requested data copy is completed, so the overall parallelism of the processor is not lost.

  In the present invention, when a task of the first processor requests data in the second memory area, another task of the first processor already requests the same data. It is preferable to write a data acquisition request indicating a duplicate request in the notification memory area. When receiving the same data acquisition request from a plurality of tasks related to the first processor, the second processor executes data copy processing only for any one data acquisition request. For example, it is conceivable to perform data copy processing for the data acquisition request that has occurred earliest. For a data acquisition request subject to copy processing, it is preferable to write a completion notification for notifying that copying has been completed into the notification memory area. Then, when the completion notification of the requested data is in the notification memory area, the first processor copies the data to the copy destination requested by another data acquisition request that requests the same data. At the same time, it is preferable to write in the notification memory area that the copying of the data acquisition request has been completed.

  In this way, when a plurality of acquisition requests are generated from the first processor for the same data of the second processor, the processing load on the second processor can be reduced.

  The present invention can be understood as a data synchronization method having at least a part of the above processing. The present invention can also be understood as a multiprocessor system that executes at least a part of the above processing, or a program for realizing such a method. Each of the above means and processes can be combined with each other as much as possible to constitute the present invention.

  For example, an aspect of the present invention is a multiprocessor system including a plurality of processors, and a shared memory that is accessible to the plurality of processors in common and has a memory area and a notification memory area allocated to each processor. A data acquisition request means for writing a data acquisition request for requesting data in a memory area allocated to another processor to the notification memory area, and a memory area allocated to the own processor in the notification memory area. The data acquisition request that requests the data in the server is monitored, and if there is a data acquisition request, the requested data is copied into the memory area allocated to the requesting processor and the copy is notified Data copy means for writing a completion notification to the notification memory area and its own processor Data processing means for monitoring whether the completion notification of the requested data acquisition request exists in the notification memory area, and if the completion notification exists, a data processing means for performing processing based on the data copied to the memory area allocated to the own processor; , Can be regarded as a multiprocessor system.

  According to the present invention, it is possible to share data with guaranteed data consistency in a multiprocessor system.

(First embodiment)
<Constitution>
The present embodiment is an engine control system for controlling an engine mounted on an automobile or the like. As shown in FIG. 1, the engine control system of this embodiment includes two CPUs 1 and 2. Further, a memory 3 that can be commonly accessed by the CPUs 1 and 2 is provided.

  Connected to the CPU 1 are a water temperature sensor 4 for detecting the cooling water temperature of the engine and an intake air temperature sensor 5 for detecting the intake air temperature of the engine. The CPU 1 periodically executes sensor input processing, inputs signals from the water temperature sensor 4 and the intake air temperature sensor 5, converts them into digital data, and stores them in the memory 3.

  Connected to the CPU 2 is a fuel injection device 6 for injecting fuel into the engine. The CPU 2 periodically executes an injection amount determination process, and determines the fuel injection amount of the fuel injection device 6 based on the water temperature and air temperature updated by the CPU 1.

  The CPUs 1 and 2 may be configured to execute processes other than the sensor input process and the injection amount determination process in parallel. In the above description, only data is unilaterally requested from the CPU 2 to the CPU 1, but both the CPUs 1 and 2 request data for tasks executed by the other CPUs, and send the requested data. It can be passed to another CPU.

  As shown in FIGS. 1 and 2, the memory 3 is logically divided into three regions 3a, 3b, and 3c. The memory area 3a is an area allocated to the CPU 1, and the memory area 3b is an area allocated to the CPU 2. The memory area allocated to each CPU is basically an area that only the CPU accesses. The notification memory area 3c is a memory area shared by the CPUs 1 and 2, and the CPUs 1 and 2 exchange information for data acquisition via this area.

  In each of the allocation areas 3a and 3b, an area for storing an execution code of a task (process) executed by each CPU, input data used for the process, and output data calculated as a process result is predetermined for each task. It has been. The area allocated to each task does not have to be a continuous area, but is a continuous area in this embodiment. Further, the areas (3a, 3b) allocated to the CPUs do not have to be continuous areas, but are continuous areas in this embodiment.

  The notification memory area 3c stores a data acquisition request message for transferring data between tasks of different CPUs. In this embodiment, the notification memory area 3c is prepared in advance for the amount of data exchange between tasks of different CPUs. However, a necessary area may be secured only when data is requested.

  FIG. 3 is a diagram showing an example of the format of the data acquisition request 7 written in the notification memory area 3c. The data acquisition request 7 includes a status 7a, a copy source address 7b, and a copy destination address 7c. The state 7a stores one of three states of “no request”, “request”, and “processing completed”. “Request” indicates that a request for data is requested from one CPU to another CPU. “Processing completed” indicates that the CPU requested to request the data has completed copying the data. “No request” is a state other than the above, and indicates that there is no request.

The copy source address 7b stores the address of data to be acquired. As described above, when the injection amount determination task executed by the CPU 2 wants to acquire the water temperature data from the sensor input process executed by the CPU 1, the water temperature data in the memory area 3a allocated to the CPU 1 is stored. Address.

  The copy destination address 7c stores a copy destination address of the requested data. In the above example, an address in the memory area 3b allocated to the CPU 2 is designated.

  The data acquisition request message 7 can adopt any format as long as it can exchange the request status and information about which data should be copied to where. For example, the information about which data is desired to be acquired does not directly specify the copy source address where the data is stored, but an identifier (ID) may be predetermined for each data and the ID may be specified. . Similarly, the designation of the copy destination address may be notified by other methods instead of directly designating the address.

  In this way, each CPU executes a data request and copy process using the data acquisition request message in the notification memory area 3c.

<Processing flow>
Next, the flow of processing performed by each CPU will be described with reference to the flowchart of FIG. The flowchart of FIG. 4 is a flowchart showing the flow of processing when a CPU executes one task. When the CPU can execute a plurality of tasks, the task having the highest priority among the tasks in the executable state is executed.

  The flowchart of FIG. 4 includes two parts, S1 (S10 to S15) representing processing as a task requesting data and S2 (S20 to S22) representing processing as a task copying data. . Each CPU executes both S1 and S2 so that both the data requesting side and the data copying side can be executed.

  First, the process S1 as a task on the data request side will be described. It is determined whether there is a process executable by the CPU (S10). Since processing cannot be continued while a data acquisition request is being issued to a task being executed by another CPU (copying from the request destination has not been completed), the process proceeds to step S20. On the other hand, after the data acquisition request message has been processed or when no data acquisition request message has been issued to another CPU, task processing can be executed, and the process proceeds to step S11.

  In step S11, it is determined whether the status 7a of the previously requested data acquisition request message is “processing completed” in the notification memory area 3c. If there is, the status of the data acquisition request message is determined. 7a is changed to “no request” (S12). Alternatively, the data acquisition request message may be deleted from the notification memory area 3c.

  Next, processing related to its own task is performed (S13). If a data acquisition request has been issued, processing is performed with reference to the data copied in the memory area allocated to the invoking task. Then, it is determined whether it is necessary to acquire data from a task executed by another CPU (S14). Here, if it is necessary to acquire data from another CPU, a data acquisition request message is written in the notification memory area (S15). The status 7a of this data acquisition request message is “request”.

  Next, the process S2 as a task for copying data will be described. The task refers to the notification memory area 3c and checks whether there is a data acquisition request message for requesting data in the area assigned to the task (S20). This can be determined by examining the copy source address 7b of the data acquisition request message in the notification memory area 3c.

  If the data of its own task is requested from a task executed by another CPU, the data is copied to the copy destination address 7c of the data request notification (S21). Then, the status 7a of the data acquisition request message in the notification memory area 3c is changed to “processing completed” (S22). In step S21, data is copied from a memory area assigned to a task of a certain CPU to a memory area assigned to a task of another CPU. If access is not made, lock processing at the time of writing is unnecessary. Note that the mechanism that prevents the requesting CPU from accessing the memory area during data request (when not acquired) may be realized simply by describing the program with such logic, or to the memory area. This may be realized by monitoring a data acquisition request prior to access.

  The task that requested the data can determine whether or not the data copy has been completed by checking the status of the data acquisition request message in the notification memory area 3c.

<Operation example>
FIG. 5 shows an example in which the sensor input task of the CPU 1 inputs data from the sensor, and the injection amount determination task of the CPU 2 receives the water temperature and air temperature data from the sensor input task and determines the injection amount. An operation example will be described. Obviously, the content of the processing performed by each task may be anything.

  The injection amount determination task of the CPU 2 writes a data acquisition request message in the notification memory area 3c in order to acquire data from the sensor input task of the CPU 1. In the figure, only one data acquisition request message is written. However, when a plurality of data is requested, a plurality of data can be acquired by one data acquisition request message. A data acquisition notification may be written.

  The sensor input task of the CPU 1 refers to the notification memory area 3c and determines whether there is a data acquisition request for its own task. This determination is made after the sensor input task processing, that is, after updating the water temperature and air temperature data that need to be updated together. Since the sensor input task of the CPU 1 has a data acquisition request message in the notification memory area 3c, the data stored in the address S1 is copied to the address D1 according to the content of the notification. Then, the status of the data acquisition request message is updated to “processing completed”.

  The injection amount determination task that issued the data acquisition request checks the status of the data acquisition request message in the notification memory area 3c at an appropriate timing. If this status remains “Requested”, it can be seen that data has not yet been copied, so the processing is not continued. On the other hand, when the status in the data acquisition request message is “processing completed”, it can be seen that the data copy is complete, so referring to the acquired data (data at address D1), Processing can continue.

  The advantages of the data synchronization method according to the present embodiment will be described with reference to FIGS. 6 and 7 are timing charts showing the timing of each process.

In the example of FIG. 6, while the CPU 1 is updating the input data from the sensor, the injection amount determination task of the CPU 2 requests acquisition of the water temperature and the air temperature. At this time, the sensor input task of the CPU 1 is not responding to the data request because it is in the process of updating data that needs to be updated all at once. Then, after both the water temperature and the air temperature are updated, data is copied according to the data request from the injection amount determination task of the CPU 2. And C
On the PU2 side, when it is detected that the data income request has been completed, the water temperature and air temperature data are updated in the memory area allocated to the injection amount determination task, and the processing is continued using this. can do.

  In this way, the CPU 1 side does not support data copy while updating data that needs to be updated in one batch, and performs data copy after the batch update processing is completed. Data integrity can be guaranteed.

  In addition, while the process of the task that requested the data on the CPU 2 side is in a waiting state until the data copy is completed, the process of the task on the request side performs a process of acquiring a lock or the like at the time of data copy Since it is not necessary, the processing is simple and fast. Further, since the task that requested the data can know whether the data acquisition has been completed simply by referring to the notification memory area, the processing is simple and high-speed. On the CPU 2 side as well, when the task that requested data is in a waiting state, other tasks can be executed, so that the parallelism as a whole is not impaired.

  Next, FIG. 7 will be described as an example. In the example of FIG. 7, when the task that requested the data refers to the notification memory area to determine whether the data acquisition has been completed, the task that requested the data has already completed the data copy. In addition, data is updated by new sensor input. Even in such a case, copying of data from the CPU 1 side to the CPU 2 side has been completed. Therefore, even if data is newly updated on the CPU 1 side, no waiting for lock or the like occurs on the CPU 2 side. Processing can be continued immediately.

  As can be seen from FIG. 7, the time interval at which a task that requests data acquisition determines completion of acquisition may be different from the time interval of data update on the requested side. In other words, the sensor input task side may update data relatively frequently, and the injection amount determination task may have time until the data acquisition completion is checked after the data acquisition request is issued. Even in such a case, the data at the time when the injection amount determination task requests data acquisition is copied to the memory area assigned to the injection amount determination task, so at the timing when the data acquisition request is issued. The processing can be continued based on the consistent data.

<Operation / Effect of Embodiment>
According to this embodiment, it is possible to guarantee data consistency and perform data sharing between processors by software processing without providing new hardware. Since it is supported by software, problems such as an increase in cost and an increase in the size of the apparatus caused by providing new hardware are not caused.

  At this time, the requesting task (CPU) does not access the memory area during the data request, so that the requested task (CPU) can execute the data copying process without performing the locking process. it can. Further, since the task requesting the data determines whether or not the copy is completed only by looking at the status in the notification memory area, the lock process is not necessary here either. That is, data sharing can be executed without using lock processing.

  Further, since the data is copied, the task that requested the data can always refer to the data and perform processing after the data is copied. From the task on which the data is requested, if the requested data is copied, there is no need to worry about the data retrieval request any more, and the request refers to the data to which the task was copied. Regardless of whether it is present or not, data can be updated in the memory area allocated to the invoking task.

  Further, according to such a data sharing method, a plurality of data requests can be issued simultaneously by one process / thread. The method of sequentially acquiring each data increases the waiting time, and the method of generating a plurality of threads increases the overhead. However, according to this method, requests can be made simultaneously within one thread, so that the processing load and waiting time are increased. High-speed processing with less can be realized.

(Second Embodiment)
<Overview>
In the first embodiment, a task for which data is requested executes data copy processing in response to each request. Here, consider the situation as shown in FIG. In FIG. 8A, a plurality of tasks executed by the CPU 2 issue data acquisition requests to the tasks of the CPU 1. In the method described in the first embodiment, the CPU 2 responds to each data acquisition request under the situation illustrated in FIG. 8A. That is, the copy process from the memory area assigned to the task executed by the CPU 1 to each memory area assigned to each task executed by the CPU 2 is executed a plurality of times (three times in FIG. 8A).

  When the number of duplicate data requests to a certain task becomes large, the task for which data is requested must perform copy processing as many times as the number of requests, resulting in an excessive processing load. Therefore, as shown in FIGS. 8B and 8C, the task executed by the CPU 1 executes the copy process only once for the task executed by the CPU 2 (FIG. 8B), and the CPU 2 for the remaining data requests. If the copy process can be executed for each task (FIG. 8C), an excessive load can be prevented even when data acquisition requests are concentrated on the CPU 1.

  In order to realize the above-described mechanism, as the state 7a of the data acquisition request message 7, a “duplicate request” indicating that the task executed by the same CPU newly requests data already requested by the CPU is newly issued. A new status is provided. Since the same data is requested, the copy source address 7b is the same between duplicate requests. On the other hand, the copy destination address 7c is different because it is an area allocated to the task that requested the data.

<Processing flow>
The processing flow of the data sharing method in this embodiment will be described with reference to FIG. The flowchart of FIG. 9 shows only a part corresponding to the process (S1) as the data requesting side of the flowchart (FIG. 4) of the data sharing method in the first embodiment. Since the process (S2) as the data copy side is the same as that in the first embodiment, it is omitted in FIG.

  The difference from the first embodiment is that Steps S16 to S18 are provided after Step S12, and Step S15 is replaced with Steps S15-1, 2, and 3.

  First, the processing of steps S16 to S18 will be described. This process corresponds to a process of copying data (FIG. 8C) on the CPU side that requests the same data repeatedly.

  It is determined that there is a data acquisition request message that has been requested with a status of “processing completed” (S11-YES), and the status is rewritten as “no request” (S12), and then in the notification memory area It is determined whether there is a data request that overlaps this data request (S16). Whether or not there is a duplicate data request can be determined by whether or not a data acquisition request message having a status of “duplicate request” and a matching copy source address is stored in the notification memory area. .

  In the case of a multiprocessor system having three or more processors, it is necessary to determine whether another task of the same processor requests the same data. This can be realized by checking whether a data acquisition request message in which the copy source address matches and the copy destination address is an address in the allocation area allocated to the same processor exists in the notification memory area. .

  If there is an overlapping data acquisition request (S16-YES), the data is copied in the area assigned to the own processor (S17) (corresponding to FIG. 8C). Then, the status of the duplicate request data acquisition request message is updated to “processing completed” (S18).

  Next, the process of steps S15-1 to S15-3 will be described. This process determines whether or not there is a duplicate request when writing a data acquisition request message to the notification memory area. If it is a duplicate request, this process writes a message that can be determined to that effect to the notification memory area. is there.

  When the data acquisition request is written when it is determined that data of another CPU is necessary (S14-YES), the notification memory area 3c is checked, and another task executed by the same processor has already made a request for the same data. It is determined whether or not it is issued (S15-1). Whether or not a request for the same data already exists can be determined by whether or not a request with the same copy source address 7b already exists in the notification memory area 3c.

  When there is no request for the same data (S15-1-NO), a data acquisition request message whose status is “Request” is stored in the notification memory area 3c (S15-2). On the other hand, if a request for the same data already exists (S15-1-YES), a data acquisition request message whose status is “duplicate request” is stored in the notification memory area 3c (S15-3).

<Operation example 1>
FIG. 10 shows a specific operation example in the case where the CPU 1 inputs data from the sensor in the wheel speed data task, and the ABS control task and the car navigation task of the CPU 2 receive and process the wheel speed data, respectively. explain. Obviously, the content of the processing performed by each task may be anything.

  First, the ABS control task writes a data acquisition request message A for requesting wheel speed data in the notification memory area 3c. Here, since there is no duplicate data acquisition request, the status 7a of the data acquisition request message A is “request”. The copy source address 7b is S1, and the copy destination address 7c is D1.

  Next, the car navigation task similarly writes a data acquisition request message B requesting wheel speed data to the notification memory 3c. Here, since the ABS control task has already issued a request A for the same data, the status 7a of the data acquisition request message B is “duplicate request”. Further, the copy source address 7b is S1 as in the ABS control task request A, and the copy destination address 7c is an address in the memory area of the own task, so becomes D2 and is different from the ABS control task request A.

The wheel speed data acquisition task of the CPU 1 refers to the notification memory area 3c and checks whether there is an acquisition request for data in the eye memory area of its own task. At this time, it can be seen that the two data acquisition requests A and B with the status “request” and “duplicate request” are notified, but the wheel speed data acquisition task side has the data acquisition request with the status “request”. Only message A is supported. That is, the data stored at the address S1 is copied only to the address D1. Then, the status of the corresponding data acquisition request message A is updated to “processing completed”.

  Next, the ABS control task refers to the notification memory area 3c and determines whether the data acquisition request requested by the own task has been processed. Since the status of the data acquisition request is “processing completed”, it is understood that the data acquisition is completed. Since the ABS control task also knows that there is a duplicate data acquisition request message B, it is assigned to the CPU 2 and copies the memory (from D1 to D2) within the area. Then, the status of the data acquisition request message A is updated to “no request”, and the status of the data acquisition request message B is updated to “processing completed”. Then, the ABS control task performs processing with reference to the data copied to the address D1.

  When the car navigation task refers to the notification memory area 3c, the status of the data acquisition request message B requested by its own task is “processing completed”, so this status is changed to “no request” and the address D2 is set. Processing is performed with reference to the copied data.

<Operation example 2>
In the above operation example, the ABS control task that issued the request first performs copying in the CPU 2, but the task that first detected that the data requested by the CPU 1 has been copied to the CPU 2 is transferred to the CPU 2. Copying within the allocated memory area may be performed. Here, an example of an operation in which a car navigation task that issues a request later executes a copy process in the memory area allocated to the CPU 2 will be described with reference to FIG.

  The process until the ABS control task and the car navigation task store the data acquisition request in the notification memory area and the wheel speed acquisition task copies the requested data (from S1 to D1) is the same as the operation example 1 described above. Therefore, the description is omitted.

  Here, since the status of the data acquisition request message A is “processing completed”, it can be seen that the copying process between the CPUs is completed. Therefore, data is copied (from D1 to D2) in the allocated memory area of the CPU 2, and the status of the data acquisition request message B is updated to “no request”. The car navigation task performs processing with reference to the data copied to the address D2.

  When the ABS control task refers to the notification memory area 3c, the status of the data acquisition request message A requested by its own task is “processing completed”, so this status is changed to “no request” and the address D1 The processing is performed with reference to the data copied to. Since the status of the data acquisition request message B is no longer “duplicate request” at the timing when the ABS control task refers to the notification memory area 3c, the ABS control task performs the copy processing as performed in the operation example 1. Absent.

<Operation / Effect of Example>
According to the method according to the present embodiment, when there are a plurality of requests for the same data from a plurality of tasks of the same CPU, it is possible to reduce the processing load of the requested CPU. .

(Modification)
In the above description, message exchange via the memory notification area is performed by rewriting the status area of the data acquisition request message, but message exchange by other methods may be performed. For example, when notifying the completion of copy processing, a message notifying that may be newly written in the notification memory area.

  In the above description, the configuration having two CPUs has been described as an example. However, even when the number of CPUs is three or more as shown in FIG. It can be carried out.

  In this case as well, since the area of the memory 3 is allocated to each CPU, the acquisition request for the task data related to which CPU can be obtained by referring to the copy source address or the copy destination address of the data acquisition request message. And which CPU task requests data acquisition.

  As shown in FIG. 13, even if a single CPU is a multi-core CPU having a plurality of processor cores, data synchronization can be performed between the processor cores. In this case, each processor core corresponds to the processor of the present invention.

It is a schematic diagram showing the system configuration in 1st and 2nd embodiment. It is a figure which shows the memory structure of a notification memory area. It is a figure which shows the format of a data acquisition request message. 5 is a flowchart illustrating a flow of processing when data is exchanged between processors in the first embodiment. It is a figure explaining the data exchange process between the processors in 1st Embodiment. It is a figure explaining the data exchange process between the processors in 1st Embodiment. It is a figure explaining the data exchange process between the processors in 1st Embodiment. It is a figure explaining the data exchange process between the processors in 2nd Embodiment. It is a flowchart which shows the flow of a process at the time of exchanging data between processors in 2nd Embodiment. It is a figure explaining the data exchange process between the processors in 2nd Embodiment. It is a figure explaining the data exchange process between the processors in 2nd Embodiment. It is a schematic diagram showing the system configuration | structure which concerns on a modification. It is a schematic diagram showing the system configuration | structure which concerns on a modification.

Explanation of symbols

1, 2 CPU
3 Memory (RAM)

Claims (10)

A first processor;
A second processor;
A shared memory accessible in common by the first and second processors, a first memory area allocated to the first processor, a second memory area allocated to the second processor, A shared memory having a notification memory area;
A data synchronization method in a multiprocessor system comprising:
A first processor writing a data acquisition request for requesting data in the second memory area into the notification memory area;
The second processor monitors whether a data acquisition request for requesting data in the second memory area exists in the notification memory area, and if there is a data acquisition request, the requested data is stored in the second memory. Copying from the area to the first memory area and writing a completion notification in the notification memory area to notify that the copying is completed;
The first processor monitors whether a completion notification for the requested data exists in the notification memory area, and if there is a completion notification, performs processing based on the data copied to the first memory area; ,
A data synchronization method in a multiprocessor system, comprising: The data acquisition request written to the notification memory area includes a status area for storing the processing status of the data acquisition request process.
The data acquisition request is written by the first processor by writing a data acquisition request including a status indicating that data acquisition is requested in the notification memory area.
Writing of the completion notification by the second processor is performed by rewriting the status area of the data acquisition request to a status indicating that copying is complete.
The data synchronization method in a multiprocessor system according to claim 1. 3. The data synchronization method in a multiprocessor system according to claim 1, wherein the copy of the requested data by the second processor is executed at a timing when the consistency of the data is taken. The first and second processors each execute a plurality of tasks.
The task execution code and the data used by the task are stored in an area allocated for each task in the memory area corresponding to the processor that executes the task.
Data acquisition requests are executed for each task that requests data.
The data synchronization method in the multiprocessor system according to any one of claims 1 to 3, wherein the requested data copy is executed within a process of a task corresponding to the requested data. When a task in the first processor requests data in the second memory area, if another task in the first processor has already requested the same data, this is a duplicate request. Write the indicated data acquisition request to the notification memory area,
When there is a data acquisition request from a plurality of tasks of the first processor for the same data, the second processor sets the copy destination requested by any one of the plurality of data acquisition requests. Copying the data and storing a completion notification for notifying that the copy of the data acquisition request is completed in the notification memory area,
The first processor monitors whether a completion notification for the requested data exists in the notification memory area, and if a completion notification exists, another data acquisition request requesting the same data requests. 5. The data synchronization method in the multiprocessor system according to claim 4, wherein the data is copied to a copy destination, and the copy of the other data acquisition request is written to the notification memory area. Multiple processors,
A shared memory accessible by the plurality of processors in common, the shared memory having a memory area and a notification memory area allocated to each processor;
A multiprocessor system comprising:
Each processor
A data acquisition request means for writing a data acquisition request for requesting data in a memory area allocated to another processor into the notification memory area;
Monitors whether there is a data acquisition request in the notification memory area that requests data in the memory area allocated to its own processor. If a data acquisition request exists, the requested data is allocated to the requesting processor. A data copy means for copying into the memory area and writing a completion notification for notifying that the copying is completed to the notification memory area;
Data that monitors whether the completion notification of the data acquisition request requested by its own processor exists in the notification memory area, and if there is a completion notification, performs data processing based on the data copied to the memory area allocated to its own processor Processing means;
A multiprocessor system comprising: The data acquisition request written to the notification memory area includes a status area for storing the processing status of the data acquisition request process.
The data acquisition request means writes a data acquisition request including a status indicating that data acquisition is requested in a notification memory area,
The completion notification writing process performed by the data copying means is performed by rewriting the status area of the data acquisition request written in the notification memory area to a status indicating that the copying is completed.
The multiprocessor system according to claim 6. 8. The multiprocessor system according to claim 6, wherein the data copying unit executes the copying of the requested data at a timing when the requested data is consistent. Each processor performs a plurality of tasks,
The task execution code and the data used by the task are stored in an area allocated for each task in the memory area corresponding to each processor.
Data acquisition requests are executed for each task that requests data.
The multiprocessor system according to any one of claims 6 to 8, wherein the requested data copy is executed in a process of a task corresponding to the requested data. The data acquisition request unit is a duplicate request when another task requests the same data when a task requests data in a memory area allocated to another processor. Write the indicated data acquisition request to the notification memory area,
When there is a data acquisition request from a plurality of tasks of the same processor for the same data, the data copy means sends the data to the copy destination requested by any one of the plurality of data acquisition requests. And a completion notification for notifying that the copy of the data acquisition request has been completed is stored in the notification memory area,
The data processing means monitors whether or not a completion notification for the requested data exists in the notification memory area, and if there is a completion notification, the copy requested by another data acquisition request that requests the same data The multiprocessor system according to claim 9, wherein the data is copied first, and the copy of the other data acquisition request is written to the notification memory area.

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