JP2009212736A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent deterioration in imprint characteristics of a ferroelectric capacitor in a semiconductor integrated circuit in which data signals of a latch circuit are held in the ferroelectric capacitor. <P>SOLUTION: The semiconductor integrated circuit has a latch circuit 10 provided with a signal holding part 12 for holding data signals D, and ferroelectric capacitors F1, F2 electrically connected to the signal holding part 12 via switches TR1, TR2. Only during a prescribed period, the switches TR1, TR2 are turned on so as to hold a remanent polarization corresponding to potential of the data signal D in the ferroelectric capacitors F1, F2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit.

  In recent years, the demand for low power consumption is becoming stricter in semiconductor integrated circuits mounted on microcomputers and the like.

  In order to reduce power consumption, for example, there is a method in which supply of power supply voltage to a module not used in the microcomputer is stopped, and current consumption in the module is reduced to zero. However, some modules have a volatile latch circuit such as a shift register or a frequency divider, and if the supply of power supply voltage is stopped, the data signals held in these latch circuits are lost. Resulting in.

  In order to solve this problem, a method is proposed in which a ferroelectric capacitor is supplementarily provided in the latch circuit, and the supply of the power supply voltage is stopped after the data signal held in the latch circuit is held in the ferroelectric capacitor. (Patent Document 1).

  FIG. 1 is a diagram showing a main part of a latch circuit 5 disclosed in Patent Document 1. In FIG.

  In this circuit 5, the retained data signal is output from the output terminal M of the inverter 1. Ferroelectric capacitors 2 and 3 are connected to the input terminal N and the output terminal M of the inverter 1, respectively. Note that one electrode of each of the ferroelectric capacitors 2 and 3 is commonly connected to the terminal P, and is set to the ground potential when the power supply voltage is supplied to the latch circuit 5.

  The ferroelectric capacitors 2 and 3 hold the data signal by utilizing the polarization of the ferroelectric thin film, and function as a nonvolatile memory that holds the data signal even after the power is turned off.

  Therefore, even after the supply of the power supply voltage to the latch circuit 5 is stopped, the potentials of the input terminal N and the output terminal M are held in the ferroelectric capacitors 2 and 3. Then, after the supply of the power supply voltage is started again, the potential held in the ferroelectric capacitors 2 and 3 is taken into the latch circuit 5, and the loss of the data signal is prevented.

  By the way, in the state where the power supply voltage is supplied, the potentials of the input terminal N and the output terminal M of the inverter 1 are opposite to each other, one being the L potential and the other being the H potential. Since the terminal P is at the ground potential, the H potential is always applied to one of the ferroelectric capacitors 2 and 3. Further, when the output of the inverter 1 is inverted, the potential held in the ferroelectric capacitors 2 and 3 is also inverted.

  However, when the potentials of the ferroelectric capacitors 2 and 3 are repeatedly inverted or when the same potential is applied to the ferroelectric capacitors 2 and 3 for a long time, the imprint characteristics of the ferroelectric capacitors 2 and 3 are increased. It will deteriorate.

  FIG. 2 is a diagram schematically showing deterioration of imprint characteristics of the ferroelectric capacitor.

  In the figure, the horizontal axis indicates the voltage V between the electrodes of the ferroelectric capacitor, and the vertical axis indicates the residual polarization charge amount Qsw of the ferroelectric thin film.

  A curve indicated by a solid line is a hysteresis curve of the ferroelectric capacitor in a state where the imprint characteristics are not deteriorated.

  When the imprint characteristic deteriorates, the hysteresis curve shifts downward as indicated by a dotted line. In this case, for example, the amount of remanent polarization when the voltage is 0 is originally Qsw1 is reduced to Qsw2, and it becomes difficult to write data to the ferroelectric capacitor.

In addition, a technique related to the present invention is also disclosed in the following Patent Document 3.
JP 2004-212477 A Japanese Patent Application Laid-Open No. 2004-78772 JP 2000-77986 A

  An object of the present invention is to prevent deterioration of imprint characteristics of a ferroelectric capacitor in a semiconductor integrated circuit in which a ferroelectric capacitor holds a data signal of a latch circuit.

  According to one aspect of the present invention, there is provided a latch circuit including a signal holding unit that holds a data signal, and a ferroelectric capacitor that is electrically connected to the signal holding unit via a switch. There is provided a semiconductor integrated circuit in which the switch is turned on only during a period, and the ferroelectric capacitor holds a residual polarization amount corresponding to the potential of the data signal.

  According to the present invention, since the data signal is held in the ferroelectric capacitor, the data signal is not lost even if the supply of the power supply voltage to the latch circuit is stopped after a predetermined period. In addition, since the ferroelectric capacitor is electrically connected to the signal holding unit only when the switch is turned on, no voltage is applied between the bipolar plates of the ferroelectric capacitor over a long period of time. Deterioration of imprint characteristics of the body capacitor can be prevented.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

  In the following embodiments, an inverted signal of a certain signal “S” is represented by a symbol “S \”. A terminal to which an inverted signal of a signal input to a certain terminal “T” is input is represented by a symbol “TX”.

(1) First Embodiment FIG. 3 is a circuit diagram of a latch circuit 10 provided in a semiconductor integrated circuit according to this embodiment.

  The latch circuit 10 includes first to third clocked inverters INV1 to INV3, first and second transfer transistors TR1 and TR2, and first and second ferroelectric capacitors F1 and F2.

  Among these, the third clocked inverter INV3 functions as the input unit 11 that takes in the data signal D from the input terminal D, and includes p-channel transistors P1, P2 and n-channel transistors between the power line and the ground line. N1 and N2 are connected in series.

  The gates of the p-channel transistor P1 and the n-channel transistor N1 are connected, and the data signal D is applied to these gates. The clock signal is input from the terminal C to the gate of the n-channel transistor N2, and the inverted signal of the clock signal is input from the terminal CX to the gate of the p-channel transistor P2.

  Further, the source / drain of the reset transistor TR3 is connected to the output terminal of the third clocked inverter INV3. The reset transistor TR3 is turned on when the reset signal RST becomes the H potential, and resets the potential at the output terminal of the third clocked inverter INV3 to the ground potential. In the following description, it is assumed that the reset signal RST is at the L potential and the reset transistor TR3 is in the OFF state unless otherwise specified.

  In the third clocked inverter INV3, when the clock signal C becomes H potential, the transistors N2 and P2 are turned on, and the ground potential GND or the power supply potential Vdd is the node according to the on / off state of the transistors N1 and P1. Output to A. When the data signal D is at the H potential, the transistor N1 is on and the transistor P1 is off, so that the ground potential (L potential) GND is output to the node A. On the contrary, when the data signal D is at the L potential, the power supply potential (H potential) Vdd is output to the node A.

  On the other hand, when the clock signal C becomes L potential, the transistors N2 and P2 are turned off, so that the node A is in a high impedance state, and the potential of the node A is fixed regardless of the potential level of the data signal D.

  Thus, the third clocked inverter INV3 has a function of taking in the data signal D in synchronization with the clock signal C and outputting the inverted signal to the subsequent stage.

  The first and second clocked inverters INV1 and INV2 have the same function as this.

  The first and second clocked inverters INV1 and INV2 are connected to each other in a loop shape and function as a signal holding unit 12 for latching (holding) the data signal D.

  Among these, the first clocked inverter INV1 has p-channel transistors P5 and P6 and n-channel transistors N5 and N6 connected in series, and a potential obtained by inverting the potential of the node A is synchronized with the clock signal C1. Output to output terminal Q.

  On the other hand, the second clocked inverter INV2 includes p-channel transistors P3 and P4 and n-channel transistors N3 and N4 connected in series, and a potential obtained by inverting the potential of the node B is synchronized with the clock signal C2 to the node. Output to A.

  Of such clocked inverters INV1 and INV2, the first clocked inverter INV1 on the output side of the latch circuit 10 may be referred to as an output buffer, and the second clocked inverter INV2 may be referred to as a resistance feedback unit. is there.

  The first ferroelectric capacitor F1 is electrically connected to the node B corresponding to the output terminal of the inverter loops of the first and second clocked inverters INV1 and INV2 via the first transfer transistor TR1 functioning as a switch. The

  The second ferroelectric capacitor F2 is electrically connected to the node A corresponding to the input terminal of the inverter loop via the second transfer transistor TR2.

  Of the electrodes of the first and second ferroelectric capacitors F1 and F2, the electrode not connected to the nodes A and B is connected to the plate terminal PL.

  Next, the latch operation of the latch circuit 10 will be described.

  When the data signal D is latched, the transfer transistors TR1 and TR2 are in an off state, and the first and second ferroelectric capacitors F1 and F2 are disconnected from the nodes B and A, respectively.

  Thereafter, the data signal D to be latched is input to the input unit 11, and when all of the clock signals C, C1, and C2 are at the H potential, the data signal D is latched in the loop of the first and second clocked inverters INV1 and INV2. The data signal D is output from the output terminal Q.

  In this state, even if there are clock signals C, C1, and C2 that have an L potential, the potential levels of the nodes A and B do not fluctuate, so that the latched state of the data signal D is maintained and the output terminal Q Continues to output data signal D.

  Such a latch circuit 10 is preferably used as a part of a shift register or the like in a CPU module included in the microcomputer.

  In this case, even if the potential levels of the data signal D and the clock signals C, C1, and C2 do not fluctuate and the on / off states of the transistors constituting the first to third transistors INV1 to INV3 do not fluctuate, A leak current may flow between the source and the drain.

  Since the leakage current hinders the reduction in power consumption of the microcomputer, in this case, it is preferable to stop the supply of the power supply voltage Vdd to the latch circuit 10 and set the leakage current to zero.

  The mode in which the supply of the power supply voltage Vdd is stopped in this manner is hereinafter referred to as a standby mode.

  In order to shift the latch circuit 10 to the standby mode, the following operation may be performed.

  FIG. 4 is a timing chart showing the operation of the latch circuit 10 before and after the standby mode.

  In the standby transition period, by setting the clock signal C to the L potential, the transistors N2 and P2 are turned off, and the node A is disconnected from both Vdd and GND. Note that the clock signal C is synchronized with the system clock signal CL in the microcomputer, and becomes L potential when the system clock signal CL rises.

  Then, by setting the read signal RD to the H potential, the first and second transfer transistors TR1 and TR2 are turned on. Further, the plate signal PL is set to the H potential.

  At this time, when the data signal D of H potential is output from the output terminal Q, the potential difference between the two polar plates of the first ferroelectric capacitor F1 becomes zero, so that it remains in the first ferroelectric capacitor F1. Polarization does not occur. On the other hand, in the second ferroelectric capacitor F2 that is electrically connected to the node A at the L potential, the potential difference between the bipolar plates becomes the H potential, and remanent polarization occurs.

  On the contrary, when the data signal D of L potential is output from the output terminal Q, the remanent polarization occurs in the first ferroelectric capacitor F1, and does not occur in the second ferroelectric capacitor F2.

  When the standby transition period ends in this way, the supply of the power supply voltage Vdd is stopped, and the latch circuit 10 enters the standby mode.

  Even during the standby mode, the data signal D latched in the latch circuit 10 is held in the form of remanent polarization in the first and second ferroelectric capacitors F1 and F2 as described above. There is no risk of D disappearing.

  On the other hand, in order to recover from the standby mode, the clock signals C, C1, and C2 are set to the L potential during the standby recovery period. As a result, the transistors P2, N2, P4, N4, P6, and N6 are turned off, and the nodes A and B are disconnected from both Vdd and GND.

  In this state, the read signal RD is set to the H potential, the transfer transistors TR1 and TR2 are turned on, and the plate signal PL is set to the H potential.

  Here, when the data signal D latched before the standby mode is at the H potential, since the residual polarization is not generated in the first ferroelectric capacitor F1, the potential difference between the bipolar plates of the ferroelectric capacitor F1 is zero. And the potential of the node B becomes the same H potential as the plate signal PL. On the other hand, remanent polarization occurs in the second ferroelectric capacitor F2, and the potential of the node A is lower than that of the PL terminal by an amount corresponding to the amount of remanent polarization charge. Therefore, even if the potential of the plate signal PL is set to the H potential. The potential of the node A becomes the L potential.

  Similarly, when the data signal D latched before the standby mode is at the L potential, the potential of the node A is the H potential and the potential of the node B is the L potential.

  In this manner, the potentials of the nodes A and B are restored to the state before the transition to the standby mode.

  Thereafter, the normal operation is resumed, and the data signal D input from the input terminal D is latched by the signal holding unit 12.

  According to the present embodiment described above, the latched data signal D is supplied to the first and second ferroelectric capacitors Q even when the supply of the power supply voltage is stopped and the latch circuit 10 is set to the standby mode. Therefore, the data signal D is not lost.

  In addition, first and second transfer transistors TR1 and TR2 are provided in front of the first and second ferroelectric capacitors F1 and F2, and these transistors TR1 are provided only for a predetermined period such as a transition period to a standby mode or a standby return period. , TR2 is turned on, and is turned off during other periods.

  Therefore, in periods other than the predetermined period, the first and second ferroelectric capacitors F1, F2 are disconnected from the signal holding unit 12, and the potentials of the nodes A, B are not applied to the ferroelectric capacitors F1, F2. . Therefore, the potentials of the nodes A and B are applied to the ferroelectric capacitors F1 and F2 for a long time, and the potentials between the plates of the ferroelectric capacitors F1 and F2 are repeatedly inverted as the potentials of these nodes are inverted. There is nothing to do. As a result, it is possible to prevent deterioration of the imprint characteristics of the ferroelectric thin film provided in the ferroelectric capacitors F1 and F2.

(2) Second Embodiment In this embodiment, the latch circuit described in the first embodiment is applied to a shift register.

  FIG. 5 is a circuit diagram of the shift register 20 provided in the semiconductor integrated circuit according to the present embodiment.

  The shift register 20 is provided inside a microcomputer such as a CPU, and includes first to fourth latch circuits 21 to 24. The circuit configuration of each of the latch circuits 21 to 24 is the same as that of the latch circuit 10 (see FIG. 3) described in the first embodiment.

  Then, the output terminal Q of the latch circuit in the previous stage is connected to the input terminal D in the subsequent stage, the clock signal CLK is input to the clock terminal C of the first and third latch circuits 21 and 23, and the half-end signal CLK \ is The signal is input to the terminal CX of the second and fourth latch circuits 22 and 24.

  Also, the clock terminals C1 and C2 of the latch circuits 21 to 24 are common, and the standby release signal RDSTB is input to the clock terminals C1 and C2. Similarly, the clock terminals CX1 and CX2 are common to the latch circuits 21 to 24, and the inverted signal RDSTB \ of the standby release signal RDSTB is input to the clock terminals CX1 and CX2.

  FIG. 6 is a timing chart showing the operation of the shift register 20.

In the serial data capture period, the shift data DS input to the input terminal D of the first latch circuit 21 is latched by the first latch circuit 21 when the clock signal CLK rises.
The shift data SD is latched by the second latch circuit 22 at the next fall of the clock signal CLK. Such an operation is performed in synchronization with the clock signal CLK, and the shift data DS is sequentially shifted to the third and fourth latch circuits 23 and 24 in the subsequent stage.

  In the serial data acquisition stop period, the supply of the clock signal CLK is stopped, and the shift data DS immediately before the serial data acquisition stop period is latched by the latch circuits 21 to 24.

  Thereafter, the operation shifts to the standby transition period, and the read signal RD and the plate signal PL become the H potential based on the standby signal STB in the microcomputer including the shift register 20.

  Thereby, as described in the first embodiment, the shift data latched in each of the latch circuits 21 to 24 is held in the ferroelectric capacitors F1 and F2 (see FIG. 3) in these latch circuits. .

  Thereafter, the standby mode is entered, the supply of the power supply voltage Vdd to the shift register 20 is stopped, and the power consumption in the shift register 20 becomes zero.

  Then, after the predetermined period has elapsed, the process proceeds to the standby return period.

  In the standby recovery period, both the read signal RD and the plate signal PL are at the H potential based on the rising edge of the standby release signal RDSTB. As a result, as described in the first embodiment, the shift data DS held in the ferroelectric capacitors F1 and F2 (see FIG. 3) is taken into the first to fourth latch circuits 21 to 24, and the standby mode is set. Return to the previous state.

  Thereafter, the process shifts again to the serial data fetching period, and the shift data DS is sequentially fetched into the latch circuits 21-24.

  According to the present embodiment described above, the latch circuit 10 described in the first embodiment is applied to the first to fourth latch circuits 21 to 24 of the shift register 20, as described with reference to FIG. Therefore, even if the supply of the power supply voltage Vdd to the shift register 20 is stopped in the standby mode, the data held in the latch circuits 21 to 24 immediately before that is stored in the ferroelectric capacitors of the latch circuits 21 to 24. Since it is held in F1 and F2 (see FIG. 3), data loss can be prevented.

  In addition, as described in the first embodiment, the ferroelectric capacitors F1 and F2 are applied with a voltage only during the transition period to the standby mode and during the standby recovery period. It is possible to prevent deterioration of the imprint characteristics of the dielectric thin film.

(3) Third Embodiment In this embodiment, the latch circuit described in the first embodiment is applied to a data register.

  FIG. 7 is a circuit diagram of the data register 30 provided in the semiconductor integrated circuit according to the present embodiment.

  The data register 30 is provided inside a microcomputer such as a CPU, and includes first to eighth latch circuits 31 to 38 having the same circuit configuration as the latch circuit 10 described in the first embodiment.

  As shown in the figure, the latch circuits 31 to 38 are provided in parallel, and an address decoder signal (clock signal) ADDR is commonly input to each terminal C. Then, an inverted signal ADDR \ of the address decoder signal ADDR is input to the terminals CX of the latch circuits 31 to 38 in common.

  Further, the standby release signal RDSTB is commonly input to the terminals C1 and C2 of the latch circuits 31 to 38, and the inverted signal RDSTB is input to the terminals CX1 and CX2 of the latch circuits 31 to 38.

  The input terminals D of the latch circuits 31 to 38 are independent, and the respective bits of the 8-bit data bus signal DBUS are taken into the latch circuits 31 to 38, respectively. Each fetched bit is output from the output terminal Q as each bit of the data register signal DR, and the peripheral circuit of the CPU is controlled by the data register signal DR.

  FIG. 8 is a timing chart showing the operation of the data register 30.

  As shown in this figure, when an instruction cycle, which is one of the CPU instruction cycles, is completed, a period for writing data to the data register 30 is started.

  In the writing period, the address decoder signal ADDR inputted to the clock terminal C of each latch circuit 31 to 38 becomes H potential, and each bit of the data bus signal DBUS is synchronized with each latch circuit 31 to 38 in synchronization with this. It is captured.

  Each bit of the data bus signal DBUS latched in this way is output as each bit of the data register signal DR.

  FIG. 8 illustrates the case where the even bit of the data bus signal DBUS is “01010101” where the even bit is H potential and the odd hit is L potential, but each bit of the data bus signal DBUS is basically independent. However, it is not limited to the illustrated example.

  Thereafter, the standby transition period starts, and the standby signal STB in the CPU rises to the H potential, so that the read signal RD and the plate signal PL become the H potential. As a result, as described in the first embodiment, each bit of the data bus signal DBUS latched in each of the latch circuits 31 to 38 is converted into the ferroelectric capacitors F1 and F2 of the respective latch circuits 31 to 38 (FIG. 3).

  Subsequently, the operation proceeds to the standby mode, and the supply of the power supply voltage Vdd is stopped. At this time, since the data bus signal DBUS immediately before the standby mode is held in the ferroelectric capacitors F1 and F2 as described above, there is no possibility of disappearance.

  Next, when the standby recovery period is entered, the standby release signal RDSTB rises and becomes H potential. In response to this, the read signal RD and the plate signal PL also become the H potential. As a result, as described in the first embodiment, each bit of the data bus signal DBUS held in the ferroelectric capacitors F1 and F2 is taken into each of the latch circuits 31 to 38, and the state immediately before the standby mode is entered. Can return to.

  Thereafter, a CPU instruction cycle such as an instruction cycle is normally performed.

  According to the present embodiment described above, since the latch circuit 10 described in the first embodiment is applied to the first to eighth latch circuits 31 to 38 of the data register 30, the data bus signal DBUS immediately before the standby mode is strong. It is held in the dielectric capacitors F1 and F2, and the loss of the data can be prevented.

  Further, since the voltage is applied to the ferroelectric capacitors F1 and F2 only during the transition period to the standby mode and during the standby recovery period, as in the first embodiment, the ferroelectric thin film is formed by applying the voltage for a long time. It is possible to prevent deterioration of imprint characteristics.

(4) Fourth Embodiment In this embodiment, the latch circuit described in the first embodiment is applied to a frequency divider circuit.

  FIG. 9 is a circuit diagram of the frequency divider circuit 40 provided in the semiconductor integrated circuit according to the present embodiment.

  The frequency dividing circuit 40 is provided inside a microcomputer such as a CPU, and includes a first frequency dividing circuit 41 and a second frequency dividing circuit 42 to which a reset signal RST is input in common. As illustrated, the output terminal J of the first frequency divider circuit 41 is connected to the clock terminal CLK of the second frequency divider circuit 42. The output terminal J of the first frequency dividing circuit 41 is connected to the terminal CLK \ of the second frequency dividing circuit 42 via the inverter 43.

  FIG. 10 is a circuit diagram of each of the first and second frequency dividing circuits 41 and 42.

  Each of the frequency dividing circuits 41 and 42 includes first and second latch circuits 46 and 47 and an inverter 48. The circuit configuration of the first and second latch circuits 46 and 47 is the same as that of the latch circuit 10 (see FIG. 3) described in the first embodiment, and is used to hold data immediately before shifting to the standby mode. Ferroelectric capacitors F1 and F2 (see FIG. 3) are provided in the latch circuits 46 and 47, respectively.

  The clock signal CLK is input to the clock terminal C of the first latch circuit 46 and the terminal CX of the second latch circuit 47, and the inverted signal CLK \ of the clock signal CLK is input to the terminal CX of the first latch circuit 46 and the second latch circuit. 47 is input to the terminal clock terminal C.

  The output terminal Q of the first latch circuit 46 is connected to the input terminal D of the second latch circuit 47, and the output terminal Q of the second latch circuit 47 is connected to the input terminal D of the first latch circuit 46 via the inverter 48. Connected.

  FIG. 11 is a timing chart showing the operation of this frequency dividing circuit. In FIG. 11, symbols G to K indicate the potentials of the nodes G to K in FIGS. 9 and 10.

  Further, the frequency divider standby release signal FDSTB is a signal that is commonly input to the terminals C1 and C2 (see FIG. 3) of the first and second latch circuits 46 and 47, and the inverted signal FDSTB \ 1 and the second latch circuits 46 and 47 are input in common to the respective terminals CX1 and CX2. In FIG. 10, since the drawing becomes complicated, these terminals C1, C2, CX1, and CX2 are omitted.

  As shown in FIG. 11, in the normal operation period, the frequency dividing operation with respect to the clock signal CLK starts with the rise of the reset signal RST, and a signal obtained by dividing the clock signal CLK by 2 is output from the nodes G to J. The rounded signal is output from node K.

  After the normal operation period ends, the standby shift period starts.

  In the standby transition period, the standby signal STB in the CPU rises to the H potential, and in response to this, the read signal RD and the plate signal PL become the H potential. As a result, the data signals output from the output terminals Q of the first and second latch circuits 46 and 47 are held in the ferroelectric capacitors F1 and F2 (see FIG. 3) of the latch circuits 46 and 47, respectively. The

  Thereafter, the standby period is entered, and the supply of the power supply voltage Vdd is stopped. At this time, since the data signal immediately before the standby period is held in the ferroelectric capacitors F1 and F2 as described above, there is no possibility of disappearance.

  Next, when the standby recovery period starts, the read signal RD, the plate signal PL, and the frequency divider standby release signal FDSTB are set to the H potential. As a result, as described in the first embodiment, the data signals held in the ferroelectric capacitors F1 and F2 are taken into the latch circuits 46 and 47, respectively, and the state immediately before the standby period is restored.

  Thereafter, the normal operation is resumed, and the frequency dividing operation for the clock signal CLK is performed again.

  According to the present embodiment described above, the latch circuit 10 described in the first embodiment is applied to the first and second latch circuits 46 and 47 provided in the first and second frequency dividing circuits 41 and 42, respectively.

  As a result, the data signal immediately before the standby mode is held in the ferroelectric capacitors F1 and F2 (see FIG. 3) to prevent the data from being lost, and the voltage is applied to the ferroelectric capacitors F1 and F2 for a long time. It is possible to prevent deterioration of the imprint characteristics of the ferroelectric thin film due to.

  The features of the present invention are added below.

(Additional remark 1) It has a latch circuit provided with the signal holding part holding a data signal, and the ferroelectric capacitor electrically connected to the signal holding part via a switch,
A semiconductor integrated circuit, wherein the switch is turned on only within a predetermined period, and the ferroelectric capacitor holds a residual polarization amount corresponding to the potential of the data signal.

(Additional remark 2) The said signal holding | maintenance part hold | maintains the said data by the inverter loop of a 1st inverter and a 2nd inverter,
The semiconductor integrated circuit according to appendix 1, wherein one electrode of the ferroelectric capacitor is electrically connected to at least one of an input end and an output end of the inverter loop via the switch.

  (Supplementary note 3) The semiconductor integrated circuit according to supplementary note 2, wherein the first inverter is an output buffer, and the second inverter is a feedback resistor.

  (Supplementary note 4) The semiconductor integrated circuit according to Supplementary note 2 or 3, wherein the first inverter and the second inverter are clocked inverters.

  (Supplementary Note 5) The semiconductor integrated circuit according to any one of Supplementary Notes 1 to 4, wherein the latch circuit further includes an input unit that captures the data signal in synchronization with a clock signal.

  (Supplementary note 6) The semiconductor integrated circuit according to supplementary note 5, wherein a plurality of stages of the latch circuits are provided to constitute a frequency dividing circuit that divides the clock signal.

  (Supplementary note 7) The semiconductor integrated circuit according to Supplementary note 5, wherein a plurality of stages of the latch circuit are provided, and a shift register is configured to sequentially shift the data signal to the latch circuit in synchronization with the clock signal.

  (Supplementary Note 8) A supplementary note is provided, wherein a plurality of the latch circuits are provided in parallel, and a data register is configured to capture each bit of the data signal of a plurality of bits in each of the latch circuits in synchronization with the clock signal. 5. The semiconductor integrated circuit according to 5.

  (Additional remark 9) The said latch circuit further has a plate terminal, The electrode of the said ferroelectric capacitor which is not connected to the said latch circuit is connected to the said plate terminal, The additional notes 1-8 characterized by the above-mentioned. The semiconductor integrated circuit in any one.

  (Supplementary note 10) The semiconductor integrated circuit according to any one of supplementary notes 1 to 9, wherein supply of a power supply voltage to the latch circuit is stopped after the predetermined period has elapsed.

FIG. 1 is a diagram illustrating a main part of a latch circuit disclosed in Patent Document 1. In FIG. FIG. 2 is a diagram schematically showing deterioration of imprint characteristics of the ferroelectric capacitor. FIG. 3 is a circuit diagram of a latch circuit included in the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 4 is a timing chart showing the operation of the latch circuit shown in FIG. FIG. 5 is a circuit diagram of a shift register included in the semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 6 is a timing chart showing the operation of the shift register shown in FIG. FIG. 7 is a circuit diagram of a data register included in the semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 8 is a timing chart showing the operation of the data register shown in FIG. FIG. 9 is a circuit diagram of a frequency divider provided in a semiconductor integrated circuit according to the fourth embodiment of the present invention. FIG. 10 is a circuit diagram of each of the first and second frequency divider circuits of FIG. FIG. 11 is a timing chart showing the operation of the frequency dividing circuit shown in FIGS.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Inverter, 2, 3 ... Ferroelectric capacitor, 5, 10 ... Latch circuit, 11 ... Input part, 12 ... Signal holding part, 20 ... Shift register, 21-24 ... 1st-4th latch circuit, 30 ... Data registers, 31 to 38, first to eighth latch circuits, 40, frequency dividing circuits, 41, 42, first and second frequency dividing circuits, 46, 47, first and second latch circuits, 48, inverters, INV1 to INV3: first to third clocked inverters, TR1, TR2: first and second transfer transistors, TR3: reset transistor, F1, F2: first and second ferroelectric capacitors.

Claims (5)

A latch circuit including a signal holding unit for holding a data signal and a ferroelectric capacitor electrically connected to the signal holding unit via a switch;
A semiconductor integrated circuit, wherein the switch is turned on only within a predetermined period, and the ferroelectric capacitor holds a residual polarization amount corresponding to the potential of the data signal.   The semiconductor integrated circuit according to claim 2, wherein the latch circuit further includes an input unit that captures the data signal in synchronization with a clock signal.   3. The semiconductor integrated circuit according to claim 2, wherein a plurality of stages of the latch circuits are provided, and a frequency dividing circuit that divides the clock signal is configured.   3. The semiconductor integrated circuit according to claim 2, wherein a plurality of stages of the latch circuits are provided, and a shift register that sequentially shifts the data signal to the latch circuits in synchronization with the clock signal is configured.   3. The data register according to claim 2, wherein a plurality of the latch circuits are provided in parallel, and each of the plurality of bits of the data signal is incorporated into each of the latch circuits in synchronization with the clock signal. Semiconductor integrated circuit.

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