JP2009205428A - Redundant information-processing system, method of normally switching host unit, and program therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable redundant information-processing system which effectively prevents a system failure due to incorrect data written into a shared memory when an active host unit and a stand-by host unit are forcibly switched. <P>SOLUTION: The redundant information-processing system is provided with: an active host unit 1 and a stand-by host unit 2 which can be mutually switched; a shared memory part 3 connected to the host units 1, 2 so as to be available; and a shared bus 103 which connects the parts. In addition, the shared memory part 3 has the first and second memory parts 6, 7, which store the same write information from the active host unit 1, and a delay control part 5 which is connected to an input stage of the second memory part 7 and delays the write information by a delay time. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a redundant configuration information processing system, and more particularly to a redundant configuration information processing system with improved reliability, a host unit switching normalization method, and a program thereof.

  A redundant configuration of system components is widely known as a basic technique for increasing the reliability and availability of an information processing system (for example, Patent Documents 1 and 2). Although there are various forms of redundant configurations, the target here is that host units 100 and 200 equipped with processors (hereinafter referred to as CPU (Central Processing Unit)) as shown in FIG. This is an information processing system having a redundant configuration of a standby system and having a common memory unit 300 connected thereto by a common bus 1030.

  In the information processing system having the configuration shown in FIG. 6, when the host unit 100 is in the operating state and the host unit 200 is in the standby state, the host unit 100 transmits data for functioning as the information processing system to the common bus 1030. The common memory unit 300 is written to / read from.

  In the system shown in FIG. 6, when the normal system switching control between the host units 100 and 200 for normal maintenance or the like is executed by an operator (maintenance person), the software of the host unit 100 performs processing in the middle of execution. Waiting for completion, the host unit 200 is notified by the switching signal 1010 that the host system is in a standby state, and the host unit 200 that has been in the standby state indicates that it has transitioned to the operating state by the switching signal 1020. 100 is notified. Thereby, the system switching according to the regular system switching procedure with software interposed is completed.

On the other hand, even when a hardware failure occurs in the active host unit 100 or in the case of forced system switching by forced reset, the host unit 200 is notified by the switching signal 1010 that the local system has become inoperable. Then, the host unit 200 that has been in the standby state transitions to the operation state. However, the switching signal 1010 in this case is configured to perform forced system switching regardless of the processing being executed, unlike the case of regular system switching.
JP 2006-268596 A JP 2007-274255 A

  The forcible system switching of the host unit in the background art described above has the following disadvantages. That is, in this case, as shown in the timing chart of FIG. 7, forced system switching is performed regardless of the processing being executed. Therefore, at this switching, the host unit 100 performs write bus access to the common memory unit 300. If it is being executed, the bus access on the common bus 1030 is interrupted, and there is a possibility that the data at that address may be rewritten as illegal data.

  In addition, when the host unit 200 which has become a new active system by switching the system takes over the processing of the host unit 100 and uses the data of the address, the host unit 200 also fails because the data is invalid data. There was an inconvenience that could go down.

(Object of invention)
In view of the above problems, the present invention avoids unauthorized data derived from forced system switching in the common memory unit without causing the unauthorized data to be involved in the switched operation system, thereby causing a system failure. It is an object of the present invention to provide a highly reliable redundant information processing system, a host unit switching normalization method, and a program therefor that can prevent the above problem.

  In order to achieve the above object, an information processing system having a redundant configuration according to the present invention includes a host unit for an active system and a standby system configured to be switchable with each other, and a common unit in which each host unit is connected to be usable. A redundant information processing system including a memory unit and a common bus connecting these units, wherein the common memory unit stores the same write information from the active host unit. And a delay control unit connected to the input stage of the second memory unit and delaying the write information by a preset delay time.

  In order to achieve the above object, the host unit switching normalization method according to the present invention includes a host unit of an operation system and a standby system configured to be switchable with each other, and each host unit via a common bus. In a redundant information processing system having a common memory unit comprising a first memory unit and a second memory unit that are connected and execute write access from the active host unit, the host unit is switched when the host unit is switched. A host unit switching normalization method for avoiding a system failure caused by illegal data held in a common memory unit, wherein when the above-mentioned active host unit is operating, Write bus access after a predetermined delay time from execution of write bus access in the first memory unit A delayed write process, a host unit switching process for switching the active host unit and the standby host unit to each other by a system switching signal output from the active host unit, and after the host unit switching process. After the write bus access operation to the second memory unit is completed, the second memory unit immediately executes read / write bus access as a working memory, and the first memory unit serves as a spare memory and the preset delay. And a memory switching step for executing write bus access over time.

  Furthermore, in order to achieve the above object, the host unit switching normalization program according to the present invention includes each host unit of the active system and the standby system configured to be mutually switchable via each host unit and a common bus. In a redundant information processing system having a common memory unit comprising a first memory unit and a second memory unit that are connected and execute write access from the active host unit, the host unit is switched when the host unit is switched. This is to avoid the occurrence of a system failure caused by illegal data held in the common memory unit.

  The host unit switching normalization program sets the write bus access to the second memory unit in advance from the execution of the write bus access in the first memory unit when the above-described active host unit is operating. Delayed write processing that is allowed to be executed in the second memory unit after a specified delay time, and the common based on the switching information when the active host unit and the standby host unit are switched to each other A delay time switching process for switching to the first memory unit as a spare memory corresponding to the standby host unit after switching the setting of the delay time set in the second memory unit of the memory unit; and the host unit After the switching, after the completion of the write bus access operation to the second memory unit, the second memory unit A memory switching connection process in which a read / write bus access is immediately executed as a memory and the first memory unit executes a write bus access after a preset delay time as a spare memory; It is made to run on the computer with which it is equipped.

  Since the present invention is configured as described above, according to this, even if illegal data derived by forced system switching of the operating system host unit due to a failure or the like is written in the memory unit in the common memory unit, it is installed in advance. Since the delay control unit functions effectively and the memory unit corresponding to the active host unit newly set by the forcible switching can be configured so that there is no invalid data, It is possible to provide an unprecedented and highly reliable redundant information processing system, a host unit switching normalization method, and a program thereof that are not involved and therefore can prevent a failure from occurring.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
Here, FIG. 2 shows an overall block configuration of the redundant information processing system according to the first embodiment. FIG. 1 shows the internal configuration of the common memory unit, which is the central content of the first embodiment.
Here, in the first embodiment, the basic configuration contents of the redundant information processing system according to the present invention will be described first, and then the specific contents thereof will be described together with the operation thereof.

  First, the redundant information processing system shown in FIGS. 1 and 2 is used for each of the active and standby host units 1 and 2 configured to be mutually switchable, and the host units 1 and 2. A common memory unit 3 that is connected to each other and a common bus 103 that connects these units are provided.

Among these, the common memory unit 3 includes a first memory unit 6 (active memory) and a second memory unit (spare memory) 7 that store the same write information from the active host unit 1, Any one of the memory units installed in the input stage of each of the first to second memory units 7 and functioning as a spare memory (in this embodiment, the second memory unit 7 before switching and the first memory unit 6 after switching) And a delay control unit 5 that delays the write information by a preset delay time.
For this reason, even if invalid data derived from forced system switching of the active host unit 1 due to a failure or the like is written to the memory units 6 and 7 in the common memory unit 3, the pre-equipped delay control unit 5 is effective. The memory unit 7 corresponding to the active host unit newly set by the forcible switching can prevent the illegal data from being present, and the switched active host unit is involved in the illegal data. Therefore, it is possible to prevent a failure from occurring.

  The delay control unit 5 inputs a write bus access from the active host unit 1 via the common bus 103, and performs a storage operation of the first memory unit (functioning as a working memory) 6 formed thereby. The execution timing is captured, and the delay time is set in accordance with the timing. Reference numeral 202 denotes a delay bus. In this embodiment, the set delay time is set for each bus access unit, or may be set to any integer multiple of twice or more.

  Here, in the first embodiment, when the standby host unit 2 described above is switched to the active host unit, the delay control target by the delay control unit 5 of the common memory unit 3 is corresponding to this. In principle, the second memory unit 7 can be switched to the first memory unit 6.

  The common memory unit 3 described above corresponds to each of the first and second memories corresponding to the write bus access sent from the active host unit 1 via the common bus 103 directly or via the delay control unit 5. The memory switching mechanism 30 for sending to the units 6 and 7 and the bus switching control unit 4 for controlling the switching operation of the memory switching mechanism 30 are provided.

  The bus switching control unit 4 operates based on the write bus access and switching signal sent from the operating host unit 1 or the switched operating host unit and operates through the memory switching mechanism 30 to perform the first, first, and second switching operations. Each of the second memory units 6 and 7 is configured to be selectively set for an active or standby host unit.

  When the standby host unit 2 is switched as the active host unit due to the forced system switching due to the accident of the active host unit 1, the bus switching control unit 4 is interrupted by the system switching. It has a function of blocking, via the memory switching mechanism 30, that a write bus access during writing to the first memory 6 is continuously input to the second memory unit 7.

  The bus switching control unit 4 of the common memory unit 3 described above writes the bus access to the second memory unit 7 when the active and standby host units 1 and 2 are switched by forced switching. Has a function of switching the roles of the first memory unit 6 and the second memory unit 7 after the completion of the process. Simultaneously with the role switching by the bus switching control unit 4, the second memory unit 7 can immediately execute the read / write bus access sent from the operational host unit as a working memory and the first memory. The unit 6 has a configuration capable of executing a write bus access sent through the preset delay time as a spare memory.

  Further, the bus switching control unit 4 is configured such that when the standby host unit 2 is switched to the active host unit by the forced system switching and there is no write bus access on the common bus 103, the bus switching control unit 4 Switching between the first and second memory units 6 and 7 is not executed and is maintained as it is. This is because when there is no write bus access, the above-described illegal data does not occur, so that unnecessary operations and controls are eliminated and data processing is speeded up.

  Here, the memory switching mechanism 30 described above is specifically connected to the common bus 103 and individually provided for each of the memory units 6 and 7, as will be described later. Bidirectional buffers 8 and 9 that allow or prevent writing / reading to / from the memory, and between the delay control unit 5 and the memory units 6 and 7 are provided corresponding to the memory units 6 and 7, respectively. One-way buffers 10 and 11 that allow or block writing to the memory units 6 and 7 are provided. As a result, each memory unit 7 or 6 as a spare memory is delayed by a predetermined time (for example, unit bus access) and sent to each memory unit 7 or 6, resulting in a state where illegal data is not sent. (In other words, illegal data storage operation is effectively prevented on the spare memory side).

  When the active host unit 1 is switched to the standby system by the host unit system forcible switching signal described above, the bus access is interrupted by this system switching. 3 is configured such that when each host unit 1 or 2 becomes an active system, it is excluded by the illegal data exclusion function that is inherently provided in the active host unit 1 or 2. Yes.

This will be described in detail below.
As described above, in the redundant configuration information processing system according to the first embodiment, the host units 1 and 2 on which the processors are mounted have a redundant configuration of the active system and the standby system, and the host units 1 and 2 have the common bus 103. And a common memory unit 3 for writing and reading data. Further, the switching signals 101 and 102 for controlling the system switching between the host unit 1 and the host unit 2 are sent to the other host units 2 and 1 through signal lines wired between the host units 1 and 2, respectively. At the same time, it is also input to the common memory unit 3.

  Therefore, in the redundant information processing system according to the first embodiment, when the system switching between the host units 1 and 2 is executed due to a failure or the like by the switching signals 101 and 102 to the common memory unit 3, In the common memory unit 3 as well, memory switching is performed within the common memory unit 3 and normalization is avoided by avoiding illegal data that may be written at the time of system switching, as will be described later, thereby allowing normal operation to continue. It has become a structure.

Next, the internal configuration of the common memory unit 3 described above will be described in further detail.
As shown in FIG. 1, the common memory unit 3 includes first and second memory units 6 and 7, and a delay control unit 5 that delays a signal on the common bus 103 and supplies the signal to the delay bus 202. And bi-directional buffers 8 and 9 for individually connecting the common bus 103 and the first and second memory units 6 and 7, respectively, and the delay bus 202 and the memory units 6 and 7 are individually connected. Unidirectional buffers 10 and 11, and a bus switching control unit 4 that performs switching control of the memory units 6 and 7 in response to switching of the host units 1 and 2 through the buffers 8, 9, 10, and 11, respectively. It is configured. Here, the memory switching mechanism 30 is configured by the buffers 8 to 11 as described above.

The normal bus 201 is a bus that relays the bus access on the common bus 103 as it is, and the delay bus 202 temporarily holds the bus access on the common bus 103 by the delay control unit 5, and the read bus access is not relayed but written This bus relays bus access as a bus cycle delayed by one bus cycle.
The influence of illegal data caused by interruption of writing to the first memory unit (active memory) 6 due to system switching due to writing to the second memory unit (reserved memory) 7 delayed by one bus cycle by the delay bus 202 will be described later. It can be eliminated.

  The bus switching control unit 4 has a function of switching the roles of the current memory and the spare memory of the first and second memory units 6 and 7. This bus switching control unit 4 monitors the switching signals 101 and 102 output from the host unit 1 or 2 and the bus access transfer direction (write or read) on the common bus 103, and switches the host unit during write access. Is detected, the buffers 8 to 11 are controlled to switch the connection combination of the memory unit 6 and the memory unit 7 to the normal bus 201 and the delay bus 202.

  Thus, in response to the system switching of the host units 1 and 2, the first and second memory units (current and spare memory units) 6 and 7 are switched within the common memory unit 3. Normal operation can be continued by avoiding illegal data that may have been written to the unit 6.

The memory switching mechanism 30 will be described in further detail.
When the host unit 1 is an active system, the first memory unit 6 is operated as a working memory, and immediate reading and writing are performed. Therefore, the bidirectional buffer 8 is set in an operational state (enabled) by a control signal s8 and a signal on the normal bus 201 is transmitted. It is configured to pass through. At this time, the one-way buffer 10 is closed (disabled) by the control signal s10.

On the other hand, in the second memory unit 7 operated as a spare memory, the bidirectional buffer 9 is closed by the non-operation state by the control signal s9 and is disconnected from the normal bus 201, but the one-way buffer 11 is controlled by the control signal s11. In this configuration, the operation of writing a signal delayed by one bus cycle on the delay bus 202 can be performed.
By this operation of writing a signal delayed by one bus cycle, even if system switching occurs during the writing operation of the current memory 6 and abnormal data is written to the current memory 6, the writing of the spare memory 7 is delayed by one cycle. Therefore, abnormal data is never written.

  Then, when the host unit is switched from the active system to the standby system by the system switching signal, the first memory unit 6 that has been the current memory until now corresponds to the spare, and the second memory that has been the spare memory. The unit 7 is configured to be switched to the working memory.

That is, in the first memory unit 6 that is the active memory, the bidirectional buffer 8 in the operating state is blocked by the control signal s8, and the one-way buffer 10 that has been in the non-operating state is set in the operating state by the control signal s10. It becomes a spare memory for writing a delay signal on the bus 202.
On the other hand, in the second memory unit 7 that is a spare memory, the unidirectional buffer 11 in the operating state waits for the completion of the bus cycle and is closed by the control signal s11 to be inactive and closed. 9 is activated by a control signal s9 and is connected to the normal bus 201 to operate as a working memory.

The bus controller 4 generates signals s8 to s11 for controlling the operation and non-operation states of the bidirectional buffers 8 and 9 and the unidirectional buffers 10 and 11 as described above.
Even if the system switching occurs and the host unit 1 is switched to the standby system, if the writing operation is not performed in the current memory unit 6, no illegal data is written. It does not have to be done.

  In addition, when the bus access is interrupted due to system switching and illegal data is written, a hardware mechanism for storing the write address of the data and excluding the data of the common memory unit 3 (current memory) from the address is provided. You may prepare. In this case, the host unit 1 or 2 described above may be configured to have an unauthorized data exclusion function that functions when the host unit 1 or 2 becomes an active host unit, thereby eliminating the aforementioned unauthorized data. .

(System switching operation)
As described above, in the memory units 6 and 7 in the common memory 3, the write bus access from the active host unit 1 to the spare second memory unit 7 is the write bus access to the working first memory unit 6. Is performed after a delay time of one bus cycle (delayed writing step). Therefore, switching of the delayed writing is also necessary for switching between the memory units 6 and 7.

  Next, when a system switchover of the active host unit occurs due to a normal system switchover procedure such as an inspection by a maintenance person (operator), or a forced system switchover occurs due to a hardware failure or forced reset, etc. A system switching operation of the information processing system will be described.

(For regular system switchover procedure)
FIG. 3 is a timing chart showing a case of a regular system switching procedure performed at the time of inspection or the like. Here, a0 a1, a2,... Indicate address information, d0, d1, d2,... Indicate transmission data, w indicates a write command, and r indicates a read command (the same applies hereinafter).
When the host unit system switching control is executed by the maintenance person (operator), as shown in FIG. 3, the software of the host unit 1 in the operating state is notified by the switching signal 101 after the process in the middle of execution is completed. The host unit 2 is notified that the host system is in a standby state, and the host unit 2 that has been in the normal standby state notifies the host unit 1 of the transition to the operation state by the switching signal 102. This completes system switching according to the regular system switching procedure mediated by software.

At this time, the bus switching control unit 4 shown in FIG. 1 detects that the host unit system switching has occurred due to the change of the switching signal 101 (see FIG. 3), but the common memory unit executed on the common bus 103. 3 is not accessed (see FIG. 3), the memory units 6 and 7 are not switched.
That is, the operation settings of the bidirectional buffers 8 and 9 and the unidirectional buffers 10 and 11 are not changed, the bidirectional buffer 8 is set in an operating state (enabled), and the bidirectional buffer 9 is set in a non-operating state (disabled). 201 is connected to the memory 6, the one-way buffer 10 is disabled, the one-way buffer 11 is enabled, and the state where the delay bus 202 is connected to the memory 7 is held.

(Forcible system switchover)
Next, FIG. 4 shows a timing chart in the case of forced system switching represented by hardware failure or forced reset.
In this case, the host unit 1 in operation notifies the host unit 2 that the host system 2 has become inoperable by the switching signal 101 even during the process regardless of the process being executed. The host unit 2 that has been in the standby state is forcibly switched over by transitioning to the operating state (system switching step).

  At this time, in response to this system switching, the memories 6 and 7 are also switched inside the common memory unit 3. That is, the bus control unit 4 detects that the host unit system switching has occurred due to the change of the switching signal 101, and simultaneously detects the write bus access of the common memory on the common bus 103, as in the case of regular system switching. Then, after the writing to the second memory unit 7 which is a spare memory by the delay bus 202 is completed, the bidirectional buffer 8 is disabled, the bidirectional buffer 9 is changed to enabled, the normal bus 201 is connected to the memory 7, and the unidirectional The memory 10 and 7 are switched by changing the buffer 10 to enabled, the one-way buffer 11 to disabled, and connecting the delay bus 202 to the memory 6 (memory switching step).

  In this way, when a forced system switchover occurs, in conjunction with the system switchover of the host units 1 and 2, to the spare second memory unit 7 to which no illegal write access is input in the common memory unit 3. By switching, it is possible to avoid using the current first memory unit 6 in the common memory unit 3 in which the host unit 2 that has newly become the active system may be rewritten as illegal data. It is possible to prevent a failure caused by illegal data at the time of switching, and to provide an information processing system with high reliability and availability.

  Here, in the first embodiment, the host unit switching normalization method is configured by the steps of the delayed write process, the system switching process, and the memory switching process described above. It is possible to avoid the occurrence of a system failure due to illegal data held in the common memory unit 3.

  Here, when the active host unit 1 is switched to the standby host unit by system switching, if there is no write bus access on the common bus 103 at the time of system switching, there is no fear that illegal data will be written. The memory switching process for switching the first and second memory units 6 and 7 of the memory unit 3 may not be executed.

  Further, of the processing contents of the above-described delayed writing process, system switching process, and memory switching process, the contents of the range to be processed by the above-described bus switching control part are programmed to be a host unit switching normalization program. It may be configured to be executed by a computer.

In this case, the host unit switching normalization program may be specified as follows.
That is, the host unit switching normalization program according to the first embodiment includes the operating system and standby system host units 1 and 2 configured to be able to switch to each other, and the host units 1 and 2 and the common bus unit 3. A redundant configuration information processing system having a common memory unit 3 including a first memory unit 6 and a second memory unit 7 connected to each other through the active host unit 1 and performing write access from the active host unit 1. This is to avoid the occurrence of a system failure due to illegal data retained in the common memory unit 3 when the host units 1 and 2 are switched.

  The host unit switching normalization program is configured such that when the active host unit 1 is operating, the write bus access to the second memory unit 7 is executed from the execution of the write bus access in the first memory unit 6. Delayed write processing that is allowed to be executed in the second memory unit 7 after a preset delay time, and the switching information when the active host unit 1 and the standby host unit 2 are switched to each other The delay for switching to the first memory unit 6 as a spare memory corresponding to the standby host unit after switching the setting of the delay time set in the second memory unit 2 of the common memory unit 3 based on After the time switching process and the host unit switching and after the completion of the write bus access operation to the second memory unit 7, Memory switching connection in which the second memory unit 7 immediately executes a read / write bus access as a working memory, and the first memory unit 6 executes a write bus access after the preset delay time as a spare memory This is characterized in that the processing is executed by a computer provided in the bus switching control unit 4.

  Further, as the above program, when the active host unit 1 is switched to the standby system by system switching, if there is no write bus access on the common bus 103 at the time of system switching, there is no possibility that illegal data is written. Therefore, it may be configured not to execute the memory switching process for performing the mutual switching of the first and second memory units 6 and 7 of the common memory unit 3.

  As described above, in the first embodiment, the working memory (first memory unit 6) and the spare memory (second memory unit 7) to be written with a certain delay in the common memory unit 3 are used. With this, even if there is a write bus access that may be rewritten to illegal data, the write is interrupted at the timing when the system switching between the host units 1 and 2 occurs. By using the spare memory (second memory unit 7) that has not been input by switching to the active memory, in the host unit 2 that newly becomes the active system by system switching, it is caused by illegal data in the common memory unit 3 Reliability, high availability information processing system, host unit switching normalization method, and program thereof It is possible to provide.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG.
FIG. 5 shows the internal configuration of the common memory unit 3B of the information processing system according to the second embodiment. As shown in FIG. 5, the second embodiment is characterized in that a delay amount setting unit 12 is added to the delay control unit 5 of the first embodiment in FIG. 1 described above. Other configurations and the operation and effects thereof are the same as those of the first embodiment (FIGS. 1 to 4) described above.

  In FIG. 5, the delay amount setting unit 12 has a function of presetting the delay amount of the delay bus 202 to be relayed from the active host unit 1 to the second memory unit 7. It is configured to notify information related to a preset delay amount.

  The delay control unit 5 notified of the delay amount from the delay amount setting unit 12 delays the bus access executed on the common bus 103 in accordance with the information related to the delay amount, and reserves the second second time via the delay bus 202. Relay to the memory unit 7 for writing.

  For this reason, in the second embodiment, the delay control unit 5 is not limited to the unit bus access, but the bus access such as double, triple,. Therefore, there is an advantage that it is highly versatile and can effectively cope with changes in the surrounding environment.

  That is, in the second embodiment, even when the bus access is not completed in one bus cycle and it is necessary to write valid data by the bus access by a plurality of consecutive bus cycles, it is necessary for the writing. By ensuring a plurality of bus cycle delay times, the validity of the data to be written to the common memory can be ensured. Therefore, the redundant information processing system and host unit having new effects not found in the first embodiment described above A switching normalization method and its program can be provided.

It is a block diagram which shows the internal structure of the common memory part in the information processing system of the redundant structure which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the whole structure of the information processing system of a redundant structure provided with the common memory part disclosed in FIG. 3 is a timing chart showing the operation of each unit when the host unit is switched synchronously by a regular system switching procedure in the first embodiment disclosed in FIG. 2. 3 is a timing chart illustrating the operation of each unit when the host unit is forcibly (asynchronously) switched in the first embodiment disclosed in FIG. 2. It is a block diagram which shows the internal structure of the common memory part in the information processing system of the redundant structure which concerns on the 2nd Embodiment of this invention. It is a block which shows an example of the redundant structure information processing system in related technology. FIG. 7 is a timing chart showing an operation of the redundant configuration information processing system shown in FIG. 6.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Active system host unit 2 Standby system host unit 3,3B Common memory part 4 Bus switching control part 5 Delay control part 6 1st memory part (working memory)
7 Second memory section (spare memory)
8,9 Bidirectional buffer 10,11 Unidirectional buffer 12 Delay amount setting unit 30 Memory switching mechanism 101,102 Switching signal 103 Common bus 201 Normal bus 202 Delay bus

Claims (13)

Redundant configuration information comprising each of the active and standby host units configured to be switchable with each other, a common memory unit to which each host unit is connected, and a common bus connecting these units. A processing system,
The common memory unit is connected to the first and second memory units for storing the same write information from the active host unit and the input stage of the second memory unit, and the write information is preset. A redundant information processing system comprising: a delay control unit that delays by a delay time. In the redundant information processing system according to claim 1,
The redundant control information system according to claim 1, wherein the delay control unit sets the delay time based on a timing at which the first memory unit executes a write bus access from the active host unit. In the redundant information processing system according to claim 1 or 2,
The redundantly configured information processing system characterized in that the set delay time is either a bus access unit or an integer multiple of twice or more. In the redundant information processing system according to claim 2,
When the standby host unit is switched to the active host unit, the target of delay control by the delay control unit of the common memory unit is correspondingly changed from the second memory unit to the first memory unit. A redundant information processing system characterized by being switched. In the redundant information processing system according to claim 2,
A memory switching mechanism in which the common memory unit sends a write bus access sent via the common bus directly or directly to the first and second memory units in a corresponding relationship via the delay control unit; A bus switching control unit for controlling the switching operation of the memory switching mechanism,
The bus switching control unit operates based on a write bus access and switching signal sent from the operating host unit of the operating host unit or the former standby host unit, and the first and first signals are transmitted via the memory switching mechanism. 2. An information processing system having a redundant configuration, wherein each of the two memory units is selected and set for an active or standby host unit. In the redundant information processing system according to claim 5,
When the standby host unit is switched as the active host unit by system switching that is forcibly executed due to a failure of the active host unit, the bus switching control unit is interrupted by the system switching. Redundant configuration information characterized by having a function of preventing, via the memory switching mechanism, a write bus access during writing to the first memory from being continuously input to the second memory unit Processing system. In the redundant configuration information processing system according to claim 5,
When the active and standby host units are forcibly switched, the bus switching control unit of the common memory unit has the first memory unit and the first memory unit after the completion of the write bus access to the second memory unit. 2 Has the function of switching the role of the memory part,
Simultaneously with the role switching by the bus switching control unit, the second memory unit can immediately execute the read / write bus access, and the first memory unit performs the write bus access through the preset delay time. An information processing system with a redundant configuration characterized in that the configuration is executable.
In the redundant configuration information processing system according to claim 5,
The bus switching control unit of the common memory unit, when the standby host unit is switched to the active host unit by the forced system switching, and when there is no write bus access on the common bus, An information processing system having a redundant configuration, characterized in that switching between the first and second memory units is maintained as is. In the redundant configuration information processing system according to claim 5,
The memory switching mechanism is connected to the common bus and is provided corresponding to each memory unit individually, and a bidirectional buffer that allows or blocks writing / reading to each memory unit; and the delay control unit; A redundant configuration characterized by comprising a unidirectional buffer provided corresponding to each memory unit and allowing or preventing writing to each memory unit between the memory units. Information processing system. In the redundant information processing system according to claim 1, 2, 5, or 7,
When the standby host unit is switched to the active host unit by the host unit system forced switching signal, the illegal data that excludes the illegal target data of the common memory unit that has been illegally written due to the bus access being interrupted by the system switching A redundant information processing system characterized in that the operational host unit has an exclusion function. Each of the active and standby host units configured to be switchable with each other, and a first memory unit and a second memory unit which are connected to the host units via a common bus and execute write access from the active host unit A redundant information processing system having a common memory unit including a memory unit, and a host for avoiding a system failure caused by illegal data held in the common memory unit when the host unit is switched A unit switching normalization method,
A delayed write step in which a write bus access to the second memory unit is executed after a delay time set in advance from execution of the write bus access in the first memory unit when the operational host unit is in operation; ,
A host unit switching step of switching between the active host unit and the standby host unit by a system switching signal output from the active host unit;
After the host unit switching step and after the completion of the write bus access operation to the second memory unit, the second memory unit immediately executes read / write bus access as a working memory, and the first memory unit A memory switching step for executing a write bus access through the preset delay time as a memory;
A host unit switching normalization method characterized by comprising: In the host unit switching normalization method according to claim 11,
In the memory switching step, when the active host unit and the standby host unit are mutually switched by a system switching signal output from the operating system host unit, a write bus access is made on the common bus when the system switching signal is received. A host unit switching normalization method characterized in that if there is no switching, the first memory unit and the second memory unit of the common memory unit are not switched. Each of the active and standby host units configured to be switchable with each other, and a first memory unit and a second memory unit which are connected to the host units via a common bus and execute write access from the active host unit A redundant information processing system having a common memory unit including a memory unit, and a host for avoiding occurrence of a system failure due to illegal data retained in the common memory unit when the host unit is switched A unit switching normalization program,
When the operational host unit is in operation, a write bus access to the second memory unit is performed in the second memory unit after a predetermined delay time from the execution of the write bus access in the first memory unit. Lazy write processing that allows it to be executed,
The standby after switching the setting of the delay time set in the second memory unit of the common memory unit based on the switching information when the active host unit and the standby host unit are switched to each other A delay time switching process for switching to the first memory unit as a spare memory corresponding to the host system unit;
After the host unit switching and after completion of the write bus access operation to the second memory unit, the second memory unit immediately executes read / write bus access as a working memory, and the first memory unit is a spare memory. A memory switching connection process for performing a write bus access through the preset delay time as
Is executed by a computer provided in the bus switching control unit.

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