JP2009199384A - Data processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing apparatus capable of accelerating processing. <P>SOLUTION: The data processing apparatus includes: a computing unit; a register for storing data processed by the computing unit; a register cache capable of accessing a register faster than a cache memory which is the saving destination of the data stored in the register; a memory bus arbiter for storing the data stored in the register cache in the cache memory when the computing unit does not access the cache memory; and a control part for controlling the input/output of the data to/from the register. The register cache has a function for storing data output from the register in accordance with the write request of the data stored in the register and a function for selecting data requested to be restored out of the data stored in the register cache and restoring the selected data to the register in accordance with the data restoration request to the register. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus that processes data input to and output from a register mounted on a microprocessor.

  The processor includes a register for holding data, and it is effective to increase the capacity of the register in order to improve the performance at the time of execution of the microprocessor. However, in a multitasking environment where the processor executes while switching between a plurality of tasks, the time required to record the register state in the cache memory tends to be relatively long. In recent years, there has been an increase in multi-core processors in which a plurality of CPU cores are mounted on one CPU die. However, in such a case, when context switching across cores occurs, transfer is performed via a cache memory or external memory that is slower than the register, which is an impediment to improving efficiency. .

  On the other hand, in Patent Document 1, in order to reduce the access time, the processor includes a register saving stack that is a memory that can be accessed at a higher speed than the memory. As a result, the contents of the register are saved and restored at high speed.

Japanese Patent Laid-Open No. 9-22355

  On the other hand, in a time-sharing system, in order to avoid the monopoly of the use of a processor by a specific task (starvation), the processor allocation time for a task with a low priority in the situation where a task with a high priority exists. (Time Quantum) may be assigned intentionally (aging). However, in the first-in last-out (FILO / stack) context switching using the stack memory described above, aging cannot be performed, and therefore context switching cannot be performed selectively. Therefore, as a result, there is a problem that the processing speed cannot be increased. This is significant in processing delay when context switching occurs across cores in a multi-core processor.

  Therefore, an object of the present invention is to provide a data processing apparatus that can increase the processing speed, which is the problem described above.

Therefore, a data processing apparatus according to one aspect of the present invention is
An arithmetic unit, a register for storing data to be processed by the arithmetic unit, a register cache capable of accessing the register at a higher speed than a cache memory to which data stored in the register is saved, and an arithmetic operation A memory bus arbiter that stores data stored in the register cache when the device is not accessing the cache memory, and a control unit that controls input and output of data to and from the register;
The register cache has a function of storing data output from the register in response to a write request for data stored in the register, and is stored in the register cache in response to a data restoration request to the register. A configuration is adopted in which the data requested to be restored among the data is selected and restored to a register.

In addition, a data processing method according to another aspect of the present invention includes:
An arithmetic unit, a register for storing data to be processed by the arithmetic unit, a register cache capable of accessing the register at a higher speed than a cache memory to which data stored in the register is saved, and an arithmetic operation A data processing apparatus comprising: a memory bus arbiter that stores data stored in the register cache in the cache memory when the device is not accessing the cache memory; and a control unit that controls input / output of data to the register A data processing method in
The data output from the register is stored in the register cache in response to the data write request stored in the register, and the restoration request is stored out of the data stored in the register cache in response to the data restoration request to the register. Select the restored data and restore it to the register,
The structure is taken.

  By configuring as described above, the present invention can restore desired data from a register cache that can be accessed at a higher speed than the cache memory for data output from the register, thereby speeding up the processing. It has an excellent effect of being able to.

  The present invention increases the processing speed of a microprocessor including an arithmetic unit and a register, and is particularly suitable for a multi-core processor including a plurality of cores configured by an arithmetic unit and a register.

And the data processor which is one form of the present invention,
An arithmetic unit, a register for storing data to be processed by the arithmetic unit, a register cache capable of accessing the register at a higher speed than a cache memory to which data stored in the register is saved, and an arithmetic operation A memory bus arbiter that stores data stored in the register cache when the device is not accessing the cache memory, and a control unit that controls input and output of data to and from the register;
The register cache has a function of storing data output from the register in response to a write request for data stored in the register, and is stored in the register cache in response to a data restoration request to the register. Select the data requested to be restored from the data and restore it to the register.
The structure is adopted.

  According to the above invention, first, the data stored in the register processed by the arithmetic unit is saved in the cache memory via the memory bus arbiter, or can be accessed at a higher speed than the cache memory. Is remembered. Note that the data stored in the register cache is stored in the cache memory when the arithmetic unit is not accessing the cache memory by the memory bus arbiter.

  When there is a write request for data stored in the register, the register cache stores the data output from the register. After that, when there is a data restoration request to the register, the register cache searches whether or not the data requested for restoration is stored in the register cache, and if there is such data, selects the data. To restore the register.

  As described above, the arithmetic unit can restore the desired data from the register cache that can be accessed at a higher speed than the cache memory without using the cache memory. Therefore, the processing speed can be increased. In particular, by applying it to a multi-core processor equipped with multiple cores composed of arithmetic units and registers, data movement across the cores is executed via a register cache, enabling further processing speedup. .

  Specifically, the register cache has a cache area for storing data output from the register and a tag area corresponding to each cache area, and is output from the register when a write request is made. Based on the function of storing the data specifying information for specifying the data in the tag area corresponding to the cache area and the data specifying information stored in the tag area at the time of the restoration request A configuration is adopted in which the cache area storing the data requested to be restored is selected and the data in the cache area is restored to the register.

  The register cache stores the specified write destination address information in the tag area as data specifying information at the time of the write request, and stores the write destination address information that matches the specified restore request address information at the time of the restore request. The cache area corresponding to the tag area is selected and the data in the cache area is restored to the register.

  Further, the register cache stores a data storage flag in a tag area corresponding to a cache area that stores data output from the register at the time of a write request, and stores the data storage flag in a tag area in which the data storage flag is set at the time of a restoration request. A configuration is adopted in which a cache area in which the data requested to be restored is stored is selected based on the stored data specifying information. The tag area is, for example, a ring buffer.

  In this way, the data stored in the register cache is managed using the tag for storing the data specifying information for specifying the data, so that any data can be selected and restored unlike the stack memory method. Becomes easy.

  More specifically, the register cache corresponds to an output destination pointer that specifies a tag area corresponding to a cache area in which data output from the register is stored next, and to the data requested to be restored at the time of the restoration request. A search target pointer that designates a tag area to be searched for whether or not the data specifying information is stored, and scans the search target pointer over each tag area at the time of restoration request, It is searched whether data specifying information corresponding to the data requested to be restored is stored in the area.

  The register cache scans the search target pointer from the next tag area specified by the output destination pointer at the time of the restoration request, and data specifying information corresponding to the data requested to be restored is stored in each tag area. Search whether or not. Alternatively, the register cache has a data storage pointer that designates the tag area in which the data specifying information is stored earliest in the tag area, and when the restoration request is made, the search target pointer is extracted from the tag area designated by the data storage pointer. Scanning is performed to search whether or not the data specifying information corresponding to the data requested to be restored is stored in each tag area.

  At this time, the register cache scans the search target pointer until it passes the tag area specified by the output destination pointer or the data storage pointer, and data specifying information corresponding to the data requested to be restored is stored in each tag area. The configuration of searching for whether or not there is is adopted. By doing so, data search can be realized at higher speed.

  Hereinafter, specific configurations and operations of the present invention will be described in the embodiments. In the embodiment, the case where the data processing apparatus according to the present invention is a multi-core processor having two cores will be described as an example. However, the number of cores is not limited to two and may be more than that. Alternatively, it may be applied to a processor having only one core. In the embodiment, the context is illustrated as an example of data input to and output from the register. However, the present invention is not limited to this, and any data may be used.

<Embodiment 1>
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing the configuration of the data processing apparatus. 2 to 4 are schematic diagrams showing the configuration of the register cache bank. 5 to 8 are flowcharts showing the operation of the data processing apparatus. 9 to 14 are diagrams showing a specific configuration and operation of the register cache bank.

[Constitution]
As shown in FIG. 1, the data processing apparatus according to the present embodiment is a multi-core processor including a core A and a core B. Specifically, the data processing apparatus includes a transmitter 100, a control circuit 101, a CPU core A having an arithmetic unit 102 and a register 103, a CPU core B having an arithmetic unit 104 and a register 105, a register cache bank 106, And a memory bus arbiter 107. The transmitter 100 may be provided outside the apparatus. Further, a cache memory 108 is connected to the outside of the apparatus via a memory bus arbiter 107.

  The signal from the transmitter 101 is output from the output terminal 1 provided in the transmitter 101, and the registers 103 and 105 incorporated in the input terminal 2 of the control circuit 101 and the CPU cores A and B, respectively. Are respectively supplied to the input terminals 3 and 3 ′, the input terminal 8 of the register cache bank 106, and the input terminal 14 of the memory bus arbiter 107. As a result, each circuit operates in synchronization with the clock signal from the transmitter 100.

  The registers 103 and 105 store data used when the arithmetic units 102 and 104 of the CPU cores A and B equipped with the registers perform calculations, respectively.

  The control circuit 101 (control unit) controls input / output of data to / from the registers 103 and 104. Specifically, a write destination control signal for controlling whether the data in the registers 103 and 105 is written to the register cache bank 106 or the cache memory 108, and a write destination address signal for designating the write destination address are output terminals. 5 is output. Then, the write destination control signal and the write destination address signal output from the output terminal 5 of the control circuit 101 are input to the input terminal 13 of the memory bus arbiter 107 and the input terminal 7 of the register cache bank 106, respectively. The

  Data stored in the registers 103 and 105 is output from the output terminals 6 and 6 ′ and input to the input terminal 12 of the memory bus arbiter 107 and the input terminal 10 of the register cache bank 106. .

  When the register cache bank 106 receives a signal to the input terminal 7 indicating that the write destination is the register cache bank by a write destination control signal from the control circuit 101, the timing at which the signal is input. The data output from the register input to the input terminal 10 is stored in the register cache bank 106. The registers 103 and 105 and the register cache bank 106 are connected by a sufficiently high-speed bus, that is, a bus that is faster than accessing the cache memory 108.

  Further, the register cache bank 106 manages the data input by its own algorithm, and when the data from the registers 103 and 105 cannot be recorded, the non-output data that has not been output to the cache memory 108 is stored in the cache memory. It waits until it outputs to 108. Note that the above-described operation of the register cache bank 106 may be realized by a circuit incorporated in advance, or may be realized by incorporating a program.

  In addition, the memory bus arbiter 107 stores the register cache bank 106 when the CPU cores A and B are not accessing the cache memory 108 as soon as the bandwidth between the CPU cores A and B and the cache memory 108 is sufficient. The stored non-output data is output to the cache memory 108.

  Here, the CPU cores A and B may be implemented with an instruction for outputting the contents of all the registers to the cache memory 108 in order to save and restore the current operation status. In response to processing by this instruction, the register cache bank 106 temporarily records the contents of all the registers 103 and 105. The register cache bank 106 outputs the recorded data from all the registers 103 and 105 to the cache memory 108 while the control circuit 101 or the registers 103 and 105 are not outputting data to the memory bus arbiter 107. .

  Further, as described above, when there is an input / output from the control circuit 101 or the registers 103 and 105 to the cache memory 108, the memory bus arbiter 107 preferentially executes the operation. On the other hand, in other cases, the non-output data stored in the register cache bank 106 is operated to be output to the cache memory 108.

  In this way, the data output from the registers 103 and 105 stored in the register cache bank 106 is output to the cache memory 108 independently of the operations of the control circuit 101 and the registers 103 and 105.

  Next, the configuration of the register cache bank 106 will be described with reference to FIGS. First, as shown in FIG. 2, the register cache bank 106 is a “register cache” (0 to 7) (cache area) that stores data output from the register, and is prepared for each register cache. It has “tags” (0 to 7) (tag areas) that hold cache validity / invalidity and cache destination addresses. In addition, “counter 1” (output destination pointer) that points (designates) the tag corresponding to the register cache to which data output from the register is next written, the latest tag that has been written to the cache memory 108 or the main memory "Counter 2" pointing to the tag to be scanned to search the register cache storing the data to be restored from the register cache bank 106 to the registers 103 and 105, "Counter 3" (Search target pointer). Here, the tag takes the form of a ring buffer. However, the tag is not necessarily limited to the ring buffer form. For example, the tag and the register cache may be associated with each other, and the tag and the register cache are necessarily included. Is not limited.

  The register cache bank 106 having such a configuration is configured to operate as follows. Here, as described above, in synchronization with the clock pulse signal output from the output terminal 1 of the transmitter 100, the output terminal 5 of the control circuit 101 controls the output source of data to be written to the cache memory 108. Is output. The signal from the output terminal 5 is input to the input terminal 7 of the register cache bank 106 and the input terminal 13 of the memory bus arbiter 107, so that the output source of data written to the cache memory 108 is the register 103, 105. The register cache bank 106 is determined. That is, a write request for designating whether the write destination of the data output from the registers 103 and 105 is the register cache bank 106 or the cache memory 108 is output. Further, the write destination address information of data output from the output terminal 5 of the control circuit 101 is input to the input terminal 7 of the register cache bank 106 and the input terminal 13 of the memory bus arbiter 107, and the contents thereof are stored in the cache memory 108. When data is written out, it is used as write destination address information (data specifying information).

  As described above, when a write request for designating the register cache bank 106 as a write destination is issued from the control circuit 101, the register cache bank 106 stores the data from the registers 103 and 105 in a predetermined register cache. The tag corresponding to the register cache stores “valid” as a flag indicating that “write destination address” and data are stored. Specifically, the “write destination address” and “valid” are stored in the tag designated by “counter 1”, and the data from the registers 103 and 105 is stored in the register cache corresponding to the tag. Remember. Then, "Counter 1" is advanced to the next tag.

  In addition, when the data stored in the register cache is full, the register cache bank 106 writes the data stored in the register cache to the cache memory 108 by the memory bus arbiter 107 as described above. Then, “counter 2” is set to designate a tag corresponding to the register cache for which writing has been completed.

  Further, when there is a data restoration request from the control circuit 101 to the registers 103 and 105 from the control circuit 101, the register cache bank 106 selects the data related to the restoration request from the register cache 106 and loads it into the registers 103 and 105. And have a function to restore. Specifically, when receiving a restoration request address that is an address for specifying data to be restored, “counter 3” is set to designate a tag immediately after the tag pointed to by “counter 1”, and the tag is set from this tag. The tags are scanned in order of increasing numbers, and the tags corresponding to the register cache storing the data to be restored are searched. Note that after the tag number 7, scanning returns to the tag number 0. Then, for each tag, it is checked whether or not the flag in the tag is “valid”, and the register corresponding to the tag in which the write destination address that matches the restoration request address exists in the tag that is “valid” Select data stored in the cache. The selected data is restored to the registers 103 and 105. The process of scanning and searching for tags with “counter 3” is performed by scanning the tags in order until, for example, the target data is selected or the tag indicating “counter 1” is overtaken. Is called. However, the scanning described above is not necessarily limited to starting from the next tag of “Counter 1” as described above, and may be performed from any tag, and the search may be performed in any order. Good.

[Operation]
Next, the operation of the above-described data processing apparatus will be described with reference to FIGS. 2 to 4 are diagrams for explaining the operation of the register cache bank 106, and FIGS. 5 to 8 are flowcharts showing the operation of each component.

  First, FIG. 2 illustrates the initial state of the register cache bank 106. As described above, when there is a write request from the control circuit 101, the register cache bank 106 indicates that the tag indicated by the counter 1 is “invalid” (No in step S11 in FIG. 6), and the register The data output from 103 and 105 is stored (step S12 in FIG. 6). That is, in the example of FIG. 2, the data is stored in the register cache 0 corresponding to the tag 0 pointed to by the counter 1, and the flag of the tag is updated to “valid” (step S13 in FIG. 6). Then, as shown in FIG. 3, the counter 1 is advanced by one (step S14 in FIG. 6). On the other hand, if the flag of the tag pointed to by the counter 1 is “valid” (Yes in step S11 in FIG. 6), the register cache may be full. The data is output to the memory 108 (step S15 in FIG. 6).

  As described above, the operation when data is output from the register cache bank 106 to the cache memory 108 is, for example, as shown in FIG. That is, when the data is full, it is checked whether the flag of the tag pointed to by the counter 2 is “valid”, and the data in the register cache corresponding to the “valid” tag (step S21 in FIG. 7). Yes), the data is output to the cache memory 108 (step S22 in FIG. 7). Then, the flag of the tag corresponding to this register cache is updated to “invalid” (step S23 in FIG. 7), and as shown in FIG. 4, the counter 2 is incremented by 1 (step S24 in FIG. 7).

  Data output from the register cache bank 106 to the cache memory 108 is performed by the memory bus arbiter 107. The operation of the memory bus arbiter 107 is shown in FIG. First, when there is data to be written from the registers 103 and 105 to the cache memory 108 by the command from the control circuit 101 described above (Yes in step S1 in FIG. 5), the data from the registers 103 and 105 is transferred to the cache memory 108. (Step S2 in FIG. 5). On the other hand, when there is no data to be written from the registers 103 and 105 to the cache memory 108 (No in step S1 in FIG. 5), if there is data to be output from the register cache bank 106 to the cache memory 108 (step S3 in FIG. 5). Yes), the data is output from the register cache bank 106 to the cache memory 108 (step S4 in FIG. 5).

  Next, a case where there is a data restoration request from the control circuit 101 or the CPU cores A and B will be described. First, the register cache bank 106 copies the data of the tag ahead of the counter 1 to the counter 3 (step S31 in FIG. 8). Then, it is checked whether or not the flag of the tag pointed to by the counter 3 is “valid” (step S32 in FIG. 8), and the tag that is “valid” (Yes in step S32 in FIG. 8), It is checked whether or not the stored write destination address matches the restoration request address for specifying data related to the restoration request (step S33 in FIG. 8). If they do not match (No in step S33 in FIG. 8), the counter 3 is incremented by one (step S34 in FIG. 8), and the contents of the next tag are examined as described above. If there is a tag whose address matches (Yes in step S33 in FIG. 8), the data stored in the register cache corresponding to the tag is output to the registers 103 and 105 to be restored (step in FIG. 8). S36). On the other hand, if the data relating to the restoration request does not exist in the register cache bank 106 (No in step S32 in FIG. 8), the data relating to the restoration request is read from the cache memory 108 or the main memory and restored to the registers 103 and 105. (Step S35 in FIG. 8).

[Example of operation]
Next, the operation when the contexts executed by the CPU cores A and B are switched will be described with reference to FIGS.

  First, an initial state of the register cache bank 106 is shown in FIG. In this state, the register cache is empty, and all the tag flags are “invalid”.

  Now, assume that the context being executed by CPU core A or CPU core B is W, and context switching has occurred. Specifically, when the context changes from W to X, the data of the registers 103 and 105 of the context X is transferred from the output terminal 6 or 6 ′ to the input terminal 10 of the register cache bank 106 and the input terminal 12 of the memory bus arbiter 107. Entered. Here, from the output terminal 5 of the control circuit 101, the fact that the data output destination of the registers 103 and 105 is the register cache bank 106 and the write destination address are determined by the input terminal 7 of the register cache bank 106 and the memory bus arbiter 107. It is assumed that the signal is output to the input terminal 13. Then, the data in the registers 103 and 105 is copied to the register cache corresponding to the tag indicated by the counter 1 of the register cache bank 106, the write destination address is recorded in the tag, and the flag indicating that the tag is “valid” is set. As a result, as shown in FIG. 10, the tag 0 stores the write destination address of the data output from the registers 103 and 105, and a flag indicating that the tag 0 is “valid”. Proceed to tag 1 where 1 is the next tag.

  Thereafter, when the context of the CPU core A or CPU core B is further switched from X to Y, the same processing as described above is executed, and the “valid” flag and the write destination address are stored in the tag 1 as shown in FIG. Is done. Then, the counter 1 proceeds to tag 2 which is the next tag. Further, when the context of CPU core A or CPU core B is switched from Y to Z, the same processing as described above is executed, and as shown in FIG. 12, the flag “valid” and the write destination address are stored in tag 2. The Then, the counter 1 proceeds to tag 3 which is the next tag. In this way, each time the context is switched and data is output from the registers 103 and 105, the above operation is repeated.

  Thereafter, when the context of CPU core A or CPU core B is switched to context Y and there is a data restoration request, first, the data of the tag next to counter 1 is copied to counter 3 as shown in FIG. Thereafter, the validity / invalidity of the tag indicated by the counter 3 is checked. If it is “valid”, it is checked whether the write destination address stored in the tag matches the restoration request address of the context Y requested to be restored. . At this time, if the write destination address in the tag does not match the restore request address of the context Y requested to be restored, the counter 3 is incremented by one as shown in FIG. Perform the check. When a tag whose tag is valid and whose address matches is found, register cache data corresponding to the tag is selected and loaded from the output terminal 9 to the input terminal 4 or 4 'of the registers 103 and 105. The scanning of the tag is performed until the tag and the address match or the counter 3 passes the counter 1. If a tag with a matching address is not found, it is assumed that the context related to the restoration request is not cached on the register cache bank 106, and data is loaded from the cache memory 108 or the main memory to the register.

  As described above, according to the present invention, the arithmetic units 102 and 104 allow the data output from the registers 103 and 105 to be accessed at a higher speed than the cache memory 108 without using the cache memory 108. Desired data can be restored. Therefore, the processing speed can be increased. In particular, by applying it to a multi-core processor equipped with a plurality of CPU cores as described above, data movement between the cores is executed via the register cache bank 106 that can be accessed at high speed. Can be realized. Furthermore, by managing data stored in the register cache using a tag in the register cache bank 106, it becomes easy to select and restore arbitrary data unlike the stack memory system.

  Here, by using a high-speed memory, a multi-port RAM, an asynchronous circuit, or the like for the above-described register cache bank 106, it is possible to further increase the speed and power. In addition, even higher speed and lower power can be achieved by installing the transmitter 100 outside or by installing a plurality of transmitters.

  In the above description, the case where the next tag of “counter 1” is designated in “counter 3” and scanning is started from this tag is exemplified, but the present invention is not limited to this. For example, among the tags that are currently “valid”, “counter 4” (data storage pointer) that stores the earliest “valid” tag is mounted in the register cache bank 106, and the “counter 4” Tag scanning may be started by hitting “Counter 3”. For example, the “counter 4” can store the tag that becomes “valid” earliest among the currently stored ones by designating the next tag of the counter 2. In this case, the search is executed until “counter 3” exceeds “counter 4”.

  The present invention can be used for various processors including a multi-core processor, and has industrial applicability.

It is a block diagram which shows the structure of a data processor. It is the schematic which shows the structure of a register cache bank. It is the schematic which shows the structure of a register cache bank. It is the schematic which shows the structure of a register cache bank. It is a flowchart which shows operation | movement of a data processor. It is a flowchart which shows operation | movement of a data processor. It is a flowchart which shows operation | movement of a data processor. It is a flowchart which shows operation | movement of a data processor. It is explanatory drawing explaining the specific operation | movement of a register cache bank. It is explanatory drawing explaining the specific operation | movement of a register cache bank. It is explanatory drawing explaining the specific operation | movement of a register cache bank. It is explanatory drawing explaining the specific operation | movement of a register cache bank. It is explanatory drawing explaining the specific operation | movement of a register cache bank. It is explanatory drawing explaining the specific operation | movement of a register cache bank.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Transmitter 101 Control circuit 102,104 Operation unit 103,105 Register 106 Register cache bank 107 Memory bus arbiter 108 Cache memory A, B CPU core

Claims (12)

An arithmetic unit, a register for storing data to be processed by the arithmetic unit, a register cache capable of accessing the register at a higher speed than a cache memory serving as a save destination of the data stored in the register, A memory bus arbiter that stores data stored in the register cache in the cache memory when the arithmetic unit is not accessing the cache memory; and a control unit that controls input and output of data to and from the register; With
The register cache has a function of storing data output from the register in response to a write request for data stored in the register, and is stored in the register cache in response to a data restoration request to the register. Having the function of selecting the data requested to be restored from among the received data and restoring it to the register,
A data processing apparatus. The register cache has a cache area for storing data output from the register, and a tag area corresponding to each cache area,
A function of storing data output from the register in the cache area at the time of the write request, and storing data specifying information for specifying the data in the tag area corresponding to the cache area;
A function of selecting the cache area in which the data requested to be restored is stored based on the data specifying information stored in the tag area at the time of the restoration request, and restoring the data in the cache area to the register Having
The data processing apparatus according to claim 1. The register cache stores the specified write destination address information in the tag area as the data specifying information at the time of the write request, and the write destination address information that matches the specified restore request address information at the time of the restore request Selecting the cache area corresponding to the tag area in which is stored, and restoring the data in the cache area to the register,
The data processing apparatus according to claim 2. The register cache stores a data storage flag in the tag area corresponding to the cache area storing the data output from the register at the time of the write request, and the data storage flag is set at the time of the restoration request. Selecting the cache area in which the data requested to be restored is stored based on the data specifying information stored in the tag area.
The data processing apparatus according to claim 2 or 3, wherein The tag area is a ring buffer.
5. A data processing apparatus according to claim 2, 3 or 4. The register cache includes an output destination pointer that specifies the tag area corresponding to the cache area in which data output from the register is stored next, and the data specification corresponding to the data requested to be restored at the time of the restoration request A search target pointer for designating the tag area to be searched for whether or not information is stored, and
At the time of the restoration request, the search target pointer is scanned on each tag area to search whether or not the data specifying information corresponding to the data requested to be restored is stored in each tag area.
6. A data processing apparatus according to claim 2, 3, 4 or 5. The register cache scans the search target pointer from the next tag area specified by the output destination pointer at the time of the restoration request, and the data specifying information corresponding to the data requested to be restored in each tag area Search whether or not is stored,
The data processing apparatus according to claim 6. The register cache has a data storage pointer that specifies the tag area in which the data specifying information is stored earliest in the tag area, and the tag area specified by the data storage pointer at the time of the restoration request The search target pointer is scanned from to search whether or not the data specifying information corresponding to the data requested to be restored is stored in each tag area.
The data processing apparatus according to claim 6. The register cache scans the search target pointer until it passes the tag area specified by the output destination pointer or the data storage pointer, and the data specifying information corresponding to the data requested to be restored in each tag area Search whether or not is stored,
9. The data processing apparatus according to claim 7, wherein the data processing apparatus is a data processing apparatus. Provided with a plurality of cores constituted by the arithmetic unit and the register,
10. A data processing apparatus according to claim 1, 2, 3, 4, 5, 6, 7, 8 or 9. An arithmetic unit, a register for storing data to be processed by the arithmetic unit, a register cache capable of accessing the register at a higher speed than a cache memory serving as a save destination of the data stored in the register, A memory bus arbiter that stores data stored in the register cache in the cache memory when the arithmetic unit is not accessing the cache memory; and a control unit that controls input and output of data to and from the register; A data processing method in a data processing apparatus comprising:
The data output from the register is stored in the register cache in response to the data write request stored in the register, and the data stored in the register cache in response to the data restoration request to the register Select the data requested to be restored and restore it to the register;
A data processing method. At the time of the write request, the data output from the register is stored in a cache area provided in the register cache, and the data is stored in the tag area provided in the register cache corresponding to the cache area. Stores data identification information to be identified,
At the time of the restoration request, the cache area in which the data requested to be restored is stored based on the data specifying information stored in the tag area is selected, and the data in the cache area is restored to the register.
The data processing method according to claim 11.

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