JP2009199338A - Design support device and method for power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the design support device of a power supply circuit for automatically designing a power supply circuit on a printed circuit board in order to make it stable against a noise. <P>SOLUTION: The information of a printed circuit board is input, and the power supply noise characteristics of a power supply circuit are derived, and whether or not a predetermined criterion is satisfied by the power source noise characteristics is decided, and when the criterion is not satisfied, a capacity is added to the inside of a semiconductor integrated circuit so that it is possible to determine whether or not the power supply circuit of the printed circuit board is stably designed against a noise. In searching power source noise characteristics, a method to perform circuit analysis is selected by using an equivalent circuit model so that it is possible to precisely and quantitatively derive the power source noise characteristics. Also, as for the capacity to be added, it is possible to easily create the equivalent circuit model of the semiconductor integrated circuit to the inside of which the capacity is added by using the equivalent circuit model of the capacity cell to be actually added. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a CAD system, and in particular, in a passive component such as a semiconductor integrated circuit (hereinafter also referred to as “LSI”) and a capacitor mounted on a printed wiring board (hereinafter also referred to as “PCB”). In consideration of noise characteristics such as voltage drop in the power supply circuit, a device for determining whether the power supply circuit of the PCB on which the LSI is mounted is unstable with respect to noise, and an LSI to which an optimal internal capacitance is added The present invention relates to a power supply circuit design support apparatus and a design support method that make it possible to design a PCB on which it is mounted in a short time.

  Conventionally, in order to normally operate an LSI mounted on a board, an attempt has been made to reduce the power noise generated between the power source and the GND by mounting an on-chip capacitor between the power source and the GND in the LSI.

  For example, as a conventional system, a semiconductor integrated circuit design system having an on-chip capacitor mounting method as disclosed in Patent Document 1 has been proposed. According to this document, a semiconductor integrated circuit design apparatus that can suppress the amount of noise generation within a predetermined range by adding a bypass capacitor having a necessary capacity near a noise source inside a more effective circuit block, and And a semiconductor integrated circuit manufacturing system using this method procedure for circuit design.

  A semiconductor integrated circuit design apparatus for automatically generating a pattern of a semiconductor integrated circuit includes input means for performing input processing of gate level logic circuit information, standard cell library information, and package information of a circuit block constituting the semiconductor integrated circuit, and the input In order to suppress the noise generation amount within a predetermined range based on the estimation result by the noise estimation unit and the noise estimation unit that estimates the noise generation amount generated in the circuit block using the information input by the unit Capacitance constraint designating means for designating capacity constraints, which are capacities of bypass capacitors for reducing power supply noise and substrate noise, which are required to be mounted on the circuit block, and a capacity of the bypass capacitor mounted on the circuit block. Comparison means for comparing the mounted capacity with the capacity constraint, and the comparison means In the comparison, when the mounting capacity is larger than the capacity constraint, the processing end means for terminating the process of automatically generating the pattern of the semiconductor integrated circuit and the mounting capacity is equal to or less than the capacity constraint in the comparison by the comparison means. In this case, a logic gate selection unit that selects a logic gate having a predetermined noise generation amount or more in the circuit block, and a bypass capacitor addition unit that adds a bypass capacitor to the logic gate selected by the logic gate selection unit. .

  According to this semiconductor integrated circuit design device, since the noise is estimated in advance to limit the capacity of the added bypass capacitor, it is not necessary to repeat the noise analysis process, and the bypass capacitor is placed in the circuit block in a short time. As a result, the amount of noise generated in the semiconductor integrated circuit can be reliably suppressed within a predetermined range in a short time.

  Further, the logic gate selection means of the semiconductor integrated circuit design apparatus described above is influenced by noise generation of each logic gate in the circuit block using the input information and the floor plan information of the semiconductor integrated circuit. Calculating a noise influence degree that is a degree to which the noise influence is generated, selecting a logic gate having the maximum noise influence degree, and adding the bypass capacitor near a noise source that causes a large noise in the circuit block. It is described that noise can be reduced more efficiently.

  FIG. 30 is a flowchart showing the processing procedure of the low noise design method disclosed in Patent Document 1.

  Patent Document 2 discloses a semiconductor device model creation method used when analyzing the behavior of power supply noise of a semiconductor device, and FIG. 31 is a configuration diagram of the semiconductor device model creation device.

Patent Document 3 describes a power supply model of a semiconductor integrated circuit and a design method thereof, and FIG. 32 is a circuit diagram of the power supply model described in Patent Document 3.
JP 2006-228252 A (Claims 1, 2, paragraphs 0024, 00255) JP 2004-234618 A JP 2001-222573 A

  However, the technique of Patent Document 1 uses a method of changing a circuit block when the capacity constraint is not satisfied. When the circuit block is changed, the LSI may not operate normally due to other conditions. In addition, since the circuit blocks to be used are determined to some extent according to the LSI design rules, the library must be changed. Furthermore, even if such a method is used, the absolute amount of capacity that can be added is determined on the floor plan, and depending on the magnitude of noise, this method may be difficult to handle.

  In addition, as a noise estimation means for estimating the noise generation amount, an LSI equivalent circuit model is created from the input data, and the noise generation amount is obtained by analyzing the model. The model configuration is up to the LSI package. Therefore, a model related to the PCB on which the LSI is mounted is not included. Noise generated inside the LSI may fluctuate greatly due to the effects of PCB substrate resonance and the like, and if there is no PCB influence, the amount of noise generation cannot be estimated correctly. LSIs are not limited to what type of PCB they are actually mounted on, but in general, it is assumed that PCBs have an effect, and noise countermeasures have been taken into account that effect. It is necessary for LSI vendors to provide LSIs from the initial stage.

  The present invention has been made to solve the above-described problems. The object of the present invention is to provide power supply noise of the PCB in the LSI mounted on the PCB and the power supply circuit of the PCB in the PCB design stage. Is quantitatively evaluated to determine whether the power supply circuit of the PCB on which the LSI is mounted is stable against noise, and based on the determination result, the structure of the LSI to which the capacitance is added and the PCB on which the LSI is mounted Provided are a power supply circuit design support apparatus and a design support method for obtaining a power supply circuit in a short time and with high accuracy.

  In order to achieve the above-described object, the present invention basically employs a technical configuration as described below.

That is, the first aspect of the power supply circuit design support apparatus according to the present invention is:
A power supply circuit design support apparatus for supporting the design of a power supply circuit so that the power supply circuit on a printed wiring board including at least a semiconductor integrated circuit and passive components operates stably against noise,
Input means for inputting predetermined input information of a printed wiring board, a semiconductor integrated circuit, and a passive component constituting the power supply circuit;
Power supply noise characteristic deriving means for deriving a power supply noise characteristic that is a noise characteristic of the power supply circuit based on the input information input from the input means;
A criterion database for storing acceptable conditions of power supply noise characteristics in the power supply circuit and storing acceptable conditions of internal capacitance values that can be added to the semiconductor integrated circuit;
The power supply noise characteristic derived by the power supply noise characteristic deriving means is compared with the permissible conditions of the power supply noise characteristic obtained from the determination reference database, and the power supply noise characteristic of the power supply circuit satisfies a predetermined condition Power noise judgment means for judging whether or not
In the power supply noise determination means, if the condition is not satisfied, a change is made to add a capacity inside the semiconductor integrated circuit, and an internal capacity addition means for inputting the changed information to the power supply noise characteristic deriving means;
The value of the internal capacitance added by the internal capacitance adding means is compared with the allowable condition of the internal capacitance value that can be added to the semiconductor integrated circuit obtained from the judgment reference database, and the necessary value for the semiconductor integrated circuit is compared. Mounting capacity condition judgment means for judging whether or not an internal capacity value can be added;
It is characterized by comprising
The second aspect is
The power supply noise characteristic deriving means includes:
Equivalent circuit model generation means for generating an equivalent circuit model of the power supply circuit from the input information;
Analyzing the equivalent circuit model and comprising a calculation means for deriving a power supply noise characteristic,
The third aspect is:
The equivalent circuit model generation means includes:
Board equivalent circuit model generation means for generating an equivalent circuit model related to the printed wiring board based on at least predetermined input information related to the printed wiring board;
LSI equivalent circuit model generation means for generating an equivalent circuit model of the semiconductor integrated circuit based on predetermined input information regarding the semiconductor integrated circuit;
It is characterized by consisting of,
The fourth aspect is
The internal capacitance adding means is configured to add an equivalent circuit model of a capacity cell actually added inside the semiconductor integrated circuit to the equivalent circuit model of the semiconductor integrated circuit. ,
The fifth aspect is:
The board equivalent circuit model generating means is configured to couple the equivalent circuit model of the passive component to the equivalent circuit model of the printed wiring board,
The sixth aspect is
The board equivalent circuit model generating means comprises a field solver that creates an equivalent circuit model based on the physical structure of the power supply wiring and the electrical characteristic information,
The seventh aspect is
A chip size changing unit for changing the chip size of the semiconductor integrated circuit and inputting the changed information to the power supply noise characteristic deriving unit when the mounting capacity condition determining unit determines that the condition is not satisfied; It is characterized by comprising.

  In the present invention, as input information regarding LSI, LSI design information including all circuit connection information and internal layout information of LSI, allowable value of power supply noise characteristic capable of normal operation of LSI, chip size information, An LSI database including data of added capacity cells is prepared. For the PCB and components to be mounted, CAD data that is layout information and a component database that is information of an equivalent circuit of components are prepared. From these input information, a power supply noise characteristic, which is a characteristic of noise generated from the power supply system of the LSI, is derived.

  Next, the power supply noise condition that is a characteristic of the power supply noise tolerance of the LSI of the power supply circuit in the PCB included in the database is read, and the derived power supply noise characteristic and the power supply noise condition are compared. Judge whether it is stable. With this processing, it is possible to automatically determine whether the power supply circuit of the PCB on which the LSI is mounted is designed to be stable against noise.

  Further, quantitatively deriving the power supply noise characteristic of the power supply can be realized by using a means of analyzing an equivalent circuit model that accurately estimates the characteristics of the power supply system of the PCB on which the LSI is mounted. In this case, as an LSI equivalent circuit model generation method, if a method in which a model capable of accurately reproducing the current flowing through the power supply terminal of the LSI is generated from the LSI design information is used, the model is automatically generated from the LSI design information. Can be generated.

  Further, when it is determined that the PCB power supply circuit is not stable against noise, a method is used in which the circuit structure is changed by adding an internal capacitance to the LSI so that the structure is stable against noise. Specifically, the model of the capacity cell prepared in the LSI is added to change the structure of the LSI. The value of the internal capacitance to be added can be determined by an equivalent equation, or an LSI equivalent circuit model to which a capacity cell is actually added is created, and the power supply noise of the PCB using that model is analyzed and determined. May be. The processing of the LSI circuit structure by adding capacity cells is not so complicated if there is LSI layout data. Whether the power supply noise characteristic is derived again from the circuit model in the changed structure and whether the power supply noise condition is satisfied Is determined, the value of the internal capacity to be added is determined. If the guideline for the change is also prepared in the library, it is possible to change the capacity cell automatically until the capacity value becomes a required value. By repeating this operation until a structure that satisfies the power supply noise condition is created, it is possible to automatically design power supply circuit structures for LSIs and PCBs that are stable against noise.

  Next, the mounting capacity condition that is the limit value of the capacity that can be added in the LSI chip included in the database is read out, and it is determined whether or not the LSI chip can be mounted with the additional internal capacity obtained by the method described above. I do. This mounting capacity condition varies depending on the LSI chip, and is a value determined by the empty space in the chip and the size of the capacity cell. By this processing, it is possible to automatically determine whether the power supply circuit of the PCB is stable against noise by adding the internal capacitance of the LSI.

  In addition, if the mounting capacity condition of the LSI chip is not satisfied in the above operation, the power supply circuit of the PCB becomes stable against noise by changing the chip size of the LSI and changing the mounting capacity condition. You can also select the method of designing. Basically, it has the same function as an LSI, and a larger chip size is prepared. By changing the mounting capacity condition to be larger, the PCB power supply circuit is stable against noise. Can be designed.

  This is because a plurality of different chip sizes are prepared in the LSI database, and if the first prepared size does not satisfy the mounting capacity condition, a larger size is selected and prepared first. If a processing guideline such as replacement is prepared in the library, an LSI with added capacity cells is automatically created on the PCB so as to be stable against noise. .

  Furthermore, by realizing the program and system to which the above method is applied, it is automatically determined from the input information and the database, whether or not the power supply circuit of the PCB is designed stably, and is internally operated so as to stably operate on the PCB. An LSI structure with added capacitance can be created. Further, by using CAD data as input information of the board layout, it is possible to easily design an LSI by linking with data of a PCB power supply circuit.

  Since the present invention is configured as described above, the following effects can be obtained.

  By determining the power supply noise condition and the mounting capacity condition, it is possible to determine whether the PCB power supply circuit is designed to be stable against noise, and to design the PCB power supply circuit on which an LSI that is stable against noise is mounted. It will be easy.

  LSI data including LSI design information and operating state, added capacity cell data, layout, size, etc., input data, component database including structural information such as PCB wiring layout information, equivalent circuit of components, etc. Whether the PCB power supply circuit is stable even for those who do not have deep knowledge of LSI and PCB power supply circuit design by preparing a database of criteria including power supply noise conditions and mounting capacity conditions It becomes possible to determine whether or not.

  Also, when there is a PCB power supply circuit that does not meet the criteria, an operation for adding internal capacitance to the LSI so as to satisfy the criteria is prepared by preparing a change guideline on how to change the structure. Thus, it becomes possible to obtain the structure of the power circuit of the LSI and the PCB designed to be stable against noise automatically.

  Furthermore, by performing analysis using an equivalent circuit model that reproduces the characteristics of LSI and PCB, it is possible to easily determine in real time whether the power supply circuit is designed stably against noise. Become. In addition, the power supply noise characteristic can be derived as an absolute value, and quantitative evaluation and countermeasures can be performed.

  It is also possible for the LSI vendor to use the system of the present invention in order to provide a more stable LSI against noise. On the vendor side, using the PCB data that the user thinks to use or standard PCB data, the system of the present invention is used to design an LSI with additional capacity cells that operate stably against noise. This makes it possible to provide an LSI that performs stable operation for the user.

  Furthermore, an LSI vendor may prepare a plurality of types of PCB data for mounting the provided LSI, and propose a PCB structure suitable for mounting the provided LSI by the system of the present invention for each PCB data. It becomes possible.

Next, an embodiment of the present invention will be described.
(First embodiment)
First, a first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows the system configuration of the first embodiment of the present invention. The design information of the circuit constituting the PCB on which the LSI is mounted and the input information including the database are input from the input device (1) to the power supply noise deriving means (2). Next, in the power supply noise deriving means (2), characteristics of noise generated from the power supply on the PCB are derived. Next, the power supply noise condition determination means (3) automatically determines whether or not the power supply circuit of the PCB on which the LSI is mounted is designed stably. Specifically, the power supply noise characteristic derived by the power supply noise characteristic deriving means (2) is compared with the power supply noise condition provided in the determination reference database (4), which is a feature of the present invention. Determines whether the power supply noise condition is satisfied.

  The power supply noise characteristics include voltage fluctuation between the power supply and GND, current flowing through the power supply, electromagnetic field emission generated from the power supply, etc., and the power supply noise deriving means (2) has one of these characteristics. Just ask. Further, the power supply noise condition provided in the determination criterion database (4) may be a condition indicating a limit value in the obtained characteristic.

  If characteristics of a plurality of power supply noise conditions are provided in the determination criterion database (4) in advance, the characteristics obtained by the power supply noise deriving means (2) may be compared with appropriate power supply noise conditions. Here, when it is determined by the power supply noise determination means (3) that the power supply circuit of the PCB does not satisfy the power supply noise condition, the internal capacity addition means (5) requires the internal capacity required to satisfy the power supply noise condition. Capacitance is added to the LSI. As the internal capacitance added here, a value that satisfies the power supply noise condition may be added as it is by an equivalent equation or the like, or a certain constant value may be selected and added according to the guidelines. Then, in the power supply noise deriving means (2), the power supply noise characteristic is derived in the power supply circuit of the PCB on which the LSI with the added internal capacitance is mounted. The power supply noise condition determination means (3) again repeats the operation of automatically determining whether the power supply circuit of the PCB on which the LSI is mounted is stably designed.

  When the power supply noise determination means (3) determines that the power supply circuit of the PCB satisfies the power supply noise condition, the added internal capacity is actually added to the LSI in the mounting capacity condition determination means (6). It is automatically determined whether it can be installed.

  Specifically, the additional internal capacitance value when the power supply noise condition determination means (3) determines that the power supply noise condition is satisfied, and the LSI chip provided in the determination reference database (4) that is a feature of the present invention. It compares with the mounting capacity condition which is the limit value of the capacity value that can be mounted within, and determines whether or not the additional internal capacity value satisfies the mounting capacity condition. Note that when the power supply noise condition is satisfied under the first input condition, the additional internal capacitance value becomes zero. Next, the result in the mounted capacity condition determining means (6) is output to the output device (7), and the processing in the system is completed.

  FIG. 6 is a flowchart showing the processing of the first embodiment of the present invention. This process starts from the circuit design information input process (S1). The information input here is, for example, a PCB on which an LSI and other components as shown in FIG. 18 are mounted to form a power supply circuit, and the layout and information of the mounted LSI and other components are taken as an example. This is information necessary for deriving the voltage fluctuation characteristics in the power supply circuit. These pieces of information are input from the input device (1) in FIG. Next, a power supply noise characteristic deriving process (S2) is performed from the inputted circuit design information. This process is performed in the power supply noise characteristic deriving means (2) in FIG. By this processing, the power supply noise characteristic in this PCB is derived.

  Next, a power noise characteristic determination process (S3) and a determination process (S4), which are comparison processes between the derived power noise characteristic and the determination criterion, are performed. This process is performed in the power supply noise condition determination means (3) in FIG. Here, a comparison process between the power supply noise condition provided in the determination reference database (4) and the obtained power supply noise characteristic is performed, and it is determined whether or not the power supply circuit of the PCB is designed stably. When it is determined that the determination criterion is not satisfied as a result of the determination processing whether or not the determination criterion is satisfied (S4), the internal capacity addition processing (S5) is performed. This process is performed in the internal capacity adding means (5) in FIG.

  By this processing, an internal capacity is added to the LSI. In this internal capacity addition process (S5), the LSI data to which the internal capacity has been added is automatically input, and in the power supply noise characteristic derivation process (S2), the LSI information to which the internal capacity has been added is used again. The operation of deriving the power supply noise characteristic is repeated. On the other hand, when it is determined that the determination criterion is satisfied as a result of the determination processing whether or not the determination criterion is satisfied (S4), the mounted capacity comparison processing (S6), which is a process for comparing the additional internal capacity with the determination criterion, is performed. . This process is performed in the mounted capacity condition determining means (6) of FIG. Here, a comparison process is performed between the mounting capacity condition provided in the criterion database (4) and the obtained additional internal capacity value, and whether or not the additional internal capacity value can actually be mounted in the LSI chip. Determined.

Next, in the result output process (S7), a process for outputting the determined result is performed. The result is output to the output device (7) in FIG. At this time, the output results include the determination result of whether the power circuit of the PCB is designed to be stable against noise, the additional internal capacitance value required for the LSI when it is not designed stably, and its addition Not only the determination result of whether or not the internal capacitance value can be mounted on the LSI chip, but also the power noise characteristics before and after the addition of the internal capacitance, and the comparison with the power noise conditions and the mounting capacitance conditions Etc. may be included. Based on these results, it is possible to evaluate by an absolute amount, such as how much margin the design is, and in which frequency range there is a problem.
(Second Embodiment)
Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 2 shows a system configuration according to the second embodiment of the present invention.

  In the second embodiment, power noise equivalent circuit analyzing means (8) is provided as power noise characteristic deriving means (2) in FIG. The power supply noise equivalent circuit analyzing means (8) is generated by an equivalent circuit model generating means (9) for generating an equivalent circuit model of the power supply circuit of the PCB from circuit design information inputted from the input device (1), and Arithmetic means (10) for deriving power supply noise characteristics using an equivalent circuit model is provided. Moreover, a capacity model adding means (11) is provided as the internal capacity adding means (5) in FIG. This capacity model adding means (11) is also described as an equivalent circuit model (hereinafter referred to as “capacitance model”) of the capacity cell actually added inside the LSI chip from the circuit design information inputted from the input device (1). ) To the LSI equivalent circuit model created by the equivalent circuit model generation means (9) (hereinafter also referred to as “LSI equivalent circuit model”).

  The equivalent circuit model generation means (9) is roughly divided into two types. One of them is an equivalent circuit model of a printed circuit board (hereinafter also referred to as a “board equivalent circuit model”) from a PCB design information and a component database, such as PCB layout and cross-sectional structure, and mounted component information. This is a substrate equivalent circuit model creation means to be created. In this board equivalent circuit model creation means, by inputting information such as the cross-sectional structure, material, and layout of the board, a field solver that can create an equivalent circuit model such as a solid layer and wiring of the board is provided. You may have.

  The other means is shown in FIG. 15 (a) or FIG. 15 (b) from the LSI all circuit connection information and layout information, the design information such as LSI operation information, and the database of the components constituting the LSI. LSI equivalent circuit model creation means for creating an LSI equivalent circuit model as described. The LSI equivalent circuit model creating means may include means for automatically creating an LSI equivalent circuit model from all circuit connection information of LSI as described in Patent Document 2 and Patent Document 3. The arithmetic means (10) may be provided with a circuit analysis engine represented by SPICE, an electromagnetic field analysis engine, or the like, and analysis of necessary power supply noise characteristics is executed.

  FIG. 7 is a flowchart showing the processing of the second embodiment of the present invention. This flowchart is a configuration in which an equivalent circuit model generation process (S8) and a circuit analysis process (S9) are performed as the power supply noise characteristic derivation process (S2) described in FIG. Among these, the equivalent circuit model generation process (S8) is performed by the equivalent circuit model generation means (9) in FIG. On the other hand, the circuit analysis process (S9) is performed in the calculation means (10) in FIG. The equivalent circuit model generation process (S8) is an equivalent circuit model (hereinafter referred to as “power system equivalent”) that shows the entire power system of the PCB on which the LSI is mounted, based on the circuit design information input from the input device (1) in FIG. Circuit model)).

  The circuit analysis process (S9) is a process of analyzing the power supply noise characteristic using the generated power supply system equivalent circuit model, and the power supply noise characteristic in the PCB is derived by this process. In addition, a capacity model addition process (S10) is performed as the internal capacity process (S5) described in FIG. This capacity model adding process (S10) is performed by the capacity model adding means (11) in FIG.

  Here, FIG. 9 is a flowchart illustrating the equivalent circuit model generation process (S8). First, by the board information input process (S13), the PCB layout and cross-sectional structure, the board design information such as information on the components to be mounted, and the parts database are input from the input device (1) in FIG. Next, a board equivalent circuit model generation process (S14) is performed, and a board equivalent circuit model including passive components to be mounted, excluding the LSI, is generated by the equivalent circuit model generation means (9) in FIG. Next, through LSI information input processing (S15), design information such as all circuit connection information and layout information of LSI, operation information of LSI, a database of parts constituting the LSI, and added capacity cells Information or the like is input from the input device (1) in FIG.

  Next, an LSI equivalent circuit model that estimates the characteristics of the LSI power supply system such as the current flowing to the LSI power supply, the equivalent admittance, the impedance of the LSI power supply wiring, etc. from the input information by the LSI equivalent circuit model generation processing (S16). 2 is generated by the equivalent circuit model generation means (9) in FIG. At this time, as an LSI equivalent circuit model, a model with a simple configuration as shown in FIG. 16A and position information and a frequency range to be analyzed as shown in FIG. A divided model or the like can be considered, but the structure selection is also described in the database. Next, the generated board equivalent circuit model and the LSI equivalent circuit model are combined by the power supply system equivalent circuit model generation process (S17), and the power supply system equivalent circuit model is converted into the equivalent circuit model generation means (9) in FIG. This process is completed.

  Here, the processing order of the generation of the substrate equivalent circuit model (S13, S14) and the generation of the LSI equivalent circuit model (S15, S16) may be reversed. The order in which the board equivalent circuit model generation process (S14) and the LSI equivalent circuit model generation process (S15) are performed after the board information input process (S13) and the LSI information input process (S15) are performed first. May be selected.

  FIG. 10 is a circuit diagram of the equivalent circuit model generation process (S13) in FIG. 9 in the case where a field solver is provided in the equivalent circuit model generation means (9) of FIG. , S14) is a flowchart showing a specific process. First, the structure input process (S18) of the substrate power supply system is performed, and the structure information of the power supply system of the printed circuit board to be obtained is input from the input device (1) in FIG. The specific information input here is, for example, a PCB constituting a power supply system circuit on which LSI and other components as shown in FIG. 18 are mounted. In this case, the power supply has a solid plane structure. Therefore, in addition to the layout information of the power supply structure of the substrate, the layer configuration and dimensions of the power supply layer, the ground layer, and the insulating layer of the substrate and the respective conductivity (σ) as illustrated in FIG. And numerical information on the structure and material characteristics such as dielectric constant (εr) and dielectric loss tangent (tan δ).

  On the other hand, even when the power source has a microstrip wiring structure as shown in FIG. 13B, the layer configuration, the dimensions of each part including the line width and line length, and the numerical values related to the respective material characteristics Information. The layer configuration and the dimensions of each part can be extracted from information held in the design CAD system of the printed wiring board. Further, FIG. 13 illustrates a substrate configuration (cross-sectional view) of a certain wiring pattern. Here, instead of material constants, a material name such as copper is input, and conductivity is stored from an internal database. It is also possible to perform processing such as replacement with a rate. In this way, the parameters of each part and the database of parts necessary for obtaining the electrical equivalent circuit of the power supply circuit of the board are input.

Next, solver processing (S19) is executed, and an equivalent circuit model of the substrate power supply system is created. This process is performed by a field solver provided in the equivalent circuit model generation means (9) of FIG. The processing performed here refers to resistance, inductance, capacitance, and the like for use in a circuit simulator such as SPICE based on parameters such as physical dimensions of wiring patterns on a printed wiring board, material constants, and layer configurations. This is a process for creating an equivalent circuit model expressed by a lumped constant or a distributed constant per unit length expressed by conductance. As this field solver, an electromagnetic field analysis engine to which a PEEC (Partial Element Equivalent Circuit) method, a FEM (Finite Element Method) method, or the like is applied may be provided. An example of an equivalent circuit model per unit length obtained by performing this processing is shown in FIG. This model is defined by a concentrated constant, resistance per unit length of the wiring, the inductance has become capacitive, each conductance _{values, R U, L U, C} U, and G _U. R _U and L _U represent the impedance Z _U per unit length of the model, and C _U and 1 / G _U represent the admittance Y _U per unit length of the model.

  If the power source has a solid plane structure as shown in FIG. 13A, the models per unit length are combined as shown in FIG. 14B to express the solid plane structure. On the other hand, when the wiring structure as shown in FIG. 13B is used, the model per unit length is combined in a ladder shape as shown in FIG. 14C to express the wiring structure. The model per unit length described in this way is connected by dimensions, so that an equivalent circuit model of the power supply of the board is generated. Of course, even if it is expressed by a distributed constant description instead of a lumped constant description I do not care.

  Next, a component data input process (S20) is performed, and a database of components other than the mounted LSI is input from the input device (1) in FIG. The specific information input here is a database of DC power supplies (regulators) and countermeasure components (chip capacitors) taking the PCB shown in FIG. 18 as an example. Here, the equivalent circuit of each component is included in the database. Suppose a model is entered. Next, the equivalent circuit model of the single board in the board power source generated by the solver process (S19) and the equivalent circuit model of each component in the model combination process (S21) are matched with the actual PCB layout in FIG. The equivalent circuit model generation means (9) is combined, and this process ends.

  Thus, a board equivalent circuit model in the PCB is generated. As the processing order, after the component data input process (S20) is first performed, the board power supply system structure information input process (S18) and the solver process (S19) may be performed. The solver process (S19) may be performed after the board power supply system structure information input process (S18) and the component data input process (S20) are simultaneously performed.

  FIG. 11 is a flowchart showing specific processing of generating an LSI equivalent circuit model (S15, S16) in FIG. At this time, as an LSI equivalent circuit model creation means in the equivalent circuit model generation means (9) of FIG. 2, the LSI equivalent circuit model creation system described in Patent Document 2 and Patent Document 3 is provided. To do.

  First, similarly to the processing of FIG. 10, by LSI information input processing (S22), design information such as all circuit connection information and layout information of LSI, operation information of LSI, and a database of components constituting the inside of LSI. The information of the added capacity cell is input from the input device (1) in FIG. Next, the operation part model generation process (S23) causes the LSI operation part described so that the current flowing from the LSI design information to the power supply terminal of the LSI can be equivalently flowed is equivalent circuit model generation means ( 9). The LSI operation part model 31 generated here can be described by a current source as described in FIG. 15, but it may be described by a transistor through which an equivalent current flows. Can be automatically generated from design information by the methods disclosed in Patent Document 2 and Patent Document 3.

  Here, FIG. 17A shows an example of a waveform of the power supply current described in the LSI operation part model or equivalently flowing in the transistor description model. This waveform represents a current waveform that fluctuates over time, but may be converted into a waveform having a frequency characteristic as described in FIG. These waveforms can be easily converted by Fourier transform or inverse Fourier transform. Further, when obtaining the frequency characteristics of the voltage of the power supply circuit, it may be replaced with an AC power supply waveform showing a constant amplitude even if the frequency varies for simplicity.

  Next, an admittance model expressing equivalent admittance in the LSI is generated by the equivalent circuit model generation means (9) in FIG. 2 by the admittance model generation processing (S24). The LSI admittance model 32 illustrated in FIG. 15 generated here can be expressed by a model composed of a capacitor and a resistor, but may be described by a model in which a transparent transistor is described. It can be automatically generated from design information by the methods disclosed in Patent Document 2 and Patent Document 3. Next, the power distribution circuit model generation processing (S25) generates an LSI power distribution circuit model in the equivalent circuit model generation means (9) in FIG. The power distribution circuit model generated here is an LSI equivalent circuit model that combines an LSI operation part model and an admittance model, and a model that is connected between two types of LSI power terminals (power terminals and GND terminals). Yes, the PCB illustrated in FIG. 18 may include a package model as well as a power supply wiring model in the LSI.

  The structure of the power distribution circuit model may be expressed by a simple inductance model 33 as illustrated in FIG. 15A, but depending on the situation, a plurality of structures may be used as illustrated in FIG. 15B. The structure may be expressed by an equivalent circuit configured by combining circuit blocks. The model of the power distribution circuit may be an equivalent circuit model prepared in a database and read in, but is created by the method described in Patent Document 2 or is a parameter such as structure or material constant. From the input information, a method of creating by a solver process using a field solver provided in the equivalent circuit model generation means (9) of FIG. 2 may be selected.

  Next, in the model combining process (S26), the created LSI operation part model, admittance model, and power distribution circuit model are combined to generate an LSI equivalent circuit model as illustrated in FIG. Ends. In this way, an equivalent circuit model of the LSI mounted on the PCB is generated. It should be noted that the order of the model creation processing (S23, S24, S25) can be appropriately changed.

  Through this process, an example of the power circuit model of the PCB in FIG. 18 is as shown in FIG. 19 by the equivalent circuit model generation process (S8) in FIG. A substrate power supply system model, a DC power supply model, and a chip capacitor model are created by the generation of the substrate equivalent circuit model (S13, S14) in FIG.

Further, an LSI equivalent circuit model, a power distribution circuit model, and a package model are created by generating an LSI equivalent circuit model (S15, S16) in FIG. 9, and these are generated by a power system equivalent circuit model generation process (S17) in FIG. Are combined to generate a power system equivalent circuit model of the PCB. In the power supply model of the board, the impedance is double (2Z _U ) and the admittance is 1/2 or 1/4 (Y _U / 2 or Y _U / 4) at the end portion, which is PEEC In the law, the end part has such a value. The number and size of the mesh is only one example, the value of Y _U varies by mesh size.

FIG. 21 is a circuit analysis process (S9) of FIG. 7 using the PCB power system equivalent circuit model illustrated in FIG. It is an example in the case of calculating | requiring. Whether the voltage fluctuation characteristic satisfies the power supply noise condition read from the determination criterion database (4) in FIG. 2 is automatically determined in the power supply noise condition determination means (3) in FIG. Here, power supply noise conditions is within the DC voltage V _CC value from the drop [Delta] V _DL, and LSI time the switching operation occurs in (ex.t = 0) from until the voltage fluctuation falls return time (e.g. switching It is assumed that the condition that the time from when the operation occurs until the width of the voltage fluctuation is within 1%) must be within _tRL .

For example, in the characteristics of the power supply voltage waveform A at the observation point to the LSI, the voltage drop value ΔV _DA satisfies the condition of ΔV _DA <ΔV _DL , but the return time t _RA is a condition of t _RA <Δt _RL. Therefore, in the circuit in which the power supply voltage waveform A is generated, it is determined that the power supply circuit of the PCB is not stable against noise.

On the other hand, in the characteristics of the power supply voltage waveform B at the observation point to the LSI, the return time t _RB satisfies the condition of t _RB <Δt _RL , but the voltage drop value ΔV _DB is a condition of ΔV _DB <ΔV _DL. Therefore, even in the circuit where the power supply voltage waveform B is generated, it is determined that the power supply circuit of the PCB is not stable against noise. Note that although the power supply noise condition here is considered by both the voltage drop value and the return time, there may be a case where only the voltage drop value is a condition. In that case, it is determined that the PCB power supply circuit is stable against noise in the circuit where the power supply voltage waveform A is generated, and the PCB power supply circuit is determined not stable to noise in the circuit where the power supply voltage waveform B is generated. become.

  Further, in the circuit model of FIG. 19, which is a power system equivalent circuit model of the PCB as illustrated in FIG. 18, the point illustrated as the time variation characteristic of the power supply voltage (in this case, indicated by 55 immediately below the LSI). Although the voltage value at the point is monitored, a power supply noise condition may be set in the characteristics of the voltage value at another monitoring point (for example, the voltage between the power supply and the ground at the end of the power supply plane). Thus, from the result of performing the circuit analysis process (S9) of the power supply system equivalent circuit model of the PCB as illustrated in FIG. 18 in FIG. 7, the power supply noise characteristic comparison process (S3) is the power supply noise determination means in FIG. It is executed in (3). As a result, the determination process (S4) as to whether or not the determination criterion is satisfied is similarly executed in the power supply noise determination means (3) in FIG.

  Here, a plurality of power supply noise conditions are prepared in the determination criterion database (4) in FIG. 2. In the power supply noise characteristic comparison process (S3) and the determination process (S4), a power supply noise characteristic derivation process (S2). It is also possible to adopt a system configuration in which the power supply noise condition corresponding to the power supply noise characteristic obtained in step S3 is automatically selected and read, and the comparison process (S3) and the determination process (S4) are performed.

  For example, it is assumed that a noise condition for the time variation characteristic of the power supply voltage and a noise condition for the frequency characteristic of the power supply voltage are prepared in the determination reference database (4). Here, as a model of the LSI equivalent circuit, a model that outputs a time waveform of the power supply current as shown in FIG. 17A is used, and in the power supply noise characteristic derivation process (S2), the time of the power supply voltage is set as the power supply noise characteristic. When the fluctuation characteristic is obtained, the power supply noise condition corresponding to the fluctuation characteristic is for the time fluctuation of the power supply voltage. Therefore, the noise condition for the time fluctuation of the power supply voltage is automatically selected from the judgment reference database (4). Will be read. Further, when a frequency variation characteristic of the power supply voltage is obtained as the power supply noise characteristic in the power supply noise characteristic derivation process (S2) using the model that outputs the frequency characteristic of the power supply current as shown in FIG. Since the corresponding power supply noise condition is for the frequency fluctuation of the power supply voltage, the noise condition for the frequency fluctuation of the power supply voltage is automatically selected from the determination reference database (4) and read.

  Here, as the power supply noise condition to be prepared, not only the time variation characteristic or frequency characteristic of the power supply voltage but also the time variation characteristic or frequency characteristic of the power supply terminal current of the LSI may be prepared, for example. Even in this case, when the time variation characteristic of the power supply terminal current of the LSI is obtained as the power supply noise characteristic, the time variation characteristic of the power supply terminal current is obtained from the determination reference database (4), and the frequency of the power supply terminal current is also obtained. When the fluctuation characteristic is obtained, the frequency fluctuation characteristic of the power supply terminal current is automatically selected.

  Here, in the determination process (S4), when it is determined that the determination criterion is not satisfied in the power supply noise characteristic, the capacity model addition process (S10) is executed in the capacity model addition means (11) in FIG. . Here, a rule of “adding a certain amount of capacity cells in the LSI chip when the power supply noise condition is not satisfied” is determined in the criterion database, and the LSI design information and database input processing ( By S22), the equivalent circuit model of the capacity cell input by the input device (1) of FIG. 2 is added to the LSI equivalent circuit model by a certain amount. By this process, the LSI becomes an LSI having a new structure in which a certain amount of capacity cells are added, and this new structure information is input, and the equivalent circuit model generation process (S8) is executed again.

  Then, the same process is repeated until the determination criterion is satisfied in the determination process (S4) in FIG. Here, as shown in FIG. 20A, the capacity cell model 41 may be added in parallel to the motion part model 31 and the admittance model 32, but reflects the actual connection information. As shown in (b), it may be added in such a structure that it is connected to the power distribution circuit 33.

  Further, this processing is internal capacitance model addition processing (S27) in the flow chart of generation of the LSI equivalent circuit model shown in FIG. 11, and the capacity is added to the created operation part model, admittance model, and power distribution circuit model of the LSI. The cell model is added, and in the model combining process (S26), these models are combined to generate an LSI equivalent circuit model to which the capacity cell is added.

  Here, in the case where there is no change in the shape of the LSI power distribution circuit, the operation part, or the admittance due to the addition of the capacity cell, the process of generating each model constituting the LSI equivalent circuit model (S23 to S25) The LSI equivalent circuit model generated last time may be used as it is. Similarly, when the structure information of the power supply system of the substrate is not affected by the addition of the capacity cell, the substrate equivalent circuit model generation process shown in FIG. 10 is not performed, and the previously generated substrate equivalent circuit model may be used as it is. .

  When the processing described above is performed and it is determined by the determination processing (S4) that the determination criterion is satisfied in the power supply noise characteristic, the mounting capacity comparison processing (S6) is performed in the mounting capacity condition determination means (6) in FIG. . Here, as an example of the determination criterion of the mounting capacity condition stored in the determination criterion database (4), the size of the capacity cell that can be added in the database of the LSI (hereinafter also referred to as “mounting capacity size”), In the determination process (S4), the size of the capacity cell having the capacity value added when it is determined that the determination criterion is satisfied in the power supply noise characteristic (hereinafter referred to as “essential additional capacity size”) is compared. In the case of the above values, it is assumed that an additional internal capacitance value can be mounted in the LSI chip.

  The determination result by the mounted capacity comparison process (S6) is output to the output device (7) in FIG. As a result to be output at this time, a determination result of whether the power circuit of the PCB is designed stably against noise, an additional internal capacitance value to the LSI required when it is not designed stably, and its additional internal Not only the determination result of whether or not the capacitance value can be mounted on the LSI chip, but also the power noise characteristics before and after the internal capacitance is added, and each power system equivalent circuit model, power noise condition, mounting capacity condition The result of the comparison may be included. Based on these results, it is possible to evaluate by an absolute amount, such as how much margin the design is, and in which frequency range there is a problem.

  In the present embodiment, the generation process of the equivalent circuit model of the power supply circuit of the PCB, the analysis process of the power supply noise characteristic, and the determination process of whether or not the LSI is designed to operate stably are constant for the input data. Therefore, even a person who does not have deep knowledge about LSI and printed circuit board wiring can easily determine whether the power supply circuit is designed to be stable and low noise. I can do it. In addition, the LSI equivalent circuit model creation method and device can be used with existing technology, and commercially available field solvers and circuit analysis tools for creating equivalent circuit models for substrates can be used. Therefore, the system of the present invention can be easily constructed.

In addition, whether or not the power supply circuit is designed stably in one type of power supply system on the PCB in this way, how much additional capacity is added in the LSI chip, and stable operation in the LSI is actually stable. Since it is possible to automatically determine whether it is possible to add a capacity that can operate, a power supply circuit configured by all the power supply systems on the PCB by sequentially repeating the same process for other power supply systems. Is automatically designed, whether it is designed stably, how much additional capacity is added in the LSI chip, and whether it is possible to add capacity that can actually operate stably in the LSI. Judgment is also possible.
(Third embodiment)
Next, a third embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 3 shows the system configuration of the third embodiment of the present invention.

  In the third embodiment, the system configuration of the second embodiment shown in FIG. 2 is provided with chip size changing means (12). The chip size changing means (12) is the LSI size of the LSI inputted from the input device when the mounting capacity condition judging means (6) judges that the LSI chip does not satisfy the voltage variation condition with respect to the additional capacity, Further, it is means for changing the information of the package and the board accompanying it and inputting the information of the changed circuit description into the power supply noise equivalent circuit analysis means (8). By providing this chip size changing means (12), it is possible to always redesign the PCB power supply circuit to a stable structure.

  FIG. 8 is a flowchart showing the processing of the third embodiment of the present invention. This flowchart is a flowchart showing the processing of the second embodiment described in FIG. 7. When the mounted capacity comparison processing (S 6) and the determination processing (S 11) are performed and the determination criteria are not satisfied, the LSI It is a flowchart provided with the process (S12) which changes chip size, changes the structure of a circuit, and inputs again.

  Similar to the flowchart of FIG. 7, circuit information input processing (S <b> 1) is performed from the input device (1) of FIG. 3, and the PCB power is generated from the input information in the equivalent circuit model generation means (9) of FIG. 3. A system equivalent circuit model generation process (S8) is performed, and a circuit analysis process (S9) using the power system equivalent circuit model is performed in the arithmetic means (10) of FIG. In 3), after the comparison processing (S3) of the analyzed power supply noise characteristic and the power supply noise condition read from the determination criterion database (4) of FIG. S4) is performed.

  If the determination criteria are not satisfied in this process, the capacity model addition process (S10) is performed in the capacity model addition means (11) of FIG. A circuit model generation process (S8) is performed. On the other hand, when the determination criterion is satisfied in the determination processing (S4), the mounting capacity comparison processing (S6) and the determination processing (S11) are performed in the mounting capacity condition determination means (6) of FIG.

  If the determination criterion is not satisfied, the chip size changing process (S12) is performed in the chip size changing unit (12) in FIG. As an example of specific means, if the mounting capacity size is smaller than the required additional capacity size, the capacity of the total number of transistors constituting the LSI chip and the number of operating transistors are equal, but the chip size is larger and the mounting capacity size Assume that a change is made to change to an LSI chip with a larger. At this time, it is assumed that the information of the larger LSI chip is stored in advance in the database of the LSI and is input by the circuit information input process (S1), and a specific change method is described in the determination reference database. It shall be written.

  Then, the new chip size LSI information is input again, and the equivalent circuit model generation process (S8) is executed again. Here, in the equivalent circuit model generation process (S8), since each element model constituting the power system equivalent circuit model created in the previous step already exists, the structure of the power system equivalent circuit model in FIG. When performing the process of changing and generating the model again (S13 to S17), only the part where the input information is changed may be changed, which is more realistic. When the determination criterion is satisfied in the mounted capacity determination process (S11), the result output process (S7) is performed, and the result is output to the output device (7) in FIG.

  FIG. 12 is a flowchart showing a specific process of the chip size changing process (S12) in FIG. First, in accordance with the determination criterion database (4) of FIG. 3, the chip change processing for changing to an LSI chip having the same chip capacity but a larger chip size is the same as the conventional one (S28). To do. Next, a chip that automatically selects the power distribution circuit, package information, etc. when the chip is changed, and combines it with the required additional internal capacity information that is already required, and changes the LSI input information The configuration information processing (S29) is performed, and the chip size changing process (S12) ends.

  Further, FIG. 22 shows an image diagram of the LSI chip size and the capacity cell. In the state of FIG. 22A, the mounted capacity size in the LSI chip 73 is smaller than the required additional capacity size of the capacity cell 74 to be added. For this reason, the LSI does not operate stably on the PCB as it is. Therefore, by changing the LSI chip 75 to a larger chip size as shown in FIG. 22B, the mounted capacity size becomes larger than the required additional capacity size of the capacity cell 74, and the structure in which the LSI operates stably on the PCB is obtained. Will be generated.

  Also, the information output to the output device (7) in FIG. 3 includes the determination result of whether or not the power supply circuit of the PCB is designed stably with respect to noise, and the information to the LSI required when it is not designed stably. Not only the additional internal capacitance value and the information of the LSI chip on which the additional internal capacitance value can be mounted, but also the respective power noise characteristics before and after the addition of the internal capacitance and before and after the LSI chip size is changed, and Results of comparison with the respective power supply system equivalent circuit models, power supply noise conditions, and mounting capacity conditions may be included. Based on these results, it is possible to evaluate by an absolute amount, such as how much margin the design is, and in which frequency range there is a problem.

  According to the present embodiment, a PCB structure having a stably designed power supply circuit can be obtained, and its power supply noise characteristics can also be obtained. In addition, if a change guideline for changing the structure of the LSI when the power supply noise condition is not satisfied in the determination reference database (4) of FIG. 3, the power supply circuit of the PCB is automatically connected to the power supply noise. The structure is changed to satisfy the condition. In addition, the generation process of the power system equivalent circuit model, the analysis process of the power supply noise characteristics, and the determination process of whether or not the LSI of the PCB operates stably only performs a certain process on the input data. Therefore, even a person who does not have deep knowledge about LSI or printed circuit board wiring can easily design a PCB having a power supply circuit designed stably.

  In addition, the LSI equivalent circuit model creation method and device can be used with existing technology, and commercially available field solvers and circuit analysis tools for creating equivalent circuit models for substrates can be used. Therefore, the system of the present invention can be easily constructed.

In addition, in one kind of power supply system on the PCB as described above, it is determined whether the power supply circuit is stably designed, or a change to a configuration that operates stably by adding an additional capacitor in the LSI chip, Since it can be automatically executed, it is possible to determine whether the power supply circuit is stably designed in all the power supply systems on the PCB by repeating the same processing for other power supply systems sequentially, or LSI It is also possible to automatically execute a change to a configuration that operates stably by adding an internal capacity in the chip.
(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 4 shows a system configuration according to the fourth embodiment of the present invention.

  In the fourth embodiment, the system according to the second embodiment described in FIG. 2 includes a storage device (13) in which each input information and database are stored. In the storage device (13), there are LSI information including all circuit connection information and layout information of LSI, design information such as LSI operation information, a database of parts constituting the LSI, information of added capacity cells, and the like. A database (14), CAD data and component database (15), which are board design information such as PCB layout and cross-sectional structure, and information on components to be mounted, and a criterion database (4) are stored. .

  In this system, instead of inputting the circuit design information for generating the board equivalent circuit model in the flowchart of FIG. 7 by the input device (1) of FIG. 2, the CAD in the storage device (13) is used as necessary. It is possible to automatically extract necessary data from the data and parts database (15). The wiring information such as the power supply in the CAD data described here generally includes information such as the wiring width, the route designation based on the XY biaxial coordinates of the wiring route, the total length of the wiring, and the connection destination. It contains information such as part names and model numbers.

  Therefore, it is possible and more practical to search the equivalent circuit model of the part in the part database from the part name of the connection destination and select the model. At this time, necessary information is obtained from the design information and LSI database (14) of the plurality of LSIs in the storage device (13) and the plurality of determination reference databases (4) in conjunction with the input CAD data (15). It is also possible and more practical to extract data.

  Specifically, the name of the LSI connected to the power supply circuit, the data of the package, etc. are automatically extracted from the CAD data, the necessary LSI all-round design information, information on the package and power distribution circuit, and the added capacity In this method, the LSI database including cell information and the power noise condition information in the power circuit are automatically selected and input. At this time, the input device (1) may not be used, or may be used only for inputting an action for starting input. This process corresponds to S103 and S104 in FIG. 10 and S105 in FIG.

  Furthermore, it is possible to output the result obtained by the power supply noise condition determination means (3) of FIG. 4 into the CAD data (15) in the storage device (13). This process is S101 in FIG. Specifically, an error is written in the power supply wiring of the substrate in the power supply circuit of the PCB displayed on the CAD and information on the countermeasure parts connected.

  For example, when CAD data is displayed as a diagram, if the structure is such that an alarm is output, such as the color of the part constituting the power supply circuit changing, the user can make the power supply circuit stable in terms of noise. It's not so easy to see at a glance the need to take measures. Further, the result obtained by the mounting capacity condition judging means (6) of FIG. 4 can be output to the LSI design information + LSI database (14) in the storage device (13).

This process is S102 in FIG. Specifically, when the mounting capacity condition is satisfied, the LSI structure information is rewritten to the information of the structure in which the obtained capacity has already been added, or when the mounting capacity condition is not satisfied, the LSI structure information is rewritten. In the information, there is an example in which information is added that indicates how much additional internal capacity is required, but not enough capacity is included in this LSI chip. In this way, by rewriting information, it is possible to obtain guidelines on what measures the designer should take.
(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 5 shows the system configuration of the fifth embodiment of the present invention.

  In the fifth embodiment, the system of the third embodiment described in FIG. 3 is provided with a storage device (13) in which each input information and database are stored. In the storage device (13), as in the fourth embodiment, design information such as all circuit connection information and layout information of LSI, operation information of LSI, and a database of components constituting the LSI are added. The LSI database (14), which is information on the capacity cells to be processed, and the CAD data and parts database (15), which is the design information of the board, which is information on the layout and cross-sectional structure of the PCB and mounted components, etc. A reference database (4) is stored.

  In this system, instead of inputting the circuit design information for generating the board equivalent circuit model in the flowchart of FIG. 8 by the input device (1) of FIG. 3, the CAD in the storage device (13) is used as necessary. It is possible to automatically extract necessary data from the data and parts database (15). In the power supply system of the board in the CAD data, it is possible to search the equivalent circuit model of the part in the part database from the part name of the connection destination and select the model, and it is more practical. is there. At this time, it is necessary to link with the input CAD data (15) from the design information and LSI database (14) of the plurality of LSIs in the storage device (13), and the plurality of criteria database (4). It is also possible and more practical to extract data.

  Specifically, the name of the LSI connected to the power supply circuit, the data of the package, etc. are automatically extracted from the CAD data, and the LSI including the necessary LSI all-round design information and the package and power distribution circuit information In this method, information on the voltage fluctuation condition and voltage frequency condition in the database and its power supply circuit is automatically selected and input. At this time, as in the fourth embodiment, the input device (1) may not be used, or may be used only for inputting an action for starting input. When the chip size changing process (S12) is performed in the flowchart of FIG. 8, the CAD data and component database (15) in the storage device (13) of FIG. 5, the LSI design information and the LSI database (14) ) Is directly accessed, and processing such as LSI chip change and structure change based on the LSI chip is performed, and the description of the CAD data is changed by the processing.

  This process corresponds to S106 and S107 in FIG. 8 and S108 in FIG. Therefore, when the processing is completed, the PCB power supply circuit is configured so that the LSI operates stably, and a stable PCB power supply circuit is automatically obtained, resulting in a more practical system configuration. Yes. At this time, the power supply circuit in the CAD data performs a process such as changing the color of the power supply system or changing the chip size of the LSI when a capacity is added to the LSI. It is also possible to see at a glance whether this has been done.

Next, the operation of the present invention will be described using a specific embodiment.
(First embodiment)
FIG. 23 shows an example of a PCB to be analyzed. An LSI having a package is mounted on a solid power supply layer that covers one surface of a substrate size 200 [mm] × 300 [mm], and a direct current voltage 3 from a direct current power supply to a solid power supply. .3V is supplied and a power supply circuit is configured. It is verified by using the system of the present invention whether or not this power supply circuit is designed stably against noise, and if it is not designed, it is possible to add a capacitor inside the LSI.

  First, as the system, the system described in the fourth embodiment shown in FIG. 4 is used.

  First, the circuit design information input process (S1) of FIG. 7 is performed. Here, a signal for capturing input information from the input device (1) is generated, and the CAD data and mounting of the PCB shown in FIG. 23 are obtained from the CAD data and the component database (15) stored in the storage device (13). A database containing the equivalent circuits of the parts being input is input. In conjunction with the CAD data, at the same time, the LSI design information stored in the storage device (13) and the LSI database (14) include design information including all circuit design information of the mounted LSI, LSI layout information, A database including an equivalent circuit of components and packages constituting the LSI, a layout data of an added capacity cell, an equivalent circuit model, and the like is input.

  At the same time, the power supply noise condition in the PCB shown in FIG. 23 is input from the determination reference database (4) stored in the storage device (13). It is assumed that the power supply noise condition includes information on the observation point and a condition for determining the time variation characteristic of the voltage at that point, and the observation point is a point immediately below the LSI as shown in FIG. To do. This process corresponds to the circuit design information input process (S1) of FIG. This process corresponds to S13 and S15 in FIG. 9. Strictly speaking, the CAD data is input in S103 in FIG. 10, the parts database is input in S104 in FIG. 10, the LSI design information and the database are input. Corresponds to each process of S105 in FIG.

  Next, an equivalent circuit model generation process (S8) in FIG. 7 is performed. First, a substrate equivalent circuit model creation process, which is a series of processes of S13 and S14 shown in FIG. 9, is performed in the equivalent circuit model generation means (9) shown in FIG. The substrate information input processing (S13) or the substrate structure information input processing (S18) in FIG. 10 has already been performed as CAD data input processing (S103). As the next step, substrate equivalent circuit model generation processing (S14) is performed.

  In this process, the solver process (S19) in FIG. 10 is executed using the field solver provided in the equivalent circuit model generation means (9) shown in FIG. Here, the PCB board structure input information input to the field solver is the shape of the power supply wiring and the material constant as shown in FIG. 13A or 13B, and is input from CAD data. It is obtained by the process (S103).

In this example, the power supply pattern has a layer structure as shown in FIG. 13A. The horizontal plane dimension of the power supply on the power supply board, the thickness t-vcc of the power supply layer, the thickness t-gnd of the ground layer, and each insulation From the values of the layer thickness t-in, the conductivity σ of each conductive layer, the relative dielectric constant ε _r and the dielectric loss tangent tan δ of each insulating layer, an equivalent circuit model having a mesh structure as shown in FIG. Create The parameter of Z _U and Y _U will depend on the mesh size of the board model, wherein upon input of the board information, "the model mesh size is 1 [mm] × 1 [mm ]" Is input at the same time, and a model is created accordingly.

In this way, specifically, for a substrate with R _U = 7.379 [mΩ], L _U = 1.257 [nH], C _U = 3.807 [pF], and G _U = 8.612e-5 [S]. Assume that a mesh model of the power supply is generated. Further, the component data input process (S20) for the component mounted on the board is also performed as the component database input process (S104).

  Next, the model combining process (S21) in FIG. 10 is executed to combine the generated board model and the model of the component other than the mounted LSI. In this example, the DC power supply and chip capacitor model input in the input process (S104) from the component database is combined with the model of the substrate on the CAD data where the DC power supply and the chip capacitor are mounted. The process is performed. In this way, the board equivalent circuit model is created in the equivalent circuit model generating means (9) shown in FIG.

  Next, the LSI equivalent circuit model generation process (S16) shown in FIG. 9 is performed in the equivalent circuit model generation means (9) shown in FIG. The LSI information input process (S16) or the LSI design information and LSI database input process (S22) in FIG. 11 already corresponds to the input of CAD data, and the LSI design information and the LSI from the storage device (13) in FIG. This is performed as a database automatic input process (S105).

  Next, an operation part model generation process (S23) in FIG. 11 is performed, and an LSI operation part model is generated from the input LSI design information and the LSI database. Here, it is assumed that the model of the gate circuit of the transistor description obtained by the method described in Patent Document 3 is generated by a method of converting into a current source. Here, it is assumed that an operation partial model is generated that illustrates a current flowing through a power supply terminal of an LSI that causes a switching operation at 24 [MHz].

  Next, LSI admittance model generation processing (S24) in FIG. 11 is performed, and an LSI equivalent admittance model is generated. Here, it is assumed that the method described in Patent Document 3 is applied and the equivalent internal capacitance of the obtained circuit is collected by a technique. Next, an LSI power distribution circuit model generation process (S25) in FIG. 11 is performed to generate an equivalent circuit model of the power distribution circuit including the LSI package. Here, it is assumed that the power distribution circuit and the package model are prepared in the component database, and since this information has already been input, no particular processing is performed. If the power supply wiring or the like in the LSI is described by information such as the board wiring in FIG. 13B, the equivalent is obtained by the solver processing by the field solver provided in the equivalent circuit model generation means (9). A circuit model needs to be generated.

  Next, the model combination process (S26) in FIG. 11 is executed, the LSI operation partial model, the equivalent admittance model, and the power distribution circuit model are combined, and the LSI equivalent circuit model is equivalent to the equivalent circuit model generating means shown in FIG. Created in (9).

  Next, the power system equivalent circuit model generation process (S17) shown in FIG. 9 is performed in the equivalent circuit model generation means (9) shown in FIG. The generated board equivalent circuit model and LSI equivalent circuit model are combined to reflect the position of the LSI on the PCB shown in FIG. 23, and the equivalent circuit model of the PCB to be obtained is equivalent circuit model generating means ( 9).

  FIG. 24 is an example of the equivalent circuit model of FIG. DC power supply equivalent circuit model (R = 600 [mΩ], L = 2.45 [nH] connected in series V = 3.3 [V] DC power supply) (93), chip capacitor (4) Equivalent circuit model (R = 400 [mΩ], L = 2.60 [nH] element model of C = 0.1 [μF] connected in series) (94), and LSI equivalent circuit model (92) Are connected to the board equivalent circuit model (91) divided by 1 [mm] × 1 [mm].

Further, the LSI package model (99) has a form expressed by an LCR ladder circuit as shown in FIG. 24, and L _PKG = 0.479 [nH], R _PKG = 0.366 [mΩ]. ], C _PKG = 12.96 [pF]. The power distribution circuit model (98) has a structure in which a series resistance of 10 [Ω] exists on the power supply side and the ground side, and the equivalent admittance model (97) has a capacitance of 3000 [pF] with a capacitance of 2. This is a model in which a resistance of 0 [mΩ] is connected in series. The motion part model (96) is a model in which a current waveform as shown in the figure repeatedly flows at a cycle of 24 [MHz].

  Next, the circuit analysis process (S9) shown in FIG. 7 is executed in the arithmetic means (10) shown in FIG. Here, in the previous circuit design information input process (S1), since the power supply noise condition is the determination condition of the time variation characteristic of the voltage at the observation point, the automatically obtained characteristic is the PCB observation in FIG. It becomes the time variation characteristic of the voltage at the point (85). Therefore, using the equivalent circuit model shown in FIG. 24 generated in the previous processing, a transient analysis is performed by the circuit analysis engine provided in the calculation means (10) of FIG. Characteristics are derived. The obtained voltage fluctuation characteristic has a time waveform shown in FIG.

  Next, comparison processing (S3) and determination processing (S4) between the power supply noise characteristic and the determination criterion shown in FIG. 7 are executed in the power supply noise condition determination means (3) shown in FIG. Here, the power supply noise condition input from the determination criterion database (4) shown in FIG. 4 is compared with the analyzed power supply noise characteristic to determine whether the power supply noise characteristic satisfies the determination criterion. Here, it is assumed that the power supply noise condition is the lower limit voltage threshold Vth = 3.069 [V] (7% voltage drop), and the determination criterion is not satisfied if the time variation characteristic of the voltage falls below this threshold even for a moment. . Although the Vth characteristic is also shown in FIG. 26, the time variation characteristic of the voltage derived by the transient analysis using the equivalent circuit model is always larger than Vth, and therefore the criterion is satisfied. It is determined that

  Next, a comparison process (S6) between the additional internal capacity and the determination criterion in FIG. 7 is performed. Here, it is assumed that the mounting capacity condition which is the determination criterion is an amount automatically determined from information on the capacity mounting area of the LSI in the LSI database and the area of the capacity cell. However, in this case, in the previous process, the power supply noise condition is satisfied without adding a capacitor in the LSI, so the additional internal capacitance is zero. Therefore, the mounting capacity condition is automatically satisfied.

  Next, the result output process (S7) in FIG. 7 is performed, the comparison result (S3) between the power supply noise characteristic and the determination criterion, the determination result (the power supply noise condition is satisfied) in the determination process (S4), and the additional internal capacity The determination result in the comparison process (S6) with the determination criterion (satisfying the mounting capacity condition) is output to the output device (7) in FIG. 4, and the series of processes ends. Here, at the same time, the equivalent circuit model of the PCB described in FIG. 24 and the characteristics shown in FIG. 26 that are the results of analysis comparison using the model may be output.

At the same time, a result output process (S101) to CAD data in FIG. 7 is performed, and the description of the CAD data (15) in the storage device (13) in FIG. 4 is changed. Here, a message that the power supply noise condition is satisfied is written in the substrate power supply wiring in the CAD data, and when the CAD data in FIG. 23 is illustrated, the color of the substrate power supply wiring changes to, for example, light blue, and the power supply noise condition You will soon see that Through the above processing, it is automatically determined whether or not the PCB power supply circuit shown in FIG. 23 is designed to be stable against noise.
(Second embodiment)
Next, the operation of the present invention will be described using another embodiment that is very similar to the previous example.

  In this example, whether the power supply circuit is designed to be stable against noise using the PCB shown in FIG. 23 as in the previous example and the system described in the fourth embodiment shown in FIG. Automatically determine whether. At this time, the power supply noise condition is different from the previous example, and it is assumed that the lower limit voltage threshold Vth = 3.135 [V] (5% voltage drop). It is assumed that the condition is that the standard is not satisfied. In this case, since the determination result is changed, when this system is used, a part of different processing is performed and another result is output.

  First, the circuit design information input process (S1), equivalent circuit model generation process (S8), and circuit analysis process (S9) in FIG. 7 are successively performed. The contents of these processes are exactly the same as those in the previous embodiment.

  Next, the comparison process (S3) and the determination process (S4) between the power supply noise characteristic and the determination criterion shown in FIG. 7 are executed in the power supply noise condition determination means (3) shown in FIG. 4, and shown in FIG. The power supply noise condition input from the determination criterion database (4) is compared with the analyzed power supply noise characteristic to determine whether the power supply noise characteristic satisfies the determination criterion. Here, the power supply noise condition is Vth = 3.135 [V] unlike the previous example. FIG. 27 shows both the time variation characteristic of the voltage derived by the transient analysis using the equivalent circuit model and the Vth characteristic. In the time variation characteristic of the voltage, there is a time when the voltage falls below Vth. Therefore, it is determined that the criterion is not satisfied.

  Next, since it is determined in the determination process (S4) that the determination criterion is not satisfied, the capacity model addition process (S10) in FIG. 7 is executed in the capacity addition means (11) shown in FIG. . Here, it is assumed that a change guideline “add capacity cells by 500 [pF] each inside the LSI when the power supply noise condition is not satisfied” is prepared in the criterion database (4). The capacity cell is added by 500 [pF]. Specifically, an equivalent circuit model for the capacity cell 500 [pF] is prepared in the input LSI database, and the model is included in the LSI equivalent circuit model created by the processing described above. As a result, an LSI equivalent circuit model with internal capacitance added is created. This process is an internal capacity model addition process (S27) in FIG.

  Then, the process returns to the equivalent circuit model generation process (S8) in FIG. 7 again, and a power system equivalent circuit model is generated using the LSI equivalent circuit model to which the capacitance model is added. Then, the circuit analysis process (S9), the comparison process (S3) between the power supply noise characteristic and the determination criterion, and the determination process (S4) are performed again. When it is determined that the determination criterion is not satisfied again by this determination process (S4), a process of adding a capacity cell for 500 [pF] again in the capacity model addition process (S10) of FIG. Then, an iterative process of returning to the equivalent circuit model generation process (S8) of FIG. 7 is performed again.

  On the other hand, when it is determined in the determination process (S4) that the determination criterion is satisfied, information on the added capacity is obtained and the process proceeds to the next process. In actuality, in this circuit, when the capacity cell is added by 2500 [pF] (when the determination criterion (S4) does not satisfy the determination criterion four times), the time variation characteristic of the voltage as shown in FIG. 28 is obtained. Since the written Vth characteristic is always satisfied, it is determined that the determination criterion is satisfied, and the process proceeds to the next process. Further, the power system equivalent circuit model at this time has a structure as shown in FIG. For reference, the time variation characteristic of the voltage when the capacity cell is added by 2000 [pF] is shown in FIG. 29. In the time variation characteristic of the voltage at this time, there is a time when the voltage is lower than Vth. Therefore, in the case of Vth = 3.135 [V], the determination criterion is not satisfied, and the capacity cell is added again by 500 [pF], and the time variation characteristic of the voltage as shown in FIG. 28 is obtained. The operation will be repeated.

  When the determination criterion is satisfied by the determination processing (S4), the comparison processing (S6) between the additional internal capacity and the determination criterion is performed in the mounted capacity condition determination means (6) in FIG. Here, the mounted capacity condition input from the determination criterion database (4) shown in FIG. 4 is compared with the additional internal capacity necessary to satisfy the power supply noise condition. Here, the mounting capacity condition is derived from the area of the area in which the capacity cell can be mounted in the LSI chip and the area of the capacity cell in the layout information in the LSI database, and here is 2000 [pF]. Suppose. Here, if the capacity cell to be added is determined, the mounting capacity condition may be given by a specific capacity value for each LSI chip given from the beginning, instead of calculating from the layout information. In the previous process, the capacity cell must be added by 2500 [pF], so that the time variation characteristic of the voltage satisfying the power supply noise condition as shown in FIG. 28 cannot be obtained, so it is determined that the mounting capacity condition is not satisfied. Is done.

  Next, the result output process (S7) in FIG. 7 is performed, and the determination result in the comparison process (S3) between the power supply noise characteristic and the determination criterion and the determination process (S4) (the power supply noise condition is satisfied when no capacity cell is added) In addition, if a 2500 [pF] capacity cell is added, the power supply noise condition is satisfied), and the determination result in the comparison process (S6) between the internal capacitance and the determination criterion (the mounted capacity condition is not satisfied) is shown in FIG. (7) is output, and a series of processing ends. Here, at the same time, the equivalent circuit model of the PCB described in FIG. 24 and FIG. 25 and the characteristics as shown in FIG. 28 which are the results of analysis comparison using the model may be output. At the same time, a result output process (S101) to CAD data in FIG. 7 is performed, and the description of the CAD data (15) in the storage device (13) in FIG. 4 is changed. Here, a message that the power supply noise condition is not satisfied as it is is written in the substrate power supply wiring in the CAD data, and when the CAD data in FIG. 23 is shown, the color of the substrate power supply wiring changes to, for example, red. As a result, it can be immediately understood that the power supply noise condition cannot be satisfied unless measures are taken.

  At the same time, a result output process (S102) to the LSI design information in FIG. 7 is performed, and the description of the LSI design information (14) in the storage device (13) in FIG. 4 is changed. Here, in order to stabilize the power supply circuit against noise, it is necessary to add a capacity cell of 2500 [pF]. However, since the mounting capacity condition is not satisfied, in the process of adding the capacity cell inside the LSI, The message “The power circuit cannot be stabilized against noise” is written. Further, reflecting the result, when the CAD data of FIG. 23 is shown, the color of the portion where the LSI is displayed is made purple, for example, so that the LSI chip does not satisfy the mounting capacity condition. Can be understood immediately. Through the above processing, whether or not the power supply circuit of the PCB shown in FIG. 23 is designed to be stable against noise can be redesigned stably against noise by adding a capacity cell in the LSI chip. It is automatically determined whether it is possible.

  In this way, even if a change that adds internal capacitance to an LSI is performed according to the change guideline, the following change guideline is prepared even if the determination criterion is not satisfied in the power supply noise condition, and the circuit structure is maintained until the determination criterion is satisfied. This makes it possible to obtain a PCB power circuit structure that is automatically designed to be stable against noise, and whether the structure can be realized in the LSI chip that is mounted at the same time. Can also be automatically determined. It should be noted that the change guideline need not be one type. “If the power supply noise condition is not satisfied, a capacity cell is added by 250 [pF] inside the LSI.

  If the power supply noise condition is still not satisfied, a capacity cell is added by 500 [pF] inside the LSI. However, it is possible to give different change guidelines for each stage.

  In addition, receiving the result that the power supply noise condition cannot be satisfied by the countermeasure of adding the capacity cell in the LSI leads to the result that another countermeasure needs to be taken in the PCB. Deriving a guideline that the PCB structure needs to be changed other than by adding capacity cells in the LSI, such as changing the LSI package or installing a chip capacitor between the PCB power supply and GND. It can also be used for the purpose of.

  Furthermore, when the LSI vendor uses the system of the present invention in advance to take measures against the LSI to be provided, there is a case where it is not certain which PCB the user will mount the LSI on. In such a case, past PCB data or standard PCB data may be used as a substitute. Here, as a standard PCB, a typical one mounted on a device that is an operation application of the LSI can be considered, for example, a mother board in a PC.

  Since these dimensions are almost fixed and the number of other ICs such as memories and the number of mounted chip capacitors can be easily estimated, if such PCB data is used, the power noise condition Is not expected to change much. Also, using this system, LSIs are mounted on various PCBs and judgments are made, so that LSIs can be used by LSI vendors and users can be used in any PCB structure. It can also be used to propose rules such as For example, it is possible to provide a rule such as “arrange 10 chip capacitors of 0.1 μF within 10 mm from one side of an LSI”.

Furthermore, in order to derive a guideline for countermeasures, it can be used for purposes such as changing the mounting capacity condition and the power supply noise condition, and judging each result. For example, when the mounting capacity condition is only the capacity cell 500 [pF], the condition that the determination condition is satisfied if the value of Vth is set as the power supply noise condition is that the mounting capacity condition is constant in this system, and Vth This value can be derived by finely swaying the value of, causing the system to execute at each value, obtaining the result at each Vth, and comparing the results.
(Third embodiment)
Next, another embodiment will be described. As the system in this case, the system described in the fifth embodiment shown in FIG. 5 is used.

  As the PCB data to be prepared, the data shown in FIG. 23 is used as in the previous example. It is determined whether or not the PCB power circuit is designed to be stable against noise, and if it is not stable, the PCB power circuit structure is changed using the system of the present invention so as to be stable.

  First, the circuit design information input process (S1) in FIG. 8 is performed. Here, a signal for capturing input information from the input device (1) is generated, and the CAD data and mounting of the PCB shown in FIG. 23 are obtained from the CAD data and the component database (15) stored in the storage device (13). The data including the equivalent circuit of the component being input is input. In conjunction with this CAD data, simultaneously from the LSI design information stored in the storage device (13) and the LSI database (14), design information including all circuit design information of the mounted LSI, LSI layout information, Data including the equivalent circuit of the components and packages constituting the LSI, the layout data of the added capacity cell, the equivalent circuit model, and the like are input.

  At the same time, the power supply noise condition in the PCB shown in FIG. 23 is input from the determination reference database (4) stored in the storage device (13). It is assumed that the power supply noise condition includes information on the observation point and a condition for determining the time variation characteristic of the voltage at that point, and the observation point is a point immediately below the LSI as shown in FIG. To do. This process corresponds to the circuit design information input process (S1) of FIG. This process corresponds to S13 and S15 in FIG. 9. Strictly speaking, the CAD data is input in S103 in FIG. 10, the parts database is input in S104 in FIG. 10, and the LSI design information and data are input in FIG. 11 corresponds to each process of S105.

  Next, an equivalent circuit model generation process (S8) in FIG. 8 is performed. First, a substrate equivalent circuit model creation process, which is a series of processes S13 and S14 shown in FIG. 9, is performed in the equivalent circuit model generation means (9) shown in FIG. The substrate information input processing (S13) or the substrate structure information input processing (S18) in FIG. 10 has already been performed as CAD data input processing (S103). As the next step, substrate equivalent circuit model generation processing (S14) is performed. In this process, the solver process (S19) in FIG. 10 is executed using the field solver provided in the equivalent circuit model generating means (9) shown in FIG.

  Here, as described in the previous embodiment, the input information of the PCB substrate structure input to the field solver is the shape of the power supply wiring as shown in FIG. 13 (a) or FIG. 13 (b). And the material constant, which are obtained by input processing from CAD data (S103). In this example, the power supply pattern has a layer structure as shown in FIG. 13A, and an equivalent circuit model having a mesh structure as shown in FIG. 14B is created. In addition, information that “the mesh size of the substrate model is 1 [mm] × 1 [mm]” is input at the same time, and a mesh model of the power supply of the substrate is generated accordingly. In addition, the component data input process (S20) for the component mounted on the board is also performed as the component database input process (S104).

  Next, the model combining process (S21) in FIG. 10 is executed to combine the generated board model and the model of the component other than the mounted LSI. In this example, the DC power supply and chip capacitor model input in the input process (S104) from the component database is combined with the model of the substrate on the CAD data where the DC power supply and the chip capacitor are mounted. The process is performed. In this way, the board equivalent circuit model is created in the equivalent circuit model generating means (9) shown in FIG.

  Next, the LSI equivalent circuit model generation process (S16) shown in FIG. 9 is performed in the equivalent circuit model generation means (9) shown in FIG. The LSI information input process (S15) or the LSI design information and LSI database input process (S22) in FIG. 11 has already been performed, and the LSI design information and the LSI database from the storage device (13) in FIG. Automatic input processing (S105).

  Next, an operation part model generation process (S23) in FIG. 11 is performed, and an LSI operation part model is generated from the input LSI design information and the LSI database. Here, it is assumed that it is generated by the method described in Patent Document 3 as in the previous embodiment. Here, it is assumed that an operation partial model is generated that illustrates a current flowing through a power supply terminal of an LSI that causes a switching operation at 24 [MHz]. Next, LSI admittance model generation processing (S24) in FIG. 11 is performed, and an LSI equivalent admittance model is generated.

  Next, an LSI power distribution circuit model generation process (S25) in FIG. 11 is performed to generate an equivalent circuit model of the power distribution circuit including the LSI package. Here, as in the previous embodiment, it is assumed that the power distribution circuit and the package model are prepared in the component database, and since this information has already been input, no particular processing is performed. If the power supply wiring or the like in the LSI is described by information such as the board wiring in FIG. 13B, the equivalent circuit model generation means (9) has the same configuration as in the previous embodiment. An equivalent circuit model needs to be generated by solver processing using the provided field solver.

  Next, the model combination process (S26) in FIG. 11 is executed, the LSI operation partial model, the equivalent admittance model, and the power distribution circuit model are combined, and the LSI equivalent circuit model is equivalent to the equivalent circuit model generating means shown in FIG. Created in (9).

  Next, the power system equivalent circuit model generation process (S17) shown in FIG. 10 is performed in the equivalent circuit model generation means (9) shown in FIG. The generated board equivalent circuit model and LSI equivalent circuit model are combined to reflect the position of the LSI on the PCB shown in FIG. 23, and the equivalent circuit model of the PCB to be obtained shown in FIG. 24 is shown in FIG. It is created in the equivalent circuit model generation means (9).

  Next, the circuit analysis process (S9) shown in FIG. 8 is executed in the arithmetic means (10) shown in FIG. Here, in the previous circuit design information input process (S1), since the power supply noise condition is the determination condition of the time fluctuation characteristic of the voltage at the observation point, the automatically obtained characteristic is the observation point of the PCB in FIG. This is the time variation characteristic of the voltage in (85). Therefore, a transient analysis is performed by the circuit analysis engine provided in the arithmetic means (10) of FIG. 5 using the equivalent circuit model shown in FIG. 24 generated in the previous processing, and is shown in FIG. 26 at the observation point. The time variation characteristic of the voltage to be obtained is derived.

  Next, a comparison process (S3) and a determination process (S4) between the power supply noise characteristic and the determination criterion shown in FIG. 8 are executed in the power supply noise condition determination means (3) shown in FIG. Here, the power supply noise condition input from the determination criterion database (4) shown in FIG. 5 is compared with the analyzed power supply noise characteristic to determine whether the power supply noise characteristic satisfies the determination criterion. Here, it is assumed that the power supply noise condition is the lower limit voltage threshold Vth = 3.135 [V] (5% voltage drop). If the time variation characteristic of the voltage falls below this threshold even for a moment, the determination criterion must be satisfied. To do. In this case, the relationship between the time variation characteristic of the voltage and the characteristic of Vth is as shown in FIG. 27. In this time variation characteristic of the voltage, since the time when the voltage falls below Vth exists, the determination criterion is satisfied. It is determined that it is not.

  Next, since it is determined in the determination process (S4) that the determination criterion is not satisfied, the capacity model addition process (S10) in FIG. 8 is executed in the capacity addition means (11) shown in FIG. Here, it is assumed that a change guideline “add capacity cells by 500 [pF] each inside the LSI when the power supply noise condition is not satisfied” is prepared in the criterion database (4). The capacity cell is added by 500 [pF]. Here, as in the previous embodiment, an equivalent circuit model for the capacity cell 500 [pF] is prepared in the input LSI database, and the model is equivalent to the LSI equivalent created by the processing described above. By adding in the circuit model, an LSI equivalent circuit model to which internal capacitance is added is created. This process is an internal capacity model addition process (S27) in FIG.

  Then, the process returns to the equivalent circuit model generation process (S8) in FIG. 8 again, and a power system equivalent circuit model is generated using the LSI equivalent circuit model to which the capacitance model is added. Then, the circuit analysis process (S9), the comparison process (S3) between the power supply noise characteristic and the determination criterion, and the determination process (S4) are performed again. When it is determined that the determination criterion is not satisfied again by this determination process (S4), a process of adding a capacity cell for 500 [pF] again in the capacity model addition process (S10) of FIG. Then, an iterative process of returning to the equivalent circuit model generation process (S8) of FIG. 8 is performed again.

  On the other hand, when it is determined in the determination process (S4) that the determination criterion is satisfied, information on the added capacity is obtained and the process proceeds to the next process. In this circuit, when the capacity cell is added by 2500 [pF] (when the determination criterion (S4) does not satisfy the determination criterion four times), the time variation characteristic of the voltage as shown in FIG. 28 is obtained. Since the written Vth characteristic is always satisfied, it is determined that the determination criterion is satisfied, and the process proceeds to the next process. The power system equivalent circuit model at that time has a structure as shown in FIG. It has become.

  Next, when it is determined that the determination criterion is satisfied by the determination processing (S4) with the power supply noise condition, the comparison processing (S6) between the additional internal capacity and the determination criterion and the determination processing (S11) are illustrated in FIG. 5 is performed in the mounting capacity condition determination means (6). Here, the mounted capacity condition input from the determination criterion database (4) shown in FIG. 5 is compared with the additional internal capacity necessary to satisfy the power supply noise condition. Here, it is assumed that the mounting capacity condition is that the capacity cell can be added up to 2000 [pF] as in the previous embodiment. In the previous process, the capacity cell must be added by 2500 [pF], so that the time variation characteristic of the voltage satisfying the power supply noise condition as shown in FIG. 28 cannot be obtained, so it is determined that the mounting capacity condition is not satisfied. Is done.

  Next, since it is determined that the determination criterion is not satisfied by the determination process (S11) with the mounting capacity condition, the chip size changing process (S12) in FIG. ) Is executed. Specifically, an operation of changing the LSI chip in the input LSI database to one having a larger mounting capacity condition is performed. Here, a change guideline “if the mounting capacity condition is not satisfied, the LSI chip is changed to one whose mounting capacity condition is larger by the capacity cell 500 [pF]” is shown in the criterion database (4) of FIG. It is assumed that the LSI chip information to be changed in each case is prepared in the LSI database (14).

  Therefore, first, a chip change process (S28) in FIG. 12 is performed, and a process of changing the current LSI chip to an LSI chip whose mounting capacity condition is for the capacity cell 2500 (2000 + 500) [pF] is performed. Next, the chip configuration information change process (S29) in FIG. 12 is performed, and the database of the internal configuration of LSI chip, layout information, etc. is changed to that of the changed chip. The chip change process (S28) and the chip configuration information change process (S29) may be a process of automatically exchanging data from the LSI design information and the LSI database (14) in FIG. This corresponds to S108 in FIG. Through this series of processing, the LSI mounted on the power supply circuit of the PCB is not changed in other operating states, but the mounted capacity condition is changed to that corresponding to the capacity cell 2500 [pF]. .

  Then, the circuit information changed by the preprocessing is further input to the power supply noise equivalent circuit analysis means (8) in FIG. 5, and the equivalent circuit model generation processing (S8) and circuit analysis processing (S9) in FIG. 8 are executed again. Is done. Here, assuming that the structure of the power system equivalent circuit model has not been changed due to the change of the LSI chip, the equivalent circuit model as shown in FIG. 24 is created by the equivalent circuit model generation process (S8). In the circuit analysis process (S9), the time variation characteristic of the voltage as shown in FIG. 27 is derived.

  Further, in the power system equivalent circuit model as shown in FIG. 24, the comparison process (S3) and the determination process (S4) between the power noise characteristics and the criterion are already performed, and the power system is stable against noise. Since it is known that the necessary capacity cell is 2500 [pF] and the information exists, the capacity cell as shown in FIG. 25 from the beginning in the equivalent circuit model generation process (S8). Is added by 2500 [pF], and the time variation characteristic of the voltage as shown in FIG. 28 is derived by the circuit analysis process (S9).

  Next, the comparison process (S3) and the determination process (S4) between the power supply noise characteristic and the determination criterion in FIG. 8 are executed again. Here, in the above-described equivalent circuit model generation process (S8) and circuit analysis process (S9), when the equivalent circuit model of FIG. 24 is created and the time variation characteristics of the voltage as shown in FIG. 27 are derived. Is determined not to satisfy the determination criterion in the determination process (S4), it is necessary to perform a process of adding capacity cells by 500 [pF] in accordance with the change guideline by the capacity model addition process (S10) again. is there.

  On the other hand, in the above-described equivalent circuit model generation process (S8) and circuit analysis process (S9), when the equivalent circuit model of FIG. 25 is created and the time variation characteristics of the voltage as shown in FIG. 28 are derived, Since it is determined in the determination process (S4) that the determination criterion is satisfied, the following comparison processing (S6) and determination processing (S11) between the additional internal capacity and the determination criterion are performed.

  Here, in the determination process (S11) with the mounted capacity condition, since the mounted capacity condition is changed so that capacity cells can be added up to 2500 [pF], it is determined that the determination criterion is satisfied this time. Therefore, the process proceeds to the next result output process (S7). If it is determined that the determination criterion is not satisfied at this time, the chip size changing process (S12) is performed again, and the LSI chip has a larger mounting capacity condition (in this case, the capacity cell is 500 [pF] larger). In other words, 2500 + 500 = 3000 [pF]).

  Next, the result output process (S7) of FIG. 8 is performed, and the determination result in the comparison process (S3) and the determination process (S4) between the power supply noise characteristic and the determination criterion (when no capacity cell is added, the power supply noise condition is satisfied) First, if a capacity cell of 2500 [pF] is added, the power supply noise condition is satisfied, the determination result by the comparison processing (S6) between the internal capacitance and the determination criterion, and the determination processing (S11) (the LSI chip that was first mounted) In this case, it is necessary to change to an LSI chip that does not satisfy the mounting capacity condition and 2500 [pF] capacity cells can be added), and the structure of the changed PCB power supply circuit (change of the LSI chip that was initially mounted) In addition, a structure in which an LSI chip capable of adding 2500 [pF] capacity cells is mounted) is output to the output device (7) in FIG. 5, and a series of processing ends.

  Here, at the same time, the equivalent circuit model of the PCB described in FIG. 24 and FIG. 25 and the characteristics as shown in FIG. 28 which are the results of analysis comparison using the model may be output. At the same time, a result output process (S106) to CAD data in FIG. 8 is performed, and the description of the CAD data (15) in the storage device (13) in FIG. 5 is changed. Here, a message that the power supply noise condition is not satisfied as it is is written in the substrate power supply wiring in the CAD data, and when the CAD data in FIG. 23 is shown, the color of the substrate power supply wiring changes to, for example, red. As a result, it can be immediately understood that the power supply noise condition cannot be satisfied unless measures are taken.

  At the same time, a result output process (S107) to the LSI design information in FIG. 8 is performed, and the description of the LSI design information (14) in the storage device (13) in FIG. 5 is changed. Here, in order to stabilize the power supply circuit against noise, it is necessary to add a capacity cell of 2500 [pF]. However, since the mounting capacity condition is not satisfied, the LSI chip has a capacity cell of 2500 [pF]. “Changed to something that can be added” is written.

  Also, reflecting the result, when the CAD data of FIG. 23 is shown, the color of the portion where the LSI is displayed is changed to, for example, green, so that the LSI chip is changed to satisfy the mounting capacity condition. It is immediately obvious that it is a thing. By the above processing, it is automatically determined whether or not the power supply circuit of the PCB shown in FIG. 23 is designed to be stable against noise, and the PCB is automatically added by adding a capacity cell in the LSI chip. This makes it possible to redesign the power supply circuit stably against noise.

  Moreover, it is also possible to update the data and the change guideline in the determination reference database from the results of these series of processes and reflect them in subsequent determinations.

  According to the present invention, voltage fluctuation characteristics in a power supply circuit on a PCB on which an LSI and other components are mounted are accurately analyzed, and applied to a purpose of determining whether the power supply circuit is designed stably against noise. Is possible. In addition, it is possible to determine whether or not each of the plurality of power supply circuits on the PCB is designed to be stable against noise and extract which power supply circuit on the board is to be taken.

  Furthermore, according to the present invention, in a power circuit on a PCB on which an LSI and other components are mounted, an internal capacity is added to the LSI so as to automatically satisfy a noise judgment criterion in the power source, and the LSI is stably designed. It is applicable to the purpose of redoing.

It is the figure which showed the system configuration | structure of the 1st Embodiment of this invention. It is the figure which showed the system configuration | structure of the 2nd Embodiment of this invention. It is the figure which showed the system configuration | structure of the 3rd Embodiment of this invention. It is the figure which showed the system configuration | structure of the 4th Embodiment of this invention. It is the figure which showed the system configuration | structure of the 5th Embodiment of this invention. It is the figure which showed the flowchart of the 1st Embodiment of this invention. It is the figure which showed the flowchart of the 2nd and 4th embodiment of this invention. It is the figure which showed the flowchart of the 3rd and 5th embodiment of this invention. It is the figure which showed the flowchart of an equivalent circuit model creation process. It is the figure which showed the flowchart of the board | substrate equivalent circuit model creation process in an equivalent circuit model creation process. It is the figure which showed the flowchart of the LSI equivalent circuit model creation process in the equivalent circuit model creation process. It is the figure which showed the flowchart of a chip size change process. It is an example of the cross-sectional structure of a board | substrate. It is an example of the equivalent circuit model of the board | substrate produced | generated by a solver process. It is an example of the equivalent circuit model structure of LSI. It is an example of the structure when the whole LSI is expressed by an equivalent circuit model. It is an example of the description inside the current source of the operation | movement part model of LSI. It is an example of the structure of PCB in which components were mounted. It is an example of the equivalent circuit model of PCB. It is an example of the structure of the equivalent circuit model of LSI to which the capacity model is added. It is an example of the voltage fluctuation characteristic as a power supply noise characteristic. It is the image figure which showed the relationship between the chip size of LSI and the capacity cell to add. It is the structure of PCB used for the Example. It is an example of the structure of the equivalent circuit model of PCB shown in FIG. 23, and each parameter. FIG. 23 shows an example of the structure of an equivalent circuit model of a PCB to which the countermeasure shown in FIG. It is a comparison waveform of the voltage fluctuation at the observation point in the equivalent circuit model of PCB and the threshold value which is the power supply noise condition. It is a comparison waveform of the voltage fluctuation at the observation point in the equivalent circuit model of PCB and the threshold value which is the power supply noise condition. It is a comparison waveform of the voltage fluctuation at the observation point in the equivalent circuit model of PCB and the threshold value which is the power supply noise condition. It is a comparison waveform of the voltage fluctuation at the observation point in the equivalent circuit model of PCB and the threshold value which is the power supply noise condition. 10 is a flowchart showing a processing procedure of a low noise design method disclosed in Patent Document 1. 10 is a configuration diagram of a semiconductor device model creation device disclosed in Patent Document 2. FIG. FIG. 10 is a circuit diagram of a power supply model described in Patent Document 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input device 2 Power supply noise characteristic derivation means 3 Power supply noise condition determination means 4 Judgment reference database 5 Internal capacity addition means 6 Mounted capacity condition determination means 7 Output device 8 Power supply noise equivalent circuit analysis means 9 Equivalent circuit model generation means 10 Calculation means 11 Capacitance model adding means 12 Chip size means 13 Storage device 14 LSI design information and LSI database 15 CAD data and parts database 21 PCB power layer and its electrical characteristics 22 PCB ground layer and its electrical characteristics 23 PCB insulating layer and its electrical characteristics Characteristic 24 PCB layer configuration and thickness information of each layer 25 Power supply metal wiring of PCB and its electrical characteristics 26 Wiring width information of power supply metal wiring of PCB 31 Operational part model in LSI equivalent circuit model 32 Admittance model 33 in LSI equivalent circuit model LSI Power distribution circuit model 34 in the equivalent circuit model First power supply terminal 35 in the LSI equivalent circuit model Second power supply terminal 36 in the LSI equivalent circuit model 37 Power supply circuit model 37 in which circuit blocks in the LSI equivalent circuit model are combined 37 LSI Operational part model 38 in the divided block of the equivalent circuit model 38 Admittance model 39 in the divided block of the LSI equivalent circuit model 39 Model 40 of the power distribution circuit in the divided block of the LSI equivalent circuit model LSI divided into circuit blocks Equivalent circuit model 51 PCB board (solid power supply structure)
52 LSI mounted on PCB (including package)
53 DC power supply connected to power supply wiring of PCB 54 Chip capacitor as a countermeasure component mounted on PCB
55 Observation point 61 on PCB 61 Equivalent circuit model 62 of PCB board part (solid power supply structure) Equivalent circuit model of LSI (including package) mounted on PCB 63 Equivalent circuit model of DC power supply connected to power supply wiring of PCB 64 Equivalent circuit model of chip capacitor, which is a countermeasure component mounted on PCB
65 Observation point 71 on equivalent circuit model Power supply voltage fluctuation waveform A
72 Power supply voltage fluctuation waveform B
73 Image of LSI chip size and mounting capacity condition 74 Capacitance cell 75 Image of LSI chip size and mounting capacity condition 81 PCB portion of embodiment (solid power supply structure)
82 LSI (including package) mounted on PCB of example
83 DC power supply connected to the power supply wiring of the PCB of the embodiment 84 Chip capacitor as a countermeasure component mounted on the PCB of the embodiment
85 Observation Point 91 on PCB of Example 91 Equivalent Circuit Model 92 of PCB Part (Power Supply Solid Structure) of Example PCB Equivalent Circuit Model of LSI (including Package) Mounted on PCB of Example 93 Example of PCB of Example Equivalent circuit model of DC power supply connected to power supply wiring 94 Equivalent circuit model of chip capacitor which is countermeasure component mounted on PCB of embodiment
95 Observation Point 96 on Equivalent Circuit Model of Example 96 Operating Part Model 97 in Equivalent Circuit Model of LSI (including Package) Mounted on PCB of Example Equivalent Circuit of LSI (including Package) Mounted on PCB of Example Admittance model 98 in model Model of power distribution circuit in equivalent circuit model of LSI (including package) mounted on PCB of embodiment 99 Model of package in equivalent circuit model of LSI (including package) mounted on PCB of embodiment 100 Capacitor cell model added to equivalent circuit model of LSI (including package) mounted on PCB of embodiment S1 Circuit design information input process S2 Power supply noise characteristic derivation process S3 Power supply noise characteristic comparison process S4 Power supply noise characteristic determination process S5 Internal capacity addition process S6 On-board capacity comparison process S7 Result output process S8 Equivalent circuit model generation process S9 Circuit analysis process S10 Capacity model addition process S11 Mounting capacity determination process S12 Chip size change process S13 Board information input process S14 Board equivalent circuit model generation process S15 LSI information input process S16 LSI equivalent circuit Model generation processing S17 Power supply system equivalent circuit model generation processing S18 Substrate structure information input processing S19 Solver processing S20 Component data input processing S21 Substrate circuit model generation processing S22 by model combination S22 LSI design information and LSI database input processing S23 Model generation processing S24 Admittance model generation processing S25 Power distribution circuit model generation processing S26 LSI equivalent circuit model generation processing by model combination S27 Internal capacitance model addition processing S28 Chip change processing S29 Chip configuration Information changing process S101 Output process to CAD data of determination result as alternative means of result output (S7) S102 LSI design information and output process to LSI database of determination result as alternative means of result output (S7) Substrate structure Input process from CAD data as an alternative means of information input (S18) S104 Input process from the parts database as an alternative means of input of component data (S20) S105 As an alternative means of input of LSI design information and LSI database (S21) LSI design information and LSI database input processing linked to CAD data S106 Board information linked to CAD data and component database data change processing S107 LSI design information linked to CAD data and LSI database data change processing S108 Chip configuration information Input and data change processing LSI design information and LSI database according to a further process

Claims (19)

A power supply circuit design support apparatus for supporting the design of a power supply circuit so that the power supply circuit on a printed wiring board including at least a semiconductor integrated circuit and passive components operates stably against noise,
Input means for inputting predetermined input information of a printed wiring board, a semiconductor integrated circuit, and a passive component constituting the power supply circuit;
Power supply noise characteristic deriving means for deriving a power supply noise characteristic that is a noise characteristic of the power supply circuit based on the input information input by the input means;
A criterion database for storing acceptable conditions of power supply noise characteristics in the power supply circuit and storing acceptable conditions of internal capacitance values that can be added to the semiconductor integrated circuit;
The power supply noise characteristic derived by the power supply noise characteristic deriving means is compared with the permissible conditions of the power supply noise characteristic obtained from the determination reference database, and the power supply noise characteristic of the power supply circuit satisfies a predetermined condition Power noise judgment means for judging whether or not
In the power supply noise determination means, if the condition is not satisfied, a change is made to add a capacity inside the semiconductor integrated circuit, and an internal capacity addition means for inputting the changed information to the power supply noise characteristic deriving means;
The value of the internal capacitance added by the internal capacitance adding means is compared with the allowable condition of the internal capacitance value that can be added to the semiconductor integrated circuit obtained from the judgment reference database, and the necessary value for the semiconductor integrated circuit is compared. Mounting capacity condition judgment means for judging whether or not an internal capacity value can be added;
A power supply circuit design support device characterized by comprising: The power supply noise characteristic deriving means includes:
Equivalent circuit model generation means for generating an equivalent circuit model of the power supply circuit from the input information;
The power supply circuit design support apparatus according to claim 1, further comprising an arithmetic unit that analyzes the equivalent circuit model and derives a power supply noise characteristic. The equivalent circuit model generation means includes:
Board equivalent circuit model generation means for generating an equivalent circuit model of the printed wiring board based on at least predetermined input information about the printed wiring board;
LSI equivalent circuit model generation means for generating an equivalent circuit model of the semiconductor integrated circuit based on predetermined input information regarding the semiconductor integrated circuit;
The power supply circuit design support apparatus according to claim 2, comprising:   4. The internal capacitance adding means is configured to add an equivalent circuit model of a capacity cell actually added inside the semiconductor integrated circuit to the equivalent circuit model of the semiconductor integrated circuit. The power supply circuit design support apparatus described.   4. The power circuit design support apparatus according to claim 3, wherein the board equivalent circuit model generation means is configured to couple the equivalent circuit model of the passive component to the equivalent circuit model of the printed wiring board. .   6. The power supply circuit design according to claim 3, wherein the board equivalent circuit model generation means includes a field solver that creates an equivalent circuit model based on the physical structure of the power supply wiring and the electrical characteristic information. Support device.   A chip size changing unit for changing the chip size of the semiconductor integrated circuit and inputting the changed information to the power supply noise characteristic deriving unit when the mounting capacity condition determining unit determines that the condition is not satisfied; The power supply circuit design support apparatus according to claim 1, comprising: a power supply circuit design support apparatus according to claim 1;   The power supply circuit design support apparatus according to claim 1, wherein the input information is stored in a storage device. A power supply circuit design support method for supporting the design of a power supply circuit so that the power supply circuit on a printed wiring board including at least a semiconductor integrated circuit and passive components operates stably against noise,
Input predetermined input information of a printed wiring board, a semiconductor integrated circuit and a passive component constituting the power supply circuit,
Based on the input information that is input, a power supply noise characteristic that is a noise characteristic of the power supply circuit is derived,
Comparing the derived power supply noise characteristic and the allowable condition of the power supply noise characteristic of the power supply circuit to determine whether the power supply noise characteristic of the power supply circuit satisfies a predetermined condition,
In the determination, if the condition is not satisfied, a capacitor is added inside the semiconductor integrated circuit,
Based on the information changed with the addition of the capacity, again derive at least the power supply noise characteristic, and determine whether the power supply noise characteristic satisfies a predetermined condition,
Further, the value of the added internal capacitance is compared with an allowable condition of the internal capacitance value that can be added to the semiconductor integrated circuit to determine whether the internal capacitance value necessary for the semiconductor integrated circuit can be added. A power circuit design support method characterized by the above. In order to derive the power supply noise characteristic,
Generating an equivalent circuit model of the power supply circuit from the input information;
The power circuit design support method according to claim 9, wherein the power circuit noise characteristic is derived by analyzing the equivalent circuit model. In order to generate the equivalent circuit model,
Generating an equivalent circuit model of the printed circuit board based on at least predetermined input information about the printed circuit board, and further generating an equivalent circuit model of the semiconductor integrated circuit based on predetermined input information about the semiconductor integrated circuit The power supply circuit design support method according to claim 10. When adding the internal capacity,
12. The power supply circuit design support method according to claim 11, wherein an equivalent circuit model of a capacity cell actually added inside the semiconductor integrated circuit is added to the equivalent circuit model of the semiconductor integrated circuit.   12. The power circuit design support method according to claim 11, wherein when generating the board equivalent circuit model, the equivalent circuit model of the passive component is coupled to the equivalent circuit model of the printed wiring board. When a capacitor is added inside the semiconductor integrated circuit and the internal capacitance value necessary for the semiconductor integrated circuit cannot be added,
Change the chip size of the semiconductor integrated circuit,
The power supply noise characteristic is derived again based on the information changed with the change of the chip size, and it is determined whether or not the power supply noise characteristic satisfies a predetermined condition. A power circuit design support method according to any one of claims 13 to 13. A computer program for supporting the design of a power supply circuit that supports the design of the power supply circuit so that the power supply circuit on the printed circuit board including at least the semiconductor integrated circuit and the passive component operates stably against noise,
The storage device of the computer stores the allowable condition of the power supply noise characteristic of the power supply circuit, and stores the allowable condition of the internal capacitance value that can be added to the semiconductor integrated circuit,
The computer
Input means for inputting predetermined input information of a printed wiring board, a semiconductor integrated circuit, and a passive component constituting the power supply circuit;
Power supply noise characteristic deriving means for deriving a power supply noise characteristic that is a noise characteristic of the power supply circuit based on the input information input by the input means;
The power supply noise characteristic derived by the power supply noise characteristic deriving means is compared with the allowable condition of the power supply noise characteristic of the power supply circuit stored in the storage device, and the power supply noise characteristic of the power supply circuit satisfies a predetermined condition. Power supply noise judgment means for judging whether or not it satisfies,
In the power supply noise determination unit, if the condition is not satisfied, the power source noise determination unit functions as an internal capacitance addition unit that adds a capacitance inside the semiconductor integrated circuit
Based on the information changed with the addition of the capacity by the internal capacity adding means, again derive at least the power supply noise characteristic, determine whether the power supply noise characteristic satisfies a predetermined condition, and further The value of the internal capacity added by the capacity adding means is compared with the allowable conditions of the internal capacity value that can be added to the semiconductor integrated circuit stored in the storage device, and the internal capacity value required by the semiconductor integrated circuit is determined. A computer program that functions as an on-board capacity condition determination unit that determines whether or not an addition is possible. The power supply noise characteristic deriving means includes:
Generating an equivalent circuit model of the power supply circuit from the input information;
16. The computer program according to claim 15, wherein the equivalent circuit model is analyzed to derive a power supply noise characteristic. In order to generate the equivalent circuit model,
Generating an equivalent circuit model of the printed circuit board based on at least predetermined input information about the printed circuit board, and further generating an equivalent circuit model of the semiconductor integrated circuit based on predetermined input information about the semiconductor integrated circuit The computer program according to claim 16. The internal capacity adding means is:
18. The computer program according to claim 17, wherein an equivalent circuit model of a capacity cell actually added inside the semiconductor integrated circuit is added to the equivalent circuit model of the semiconductor integrated circuit. When a capacitor is added inside the semiconductor integrated circuit and the internal capacitance value necessary for the semiconductor integrated circuit cannot be added,
Change the chip size of the semiconductor integrated circuit,
Based on the information changed with the change of the chip size, at least the power supply noise characteristic is derived again, and it is determined whether the power supply noise characteristic satisfies a predetermined condition, A computer program according to any one of claims 15 to 18.

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