JP2009182659A - Timing synchronizing method, synchronization device, synchronization system, and synchronization program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a timing synchronizing method capable of achieving accurate synchronization by simple structure and process even in a high-speed communication network; a synchronization device; a synchronization system; and a synchronization program. <P>SOLUTION: This timing synchronization device connected to a communication network includes: a sampling pulse oscillation circuit 300 oscillating reference timing; a latch register A33 holding the reference timing; a latch register B34 holding received timing of a synchronizing frame received via the communication network; a deviation value calculation part 331 calculating a deviation value between the reference timing and the reception timing; and a reference timing compensation part 333 compensating the reference timing of the sampling pulse oscillation circuit 300 based on the deviation value. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a timing synchronization method, a synchronization device, a synchronization system, and a synchronization program for synchronizing and tuning timing between devices in a device that transmits and receives information via a communication network, for example.

  Various devices connected to the communication network may need to synchronize their managed times in order to make their operations coincide with each other at a desired timing. Such time synchronization is generally performed by a master station having a reference time transmitting a time synchronization frame carrying time information based on the reference time via a communication network, and a slave station receiving the time synchronization frame. This is realized by synchronizing the time of the slave station with the time of the master station based on the time information in the time synchronization frame.

However, a delay time occurs in transmission / reception of information via the communication network. There are the following types of delay times.
[Software execution delay time (transmission processing)]
The software execution delay time in the transmission process is a delay time that occurs until the time synchronization frame generated by the software is transmitted from the device to the communication line. The delay time fluctuates depending on the operation frequency of other processes and the priority of the time synchronization process.

[Transmission delay time]
The transmission path delay time is a signal relay time of a relay (signal amplification) device installed on the communication line at regular intervals. Network devices such as repeaters, bridges, and routers correspond to relay devices. The repeater has a constant relay time, but the bridge and router perform buffering in accordance with the frame priority in the apparatus, so that fluctuations in delay time occur.

[Software execution delay time (reception processing)]
The software execution delay time in the reception process is a delay time that occurs from when the time synchronization frame arrives at the device until it is actually captured and processed by software. By making the frame capture process by software interrupt driven, the variation in delay time can be reduced. In the case of a processing configuration in which the presence / absence of a frame arrival is implemented by polling, the delay time can be reduced by shortening the polling interval.

  In the transmission and reception of information via the communication network, the delay time and the fluctuation as described above occur. Therefore, accurate time synchronization can be realized only by acquiring the reference time from the time synchronization frame via the communication network. I can't. In order to cope with this, the following time synchronization methods have been proposed.

  For example, Non-Patent Document 1 describes NTP (Network Time Protocol), which is a representative technique of a time synchronization method in a communication network. NTP is a protocol that functions in the application layer of the OSI basic reference model. The application layer is located above the transport layer in which UDP (User Datagram Protocol) functions.

  This UDP is a protocol that improves the transfer efficiency by omitting delivery confirmation and the like like TCP, and the NTP generates a time information packet as a UDP packet and sends out the line. At this time, the delay time and fluctuation caused by the execution of software processing and the transmission path are measured, and the delay time and fluctuation are absorbed by a correction algorithm unique to NTP, thereby realizing highly accurate time synchronization.

Patent Document 1 describes an example in which a representative technique for sampling synchronization is applied to a current-operated relay system. This sampling synchronization method achieves high-precision synchronization by using the following methods (1) to (3), minimizing delay time fluctuations that occur in frame communication, and making it possible to acquire correction factors. is doing.
(1) Fixed frame transmission timing by hardware mechanism
(2) Stabilization of transmission line delay time by dedicated line
(3) Mechanism to acquire and latch (hold) frame reception timing

In the conventional time synchronization method as described above, the synchronization process can be performed while correcting the delay time and the fluctuation occurring in the communication process.
RFC (Request for Comments) 958: NTP (Network Time Protocol) Japanese Patent Laid-Open No. 2-155421

  By the way, when adopting NTP, in the local network, it is necessary to either install an NTP server in the system or connect to a global network so that an external NTP server can be accessed. However, the installation of an NTP server is disadvantageous in terms of cost, and in addition, there are many problems such as the need for recovery measures when the server is down. In addition, connecting to a global network leaves the possibility of information leaking to the outside, and there are security issues.

  In recent years, high-speed Ethernet with an increased communication speed of 100 Mbps has become widespread (Ethernet is a registered trademark and corresponds to IEEE 802.3). Even in such a communication system using high-speed Ethernet, in order to realize highly accurate synchronization control between devices, it is necessary to measure and acquire fluctuations in delay time and suppress this.

  However, in such high-speed Ethernet, a general-purpose network LSI (NIC: Network Interface Controller) element is generally adopted as an interface for communication hardware. For this reason, there is no special mechanism for stabilizing the transmission timing and measuring the delay time, unlike the sampling synchronization method of the current differential relay described above.

  In order to cope with this, in conventional devices, synchronization control processing and frame transmission / reception processing are performed as highest priority tasks and interrupt processing, with the objective of minimizing the execution delay time of large software processing, particularly as a fluctuation factor. It was implemented. However, there are cases where devices with complex functions have multiple interrupt processing, or control / monitoring processing that is the original function of the device must be preferentially operated. It was difficult to execute with the highest priority.

  Recently, Gigabit Ethernet with a communication speed increased to 1 Gbps has been developed. In such gigabit Ethernet, when continuous reception frames occur, software processing by CUP cannot follow, and there is a difference between the time when the time synchronization frame actually arrives at the device and the time when the time synchronization frame is processed. End up.

  The reason why the software processing by the CPU cannot follow when reception frames are continuously generated will be described in detail below. First, FIG. 23 shows a functional block diagram of a general network control circuit. This network control circuit has a configuration in which a CPU 101 that executes software processing, a transmission buffer memory 102, a reception buffer memory 103, a NIC (Network Interface Controller) 107, and a connector (RJ45) 106 are connected.

  In frame transmission control by the network control circuit, the CPU 101 writes transmission frame data to the transmission buffer memory 102 and then gives a transmission command to the NIC 107. Then, the NIC 107 extracts transmission frame data from the transmission buffer memory 102, performs frame generation and analog conversion processing by the MAC layer control circuit 104 and the physical layer control circuit 105 inside the NIC 107, and then transmits a transmission frame from the connector 106. Sent.

  In frame reception control, a received frame received via the connector 106 is taken into the NIC 107 and subjected to digital conversion and data extraction processing, and then the received frame data is stored in an empty area of the reception buffer memory 103. Written. When the CPU 101 confirms the change in the empty area of the reception buffer memory, the CPU 101 extracts the reception frame data from the reception buffer memory.

  As the buffer memories 102 and 103 for both transmission and reception, a ring method or a descriptor method is adopted. As shown in FIG. 24, the ring method has a buffer memory structure composed of a buffer index 201 and a buffer body 202. The buffer body 202 has a relatively large capacity so that data for a plurality of frames can be stored.

  The buffer index 201 has a function of a pointer that points to the head of the empty area of the buffer main body 202. This pointer indicates that transmission frame data can be written in an area after the buffer index 201 in the transmission buffer memory 102, and indicates the end of the latest reception frame data in the reception buffer memory 103.

  As shown in FIG. 25, the descriptor method has a buffer memory structure composed of a plurality of buffer descriptors 211 to 214 and buffer bodies 215 to 218 corresponding thereto. Since the buffer bodies 215 to 218 store only one frame of data per one, the capacity of one buffer body is the maximum length of one frame.

  In the buffer descriptors 211 to 214, as shown in FIG. 26, the use / unused status of the buffer bodies 215 to 218 is stored as a flag, and in the transmission control, the empty buffer bodies 215 to 218 can be searched. In the reception control, it is possible to search for unprocessed received frame data.

  Note that whether to select the ring method or the descriptor method is determined by the size of the communication frame, the physical capacity of the transmission buffer memory 102 and the reception buffer memory 103, and there is no particular advantage between the two. .

  With the configuration of the network control circuit as described above, continuous transmission / reception of a plurality of frames is possible. However, in reality, a delay occurs due to dragging to the slower of the CPU operating speed (software processing speed) or the communication line speed.

  That is, when the CPU operating speed is faster than the communication line speed, the transmission control causes the transmission frame data to be stored more frequently in the transmission buffer memory, and the CPU writes the data to the transmission buffer memory and transmits it to the NIC. The difference between the commanded timing and the actual transmission timing is increased. In this case, in the reception control, the difference between the frame arrival timing and the frame processing timing by the CPU is small.

  On the other hand, when the communication speed is faster than the operation speed of the CPU, the reception control frequently increases the reception frame data in the reception buffer memory, and the timing at which the reception frame arrives and the CPU receives the reception frame data. Difference from the timing at which the process is taken out from the reception buffer memory and the process is executed.

  Recently, both the CPU operating speed and the communication speed are higher than the conventional one, but there is a remarkable increase in the communication speed. In addition, there are few situations where the CPU can be bundled only with communication processing due to the multi-functionality of one CPU and the provision of multiple communication channels. If anything, the communication speed is higher than the operation speed of the CPU. It is easy to fall under the case of fast. Therefore, the number of cases where the CPU cannot follow the continuous frame reception tends to increase.

  Furthermore, since the conventional time synchronization method is a method for obtaining the transmission delay time by reciprocating the frame, the communication load and the delay time increase due to the increase in the number of stations. Because of these factors, network systems using high-speed Ethernet could not achieve highly accurate time synchronization.

  The present invention has been proposed in order to solve the above-described problems of the prior art, and an object of the present invention is to realize high-precision synchronization with a simple configuration and processing even in a high-speed communication network. A timing synchronization method, a synchronization device, a synchronization system, and a synchronization program are provided.

  In order to achieve the above object, the present invention provides a timing synchronization method for synchronizing a reference timing by a timing synchronization apparatus that is connected to a communication network and includes a reference timing oscillation unit that oscillates a reference timing. It has the technical features.

  First, the timing synchronization apparatus includes a reference timing holding unit, a reception timing holding unit, a deviation value calculation unit, and a reference timing correction unit. The reference timing holding unit holds the reference timing, the reception timing holding unit holds the reception timing of the synchronization frame received via the communication network, and the deviation value calculation unit is held in the reference timing holding unit. Based on the received reference timing and the reception timing held in the reception timing holding unit, a deviation value that is a value related to the deviation of the reference timing is calculated, and the reference timing correction unit performs the reference timing oscillation unit based on the deviation value. Correct the reference timing.

  In the present invention as described above, the reference timing is set based on a simple process of holding the reference timing and the reception timing of the synchronization frame and calculating a deviation value indicating the deviation between the held reference timing and the reception timing. By correcting, accurate time synchronization can be realized. In addition, by maintaining the reference timing and reception timing used for calculating the deviation value, it is possible to perform highly accurate synchronous control even in an operation at a low priority without being affected by software processing delay.

  According to the present invention as described above, it is possible to provide a timing synchronization method, a synchronization device, a synchronization system, and a synchronization program capable of realizing high-precision synchronization with a simple configuration and processing even in a high-speed communication network. .

Hereinafter, embodiments of a timing synchronization device, a synchronization system, and a synchronization method according to the present invention will be described with reference to FIGS. In addition, about the structure similar to the above-mentioned prior art, description is simplified.
[1. First Embodiment]
[1-1. Constitution]
[1-1-1. overall structure]
As shown in FIG. 1, the present embodiment includes a sampling pulse oscillation circuit 300, a general-purpose network control circuit 310, a frame transmission / reception timing control circuit 320, a CPU 330, a connector 340, and the like.

[1-1-2. Sampling pulse oscillation circuit]
The sampling pulse oscillation circuit 300 includes a clock oscillation circuit, and divides the oscillation clock to generate a reference pulse inside the device. The sampling pulse oscillation circuit 300 corresponds to a reference timing oscillation unit in claims, and uses a reference pulse as a reference timing.

[1-1-3. General-purpose network control circuit]
The general-purpose network control circuit 310 is a network control unit including a NIC 313, a transmission buffer memory 311, and a reception buffer memory 312, as in the above-described conventional technology. A typical example of the general-purpose network control circuit 310 is a network interface card for a personal computer, but the present invention is not limited to this.

[1-1-4. Frame transmission / reception timing control circuit]
The frame transmission / reception timing control circuit 320 includes physical layer control circuits 321, 322, a transmission frame holding buffer memory 323, a transmission timing control circuit 324, a reception frame type verification circuit 325, a counter counting circuit 332, a crystal oscillator 327, and the like. .

  The physical layer control circuit 321 is an interface for exchanging physical layer level signals with the general-purpose network control circuit 310. The physical layer control circuit 322 is an interface for exchanging physical layer level signals with a communication network (not shown).

  Note that most of the NIC 313 in the general-purpose network control circuit 310 is distributed as an element in which the MAC layer control circuit 314 and the physical layer control circuit 315 are integrated, and the interface after that is an analog-converted signal.

  However, in the frame transmission / reception timing control circuit 320, the signal needs to be digital in order to refer to the frame data to be communicated. For this reason, the physical layer control circuit 321 once digitizes the signal input from the general-purpose network control circuit 310, and also converts the signal output from the received frame type verification circuit 325 into an analog signal so that the general-purpose network control circuit 310 Output to.

  Further, the physical layer control circuit 322 converts the signal output via the connector 340 into an analog signal and digitizes the signal input via the connector 340. As described above, the physical layer control circuits 321 and 322 cooperate with each other in the form of signals exchanged between them.

  The connector 340 is an interface for performing a physical connection with a communication line for accessing the communication network. In this embodiment, for example, a standard 8-core modular RJ45 used in Ethernet is used, but the present invention is not limited to this.

  The transmission frame holding buffer memory 323 and the transmission timing control circuit 324 are frame transmission control means. The transmission frame holding buffer memory 323 is a means for holding the transmission frame for temporarily saving it. The transmission timing control circuit 324 is means for taking out a transmission frame from the transmission frame holding buffer memory 323 according to the reference timing oscillated from the sampling pulse oscillation circuit 300 and sending it to the physical layer control circuit 322.

  The reception frame type verification circuit 325 is a frame reception control unit, and is a unit that determines the type of a frame received via the physical layer control circuit 322. The determination of the frame type by the received frame type verification circuit 325 is performed by referring to a frame type field described later.

  As shown in FIG. 2, the counter counting circuit 326 counts the free-run counter 31 in response to external commands from the free-run counter 31, the sampling pulse oscillation circuit 300, and the reception frame type verification circuit 325 that are incremented by the clock of the crystal oscillator 327. A latch circuit 32 that holds (latches) a value, a latch register A33, a latch register B34, and the like are provided.

  The free-run counter 31 is a counter having a long circulation width (period) such as a 32-bit length or a 64-bit length. The latch circuit 32 is means for taking out the value of the free-run counter 31 at the timing when a latch command is issued from the sampling pulse oscillation circuit 300 or the reception frame type verification circuit 325. The latch circuit 32 also has a function of identifying the latch command source and distributing the latch register A33 and latch register B34 for storing the count value.

  The latch register A33 is a register that stores the value of the free-run counter 31 taken out by the latch circuit 32, that is, the timing of the rising edge of the sampling pulse when a latch command is issued from the sampling pulse oscillation circuit 300 (holding the reference timing). Part). The latch register B34 is a register that stores the value of the free-run counter 31 fetched by the latch circuit 32, that is, the reception timing of the synchronization frame when the latch command is issued from the reception frame type verification circuit 325 (reception timing holding). Part).

  As described above, the counter counting circuit 326 includes a plurality of latch registers A33 and B34, and can allocate the latch registers A33 and B34 to be stored according to the type of latch command (external signal) to be generated.

[1-1-5. CPU]
The CPU 330 is an arithmetic circuit and functions as means for controlling the entire timing synchronization apparatus including software. The CPU 330 is connected to the general-purpose network control circuit 310, the counter counting circuit 326, and the sampling pulse oscillation circuit 300 by an internal bus. The CPU 330 functions as a deviation value calculation unit 331, a correction determination unit 332, and a reference timing correction unit 333 according to a predetermined program.

  The deviation value calculation unit 331 is means for calculating a deviation value between the reference timing and the reception timing of the synchronization frame. This shift value means a difference (shift) between the reception (incoming) timing of the synchronization frame and the reference timing, or a shift width described later. The correction determination unit 332 compares a threshold value set in a storage unit (not shown) such as a memory in advance with a deviation or a deviation width, and determines whether or not correction is necessary depending on whether or not the threshold value is exceeded. It is a means to determine.

  The reference timing correction unit 333 is means for correcting the reference timing based on the calculated deviation value. The correction of the reference timing is performed by the CPU 330 giving a predetermined frequency division value to the sampling pulse oscillation circuit 300 through the internal bus and adjusting the pulse width.

[1-2. Action]
The operation of the present embodiment having the above configuration will be described with reference to FIGS. Here, as shown in FIG. 3, assuming that the master station M and the slave station S each having a timing synchronization device are connected by 1: 1, the timing synchronization device of the slave station S has its own A case where the reference timing is corrected will be described.

[1-2-1. Frame configuration]
First, an example of a field configuration of a frame transmitted and received between timing synchronization apparatuses is as shown in FIG. 4, and details thereof are as follows. Note that dst_mac, src_mac, ether_type, and FCS conform to the Ethernet frame format.

dst_mac: Destination station MAC address src_mac: Source station MAC address ether_type: Ethernet frame type Deviation value: Deviation (difference) or gap between synchronization frame arrival timing and reference timing Inter-device contact information: Arbitrary contact information FCS: Frame Check sequence code

  The MAC address (Media Access Control address) is a unique physical address for identifying hardware constituting each node on the network. The destination station MAC address is the MAC address of the destination station, and the source station MAC address is the MAC address of the source station.

Further, ether_type is a type field indicating the frame type, and generally a code indicating the type of the upper layer protocol of the Ethernet layer is inserted. The codes corresponding to typical protocols are as follows.
IPV4 (Internet Protocol version 4): 0800
ARP (Address Resolution Protocol): 0806
SNMP (Simple Network Management Protocol): 814C
NetBIOS (Network Basic Input Output System): 8191

  However, in the case of the synchronization frame of this embodiment, codes other than these reserved codes (for example, A001) are used. As a result, the received frame type verification circuit 325 can distinguish the synchronization frame from other frames. When the deviation value is not calculated, a blank or a value indicating that the deviation value is not calculated is inserted into the field corresponding to the deviation value of the synchronization frame.

[1-2-2. Operation during frame transmission]
Next, the operation at the time of frame transmission will be described with reference to the flowchart of FIG. The transmission frame data generated by the CPU 330 (step 501) is stored in the transmission buffer memory 311 in the generation order (step 502). Thereafter, the CPU 330 issues a transmission command to the NIC 313 to start a frame transmission operation by internal processing of the NIC 313 (step 503).

  Inside the NIC 313, the MAC layer control circuit 314 generates a transmission frame corresponding to the communication network based on the transmission frame data (step 504). The physical layer control circuit 315 converts the transmission frame into an analog signal (step 505) and sends it to the frame transmission / reception timing control circuit 320 (step 506).

  In the frame transmission / reception timing control circuit 320, the physical layer control circuit 321 generates a transmission frame obtained by digitizing an analog signal (step 507). The generated transmission frame is accumulated in the transmission frame holding buffer memory 323 (step 508).

  The transmission timing control circuit 324 extracts and transmits the transmission frame stored in the transmission frame holding buffer memory 323. This timing is performed in accordance with detection of a state change of the external input signal. In the present embodiment, the sampling pulse signal generated by the sampling pulse oscillation circuit 300 is used as the external input signal (step 509). As a result, the transmission frame can be transmitted in synchronization with the reference timing of the device (step 510).

  Further, the physical layer control circuit 322 converts the transmission frame into an analog signal again (step 511), and transmits the analog signal to the communication line via the connector 340 (step 512).

[1-2-3. Operation when receiving a frame]
Next, the operation at the time of frame reception will be described with reference to the flowchart of FIG. The physical layer control circuit 322 generates a reception frame obtained by converting the analog signal received via the connector 340 (step 601) into a digital signal (step 602), and passes it to the reception frame type verification circuit 325.

  The received frame type verification circuit 325 refers to the frame type (ether_type) in the frame configuration shown in FIG. 4 and determines whether or not it is a synchronization frame (step 603). If the frame is for synchronization (step 604), the received frame type verification circuit 325 outputs a latch command to the counter counting circuit 326 (step 605). The latch circuit 32 that has received the latch command causes the latch register B34 to hold the counter value at that timing (step 606).

  At the same time, the received frame type verification circuit 325 passes the received frame to the physical layer control circuit 321 via the internal bus. The physical layer control circuit 321 converts the received frame into an analog signal (step 607) and passes it to the general-purpose network control circuit 310.

  The physical layer control circuit 315 in the NIC 313 generates a reception frame obtained by digitizing an analog signal (step 608). The MAC layer control circuit 314 extracts received frame data from the received frame (step 609), and stores the received frame data in the reception buffer memory 312 (step 610). The stored reception frame data is appropriately extracted from the reception buffer memory 312 according to a read command from the CPU 330 (step 611) and subjected to software processing (step 612).

[1-2-4. Correction of reference timing]
Next, the procedure for correcting the reference timing will be described with reference to the flowchart of FIG. First, as described above, the latch command is input from the sampling pulse oscillation circuit 300 and the reception frame type verification circuit 325. That is, the sampling pulse oscillation circuit 300 issues a latch command at the rising edge of the sampling pulse (steps 701 and 702). Then, the latch circuit 32 in the counter counting circuit 326 stores the timing of the rising edge of the sampling pulse in the latch register A33 as the reference timing inside the device (step 703).

  When the received frame type verification circuit 325 detects a synchronization frame (step 704), it issues a latch command (step 705). Then, the latch circuit 32 stores the reception timing of the received synchronization frame in the latch register B34 (step 706).

  Based on the stored reference timing and synchronization frame reception timing, the deviation value calculation unit 331 calculates a deviation value (step 707). In this calculation, a difference (also referred to as elapsed time or deviation) between the reference timing and the synchronization frame reception timing is obtained, and a deviation width between the reference timing of the local station and the reference timing of the counterpart station is calculated based on the difference. By doing.

  FIG. 8 is a diagram illustrating an example of a difference (displacement) in the reference timing between the master station M and the slave station S. This deviation is due to the difference in the power-on timing of each station. This deviation also includes accumulation of errors caused by the accuracy characteristics of the crystal oscillator in the sampling pulse oscillation circuit 300.

FIG. 9 is a diagram illustrating an example of a case where the reference timings of the master station M and the slave station S are shifted. In this case, “pulse width + deviation” is the deviation width β of the master station M, and “pulse width−deviation” is the deviation width α of the slave station S.
Deviation width α ≠ deviation width β
It is.

On the other hand, FIG. 10 is a diagram illustrating an example of a case in which the reference timings of the master station M and the slave station S coincide with each other.
Deviation width α = Deviation width β
It becomes.

  In the present embodiment, since a high-speed network is assumed, FIG. 9 and FIG. 10 are represented assuming that the transmission line delay time is almost zero. However, even when there is a transmission line delay time, if the uplink / downlink delay time is equal and the delay time is smaller than the sampling pulse width, the considered deviation width α and deviation width β are the same. The following equation holds.

  Therefore, if the reference timing correction unit 333 adjusts the sampling pulse oscillation circuit 300 of the slave station S so that the deviation width α and the deviation width β match, the reference timing of the slave station S is changed to the reference timing of the master station M. Can be synchronized.

Here, FIG. 11 shows an example of correction by the reference timing correction unit 333 adjusting the sampling pulse width. The meanings of the reference width T and the correction width Ts in FIG. 11 are as follows.
Reference width T: the width of the sampling pulse, which is a time width generated by dividing the input clock by a fixed value. Since the master station M does not perform correction, the reference width is maintained.
Correction width Ts: a time width generated with a division value of −1 used for generating the reference width T.

  That is, when the synchronization is normal, the pulse width becomes the reference width T based on the fixed frequency division value. When the correction determination unit 332 determines that the deviation or deviation width of the reference timing between the master station M and the slave station S has exceeded a predetermined threshold (step 708), a correction operation is performed. Since the master station M is a reference, no correction operation is performed. It only determines whether the slave station S is synchronized normally.

  The correction operation is performed by distinguishing between advance correction and delay correction. When the own station (slave station) is moving forward as in the example of FIG. 9 (step 709), the forward correction is made (step 710). In the advance correction, the frequency division value is set to a fixed value −1, the sampling pulse width is shortened, and thereby the position of the reference timing of the own station is slid.

  If the own station is delayed (step 709), the delay is corrected (step 711). Delay correction is the reverse of lead correction, that is, the divided value is set to a fixed value +1, the sampling pulse width is increased, and the reference timing position of the own station is slid.

  9 and 10 is the deviation width measured by the master station M, and the deviation width α is the deviation width measured by the slave station S. In the communication frame configuration shown in FIG. 4, the deviation value (deviation or deviation width) calculated by each station is acquired by placing it on a synchronization frame and communicating with each other. At this time, if a plurality of synchronization frames are transmitted in the reference timing section, the value of the latch register B34 becomes the later received timing, and there is a concern that an accurate deviation value cannot be obtained.

  However, in the present embodiment, as shown in FIG. 1, the CPU 330 is configured to enter the reference timing. For this reason, it is possible to easily suppress the generation of a plurality of synchronization frames in the interval of the reference timing by performing a software process that generates a synchronization frame with the reference timing interposed at least once.

  Further, as shown in the frame configuration of FIG. 4, in addition to the deviation value, any contact information corresponding to the system can be placed in the synchronization frame. However, it is also possible to communicate using an arbitrary information frame with a different frame type from the synchronization frame. At that time, when the transmission frame data is stored in the transmission buffer memory 311 from the CPU 330 in the preceding stage of the information frame from the synchronization frame, the timing at which the synchronization frame is sent to the communication line is delayed by the accumulated frame size. There is a concern that an accurate gap width cannot be obtained.

  However, similar to the above, this can be easily dealt with by monitoring the occurrence of the reference timing by software processing. In other words, storage in the transmission buffer memory 311 is limited to one time within the reference timing interval, and in a cycle in which the synchronization frame is transmitted, the synchronization frame data is stored at the head of the transmission buffer memory 311 and the arbitrary information frame is thereafter stored. Data should be stored.

[1-3. effect]
According to the present embodiment as described above, a simple server or mechanism is not required, and the difference between the reference timing and the reception timing, the pulse deviation width generated thereby, is calculated, and the pulse width is adjusted. By processing, the reference timing can be corrected and synchronized accurately. In addition, by latching the timing value used for the calculation of the deviation width, highly accurate synchronous control can be realized even in the operation with low priority without being affected by the software processing delay of the CPU 330.

  The NTP is a method in which the master station M adds a reception time to the synchronization frame reception from the slave station S and returns the synchronization frame. However, in the present embodiment, the synchronization frame transmitted from the master station M and the synchronization frame transmitted from the slave station S do not require correlation and followability. The deviation values measured by both stations may be communicated (transmitted) in an arbitrary cycle according to the required synchronization accuracy. Connecting to a global network is not essential and there are no security issues.

  Further, in the present embodiment, as shown in the frame configuration of FIG. 1, the ether_type is implemented with a special code that does not overlap with the representative type code. As a result, other frames such as TCP / IP packets and ARP packets used for general information communication can be transmitted on the same network.

[2. Second Embodiment]
[2-1. Constitution]
A second embodiment of the present invention will be described with reference to FIGS. That is, this embodiment is basically the same as the first embodiment. However, as shown in FIG. 12, the difference is that time information is added to the synchronization frame used in the first embodiment. This time information indicates the time of the transmitting station. In the present embodiment, as shown in FIG. 13, the CPU 330 also functions as a time calculation unit 334 and a time correction unit 335 according to a predetermined program.

[2-2. Effect]
In the present embodiment as described above, when generating the synchronization frame in the master station M, the time information is put together with the deviation value. After confirming that the synchronization with the master station M has been established, the CPU 330 in the slave station S calculates the time based on the time information in the synchronization frame received from the master station M, and the time The correction unit 335 rewrites the time of the own station.

  As a result, the internal time of the device can be synchronized with high accuracy. This time information represents all the information that can be generated based on the reference timing. In addition to the standard time with date, the time information includes the absolute time on the system, the address value indicating the order of sampling pulses, and the counter value. Something like that.

  A procedure for obtaining a transmission delay time when a count value is used as a form of time information (time tag) will be described with reference to FIG. The replacement from the count value to the standard time unit (hour minute second, millisecond, etc.) can be obtained by multiplying the count value by a preset conversion coefficient. The transmission / reception time tags of each synchronization frame are a to d.

First, the count differences z and z ′ obtained from the transmission / reception time tags a to d are as follows.
z = b-a
z ′ = d−c

The counter deviation widths y and y ′ are as follows.
y = z + x
y ′ = z′−x ′

Here, since the transmission delay time α = the transmission delay time α ′, and the counter update interval of the master station M and the slave station S is constant,
・ Counter step width x = x '
・ Counter deviation width y = y '
It becomes.

From the above
y = (b−a) + x or y = (d−c) −x
2y = (ba) + x + (dc) -x
2y = (ba) + (dc)
Therefore, the deviation width y of the counter is
y = ((ba) + (dc)) / 2
It becomes.

further,
Transmission delay time α = x × time conversion count n, and from the above,
x = y−z = ((ba) + (dc)) / 2− (ba)
Therefore, the transmission delay time α is
α = {((ba) + (dc)) / 2- (ba)} × n
It becomes.

[3. Third Embodiment]
A third embodiment of the present invention will be described with reference to FIGS. The present embodiment is premised on a configuration in which a plurality of slave stations S1 to Sx are provided with respect to the master station M as shown in the station configuration example of FIG. In such a case, it is necessary to measure a deviation value between the reception timing of the synchronization frame transmitted from each slave station S1 to Sx and the reference timing of the master station M, and notify the slave station S1 to Sx. .

  Therefore, in the present embodiment, as many latch registers B34 to x36 as the number of slaves can be notified as shown in FIG. 16, and deviation values b to x corresponding to each slave station S can be notified as shown in FIG. A frame configuration is required.

  That is, the counter counting circuit 326 shown in FIG. 16 is basically the same as that of the first embodiment shown in FIG. However, in the present embodiment, there are a plurality of latch registers B34 to x36 in which the reception timing of the synchronization frame is stored at the time of a latch command from the reception frame type verification circuit 325. Which latch register B34 to x36 is stored depends on the frame type in the synchronization frame. Note that the latch circuit 32 assigns a register for identifying the latch command source and storing the count value.

The frame configuration of FIG. 17 is characterized by the following points compared to the synchronization frame used in the first embodiment.
dst_mac: Destination station MAC address
Transmission from master station M = all slave stations S can receive
Multicast address
Transmission from slave station S = only master station M can receive
Multicast or unicast address

In addition, since the reception timing is latched by ether_type (frame type), the master station S and each slave station M have different codes. The following is a code example.
Master station M = A000
Slave station S1 = B001
Slave station S2 = B002
Slave station Sx = B00x

  Note that each slave station S1 to Sx only needs to obtain a reference timing shift value between its own station and the master station M, and therefore can process with only one latch register B34 as shown in FIG. Therefore, the frame type to be determined may be only the transmission frame type of the master station M.

  Also, the frame type of the synchronization frame transmitted from each slave station S1 to Sx needs to be distinguished from the other slave stations S1 to Sx, and as an example, it is distributed to B001, B002, and B00x. This may be considered equivalent to a general station address.

  On the other hand, since the master station M needs to separately identify the reception timing of the synchronization frame transmitted from each of the slave stations S1 to Sx and measure the deviation value, as shown in FIG. The latch registers B34 to x36 corresponding to the number of slave stations S1 to Sx are required.

  When the master station M processes the received synchronization frame, the master station M refers to the latch registers B34 to x36 corresponding to the source slave stations S1 to Sx (= frame types B001 to B00x) and obtains a deviation value. Can do.

  As shown in FIG. 17, the deviation value obtained in this way is stored in the deviation widths b to x in the synchronization frame and multicasted to notify the slave stations S1 to Sx of the deviation value. Can do. Each time the number of slave stations increases, the master station M increases the number of synchronization frames received. However, the master station M aggregates a plurality of deviation values into one synchronization frame and multicasts it to all the slave stations S1 to Sx. There is no increase in the number of transmission frames.

  According to the present embodiment as described above, since sampling synchronization and time synchronization with a plurality of slave stations S1 to Sx can be performed in one frame, it can be realized with a minimum communication load. In addition, since the synchronization correction of each of the slave stations S1 to Sx is independent, the synchronization can be established in the required time that is the same as the 1: 1 communication even when the number of slave stations increases or decreases.

[4. Fourth Embodiment]
A fourth embodiment of the present invention will be described with reference to FIGS. That is, in the present embodiment, as shown in FIG. 18, the CPU 330 in each of the slave stations S1 to Sx monitors whether or not the synchronization frame from the master station M can be normally received (FIG. 19). And a switching unit 337 for switching to the proxy master when an abnormality occurs (FIG. 20).

  For example, the monitoring unit 336 previously sets a value such as n times the regular reception interval in a storage unit such as a memory, and detects a reception timeout based on a comparison between the set value and an unreceivable time. , The master station M is considered to be abnormal. At this time, any one switching unit 337 among the slave stations S1 to Sx switches to the proxy master and maintains the synchronization of the devices.

  The switching to the proxy master by the switching unit 337, for example, gives priority to which slave station S1 to Sx to switch to by adding the station address value of the slave station S1 to Sx as a coefficient to the reception timeout time. It is possible to have it.

  In the third embodiment, only one latch register B34 for holding the reception timing is required for the slave station S. However, in this embodiment, since switching to the proxy master M 'is performed, each slave station S also requires the same number of latch registers B34 to x36 for holding reception timing as the master station M.

  According to the present embodiment as described above, in a 1: n type station configuration in which a plurality of slave stations S1 to Sx are connected to the master station M, even if the master station M is down, the slave station S1 ~ Sx can be a proxy master station to maintain the synchronization of a healthy device connected to the communication network. For this reason, even if the master station M goes down due to a failure or the like, the master station M does not self-run with the accuracy of only its own crystal oscillator 327, and the reference timings of the slave stations S1 to Sx may shift over time. Absent.

[5. Fifth Embodiment]
A fifth embodiment of the present invention will be described with reference to FIG. That is, in this embodiment, as shown in FIG. 21, the connection configuration of the communication network is changed from master station M → submaster station (slave station having the same function as the master station) SM → slave stations S1 to Sx, master station M → Sub master station (slave station having the same function as the master station) SM ′ → Slave stations S1 ′ to Sx ′ are connected in a hierarchical structure, and the number of slave stations connected to one master station M is set to a fixed number. It is the one that has been suppressed.

  In the present embodiment as described above, when synchronization with the master station M is established, the sub-master station SM performs synchronization frame communication with the slave stations S1 to Sx while maintaining synchronization. Thereby, establishment and maintenance of synchronization between the sub master station SM and the slave stations S1 to Sx are realized. The same applies to the sub master station SM 'and the slave stations S1' to Sx '.

  The number of slave stations S that can be connected to the master station M can be roughly determined from the communication speed and the frame length. For example, when transferring a 64-byte synchronization frame at a communication speed of 100 Mbps, the communication time takes about 5 microseconds. If five slave stations S transmit synchronously, the transit delay time by the relay device is a maximum of 20 microseconds. Seconds (minimum is zero delay).

  When the number of bytes of the synchronization frame is doubled, the passing delay is also doubled, and when the communication speed is 10 times, the passing delay is 1/10. Since this delay time becomes a synchronization error, the number of connected slave stations may be determined according to the synchronization accuracy.

  According to the present embodiment as described above, the communication structure of the master station M is reduced by the hierarchical structure in which the sub-master stations SM, SM ′, etc. are interposed in the 1: n type station configuration, and the communication is performed. The limit on the number of stations that can be connected on the network can be expanded, and all stations can be synchronized with high accuracy. Thereby, the present invention can be applied even on a large-scale network system.

  Therefore, even when the reference timings of a large number of slave stations S are synchronized and the frame transmission timings for synchronization overlap, a delay in passage caused by an increase or fluctuation in buffering time due to a repeater or router is prevented. Thus, accurate synchronization control can be maintained.

[6. Other Embodiments]
The present invention is not limited to the embodiment as described above. For example, in the above-described embodiment, the sampling pulse width of the slave station S is set as the correction width Ts, and the operation is finely corrected for each sampling. However, since the “deviation” that is the difference has been acquired, it is possible to match the next sampling pulse as a reference width T-deviation in one shot.

  In the above-described embodiment, the `` deviation '' that is a simple difference and the `` deviation width '' that considers the relationship between the pulse width are distinguished and used, but the deviation value in the claims is any value related to deviation, In other words, this is a wide concept including both the above-described “deviation” and “deviation width”. In the present invention, the reference timing is corrected based on the “deviation” (for example, the above-described one-time adjustment). included.

  Further, when the reference timing cannot be changed rapidly, there is a method in which the sampling pulse width next to the correction width Ts is returned to the reference width T, and after several sampling pulse times have elapsed, the correction width Ts is set again. . As described above, the correction operation requires an operation suitable for the processing performed at the reference timing and its cycle, and various methods can be considered. Therefore, in the present invention, the method and method of the correction operation are not limited. .

  Further, it is the data link layer (equivalent to driver interface processing) that generates an Ethernet frame (generation / addition of an Ethernet header and FCS). Including the software processing of the data link layer (including the MAC sublayer and the LLC sublayer), if it is within the program design range, it is easy to add a type value to be written to ether_type.

  However, there are cases where special codes cannot be incorporated into ether_type due to the software configuration of communication processing. For example, when a general packaged TCP / IP interface process is used as a software configuration, it is difficult to operate the data link layer. There is also a one-chip network LSI with a built-in protocol stack such as TCP / IP. In this case, the software interface is only for user data exchange, and all data link layer operations are performed inside the LSI. It cannot be accessed from the software.

  In order to cope with this, UDP / IP frame communication can be used as a synchronization frame. For example, as shown in FIG. 22, the frame type, the gap width, and the inter-device communication information are stored in the user data part of the UDP packet, and the determination position by the received frame type verification circuit 325 is determined by the ether_type of the Ethernet header and the UDP packet. What is necessary is just to set it as two places of the frame classification of a user data part. Note that TCP / IP packets are difficult to apply to synchronization frames because of delays and retransmissions in the course of protocol processing.

  Various circuits for realizing the timing synchronization device and the synchronization method are conceivable, such as an IC chip such as an ASIC or a CPU that realizes these functions, other peripheral circuits, a system LSI that integrates a plurality of functions, and the like. It is a thing and is not limited to a specific thing. The scope of hardware processing and software processing is also free.

  In addition, the present invention can also be realized by controlling a general-purpose computer such as a personal computer or a server device with a program. The program in this case realizes the function of each unit in the present embodiment by physically utilizing computer hardware, such as a hard disk, a CD-ROM, a DVD-ROM, etc. These various recording media are each an embodiment of the present invention. Therefore, for example, the present invention can be configured by installing an application program in a computer.

  Further, any wired or wireless transmission path or transmission medium can be applied to the communication network, and it does not matter what LAN or WAN is used. Any communication protocol that can be used at present or in the future can be applied.

Functional block diagram showing the configuration of the first embodiment of the present invention Functional block diagram showing the counter counting circuit of FIG. Connection diagram of master station and slave station in the first embodiment of the present invention Synchronization frame configuration diagram in the embodiment of FIG. The flowchart which shows the procedure of the frame transmission process in embodiment of FIG. The flowchart which shows the procedure of the frame reception process in embodiment of FIG. The flowchart which shows the procedure of the correction process of the reference timing in embodiment of FIG. Diagram showing the difference (difference) in the reference timing between the master station and slave station A diagram showing the case where the difference width of the reference timing differs between the master station and slave station A diagram showing the case where the reference timing gap between the master station and slave station matches. The figure which shows the example of correction of the reference timing of the slave station Synchronization frame configuration diagram according to the second embodiment of the present invention Functional block diagram of the CPU in the second embodiment of the present invention The figure explaining calculation of the transmission delay time in the 2nd Embodiment of this invention. Connection diagram of master station and multiple slave stations in the third embodiment of the present invention Functional block diagram showing a counter counting circuit in a third embodiment of the present invention Synchronization frame configuration diagram according to the third embodiment of the present invention Functional block diagram of CPU in the fourth embodiment of the present invention Connection diagram of master station and slave station at normal time in the fourth embodiment of the present invention Connection diagram of master station and slave station at the time of failure in the fourth embodiment of the present invention Connection diagram of hierarchical master station and slave station in the fifth embodiment of the present invention Synchronization frame configuration diagram in another embodiment of the present invention Functional block diagram showing a typical network control circuit Diagram showing ring type buffer memory configuration Diagram showing descriptor type buffer memory configuration The figure which shows the example of storage frame data of FIG.

Explanation of symbols

31 ... Free-run counter 32 ... Latch circuit 33 ... Latch register A
34 ... Latch register B
35 ... Latch register C
36 ... Latch register x
DESCRIPTION OF SYMBOLS 102 ... Transmission buffer memory 103 ... Reception buffer memory 106, 340 ... Connector 201 ... Buffer index 211-214 ... Buffer descriptor 202, 215-218 ... Buffer main body 300 ... Sampling pulse oscillation circuit 310 ... General-purpose network control circuit 311 ... Transmission buffer memory 312 ... Reception buffer memory 314 ... MAC layer control circuit 315 ... Physical layer control circuit 320 ... Frame transmission / reception timing control circuits 321 and 322 ... Physical layer control circuit 323 ... Transmission frame hold buffer memory 324 ... Transmission timing control circuit 325 ... Reception frame type Test circuit 326 ... counter counting circuit 327 ... crystal oscillator 331 ... deviation value calculation unit 332 ... correction determination unit 333 ... reference timing correction unit 334 ... time calculation unit 335 ... time correction 336 ... monitoring unit 337 ... switching unit

Claims (11)

In a timing synchronization method in which a reference timing is synchronized by a timing synchronization device that is connected to a communication network and includes a reference timing oscillation unit that oscillates a reference timing.
The timing synchronization device includes a reference timing holding unit, a reception timing holding unit, a deviation value calculation unit, and a reference timing correction unit,
The reference timing holding unit holds the reference timing;
The reception timing holding unit holds the reception timing of the synchronization frame received via the communication network;
The deviation value calculation unit calculates a deviation value that is a value related to a deviation of the reference timing based on the reference timing held in the reference timing holding unit and the reception timing held in the reception timing holding unit,
The timing synchronization method, wherein the reference timing correction unit corrects a reference timing by the reference timing oscillation unit based on the deviation value. In the timing synchronizer connected to the communication network,
A reference timing oscillator for oscillating a reference timing;
A reference timing holding unit for holding the reference timing;
A reception timing holding unit that holds the reception timing of the synchronization frame received via the communication network;
A deviation value calculation unit that calculates a deviation value that is a value related to a deviation of the reference timing based on the reference timing held in the reference timing holding unit and the reception timing held in the reception timing holding unit;
A timing synchronization device comprising:   The timing synchronization apparatus according to claim 2, further comprising a network control unit that generates and transmits a synchronization frame including the shift value.   The timing synchronization apparatus according to claim 3, further comprising a transmission timing control unit that controls transmission timing of the synchronization frame based on the reference timing.   5. The timing synchronization device according to claim 2, further comprising a reference timing correction unit that corrects a reference timing of the reference timing oscillation unit based on the deviation value. 6.   A correction determination unit that determines whether or not correction based on the reference timing is necessary based on a shift value included in a synchronization frame received via a communication network and a shift value calculated by the shift value calculation unit; The timing synchronizer according to claim 2, wherein: A time calculation unit for calculating the internal time based on the reference timing;
A time correction unit for correcting the internal time based on time information included in the synchronization frame;
The timing synchronizer according to claim 2, wherein the timing synchronizer is provided. A master station and a plurality of slave stations connected via a communication network each have the timing synchronization device according to any one of claims 2 to 7,
The timing synchronization system, wherein the master station performs multicast distribution of a synchronization frame to the slave station.   9. The timing synchronization system according to claim 8, further comprising a switching unit that switches the slave station to a master station.   The timing synchronization system according to claim 8 or 9, wherein a plurality of slave stations are connected via a sub-master station having a function equivalent to that of the master station. In a timing synchronization program that is connected to a communication network and causes a computer having a reference timing oscillation unit that oscillates a reference timing to execute synchronization of the reference timing,
In the computer,
Holding the reference timing;
Hold the reception timing of the synchronization frame received via the communication network,
Calculating a deviation value which is a value relating to a deviation between the reference timing and the reception timing;
A timing synchronization program for correcting a reference timing by the reference timing oscillator based on the deviation value.

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