JP2009152391A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor devices, generating a strain in a channel without being accompanied by increase of the process cost much. <P>SOLUTION: A gate pattern, in which a semiconductor film and a block film having a density higher than that of the semiconductor film are formed in this order on the surface of a part of the semiconductor substrate (a). Impurities for source and drain are injected to the surface layer part of the semiconductor substrate (b) using the gate pattern as a mask. An impurity for forming strain and different from the impurities for source and drain is injected into the semiconductor substrate using the gate pattern as a mask (c). The semiconductor substrate is heat-treated to recrystallize the region, into which the impurity for forming strain has been injected (d). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which strain is generated in a channel region and the semiconductor device.

  In a transistor capable of high-speed operation, a so-called high-end transistor, an attempt has been made to improve the performance by applying strain to the silicon channel separately from device scaling. When strain is applied to silicon (Si), the structure of the Si energy band edge changes, and as a result, carrier mobility is improved. It is known that when an elongation strain is generated in the channel direction of the nMOS transistor, the mobility of electrons is improved, and when a contraction strain is generated in the channel direction of the pMOS transistor, the mobility of holes is improved.

  Non-Patent Document 1 below shows that the channel is biaxial by the method of epitaxially growing SiGe on a Si substrate (optimum for a pMOS transistor) or the method of epitaxially growing Si on a SiGe film with relaxed strain (optimum for an nMOS transistor). A technique for causing distortion is disclosed. Non-Patent Document 2 discloses a technique for generating strain in a channel by embedding SiGe in the source and drain regions of a pMOS transistor. Non-Patent Document 3 discloses a technique for generating strain in a channel by embedding SiC in the source and drain regions of an nMOS transistor.

  A method for embedding SiGe or SiC in the source and drain will be briefly described. After forming a sidewall spacer on the side surface of the gate electrode, the substrate surface is dug to form a recess. Filling is performed by selectively epitaxially growing SiGe or SiC in the recess.

F. Schaffler, Semicond. Sci. & Technol. 12, pp.1515 (1997) T. Ghani et al. IEDM Tech. Dig. Pp.978 (2003) K. W. Ang et al., IEDM Tech. Dig., Pp. 1069 (2004)

  Formation of a recess in the surface of the Si substrate and selective epitaxial growth of SiGe or SiC in the recess increase process costs. In particular, the selective growth of SiC is more difficult than the selective growth of SiGe and has not yet been put into practical use. Furthermore, it is difficult to form a metal silicide film such as NiSi on SiC at an appropriate temperature. For this reason, it is difficult to obtain good source and drain contacts.

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of generating distortion in a channel without significantly increasing the process cost. Another object of the present invention is to provide a semiconductor device capable of generating distortion in a channel and ensuring good source and drain contacts.

The manufacturing method of this semiconductor device is as follows:
(A) forming a gate pattern in which a semiconductor film and a block film having a higher density than the semiconductor film are stacked in this order on a part of the surface of the semiconductor substrate;
(B) implanting source and drain impurities into the surface layer of the semiconductor substrate using the gate pattern as a mask;
(C) implanting a strain forming impurity different from the source and drain impurities into the semiconductor substrate using the gate pattern as a mask;
(D) heat-treating the semiconductor substrate and recrystallizing the region into which the strain forming impurities are implanted.

This semiconductor device
A semiconductor substrate having a surface layer portion made of silicon;
A gate electrode formed on a partial region of the surface of the semiconductor substrate;
N-type source and drain regions formed in the surface layer portion of the semiconductor substrate on both sides of the gate electrode;
A metal silicide film formed on the surface of the source and drain regions;
A region made of SiC disposed under the metal silicide film,
Distortion occurs in the channel region under the gate electrode.

  By disposing the block film, it is possible to prevent excessive distortion forming impurities from being implanted into the semiconductor film in the gate pattern. By recrystallizing the region into which the strain forming impurity is implanted, strain can be generated in the channel region directly under the gate.

  With reference to FIGS. 1A to 1H, a method of manufacturing a semiconductor device according to the first embodiment will be described.

  An element isolation insulating film 11 is formed on the surface layer portion of the semiconductor substrate 10 made of silicon by a shallow trench isolation (STI) method. A p-type well 12 is formed by implanting p-type impurities into the surface layer portion of the active region 13 defined by the element isolation insulating film 11.

  A gate insulating film 15 made of silicon oxide containing nitrogen is formed by thermally oxidizing and nitriding the surface of the semiconductor substrate 10. A typical thickness of the gate insulating film 15 is 1 to 2 nm. Formation of the gate insulating film 15 and introduction of nitrogen are determined from the viewpoint of required performance and reliability of the MOS transistor. A high dielectric constant insulating material having a dielectric constant higher than that of silicon oxide or silicon nitride may be used for the gate insulating film 15. The gate insulating film 15 may be a laminated film made of these insulating materials.

  On the gate insulating film 15 and the element isolation insulating film 11, a gate silicon film 16a made of polycrystalline silicon and having a thickness of several tens of nm is deposited by chemical vapor deposition (CVD) or the like. The gate silicon film 16a may be formed of amorphous silicon.

  A barrier film 17a made of silicon nitride is deposited on the polysilicon film 16a for gate by CVD or the like. The thickness of the barrier film 17a is, for example, 5 nm. A block film 18a made of tungsten (W) is deposited on the barrier film 17a, for example, by sputtering. The barrier film 17a suppresses the reaction between Si in the gate polysilicon film 16a and W in the block film 18a. Furthermore, the barrier film 17a also has a role as an etching stopper when removing the block film 18a in a later process.

  The block film 18a, the barrier film 17a, and the gate polysilicon film 16a are patterned into the shape of the gate electrode.

  As shown in FIG. 1B, a gate pattern 19 including a silicon gate electrode 16, a barrier film 17, and a block film 18 is formed. Note that the gate insulating film 15 may be etched to expose the surface of the semiconductor substrate 10.

  Using the gate pattern 19 as a mask, an n-type impurity, for example, P or As, is implanted into the surface layer portion of the semiconductor substrate 10 on both sides thereof to form the source and drain extension portions 20.

  As shown in FIG. 1C, a first spacer 21 made of, for example, silicon oxide is formed on the side surface of the gate pattern 19. The thickness of the first spacer 21 is, for example, 5 nm. Using the gate pattern 19 and the first spacer 21 as a mask, an n-type impurity is implanted into the surface layer portion of the semiconductor substrate 10 on both sides thereof to form deep source and drain regions. By performing activation annealing, a source region 22S and a drain region 22D having extension portions are formed.

  As shown in FIG. 1D, a second spacer 25 made of silicon oxide is formed on the side surface of the first spacer 21. The total film thickness of the first spacer 21 and the second spacer 25 is, for example, 20 to 40 nm.

Cluster carbon is implanted into the semiconductor substrate 10 using the gate pattern 19, the first spacer 21, and the second spacer 25 as a mask. As the cluster carbon, for example, C ₇ H ₇ , C ₁₄ H ₁₄ , C ₁₆ H _{10 and the} like can be used. When C ₇ H ₇ is used as the cluster carbon, the acceleration energy is 5 to 70 keV (corresponding to 1 to 10 keV when C is injected), and the dose is 1 × 10 ¹⁴ to 2 × 10 ¹⁵ cm ⁻² (C only) Is equivalent to 7 × 10 ^{14 to} 7 × 10 ¹⁵ cm ⁻² in the case of injection. Typically, the acceleration energy is 35 keV, and the dose is 5 × 10 ¹⁴ cm ⁻² . When implantation is performed under these conditions, the implantation depth Rp is about 20 nm, and the standard deviation ΔRp is about 20 nm. The peak concentration is about 1 × 10 ²¹ cm ⁻³ .

The region into which cluster carbon has been implanted is made amorphous. By annealing after the implantation, the amorphous region is recrystallized. As a result, a strain generation region 27 made of SiC is formed. When the peak concentration of carbon is 1 × 10 ²¹ cm ⁻³ , SiC carbon is about 20 atomic% in a region corresponding to the peak concentration.

  For the formation of the strain generation region 27, recrystallization by solid phase growth may be used, or recrystallization by annealing at a high temperature for a short time may be used. When performing recrystallization by solid phase growth, annealing is performed at about 500 ° C. for about 6 hours, for example. When annealing at a high temperature for a short time, the annealing temperature is about 1050 ° C. and the annealing time is about 10 seconds. High-temperature short-time annealing can also serve as activation annealing of impurities implanted for forming the source and drain.

  In a low-temperature process using solid phase growth, end-of-range defects in which defects such as dislocations caused by ion implantation are clustered may remain. When it is required to suppress leakage current or the like due to end-of-range defects, it is preferable to employ high-temperature and short-time annealing.

  Since the lattice constant of SiC is smaller than the lattice constant of Si single crystal, elongation strain occurs in the strain generation region 27 made of SiC epitaxially grown from the Si single crystal region. As a result, an elongation strain in the in-plane direction is generated in the channel region immediately below the gate electrode 16.

  As shown in FIG. 1E, a protective film 30 made of silicon nitride is deposited on the entire surface of the substrate by CVD. The protective film 30 is subjected to chemical mechanical polishing (CMP) until the block film 18 is exposed. In this CMP process, the block film 18 made of W serves as a stopper. After the block film 18 is exposed, the block film 18 is removed using ammonia perwater or an alkaline solution.

  As shown in FIG. 1F, the barrier film 17 made of silicon nitride is exposed. Thereafter, the barrier film 17 and the protective film 30 made of silicon nitride are removed using phosphoric acid.

  As shown in FIG. 1G, the upper surfaces of the source region 22S, the drain region 22D, and the gate electrode 16 are exposed. As shown in FIG. 1H, metal silicide films 32S, 32D, and 32G are formed on the surfaces of the source region 22S, the drain region 22D, and the gate electrode 16 by a self-aligned silicide (salicide) process, respectively. Nickel silicide, cobalt silicide, or the like is used for the metal silicide films 32S, 32D, and 32G.

  Since the in-plane elongation strain is generated in the channel region, the carrier mobility of the nMOS transistor can be increased. The strain generation region 27 is implanted in a self-aligning manner using the block film 18 formed on the gate electrode 16 as a mask. Further, there is no need to form a recess for forming the strain generation region 27 or to perform selective epitaxial growth of SiC by CVD. For this reason, the manufacturing cost can be reduced.

  The block film 18 blocks the permeation of cluster carbon when cluster carbon is injected as shown in FIG. 1D. Thereby, it is possible to prevent carbon from being excessively injected into the gate electrode 16. In order to prevent cluster carbon permeation, it is preferable to use a material having a higher density (mass per unit volume) than the gate electrode 16 as the material of the block film 18. In particular, it is preferable to use a metal having a large mass number. Examples of metals that can be suitably used include Ta and Mo in addition to W used in the first embodiment. Further, oxides, nitrides, or carbides of these metals may be used.

  A suitable value for the thickness of the block film 18 is determined by the acceleration energy at the time of cluster carbon implantation. In general, in order to prevent excessive carbon injection into the gate electrode 16, the block film 18 is preferably set to 30 nm or more. If the block film 18 is too thick, the removal process becomes difficult. For this reason, it is preferable to set it as the thickness of 100 nm or less.

  In order to generate sufficient strain in the channel region, the carbon concentration of the strain generation region 27 is preferably 1 atomic% or more.

As the carbon concentration increases, it becomes difficult to form a metal silicide film. In order to form the metal silicide films 32S, 32D, and 32G shown in FIG. 1H with good reproducibility, the carbon concentration on the surface of the semiconductor substrate 10 is preferably 1 × 10 ²⁰ cm ⁻³ or less.

  In the first embodiment, an nMOS transistor is manufactured. However, when a pMOS transistor is manufactured, shrinkage strain may be generated in the strain generation region 27. For example, SiGe can be used for the strain generation region 27.

  It is preferable to select an impurity to be implanted for forming the strain generation region 27 so as not to have a great influence on the operation of the MOS transistor. For example, it is preferable to use an impurity that does not impart conductivity to the semiconductor substrate 10. Examples of such impurities include group IV elements such as C and Ge.

  It is also possible to form both an nMOS transistor and a pMOS transistor on a single substrate. In this case, only the nMOS transistor is formed by the method according to the first embodiment, and the pMOS transistor can be formed by adopting a conventional method using formation of recesses in the source and drain regions and selective growth of SiGe. Good.

  Next, with reference to FIGS. 2A to 2C, description will be made on a semiconductor device manufacturing method according to the second embodiment.

  The structure shown in FIG. 2A is the same as the structure shown in FIG. 1G, which is an intermediate stage of the manufacturing method according to the first embodiment. The steps so far are the same as those of the manufacturing method according to the first embodiment.

  As shown in FIG. 2B, an elevated source region 40S and an elevated drain region 40D are formed by selectively growing silicon on the source region 22S and the drain region 22D. At this time, silicon is deposited on the gate electrode 16 to form a gate upper silicon film 40G.

  As shown in FIG. 2C, metal silicide films 43S, 43D, and 43G are formed on the surfaces of the elevated source region 40S, the elevated drain region 40D, and the gate upper silicon film 40G, respectively.

  After the cluster carbon is injected to form the strain generation region 27, C may diffuse to the substrate surface by a thermal process, and the carbon concentration on the surface may increase. As the carbon concentration increases, it becomes difficult to form a metal silicide film. When the elevated source and drain structure is adopted, the carbon concentration of the surface of the silicon region where the metal silicide film is formed, that is, the elevated source region 40S and the elevated drain region 40D is not affected by the implantation of cluster carbon. For this reason, it can be avoided that the difficulty in forming the metal silicide films 43S, 43D, and 43G is increased.

  Next, with reference to FIG. 3A and FIG. 3B, the manufacturing method of the semiconductor device by the 3rd Example is demonstrated. The steps of forming the source region 22S and the drain region 22D shown in FIG. 1C of the manufacturing method according to the first embodiment are the same as those of the manufacturing method according to the third embodiment. In the third embodiment, the second spacer 25 shown in FIG. 1D is not formed.

  As shown in FIG. 3A, cluster carbon is implanted using the block film 18 and the first spacer 21 as a mask. Thereafter, the strain generation region 27 is formed by heat treatment. The cluster carbon injection conditions are the same as in the first embodiment.

  As shown in FIG. 3B, metal silicide films 32S, 32D, and 32G are formed on the surfaces of the source region 22S, the drain region 22D, and the gate electrode 16, respectively. The method for forming the metal silicide films 32S, 32D, and 32G is the same as that in the manufacturing method according to the first embodiment.

  In the third embodiment, since the second spacer 25 formed in the first embodiment is not formed, the strain generation region 27 approaches the channel region directly below the gate electrode 16. For this reason, a larger strain can be generated in the channel region. In the third embodiment, it is possible to adopt the elevated structure of the second embodiment.

  With reference to FIGS. 4A and 4B, a method for fabricating a semiconductor device according to the fourth embodiment will be described. Hereinafter, description will be made by paying attention to differences from the manufacturing method according to the first embodiment.

  As shown in FIG. 4A, after forming the gate insulating film 15, a gate metal film 50 a having a thickness of about 10 nm is deposited on the gate insulating film 15 and the element isolation insulating film 11. Further thereon, a gate silicon film 16a, a barrier film 17a, and a block film 18a having a thickness of several tens of nm are sequentially deposited. For example, TiN, TaC, TaN, HfN, or the like is used for the gate metal film 50a. The subsequent steps are the same as the steps from FIG. 1B to FIG. 1H of the first embodiment.

  As shown in FIG. 4B, a MOS transistor in which a metal gate electrode 50 is disposed on the gate insulating film 15 is obtained.

  Also in the fourth embodiment, since the block film 18 is disposed on the gate electrode 16, as in the first embodiment, excessive injection of carbon into the gate electrode 16 made of silicon is prevented. be able to. Therefore, the metal silicide film 32G can be easily formed on the surface of the gate electrode 16.

  In the fourth embodiment, the silicon gate electrode 16 is disposed on the metal gate electrode 50. However, the metal gate electrode 50 alone may constitute the gate electrode. When cluster carbon is implanted into the metal gate electrode 50, there is a concern that the work function varies. By preventing the cluster carbon from being injected by the block film 18, the work function of the metal gate electrode 50 can be prevented from changing.

  Also in the fourth embodiment, an elevated structure may be adopted as in the second embodiment, or the second spacer 25 may be omitted as in the third embodiment.

  With reference to FIGS. 5A to 5F, description will be made on a semiconductor device manufacturing method according to the fifth embodiment.

  The structure in the middle of manufacturing shown in FIG. 5A is basically the same as the structure shown in FIG. 1D of the first embodiment. However, in the fifth embodiment, a dummy gate insulating film 61 and a dummy gate electrode 62 are formed in place of the gate insulating film 15 and the gate electrode 16 shown in FIG. 1D of the first embodiment. The dummy gate insulating film 61 is made of silicon oxide, and the dummy gate electrode 62 is made of polysilicon or amorphous silicon. The dummy gate insulating film 61, the dummy gate electrode 62, the barrier film 17, and the block film 18 constitute a dummy gate structure 60.

  As shown in FIG. 5B, metal silicide films 32S and 32D are formed on the surfaces of the source region 22S and the drain region 22D. Since the block film 18 is exposed on the upper surface of the dummy gate structure 60, a metal silicide film is not formed.

  As shown in FIG. 5C, after an interlayer insulating film 65 made of silicon oxide or the like is deposited, CMP is performed until the block film 18 is exposed.

  As shown in FIG. 5D, the dummy gate structure 60 is removed. A recess 60A is formed in the region where the dummy gate structure 60 was formed. The semiconductor substrate 10 is exposed on the bottom surface of the recess 60A.

  As shown in FIG. 5E, a gate insulating film 67 made of silicon oxide containing nitrogen is formed by thermally oxidizing and thermally nitriding the surface layer portion of the semiconductor substrate 10 exposed on the bottom surface of the recess 60A.

  As shown in FIG. 5F, a metal gate electrode 68 is filled in the recess 60A. The metal gate electrode 68 is formed by depositing a metal film on the entire surface of the substrate and then performing CMP. For the metal gate electrode 68, for example, TiN, TaC, TaN, HfN or the like is used.

  In the fifth embodiment, as in the first embodiment, distortion can be generated in the channel region. When cluster carbon is injected into the dummy gate electrode 62, it becomes difficult to remove the dummy gate electrode 62 in the process shown in FIG. 5D. In the fifth embodiment, since the block film 18 suppresses the injection of cluster carbon into the dummy gate electrode 62, the dummy gate electrode 62 can be easily removed.

  A method for manufacturing a semiconductor device according to the sixth embodiment will be described with reference to FIGS. 6A to 6I.

  An insulating film 72 made of silicon oxide is disposed on a support substrate 71 made of semiconductor, and a semiconductor layer (element forming layer) 73 made of silicon is placed thereon. The three layers constitute an SOI substrate 70.

  On the element formation layer 73, the gate insulating film 15, the gate silicon film 16a, the barrier film 17a, and the block film 18a are formed in order. The method for forming these films is the same as in the first embodiment.

  As shown in FIG. 6B, the gate pattern 19 is formed by patterning the gate silicon film 16a, the barrier film 17a, and the block film 18a. Using the gate pattern 19 as a mask, an n-type impurity is implanted into the element formation layer 73 to form the source and drain extension portions 20.

  As shown in FIG. 6C, a first spacer 21 made of, for example, silicon oxide is formed on the side surface of the gate pattern 19.

  As shown in FIG. 6D, silicon is selectively epitaxially grown on the element formation layer 73 outside the first spacer 21. A source elevated film 75S is formed on one side of the gate pattern, and a drain elevated film 75D is formed on the other side. Deep regions of the source and drain are formed by implanting n-type impurities into the elevated films 75S and 75D and the element formation layer 73 therebelow.

  As shown in FIG. 6E, cluster carbon is implanted into the elevated films 75S and 75D and the element formation layer 73 using the block film 18 and the first spacer 21 as a mask. At this time, the implantation is performed under the condition that the cluster carbon does not reach the interface between the element formation layer 73 and the insulating film 72.

  Annealing is performed to recrystallize the region into which the cluster carbon has been implanted. Thereby, the strain generation region 27 made of SiC is formed. Since the cluster carbon does not reach the bottom surface of the element formation layer 73, a single crystal region of Si remains in a part below the element formation layer 73. Recrystallization is performed by epitaxial growth from this single crystal region.

  As shown in FIG. 6F, after depositing a protective film 80 made of silicon nitride, CMP is performed until the block film 18 is exposed. Thereafter, the exposed block film 18 is removed.

  As shown in FIG. 6G, the barrier film 17 disposed under the block film 18 is exposed. The exposed barrier film 17 and protective film 80 are removed.

  As shown in FIG. 6H, the silicon gate electrode 16 and the elevated films 75S and 75D are exposed.

  As shown in FIG. 6I, metal silicide films 78S, 78D, and 78G are formed on the exposed surfaces of the elevated films 75S and 75D and the gate electrode 16, respectively.

  Also in the sixth embodiment, by forming the strain generation region 27, strain can be generated in the channel region immediately below the gate electrode 16. In the step shown in FIG. 6E, the block film 18 prevents carbon from being injected into the silicon gate electrode 16. Therefore, the metal silicide film 78G can be easily formed on the upper surface of the silicon gate electrode 16.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  The following appendices are further disclosed with respect to the embodiments including the first to sixth examples.

(Appendix 1)
(A) forming a gate pattern in which a semiconductor film and a block film having a higher density than the semiconductor film are stacked in this order on a part of the surface of the semiconductor substrate;
(B) implanting source and drain impurities into the surface layer of the semiconductor substrate using the gate pattern as a mask;
(C) implanting a strain forming impurity different from the source and drain impurities into the semiconductor substrate using the gate pattern as a mask;
(D) a method of manufacturing a semiconductor device, including a step of heat-treating the semiconductor substrate and recrystallizing a region into which the strain forming impurity is implanted.

(Appendix 2)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the source and drain impurities are n-type impurities, and re-crystallization occurs in the step (d) to cause elongation strain in a channel region under the gate pattern. .

(Appendix 3)
The manufacturing method of a semiconductor device according to appendix 2, wherein at least a surface layer portion of the semiconductor substrate is made of silicon, and the strain forming impurity is carbon.

(Appendix 4)
In the steps (c) and (d), under the condition that a strain generating region made of SiC having a carbon concentration of 1 atomic% or more is formed in the semiconductor substrate, the strain forming impurities are implanted and heat-treated. The method for manufacturing a semiconductor device according to appendix 3, which is performed.

(Appendix 5)
In the steps (c) and (d), the implantation of the strain forming impurities under the condition that the carbon atom concentration on the surface of the semiconductor region containing silicon on both sides of the gate pattern is 1 × 10 ²⁰ cm ⁻³ or less, And manufacturing method of the semiconductor device according to attachment 3 or 4, wherein heat treatment is performed.

(Appendix 6)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the source and drain impurities are p-type impurities, and recrystallization occurs in the step (d), thereby causing elongation strain in a channel region under the gate pattern. .

(Appendix 7)
After the step (c), forming a protective film on the semiconductor substrate so as to cover the gate pattern;
Removing the protective film on the gate pattern and exposing the block film;
Removing the exposed block film and the protective film;
The method according to any one of appendices 1 to 6, further comprising: forming a metal silicide film on the exposed surface of the semiconductor substrate and the surface of the semiconductor film in the gate pattern after removing the protective film. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.

(Appendix 8)
The step (b)
Implanting impurities for source and drain extension portions into the surface layer portion of the semiconductor substrate using the gate pattern as a mask;
Forming a first spacer on a side surface of the gate pattern;
Implanting impurities for deep regions of the source and drain into the surface layer portion of the semiconductor substrate using the gate pattern and the first spacer as a mask,
The method of manufacturing a semiconductor device according to any one of appendices 1 to 4, wherein in the step (c), the strain forming impurity is implanted using the gate pattern and the first spacer as a mask.

(Appendix 9)
The step (c) further includes a step of forming a second spacer on a side surface of the first spacer, and using the gate pattern, the first spacer, and the second spacer as a mask, Item 9. The method for manufacturing a semiconductor device according to Appendix 8, wherein the impurity for forming the strain is implanted.

(Appendix 10)
After the step (d),
Depositing an interlayer insulating film on the semiconductor substrate and the gate pattern;
Removing the interlayer insulating film on the gate pattern to expose an upper surface of the gate pattern;
Removing the gate pattern;
Forming a gate insulating film on the surface of the semiconductor substrate in the region where the gate pattern is removed;
The method for manufacturing a semiconductor device according to any one of appendices 1 to 6, further comprising a step of filling a gate electrode in a recess formed by removing the gate pattern.

(Appendix 11)
The semiconductor substrate is
An SOI substrate in which an element formation layer made of a semiconductor containing silicon is formed on an insulating film,
After the step (b) and before the step (c),
Forming a first spacer on a side surface of the gate pattern;
A step of selectively growing an elevated film made of a semiconductor containing silicon on the element formation layer outside the first spacer,
Any one of Supplementary notes 1 to 9, wherein in the step (c), the strain forming impurity is implanted into the element formation layer and the elevated film using the gate pattern and the first spacer as a mask. The manufacturing method of the semiconductor device as described in 2.

(Appendix 12)
12. The method for manufacturing a semiconductor device according to claim 11, wherein in the step (c), the strain forming impurity is implanted under a condition that the strain forming impurity does not reach the bottom surface of the element forming layer.

(Appendix 13)
A semiconductor substrate having a surface layer portion made of silicon;
A gate electrode formed on a partial region of the surface of the semiconductor substrate;
N-type source and drain regions formed in the surface layer portion of the semiconductor substrate on both sides of the gate electrode;
A metal silicide film formed on the surface of the source and drain regions;
A region made of SiC disposed under the metal silicide film,
A semiconductor device extending in a channel region under the gate electrode and causing distortion.

It is sectional drawing (the 1) of the apparatus in the manufacture middle stage of the manufacturing method of the semiconductor device by a 1st Example. It is sectional drawing (the 2) of the apparatus in the manufacture middle stage of the manufacturing method of the semiconductor device by a 1st Example. It is sectional drawing (the 3) of the apparatus in the middle of manufacture of the manufacturing method of the semiconductor device by a 1st Example. It is sectional drawing of the apparatus in the manufacture middle stage of the manufacturing method of the semiconductor device by a 2nd Example. It is sectional drawing of the apparatus in the manufacture middle stage of the manufacturing method of the semiconductor device by 3rd Example. It is sectional drawing of the apparatus in the manufacture middle stage of the manufacturing method of the semiconductor device by a 4th Example. It is sectional drawing (the 1) of the apparatus in the manufacture middle stage of the manufacturing method of the semiconductor device by a 5th Example. It is sectional drawing (the 2) of the apparatus in the middle of manufacture of the manufacturing method of the semiconductor device by a 5th Example. It is sectional drawing (the 1) of the apparatus in the middle of manufacture of the manufacturing method of the semiconductor device by a 6th Example. It is sectional drawing (the 2) of the apparatus in the manufacture middle stage of the manufacturing method of the semiconductor device by a 6th Example. It is sectional drawing (the 3) of the apparatus in the middle of manufacture of the manufacturing method of the semiconductor device by a 6th Example.

Explanation of symbols

10 substrate 11 element isolation insulating film 12 p-type well 15 gate insulating film 16 gate electrode 17 barrier film 18 block film 19 gate pattern 21 first spacer 22S source region 22D drain region 25 second spacer 27 strain generation region 30 protective film 32S, 32D, 32G Metal silicide film 40S Elevated source region 40D Elevated drain region 40G Gate upper silicon film 43S, 43D, 43G Metal silicide film 50 Metal gate electrode 61 Dummy gate insulating film 62 Dummy gate electrode 65 Interlayer insulating film 67 Gate Insulating film 68 Metal gate electrode 70 SOI substrate 71 Support substrate 72 Insulating film 73 Element formation layers 75S, 75D Elevated film 80 Protective films 78S, 78D, 78G Metal silicide film

Claims (5)

(A) forming a gate pattern in which a semiconductor film and a block film having a higher density than the semiconductor film are stacked in this order on a part of the surface of the semiconductor substrate;
(B) implanting source and drain impurities into the surface layer of the semiconductor substrate using the gate pattern as a mask;
(C) implanting a strain forming impurity different from the source and drain impurities into the semiconductor substrate using the gate pattern as a mask;
(D) a method of manufacturing a semiconductor device, including a step of heat-treating the semiconductor substrate and recrystallizing a region into which the strain forming impurity is implanted.   The semiconductor device according to claim 1, wherein the source and drain impurities are n-type impurities, and recrystallization in the step (d) causes elongation strain in a channel region under the gate pattern. Method.   The method of manufacturing a semiconductor device according to claim 2, wherein at least a surface layer portion of the semiconductor substrate is formed of silicon, and the strain forming impurity is carbon.   In the steps (c) and (d), under the condition that a strain generating region made of SiC having a carbon concentration of 1 atomic% or more is formed in the semiconductor substrate, the strain forming impurities are implanted and heat-treated. The manufacturing method of the semiconductor device of Claim 3 to perform. A semiconductor substrate having a surface layer portion made of silicon;
A gate electrode formed on a partial region of the surface of the semiconductor substrate;
N-type source and drain regions formed in the surface layer portion of the semiconductor substrate on both sides of the gate electrode;
A metal silicide film formed on the surface of the source and drain regions;
A region made of SiC disposed under the metal silicide film,
A semiconductor device extending in a channel region under the gate electrode and causing distortion.

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