JP2009137004A - Microelectromechanical device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve mechanical strength of a microelectromechanical device (MEMS) having a movable part, and improve a yield ratio and reliability. <P>SOLUTION: In the microelectromechanical device (MEMS) having the movable part, a filling material is filled in a portion which is a hollow part in a conventional microelectromechanical device. An insulating material with elasticity is used for the filling material. For example, elastomer is used as an insulating material with elasticity. As the hollow part is filled, the mechanical strength is improved. Further, warpage of a structural body in a manufacturing process is prevented to improve the yield ratio. As the microelectromechanical device is manufactured in this way, reliability of the same is improved. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a micro electro mechanical device. The present invention also relates to a method for manufacturing the microelectromechanical device.

  In recent years, research on MEMS (Micro Electro Mechanical System) has been actively promoted. MEMS is an abbreviation for a microelectromechanical system, and is sometimes simply called a micromachine. A micromachine generally refers to a microdevice in which a “microstructure having a three-dimensional structure and moving” and an “electronic circuit having a semiconductor element” manufactured using a semiconductor microfabrication technique are integrated. Unlike the semiconductor element, the above micro structure generally has a movable portion.

The microstructure has a structural layer and a hollow portion, and the structural layer has a movable portion. Since the movable part of the structural layer operates, the above-described microstructure needs mechanical strength. In Patent Document 1, as an example of a microstructure having high mechanical strength, a layer including polycrystalline silicon that is thermally crystallized or laser-crystallized using a metal is provided, and a space is provided below or above the layer. There is disclosed a micromachine having
Japanese Patent Laid-Open No. 2007-1004

  The conventional microstructure has a hollow portion in order to secure an operation area of the movable portion. The formation of the hollow portion is performed by first forming a sacrificial layer at a location that becomes the hollow portion, and then removing the sacrificial layer by etching or the like after forming the structural layer or the like. For example, in a microstructure in which the movable portion of the structure layer operates in a direction perpendicular to the substrate surface, a lower portion of the microstructure is formed, a sacrificial layer is formed on the lower portion of the microstructure, and the sacrificial layer is formed on the sacrificial layer. The upper portion of the microstructure is formed, and the sacrificial layer is removed by etching or the like after the upper portion of the microstructure is formed. In this way, a microstructure having a hollow portion is manufactured.

  However, when the hollow portion is formed using the sacrificial layer as described above, the upper electrode of the microstructure and the lower electrode of the microstructure are in strong contact or the like during the manufacturing process, and are easily damaged. There is a problem. Further, there is a problem that normal operation cannot be performed due to sticking between the upper electrode and the lower electrode. Here, sticking refers to a phenomenon in which the upper electrode and the lower electrode are in strong contact with each other and cannot be separated by the operation of the movable portion of the microstructure.

  Furthermore, when the hollow portion is formed using the sacrificial layer, the sacrificial layer is not completely etched, resulting in a problem that etching remains.

  Alternatively, when the upper portion of the manufactured microstructure is operated, the microstructure may be damaged or destroyed. This is particularly remarkable when the height of the hollow portion is high or the toughness of the structural layer is not sufficient.

  Furthermore, there is a problem that by providing the hollow portion, the structure having the hollow portion is deformed by warpage or the like, and a desired structure cannot be obtained.

  In view of the above problems, a microstructure and a manufacturing method thereof in which the above problems are solved without complicating the manufacturing process are provided.

  One feature of the present invention is a microstructure in which a pair of opposed electrodes are isolated by a space and at least one electrode is provided in a movable structure, and the space is filled with an insulating material. It is a structure. As the insulating material, an elastic material is used so that the filling material layer formed of the insulating material can be deformed when the movable portion operates. Here, the material having elasticity refers to a material that can support the structural layer and has an elastic modulus that does not hinder the operation of the structural layer.

  One aspect of the present invention is a microelectromechanical device having a microstructure, the microstructure including a lower electrode layer provided on an insulating surface and a filling material layer provided on the lower electrode layer And an upper electrode layer facing the lower electrode provided on the filler material layer, and a structural layer provided on the upper electrode layer, and the structural layer is formed on the lower electrode layer. It is a micro electro mechanical device characterized in that it has a structure that can move in a direction toward or away from the lower electrode layer, and preferably the filling material layer has an insulating material having elasticity.

  Alternatively, one aspect of the present invention is a microelectromechanical device including a microstructure, and the microstructure includes a filler material layer provided over an insulating surface and an upper portion provided over the filler material layer. An electrode layer and a structure layer provided on the upper electrode layer, the structure layer having a structure movable in a thickness direction of the filler material layer, and the filler material layer has elasticity. A microelectromechanical device characterized by being an insulating material.

  In the microelectromechanical device having the above configuration, the insulating material is preferably an elastomer or a thermoplastic elastomer.

  According to another aspect of the present invention, a lower electrode layer is formed on an insulating surface, a first filling material layer made of an insulating material having elasticity is formed on the lower electrode layer, and the first filling material layer is formed. An upper electrode layer is formed on the upper electrode layer, and a structural layer is formed on the upper electrode layer.

  Alternatively, according to one aspect of the present invention, a lower electrode layer is formed on an insulating surface, a film made of an insulating material having elasticity is formed on the entire surface of the lower electrode layer, and the insulating material having elasticity is formed. A metal mask is selectively formed on the film, the elastic film is etched using the metal mask to form a filling material layer, an upper electrode layer is formed on the filling material layer, and the upper electrode A method for manufacturing a microelectromechanical device is characterized in that a structural layer is formed on a layer.

  And in the manufacturing method of the micro electro mechanical apparatus which has the said structure, it is preferable that the said insulating material is an elastomer or a thermoplastic elastomer. This is because it is easy to form a filling material layer having elasticity. Moreover, the process after formation can be performed favorably by using a thermoplastic elastomer. That is, it becomes easy to process into various shapes and process with high accuracy.

  Furthermore, the elastomer or the thermoplastic elastomer is preferably formed by dissolving in a solvent. This is because various preferred production methods such as a spin coating method can be applied by using a solvent.

  The elastomer or the thermoplastic elastomer is most preferably formed by a spin coating method. This is because, by using the spin coating method, the filling material layer can be formed without unevenness in the thickness and film quality.

  In this specification, the material having elasticity means a material that does not hinder the operation of the structural layer that is the movable part and that is elastically deformed without being plastically deformed by the operation of the structural layer that is the movable part. .

In this specification, an elastomer means an organic resin material having flexibility and impact resilience, and has a Young's modulus of about 1.0 × 10 ⁶ Pa to 1.0 × 10 ⁷ Pa. Say.

  In this specification, the thermoplastic elastomer refers to an elastomer that has flexibility and rebound resilience, etc. at room temperature, and can be molded by heating. Thermoplastic elastomers include urethane, styrene, vinyl or ester, but are not limited to specific materials.

  Note that as the material having elasticity, it is preferable to use a material that is softened or cured by performing a predetermined treatment (heat, chemical solution treatment, or the like) after formation. In particular, it is preferable to use a material that can be softened and cured reversibly by performing a predetermined treatment.

  Damage and destruction of the microstructure due to the operation of the upper portion of the microstructure can be prevented. Therefore, even when the height of the hollow portion is large or the toughness of the structural layer cannot be sufficiently ensured, the microstructure can be manufactured.

  A microstructure that can be repeatedly operated without sticking between the electrodes can be manufactured.

  In addition, since it is not necessary to form a sacrificial layer in the manufacturing process, a decrease in yield due to the remaining sacrificial layer can be prevented, and a microstructure can be manufactured with high yield.

  Furthermore, a microstructure can be manufactured without going through a complicated manufacturing process. In addition, the thickness of the filling material layer included in the microstructure can be made uniform.

  Embodiments will be described below with reference to the drawings. However, since it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention, only the description of the embodiments described below is applicable. It is not construed as limiting.

(Embodiment 1)
A microstructure and a method for manufacturing the microstructure will be described with reference to drawings.

  FIG. 1 illustrates an example of a cross-sectional view (FIG. 1A) and a top view (FIG. 1B) of a microstructure of the present invention. In the microstructure illustrated in FIG. 1, a lower electrode layer 101 is provided over a substrate 100, and a filler material layer 102 is provided over the lower electrode layer 101. An upper electrode layer 103 is provided on the filling material layer 102, and a structural layer 104 is provided on the upper electrode layer 103. The distance between the lower electrode layer 101 and the upper electrode layer 103 is d (m).

The lower electrode layer 101 and the upper electrode layer 103 are separated from each other by a filling material layer 102 to form a capacitor element. Here, assuming that the areas of the lower electrode and the upper electrode are equal S (m ² ), the capacitance of this capacitive element is C (F), and the dielectric constant is ε (F / m), the following equation ( 1) is established.

Here, when the structural layer 104 is pushed down, the distance d between the lower electrode layer 101 and the upper electrode layer 103 changes, and the capacitance changes. The capacitance change amount ΔC at this time is expressed by the following equation (2) when the capacitance C ₀ before being pushed down and the capacitance C ₁ after being pushed down are used.

That is, if the interval before being depressed is d ₀ and the interval after being depressed is d ₁ , ΔC is expressed by the following equation (3).

  Therefore, by detecting ΔC, the amount of change in the distance d between the lower electrode layer 101 and the upper electrode layer 103 becomes clear.

  FIG. 2 shows an example of a conventional microstructure. In the microstructure shown in FIG. 2, the portion where the filler material layer 102 is provided in the microstructure shown in FIG. 2A is a cross-sectional view, and FIG. 2B is a top view.

  Next, an example of a method for manufacturing the microstructure illustrated in FIG. 1 will be described with reference to the drawings. First, the lower electrode layer 101 is selectively formed over the substrate 100 (see FIG. 3A).

  The substrate 100 is not particularly limited, and for example, a semiconductor substrate, a glass substrate, a quartz substrate, a plastic substrate, a stainless steel substrate, or the like can be used, but an insulating substrate is preferably used. In the case of using a semiconductor substrate or a stainless steel substrate, it is preferable to form an insulating film on these substrates to provide an insulating surface.

  For the lower electrode layer 101, for example, a conductive film is formed on the substrate 100, a resist mask is formed on the conductive film by a photolithography method, and a desired portion of the conductive film is removed by etching or the like using the resist mask. By doing so, it can be formed selectively. The material for forming the lower electrode layer 101 is not particularly limited, and may be formed using a conductive material. As the conductive material, for example, an element selected from tantalum, tungsten, titanium, molybdenum, aluminum, and copper, or an alloy material or a compound material containing these elements as main components may be used. Alternatively, silicon to which an impurity element of one conductivity type is added may be used, or a transparent conductive film such as indium tin oxide (ITO) may be used. Note that there is no particular limitation on the formation method, and a sputtering method, a CVD method, a droplet discharge method, or the like can be used. When a droplet discharge method is used, a desired pattern can be formed without performing etching, so that the number of steps is reduced. Note that the lower electrode layer 101 may be a single layer or a stack of a plurality of layers.

  Next, the filler material layer 102 is formed over the lower electrode layer 101. Since the filling material layer 102 is preferably formed of an organic material, it is difficult to form a pattern by etching using a resist mask. Therefore, the case where a metal film is used as a mask will be described below.

  First, the organic film 120 is formed over the lower electrode layer 101, the metal film 121 is formed over the organic film 120, and the resist mask 122 is selectively formed over the metal film 121 (see FIG. 3B). . The organic film 120 is formed using a material for forming a filling material layer 102 described later. As a formation method, for example, a spin coating method or the like may be used.

  Next, the metal film 121 is etched using the resist mask 122 to form the metal mask 123 (see FIG. 3C). The etching of the metal film 121 may be set according to the material constituting the metal film. For example, when the material of the metal film 121 is tungsten, dry etching in a chlorine gas atmosphere can be used. It is preferable to apply a condition in which an etching selection ratio is obtained with respect to the resist mask 122 and the organic film 120 (that is, an etching rate with respect to the metal film 121 is high and an etching rate with respect to the organic film 120 and the resist mask 122 is low). Thereafter, the resist mask 122 is removed.

  Next, the organic film 120 is etched using the metal mask 123, whereby the filler material layer 102 is formed (see FIG. 3D). For the etching of the organic film 120, for example, dry etching may be performed using oxygen gas. Thereafter, the metal mask 123 is removed. Note that the metal mask 123 may be used as the upper electrode of the microstructure without being removed. In the case where the metal mask 123 is used as the upper electrode of the microstructure without being removed, the metal mask 123 may be processed into a desired shape by etching.

  In the above description, an example in which etching using a metal mask is applied to the formation of the filling material layer 102 is described, but the present invention is not necessarily limited thereto. For example, a pattern can be formed by mixing a photosensitive material in the organic film 120 and performing exposure.

  As described above, the filler material layer 102 can be selectively formed over the lower electrode layer 101 (see FIG. 3E). Since the filler material layer 102 is deformed in accordance with the operation of the microstructure, the filler material layer 102 is formed using a film of an insulating material having elasticity that can withstand this deformation. After the material film is formed, a desired portion can be selectively formed by etching and removing in the same manner as the lower electrode layer 101. Alternatively, it may be selectively formed by a droplet discharge method or the like.

  As a material for forming the filling material layer 102 of the present invention, an insulating material having elasticity is used. Preferably, a material that is softened or hardened by performing a predetermined treatment (heat, chemical solution treatment, or the like) after formation is used. Examples of such a material include an elastomer or a thermoplastic elastomer. It is preferable to use an elastomer or a thermoplastic elastomer because it is easy to form.

The elastomer refers to an organic resin material having flexibility and impact resilience, and has a Young's modulus of about 1.0 × 10 ⁶ Pa to 1.0 × 10 ⁷ Pa. Plastomer is a synonym for elastomer.

  Note that a polymer elastomer is preferably used as a material for forming the filler material layer 102. Polymer elastomers include polyurethane resin, ethylene-vinyl acetate resin, ethylene-ethyl acrylate resin, polyester resin, polyamide resin, butadiene rubber, butyl rubber, styrene butadiene rubber, nitrile rubber, isoprene rubber, chloroprene rubber, silicone rubber, etc. These synthetic rubbers, or a modification thereof, are not limited thereto. One or more kinds of these materials may be combined, or a plasticizer or the like may be added to adjust the elastic modulus.

  As a method for forming the polymer elastomer, for example, an impregnation method, a coating method, a screen method, a gravure method, a spray method or a droplet discharge method may be used. In the case of forming by these methods, it is necessary to solidify the elastomer after forming with a solution containing a polymer elastomer material as a solute. Therefore, the polymer elastomer used as the filler material layer is preferably a room temperature dry elastomer or a room temperature crosslinkable elastomer. This is because when a room temperature dry elastomer or a room temperature cross-linkable elastomer is used, a process for heating the elastomer (such as a heat treatment or a drying process) is unnecessary and the manufacturing process is simplified.

  In addition, room temperature drying type elastomers or room temperature cross-linking type elastomers are not only those that dry at room temperature or those that form crosslinking at room temperature, but those that dry at a temperature slightly higher than room temperature, or those that form a bridge at a temperature slightly higher than room temperature. Something to do is also included. Further, it is preferable to use a solvent having a boiling point slightly higher than room temperature rather than a solvent having a boiling point similar to that of room temperature. This is because if the boiling point is close to room temperature, boiling may occur during formation. For example, it is preferable to use benzene (boiling point: 80 ° C.) or chloroform (boiling point: 61 ° C.) rather than methylene chloride (boiling point: 40 ° C.) or acetone (boiling point: 56 ° C.). Furthermore, any solvent that can be evaporated by leaving it to stand for a certain time or longer can be used.

  Note that room temperature generally refers to a temperature range of approximately 15 ° C. to 25 ° C., but the present invention is not limited to this. As the room temperature dry elastomer or the room temperature cross-linkable elastomer, those that dry at about 0 ° C. or more and about 100 ° C. or less, or those that form a cross-link at about 0 ° C. or more and about 100 ° C. or less may be used. Of course, it is preferable that the drying or the formation of the cross-linking is at a low temperature within the above temperature range.

  As a method for forming the elastomer or thermoplastic elastomer used as the filler material layer 102, a spin coating method is most preferably used. This is because by using the spin coating method, the filling material layer 102 can be formed without unevenness in thickness and film quality. By increasing the uniformity of the thickness and film quality of the filler material layer 102, unevenness in the strength distribution of the filler material layer 102 can be prevented, which is preferable because yield and reliability are improved.

  The room temperature dry elastomer can be produced by dissolving a solid polymer elastomer in an organic solvent that volatilizes at room temperature. For example, solvent diluted urethane or solvent diluted acrylic may be used.

  The room temperature cross-linkable elastomer is a moisture curable type that absorbs moisture in the air and cures, or is cured by energy such as ultraviolet light (UV), electron beam (EB), or visible light (UV curable type, EB curable type or Visible light curing type) may be used. In the case of using a visible light curable type, it is only necessary to perform a predetermined treatment in a space where visible light is blocked and to be exposed to visible light only when the elastomer is cured. By using a visible light curable type, it is possible to form a filling material layer without irradiating an already formed layer with ultraviolet light or an electron beam. Is unnecessary and preferable. These can be produced without dissolving the elastomer in an organic solvent or the like, or dispersing the elastomer in water, or using a medium such as a solvent.

  When a polymer elastomer solid is dispersed in water and applied, it is difficult to form it uniformly. This is because solid ink has many hydrophobic components. Therefore, it is preferable to form the elastomer without dispersing it in water. As the room temperature crosslinking type, for example, a moisture-curing urethane resin or an ultraviolet-curing acrylic resin can be used. The room temperature dry elastomer and the room temperature cross-linked elastomer can be formed without particularly high temperature, and the filling material layer can be formed without altering the already formed layer.

  Moreover, since it is difficult to process an elastomer into a desired shape, a thermoplastic elastomer may be used. Use of a thermoplastic elastomer is preferable because molding becomes easy. That is, it is preferable because it becomes easy to process into various shapes and to process with high accuracy.

  The thermoplastic elastomer refers to an elastomer that has flexibility and rebound resilience, etc. at room temperature, and exhibits plasticity upon heating. Thermoplastic elastomers include urethane, styrene, vinyl or ester, but are not limited to specific materials. Alternatively, a material that develops plasticity by performing a predetermined treatment may be used.

  Next, the upper electrode layer 103 is formed over the filler material layer 102 (see FIG. 3F). The upper electrode (second electrode) is formed at a position facing the lower electrode (first electrode). The upper electrode layer 103 may be formed using the same material as that of the lower electrode layer 101 by the same method. That is, a conductive film may be formed over the entire surface and a desired portion may be removed by etching.

  Next, the structural layer 104 is selectively formed over the upper electrode layer 103 so as to cover the filler material layer 102 (see FIG. 3G). The structure layer 104 may be formed by forming a material film over the entire surface and removing a desired portion of the material film by etching, like the first electrode layer and the like.

  The material of the structural layer 104 is not limited to a specific material as long as the material has a certain degree of toughness. For example, a stacked structure in which a titanium film is stacked over an aluminum film and silicon oxynitride is formed over the titanium film can be used. Here, the aluminum film and the titanium film may be formed by a sputtering method, and the silicon oxynitride film may be formed by a CVD method or the like, but the formation method is not particularly limited.

  As described above, the microstructure of the present invention can be formed. Unlike the conventional microstructure, the microstructure of the present invention is filled with a deformable material in the hollow portion. Therefore, a microstructure having higher mechanical strength than a conventional microstructure having a hollow portion can be manufactured. By improving the mechanical strength, it is possible to prevent the occurrence of defects during the manufacturing process or operation, so that the yield is improved and the reliability is improved.

  Moreover, since the microstructure of the present invention does not have a hollow portion, it is not necessary to form a sacrificial layer. Accordingly, the step of forming the sacrificial layer and the step of removing the sacrificial layer are unnecessary, and the number of manufacturing steps can be reduced. Further, in the production of a conventional microstructure, when the sacrificial layer is not sufficiently removed by etching, the remaining sacrificial layer may reduce the yield. By applying the present invention, a decrease in yield due to the remaining sacrificial layer can be prevented, and the yield can be improved.

  Further, when the microstructure includes a strain gauge by the upper electrode layer 103 and the structural layer 104, the lower electrode layer 101 is not necessarily formed. The present invention can be applied not only to sensors but also to actuators.

  Alternatively, when a bimetal is applied to the structural layer 104, an actuator driven by the bimetal effect can be manufactured.

  By using such a microstructure, a mechanical sensor can be manufactured. For example, a pressure sensor can be produced by this mechanical sensor. In addition, an interference display or the like can be manufactured by using the actuator.

  In the above description, the side surface of the filling material layer is not tapered, but the present invention is not limited to this, and the side surface of the filling material layer may be tapered (FIG. 10A). See). In the microstructure illustrated in FIG. 10A, the lower electrode layer 131 is provided over the substrate 100, and the filler material layer 132 is provided over the lower electrode layer 131. An upper electrode layer 133 is provided on the filling material layer 132, and a structural layer 134 is provided on the upper electrode layer 133. The side surface of the filling material layer 132 is processed into a tapered shape. By making the side surface of the filling material layer 132 into a tapered shape, a structural layer or the like formed thereon can be formed with good coverage. Therefore, disconnection of wirings electrically connected to the lower electrode layer 131 and the upper electrode layer 133 of the microstructure can be prevented, and the yield in the manufacturing process is improved.

  Furthermore, the filling material layer of the present invention can be formed by a droplet discharge method (see FIG. 10B). 10B, the lower electrode layer 136 is provided over the substrate 100, and the filler material layer 137 is provided over the lower electrode layer 136. In the microstructure illustrated in FIG. An upper electrode layer 138 is provided on the filling material layer 137, and a structural layer 139 is provided on the upper electrode layer 138. The filling material layer 137 formed by a droplet discharge method is formed in a curved surface shape. That is, you may form so that the surface of a filling material layer may become a curved surface.

  As described above, the present invention is not limited to one embodiment, and can be applied to microstructures having various structures. By providing the filling material layer in the space that was a hollow portion in the conventional microstructure, damage and destruction of the microstructure due to the operation of the upper portion of the microstructure can be prevented. Therefore, even when the height of the hollow part is large or the toughness of the structural layer cannot be sufficiently secured, a microstructure having a high mechanical strength and high reliability and having a movable part is manufactured with high yield. Can do.

  In the microstructure, since the lower electrode and the upper electrode are not in contact with each other, sticking between the electrodes does not occur, and a microstructure that can be repeatedly operated can be manufactured.

  In addition, since it is not necessary to form a sacrificial layer in the manufacturing process of the microstructure of the present invention, it is possible to prevent the occurrence of defects due to the etching residue of the sacrificial layer and to manufacture the microstructure with a high yield.

  Furthermore, by using the method for manufacturing a microstructure according to the present invention, a microstructure can be manufactured without going through a complicated manufacturing process. In addition, the thickness of the filling material layer included in the microstructure can be made uniform.

  Note that this embodiment mode shows only the simplest example, and various modes can be employed depending on the function of the microstructure. In particular, the size or shape of the microstructure can be changed as appropriate by the practitioner.

  As described above, the microstructure of the present invention can be manufactured.

(Embodiment 2)
In this embodiment mode, a structural example of a semiconductor device of the present invention and a manufacturing method thereof will be described with reference to drawings.

  The semiconductor device of the present invention belongs to the field of micromachines, and generally has a size of micrometer to millimeter unit. Further, when manufactured to be incorporated as a part of a certain mechanical device, the semiconductor device may have a size of a metric unit so that it can be easily handled during assembly.

  FIG. 4 is a block diagram showing an example of the semiconductor device of the present invention. The semiconductor device 231 of the present invention includes an electric circuit portion 232 and a structure portion 233. The electric circuit portion 232 is provided using a semiconductor element, and includes a control circuit 234 that controls the structure portion 233 and an interface 235 that communicates with the external control device 230. In addition, the structure portion 233 includes a sensor 236, an actuator 237, a switch, and the like which are provided using a microstructure. The structure body 233 may include any one of a sensor, an actuator, and a switch.

  The electric circuit unit 232 may include a central processing unit for processing information obtained by the structure unit 233, a memory for storing the processed information, and the like.

  The external control device 230 performs an operation such as transmitting a signal for controlling the semiconductor device 231, receiving information obtained by the semiconductor device 231, or supplying driving power to the semiconductor device 231.

  In addition, this invention is not limited only to said structural example. In other words, the semiconductor device of the present invention only needs to include an electric circuit that controls the microstructure and the microstructure controlled by the electric circuit, and other structures are not limited to those in FIG.

  Next, a method for manufacturing a microstructure and a semiconductor element over the same substrate in order to manufacture the semiconductor device of the present invention described above will be described with reference to FIGS. Each drawing shows a top view and a cross-sectional view at OP of the top view.

  The microstructure and the semiconductor element of the present invention can be formed over a substrate having one insulating surface (hereinafter referred to as an insulating substrate). Here, examples of the insulating substrate include a glass substrate, a quartz substrate, and a plastic substrate. Furthermore, a conductive substrate such as metal or a substrate in which an insulating layer is formed on a semiconductor substrate such as silicon may be used. By forming a microstructure and a semiconductor element over one plastic substrate, a highly flexible and thin semiconductor device can be manufactured. In addition, a thin semiconductor device can be manufactured by thinning the glass substrate by polishing or the like.

  In the semiconductor device of the present invention, the microstructure has a filler material layer. The filler material layer is preferably formed of an elastomer as described in the first embodiment. However, since an elastomer often does not have heat resistance enough to withstand the manufacturing process of a thin film transistor, in this embodiment mode, a manufacturing method in which a thin film transistor is first formed over a substrate and then a microstructure is formed Will be described.

  First, the base film 202 is formed over the insulating substrate 201. The base film 202 is formed by a single layer or a stacked layer of insulating films such as a silicon oxide-based material film or a silicon nitride-based material film. Here, a case where an insulating film having a two-layer structure is formed as the base film 202 will be described. Note that the base film 202 is not necessarily provided if not particularly necessary.

  Note that a silicon oxide-based material refers to silicon oxide containing oxygen and silicon as main components or silicon oxynitride in which silicon oxide contains nitrogen and the oxygen content is higher than the nitrogen content. The silicon nitride-based material refers to silicon nitride containing nitrogen and silicon as main components, or silicon nitride oxide in which silicon nitride contains oxygen and the nitrogen content is higher than the oxygen content.

In this embodiment mode, the base film 202 has a two-layer structure. As the first layer of the base film 202, for example, a silicon nitride material film formed using SiH ₄ , NH ₃ , N ₂ O, and H ₂ as a reaction gas by a plasma CVD method has a thickness of 10 nm to 200 nm. The thickness is preferably 50 nm to 100 nm. Here, a silicon nitride oxide film with a thickness of 50 nm is formed. Next, a silicon oxide-based material film formed using SiH ₄ and N ₂ O as a reaction gas by a plasma CVD method as a second layer of the base film 202 on the first layer has a thickness of 50 nm to 200 nm. And preferably with a thickness of 100 nm to 150 nm. Here, a silicon oxynitride film with a thickness of 100 nm is formed.

  Next, a semiconductor film is formed over the base film 202 and etched into an arbitrary shape, so that the semiconductor layer 204 is obtained (see FIGS. 5A1 and 5A2). The semiconductor layer 204 can be formed of a material containing silicon as a main component. Examples of the material having silicon include a material made of silicon, or a silicon germanium material having about 0.01 to 4.5 atomic% of germanium.

  The semiconductor layer 204 can have a crystalline state or an amorphous state. Here, an amorphous semiconductor film is formed, and a crystalline semiconductor film which is crystallized by performing heat treatment on the amorphous semiconductor film is formed. For the heat treatment, heating by a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (hereinafter referred to as lamp annealing), or a combination thereof can be used.

In the case of using laser irradiation, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. As laser light, Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor Laser light oscillated from one or a plurality of lasers or gold vapor lasers can be used. By irradiating the fundamental wave of such laser light or the second to fourth harmonic laser light, a crystal having a large grain size can be obtained. For example, the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser beam at this time is 0.01 mW / cm ² or more 100 MW / cm ² degrees or less, preferably 0.1 MW / cm ² or more 10 MW / cm ² or less. The scanning speed is about 10 cm / sec or more and 2000 cm / sec or less.

  Note that continuous wave fundamental laser light and continuous wave harmonic laser light may be irradiated, or continuous wave fundamental laser light and pulsed harmonic laser light may be irradiated. Also good.

  Alternatively, a pulse oscillation type laser beam that is oscillated at a frequency at which the laser beam of the next pulse can be irradiated before the semiconductor layer is melted by the laser beam and solidified can be used. By oscillating laser light at such a frequency, crystal grains continuously grown in the scanning direction can be obtained. The specific oscillation frequency of the laser beam is 10 MHz or more. This is remarkably high as compared with a frequency band of several tens Hz to several hundreds Hz that is usually used.

  Alternatively, heat treatment may be performed by means other than laser irradiation. For example, heat treatment using a heating furnace can be performed. In the case of using a heating furnace, the amorphous semiconductor film is preferably heated at 400 ° C to 550 ° C for 2 hours to 20 hours. At this time, the temperature may be set in multiple stages in a range of 400 ° C. or higher and 550 ° C. or lower so that the temperature gradually increases. In the case of setting in multiple stages, by setting the temperature in the first stage to about 400 ° C., hydrogen contained in the amorphous semiconductor film is released, so that the film roughness during crystallization is reduced or the film Disappearance can be prevented. Furthermore, it is preferable to use a metal that promotes crystallization, such as nickel, because crystallization is possible by heating at a relatively low temperature. As a metal for promoting crystallization, not only nickel but also metals such as Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au can be used.

  Further, the amorphous semiconductor film may be crystallized by using a heat treatment with a heating furnace and a heat treatment with a laser in combination.

  Note that the metal that promotes crystallization serves as a contamination source of the semiconductor device, and thus is preferably removed or reduced after crystallization. In this case, after crystallization by heat treatment by a heating furnace or heat treatment by laser irradiation, a layer serving as a gettering sink is formed on the semiconductor layer and heated to move the metal to the gettering sink. Can be removed or reduced. As the gettering sink, a polycrystalline semiconductor film or a semiconductor film to which an impurity element is added can be used. For example, a polycrystalline semiconductor film to which an inert element such as argon is added can be formed over the semiconductor film, and this can be used as a gettering sink. By adding an inert element, the polycrystalline semiconductor film can be strained, and the metal can be effectively captured by the strain. In addition, metal can be captured by forming a semiconductor film to which an element such as phosphorus is added.

  The semiconductor layer 204 is not limited to an amorphous semiconductor film or a crystallized film thereof. For example, a semiconductor substrate on which a damaged layer is formed by doping of hydrogen ions or the like is attached to the insulating substrate 201 or an insulating substrate 201 on which an insulating film is formed, and is peeled off from the damaged layer. A single crystal semiconductor layer may be used. Note that an insulating film may also be provided on the surface to which the semiconductor substrate is bonded. Since the semiconductor layer formed in such a process has very good electrical characteristics (for example, high mobility), a high-performance semiconductor device using the microstructure of the present invention can be provided. . For example, power consumption is reduced. Furthermore, the area occupied by the electric circuit portion 232 in FIG. 4 can be reduced.

  Note that since the microstructure according to the present invention is of a variable capacitance type, it is necessary to detect a minute change in capacitance. Therefore, it is very effective to use a semiconductor with good crystallinity as the semiconductor layer.

  Next, a gate insulating film 206 is formed over the semiconductor layer 204 (see FIGS. 5A1 and 5A2). As with the base film 202, the gate insulating film 206 can be formed by a plasma CVD method, a sputtering method, or the like using a silicon oxide-based material, a silicon nitride-based material, or the like. In this embodiment, a silicon oxynitride film with a thickness of 110 nm is formed as the gate insulating film 206 by a plasma CVD method. Needless to say, the gate insulating film 206 is not limited to a silicon oxynitride film, and may be formed using a single layer or a stacked layer of insulating films containing other silicon.

The gate insulating film 206 can also be formed by high-density plasma treatment. Here, the high-density plasma treatment is a plasma density of 1 × 10 ¹¹ cm ⁻³ or more, preferably 1 × 10 ¹¹ cm ⁻³ or more and 9 × 10 ¹⁵ cm ⁻³ or less, and a microwave (for example, a frequency of 2.45 GHz). ) Or the like. When plasma is generated under such conditions, the low electron temperature becomes 0.2 eV or more and 2.0 eV or less. In this way, the high-density plasma with a low electron temperature has a low kinetic energy of active species, so that plasma damage is small and a film with few defects can be formed. As described above, an insulating film formed by high-density plasma treatment has a favorable interface state between the insulating film and a layer in contact with the insulating film. Therefore, when the gate insulating film 206 is formed using high-density plasma treatment, an interface state with the semiconductor layer 204 can be improved. As a result, the electrical characteristics of the semiconductor element can be improved.

  Furthermore, not only the gate insulating film 206 but also the base film 202 and other insulating films can be formed using high-density plasma treatment.

  Next, a conductive film to be the gate electrode layer 207 included in the semiconductor element is formed over the gate insulating film 206, and a conductive layer having a desired shape is obtained by etching or the like (see FIGS. 5B1 and 5B2). . The gate electrode layer 207 can be formed by a sputtering method, a CVD method, or the like using a conductive metal such as tungsten, a compound, or the like. Note that the gate electrode layer 207 may be formed by stacking two or more conductive materials. Further, the side surface may be etched into a tapered shape. Note that here, a tungsten film is formed as a single layer and used as a gate electrode layer.

A pattern for obtaining a desired shape is formed by forming a resist mask using a photolithography method and performing anisotropic dry etching. As an etching method, for example, an ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the insulating substrate 201 side, the temperature of the electrode on the insulating substrate 201 side, etc.) consider the thickness of the film to be etched, etc. And decide. Note that as the etching gas, a chlorine-based gas such as Cl ₂ , BCl ₃ , SiCl _4, or CCl ₄ , a fluorine-based gas such as CF ₄ , SF _6, or NF _3, or an O ₂ gas can be used.

  Next, an impurity element is added to a predetermined region of the semiconductor layer 204 to form a P-type impurity region 211 and an N-type impurity region 212 (see FIGS. 5C1 and 5C2). These impurity regions can be selectively formed by forming a resist mask by a photolithography method and adding an impurity element. As a method for adding the impurity element, an ion doping method or an ion implantation method can be applied. Typically, phosphorus (P) or arsenic (As) can be used as the impurity element imparting N-type, and boron (B) can be used as the impurity element imparting P-type.

  Next, an insulating film made of a silicon nitride material or a silicon oxide material is formed by a plasma CVD method or the like, and the insulating film is anisotropically etched in the vertical direction, so that the insulating layer in contact with the side surface of the gate electrode layer 207 is formed. (Hereinafter referred to as sidewall 209) is formed (see FIGS. 5C1 and 5C2).

  Next, an impurity element is further added to the semiconductor layer 204 having the N-type impurity region 212, and a high-concentration N-type impurity region 210 having an impurity concentration higher than that of the N-type impurity region 212 provided below the sidewall 209 is formed. Form.

  In the case where the gate electrode layer 207 is stacked using different conductive materials and the side surface is tapered, the sidewall 209 is not necessarily formed. This is because when the side surface of the gate electrode layer 207 is tapered, the N-type impurity region 212 and the high-concentration N-type impurity region 210 can be formed by adding the impurity element once.

  Note that by forming the high-concentration N-type impurity region 210 and the N-type impurity region 212 as described above, the thin film transistor can have an LDD (Lightly Doped Drain) structure. When the thin film transistor has an LDD structure, a short channel effect can be prevented. Since the short channel effect is more likely to occur as the size of the thin film transistor is smaller, the LDD structure is preferable as the size of the thin film transistor is decreased. Only the N-type semiconductor element may have an LDD structure.

  Next, after the impurity region is formed, heating or irradiation with infrared light or laser light is performed to activate the impurity element. In addition, plasma damage to the gate insulating film 206 or plasma damage to the interface between the gate insulating film 206 and the semiconductor layer 204 can be recovered simultaneously with activation. In particular, when an impurity element is activated by an excimer laser from the front surface or the back surface of the insulating substrate 201 in an atmosphere of room temperature to 300 ° C., the activation can be effectively performed. Alternatively, the second harmonic of the YAG laser may be irradiated and activated. A YAG laser is preferred as a laser irradiation means because of its low maintenance frequency.

  Alternatively, a passivation film made of an insulating material such as silicon oxynitride or silicon oxide may be formed so as to cover the conductive layer to be the gate electrode layer 207 and the semiconductor layer 204. Further, the film may be hydrogenated by heating after formation of the passivation film or irradiation with infrared light or laser light. For example, a silicon oxynitride film is formed to a thickness of 100 nm using a plasma CVD method, and then heated at 300 to 550 ° C. for 1 to 12 hours using a clean oven, whereby the semiconductor layer 204 is hydrogenated. It can be performed. For example, heating is performed at 410 ° C. for 1 hour in a nitrogen atmosphere using a clean oven. In this step, hydrogen can be included in the passivation film, and dangling bonds of the semiconductor layer 204 generated by addition of the impurity element can be terminated. At the same time, the activation process of the impurity region can be performed.

  Through the above steps, an N-type semiconductor element 213 and a P-type semiconductor element 214 which are thin film transistors are formed (see FIGS. 5C1 and 5C2).

  Subsequently, an interlayer insulating layer 215 is formed so as to cover the entire semiconductor element (see FIGS. 6A1 and 6A2). The interlayer insulating layer 215 can be formed using an insulating inorganic material, organic material, or the like. As the inorganic material, silicon oxide, silicon nitride, or the like can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane resin, or polysilazane can be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon and oxygen. As a substituent, an organic group (eg, an alkyl group or aromatic hydrocarbon) or a fluoro group may be used. Polysilazane is formed using a polymer material having a bond of silicon and nitrogen as a starting material.

  Note that in the case where the interlayer insulating layer 215 is formed using an inorganic material by a CVD method or the like, the interlayer insulating layer 215 is preferably planarized by a CMP (Chemical Mechanical Polishing) method or the like after the formation.

  Next, the interlayer insulating layer 215 and the gate insulating film 206 are sequentially etched to form contact holes. The etching process can be performed by a dry etching method or a wet etching method. In this embodiment mode, the contact hole is formed by a dry etching method.

  Next, a conductive layer 217 is formed over the interlayer insulating layer 215 and in the contact hole 216, and is etched into a desired shape, thereby forming a source electrode and a drain electrode, and further, wirings constituting an electric circuit (FIG. 6). (See (A1) and (A2)). As the conductive layer 217, a film formed of an element of aluminum, titanium, molybdenum, tungsten, or silicon, or an alloy film using these elements can be used.

  In the case where the conductive layer 217 has a rectangular shape due to layout restrictions and has a corner portion, etching or the like is preferably performed so as to have a rounded shape. By etching into a rounded shape, generation of dust during the manufacturing process can be suppressed and yield can be improved. The same applies to the gate electrode layer and the semiconductor layer.

  Through the above steps, a thin film transistor, an interlayer insulating layer 215 covering the thin film transistor, and a conductive layer 217 serving as a wiring connected to the thin film transistor can be formed.

  Next, a microstructure is formed over the interlayer insulating layer 215. The method described in Embodiment 1 may be applied to the method for manufacturing the microstructure.

  Note that the case where the conductive layer 217 serves as a source electrode and a drain electrode of a thin film transistor and a lower electrode of a microstructure is described here. Therefore, the lower electrode of the microstructure is already formed in the above process. However, the present invention is not limited to this, and the conductive layer 217 and the lower electrode of the microstructure may be formed separately.

  Next, a filler material layer 218 is formed over the lower electrode formed by the conductive layer 217. The filler material layer 218 may be formed using a material and a method similar to those of the filler material layer 102 in Embodiment 1.

  Next, a conductive layer 219 for forming an upper electrode is formed on the filler material layer 218 formed in a desired pattern, and a structural layer 220 is formed on the conductive layer 219 formed in a desired pattern. The conductive layer 219 and the structural layer 220 may be formed using a material and a method similar to those of the upper electrode layer 103 and the structural layer 104 in Embodiment 1.

  As described above, the microstructure and the transistor of the present invention can be manufactured over the same substrate (see FIGS. 7A1 and 7A2).

  Note that the conductive layer 217 may form an upper electrode instead of the lower electrode of the microstructure (see FIG. 7B).

  In the above description, a thin film transistor is used as a transistor. However, the present invention is not limited to this, and the transistor may be an FET (Field Effect Transistor). Alternatively, an SOI (Silicon On Insulator) substrate may be used as the substrate (see FIG. 9). FIG. 9A shows an example in which the conductive layer 238 becomes the source and drain electrodes of the FET and the lower electrode of the microstructure, and FIG. 9B shows the source and drain electrodes of the FET. In addition, the upper electrode of the microstructure is an example.

  Note that although the case where a microstructure is formed over an interlayer insulating layer formed so as to cover the transistor after formation of the transistor is described in this embodiment, the present invention is not limited thereto. Each layer of the microstructure is formed while forming each layer of the transistor if the filling material layer included in the microstructure does not break or change due to temperature during the manufacturing process of the transistor or due to a chemical solution used. You can also. For example, the gate electrode of the transistor and the lower electrode of the microstructure can be formed by patterning the same layer, and the source and drain electrodes of the transistor and the upper electrode of the microstructure can be formed by patterning the same layer. For example, this can be realized by using an organic transistor. An organic transistor is a transistor to which an organic semiconductor such as pentacene is applied. Hereinafter, an example of a method for manufacturing an organic thin film transistor (hereinafter referred to as an organic TFT) will be briefly described.

  FIG. 8 shows a top view and a cross-sectional view when a bottom contact type organic TFT is used as a transistor. In bottom contact type organic TFT, after forming a source electrode and a drain electrode, an organic-semiconductor film is formed.

  First, the base film 302 is formed over the insulating substrate 301, and the gate electrode layer 307 is formed over the base film 302. The base film 302 can be formed in the same manner as the base film 202, and the gate electrode layer 307 can be formed in the same manner as the gate electrode layer 207.

  Note that the insulating substrate 301 can be similar to the insulating substrate 201. However, the insulating substrate 301 is preferably a substrate made of plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a synthetic resin such as acrylic. . A substrate made of such a synthetic resin has flexibility and is lightweight.

  In addition to the sputtering method, the gate electrode layer 307 may be formed by a screen printing method, a roll coater method, a droplet discharge method, a spin coating method, an evaporation method, or the like. A conductive polymer or the like may be used.

  The droplet discharge method is a method capable of selectively forming a pattern, and selectively discharges (including ejection) a droplet of a composition mixed with a material such as a conductive film or an insulating film. This is a method for forming a conductive film. As a droplet discharge method, there is typically an ink jet method.

  When a conductive film is formed by a droplet discharge method, a conductive material is mixed in a solvent and used. As a conductor mixed in the solvent, gold, silver, copper, platinum, palladium, tungsten, nickel, tantalum, bismuth, lead, indium, tin, zinc, titanium or aluminum, alloys made of these, and dispersible nanoparticles thereof Alternatively, silver halide fine grains can be used.

  When forming a conductive film by a screen printing method or the like, a conductive paste is used. As the conductive paste, conductive carbon paste, conductive silver paste, conductive copper paste, conductive nickel paste, or the like can be used. After a predetermined pattern is formed with a conductive paste, it is preferably dried and then subjected to heat treatment at about 100 to 200 ° C. to flatten (also referred to as leveling) and harden.

  Note that the gate electrode layer 307 can form not only the gate electrode of the thin film transistor but also the lower electrode of the microstructure.

  After the gate electrode layer 307 is formed, the gate insulating film 306 is formed. The gate insulating film 306 may be formed using a material and a method similar to those of the gate insulating film 206. Although the CVD method is used here, it may be formed by a sputtering method, a spin coating method, an evaporation method, or the like. Alternatively, a siloxane resin, polysilazane, or the like may be used similarly to the interlayer insulating layer 215. Alternatively, an insulating film formed by anodizing the gate electrode may be used as the gate insulating film.

  Next, a filler material layer 318, an upper electrode layer 319, and a structural layer 320 are formed. The filler material layer 318 may be formed using a material and a method similar to those of the filler material layer 102 in Embodiment 1. The upper electrode layer 319 may be formed using a material and a method similar to those of the gate electrode layer 307. The structural layer 320 may be formed using a material and a method similar to those of the structural layer 104 in Embodiment 1.

  Next, a source and drain electrode layer 316 of the thin film transistor is formed over the gate insulating film 306. The source and drain electrode layers 316 can be formed using a material and a method similar to those of the gate electrode layer 307. Note that the source and drain electrode layers 316 need to be in ohmic contact with an organic semiconductor film to be formed later. Therefore, when the material of the organic semiconductor film has p-type conductivity, it is preferable to use a material having a work function larger than the ionization potential of the material of the organic semiconductor film. It is preferable to use a material having a work function smaller than the ionization potential of the material of the organic semiconductor film. Here, since p-type pentacene is used as the material of the organic semiconductor film, tungsten having a relatively high work function is used as the material of the source and drain electrode layers 316. However, it is not limited to this.

  Next, an organic semiconductor film 304 is formed over the gate insulating film 306 and the source and drain electrode layers 316. As described above, pentacene is used as the material of the organic semiconductor film of this embodiment. However, the material of the organic semiconductor film is not limited to this, and an organic molecular crystal or an organic polymer compound may be used. Specific examples of the organic molecular crystal include polycyclic aromatic compounds, conjugated double bond compounds, carotenes or macrocyclic compounds, or complexes thereof, phthalocyanines, or charge transfer complexes (CT complexes). For example, anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), TTF (tetrathiafulvalene): TCNQ (tetracyanoquinodimethane) complex, DDPH (diphenylpicrylhydrazyl), dye , Proteins, perylenetetracarboxylic acid derivatives such as PTCDA, naphthalenetetracarboxylic acid derivatives such as NTCDA, and the like can be used. Specific examples of the organic polymer compound include a π-conjugated polymer, a phthalocyanine metal complex, and an iodine complex. In particular, a polyacetylene, polyaniline, polypyrrole, polythienylene, polythiophene derivative, poly (3 alkylthiophene), polyparaphenylene derivative or polyparaphenylene vinylene derivative, which is a π-conjugated polymer whose skeleton is composed of conjugated double bonds, is used. It is preferable.

  The organic semiconductor film 304 may be formed by a method that can form a film having a uniform thickness. As a specific method, an evaporation method, a spin coating method, a bar coating method, a solution casting method, a dipping method, or the like may be used. Here, pentacene, which is an organic semiconductor material, is formed as the organic semiconductor film 304 over the gate insulating film 306 and the source and drain electrode layers 316 by a vacuum evaporation method which is a kind of evaporation method. The organic semiconductor film 304 is preferably formed selectively, such as through a mask.

  Note that as a pretreatment for forming the organic semiconductor film, a plasma treatment may be performed on a surface on which the organic semiconductor film is formed. Alternatively, a film that improves the adhesion or interface state with respect to the surface on which the organic semiconductor film is formed, for example, a self-assembled monomolecular film (SAM) or an alignment film may be formed.

  Then, after the organic semiconductor film is formed, the insulating substrate 301 is subjected to heat treatment. The upper limit of the temperature of the heat treatment is lower than the temperature at which the organic semiconductor film 304 evaporates or decomposes. Heat treatment at a high temperature within this temperature range improves the characteristics of the organic TFT. Further, the temperature at this time is preferably equal to or lower than the melting point of the organic semiconductor film.

Note that the heat treatment may be performed in the air, but is preferably performed in an inert gas atmosphere such as nitrogen or argon in consideration of deterioration of the organic semiconductor film due to oxygen or water. Furthermore, it is more preferable to perform the heat treatment under reduced pressure (for example, 1.3 × 10 ⁻³ Pa to 6.7 × 10 ⁴ Pa).

  Note that the present invention is not limited to the above description, and the microstructure may be formed after the organic TFT is formed, or the organic TFT may be formed after the microstructure is formed.

  As described above, the bottom contact type organic TFT and the microstructure can be manufactured over the same substrate (see FIGS. 8A1 and 8A2).

  The organic TFT of the present application is preferably covered with a protective film. Here, an insulating inorganic film is used as the protective film. By covering the organic TFT with the insulating inorganic film, damage to the organic semiconductor film, which may occur due to the formation of the microstructure, can be reduced, and the influence on the electrical characteristics of the organic TFT can be reduced. The protective film 322 covers at least the organic semiconductor film 304.

  The organic TFT applied to the present invention is not limited to the bottom contact type described above, and may be a top contact type. The manufacturing method will be briefly described below with reference to FIGS. 8B1 and 8B2.

  First, the gate electrode layer 407 is formed over the insulating substrate 401 by using the same material and the same method as in the bottom contact, and the gate insulating film 406 is formed to cover the gate electrode layer 407. Note that a base film 402 is formed over the insulating substrate 401.

  Note that the gate electrode layer 407 forms not only the gate electrode of the thin film transistor but also the lower electrode of the microstructure.

  Next, a filler material layer 418, an upper electrode layer 419, and a structure layer 420 are formed. The filler material layer 418 may be formed using a material and a method similar to those of the filler material layer 102 in Embodiment 1. The upper electrode layer 419 may be formed using a material and a method similar to those of the gate electrode layer 407. The structural layer 420 may be formed using a material and a method similar to those of the structural layer 104.

  Next, an organic semiconductor film 404 is formed over the gate insulating film 406. Note that pentacene is also used as the organic semiconductor material in this embodiment. However, the organic semiconductor film material is not limited to this, and an organic molecular crystal or an organic polymer compound may be used. Specific examples of the organic molecular crystal include polycyclic aromatic compounds, conjugated double bond compounds, carotenes or macrocyclic compounds, or complexes thereof, phthalocyanines, or charge transfer complexes (CT complexes). For example, anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), TTF (tetrathiafulvalene): TCNQ (tetracyanoquinodimethane) complex, DDPH (diphenylpicrylhydrazyl), dye , Proteins, perylenetetracarboxylic acid derivatives such as PTCDA, naphthalenetetracarboxylic acid derivatives such as NTCDA, and the like can be used. Specific examples of the organic polymer compound include a π-conjugated polymer, a phthalocyanine metal complex, and an iodine complex. In particular, a polyacetylene, polyaniline, polypyrrole, polythienylene, polythiophene derivative, poly (3 alkylthiophene), polyparaphenylene derivative or polyparaphenylene vinylene derivative, which is a π-conjugated polymer whose skeleton is composed of conjugated double bonds, is used. It is preferable.

  The organic semiconductor film 404 may be formed by a method that can form a film having a uniform thickness. Specifically, an evaporation method, a spin coating method, a bar coating method, a solution casting method, a dipping method, or the like may be used. Here, pentacene which is an organic material is formed over the gate insulating film 406 by a vacuum evaporation method. The organic semiconductor film 404 is preferably formed selectively, such as through a mask.

  Note that as a pretreatment for forming the organic semiconductor film, a plasma treatment may be performed on a surface on which the organic semiconductor film is formed. Alternatively, a film that improves adhesion to the formation surface of the organic semiconductor film or a film that improves the interface state, such as a self-assembled monomolecular (SAM) film or an alignment film, may be formed.

  Note that although the organic semiconductor film 404 is formed after the formation of the filling material layer 418 here, the filling material layer 418 may be formed after the formation of the organic semiconductor film 404. After the gate electrode layer 407 is formed, the filler material layer 418 may be formed before the source and drain electrode layers 416 are formed. However, in order to improve the electrical characteristics of the organic semiconductor film, the organic semiconductor film 404 is preferably formed after the filling material layer 418 is formed. In that case, the ultraviolet light irradiation treatment or the plasma treatment is preferably performed after the filling material layer 418 is formed and before the organic semiconductor film 404 is formed.

  After that, the source and drain electrode layers 416 are formed. The source and drain electrode layers 416 may be formed using the same material and the same formation method as in the bottom contact.

  Note that the source and drain electrode layers 416 need to be in ohmic contact with the organic semiconductor film 404. Therefore, when the material of the organic semiconductor film has p-type conductivity, it is preferable to use a material having a work function larger than the ionization potential of the material of the organic semiconductor film. It is preferable to use a material having a work function smaller than the ionization potential of the material of the organic semiconductor film. Here, since p-type pentacene is used as the material of the organic semiconductor film, tungsten having a relatively high work function is used as the material of the source and drain electrode layers 416.

  Then, after the organic semiconductor film is formed, the insulating substrate 401 is subjected to heat treatment. The upper limit of the temperature of the heat treatment is lower than the temperature at which the organic semiconductor film 404 evaporates or decomposes. Heat treatment at a high temperature within this temperature range improves the characteristics of the organic TFT. Further, the temperature at this time is preferably equal to or lower than the melting point of the organic semiconductor film.

Note that the heat treatment may be performed in the air, but is preferably performed in an inert gas atmosphere such as nitrogen or argon in consideration of deterioration of the organic semiconductor film due to oxygen or water. Furthermore, it is more preferable to perform the heat treatment under reduced pressure (for example, 1.3 × 10 ⁻³ Pa to 6.7 × 10 ⁴ Pa).

  Note that the present invention is not limited to the above description, and the microstructure may be formed after the organic TFT is formed, or the organic TFT may be formed after the microstructure is formed.

  As described above, the top contact type organic TFT and the microstructure can be manufactured over the same substrate (see FIGS. 8B1 and 8B2).

  Note that the organic TFT of the present embodiment is preferably covered with a protective film. Here, an insulating inorganic film is used as the protective film. By covering the organic TFT with the insulating inorganic film, damage to the organic semiconductor film, which may occur due to the formation of the microstructure, can be reduced, and the influence on the electrical characteristics of the organic TFT can be reduced. The protective film 422 covers at least the organic semiconductor film 404.

  In the above description, the lower electrode and the gate electrode of the microstructure are formed in the same process by patterning the same layer, and the upper electrode, the source electrode, and the drain electrode of the microstructure are formed by patterning the same layer. Although the case where it formed in the same process was demonstrated, this invention is not limited to this. For example, even when organic TFTs are used, they may not be formed in the same process as the same layer.

  Further, according to the present invention, a microstructure and a semiconductor element are manufactured over the same substrate, so that a semiconductor device that does not require assembly or a package and does not require manufacturing costs can be provided. In addition, the manufacturing process can be greatly reduced.

  As described above, the microstructure and the transistor of the present invention can be formed over the same substrate. As described above, the microstructure of the present invention can be manufactured by applying various methods.

  The microstructure of the present invention manufactured as described above can be applied to a pressure sensor, an interference display, or the like.

(Embodiment 3)
A strain gauge (also referred to as a strain gauge) can be manufactured by applying the present invention. In this embodiment mode, a strain gauge manufactured by applying the present invention will be described with reference to the drawings.

  FIG. 11 is a schematic diagram of a strain gauge manufactured using a microstructure to which the present invention is applied. Note that FIG. 11B is a top view and FIG. 11A is a cross-sectional view taken along line X-X ′ in FIG.

  In the microstructure illustrated in FIG. 11, a filler material layer 501 is provided over a substrate 500, a conductive layer 502 is provided over the filler material layer 501, and a structural layer 503 is provided over the conductive layer 502. The conductive layer 502 is formed with a pattern having a predetermined length.

  Here, the strain gauge will be described. A strain gauge refers to a measuring instrument that can measure the amount of change in resistance that occurs when an object is distorted and can measure the amount of strain of the object from the amount of change. Since the change amount of the resistance value at this time is very small, it is detected by converting to a voltage using a Wheatstone bridge circuit.

FIG. 12 shows a Wheatstone bridge circuit used in the present embodiment. The Wheatstone bridge circuit shown in FIG. 12 includes a strain gauge 510, a first resistance element 511, a second resistance element 512, and a third resistance element 513, and four resistances that a generally well-known Wheatstone bridge circuit has. One of the elements is a strain gauge. If the initial resistance value of the strain gauge is r, the resistance value of the first resistance element 511 is R ₁ , the resistance value of the second resistance element 512 is R ₂ , and the resistance value of the third resistance element 513 is R ₃ , relationship of the following equation (4) is established between the output voltage _{V out} and the input voltage _{V in.}

_{Here, r = R 1 = R 2} = and _R 3 = R, strain the strain gauge resistance values are introduced to the changes to R + [Delta] R, the variation [Delta] V _out of the output voltage _{V out} is the following formula (5) It is represented by

When sufficiently large resistance value R, since the ΔR«R, ΔV _out is represented by the following equation (6).

  Here, K is a gauge factor obtained experimentally, and is a constant value. A relation of εK = ΔR / R is established between the strain amount ε and the gauge factor K. Therefore, the strain amount ε can be obtained by measuring ΔR. The strain gauges described in this embodiment may be arranged in a matrix.

  By applying the microstructure of the present invention to produce a strain gauge, the structural layer can be prevented from being broken. Therefore, it is possible to provide a strain gauge having a movable part with high mechanical strength and high reliability. In addition, the yield in the strain gauge manufacturing process can be improved.

FIG. 6 illustrates an example of a microstructure. FIG. 6 illustrates an example of a microstructure. 10A and 10B illustrate an example of a method for manufacturing a microstructure. The block diagram explaining an example of a micro electromechanical device. 8A and 8B illustrate an example of a method for manufacturing a microelectromechanical device. 8A and 8B illustrate an example of a method for manufacturing a microelectromechanical device. 8A and 8B illustrate an example of a method for manufacturing a microelectromechanical device. The figure explaining an example of a micro electromechanical device. The figure explaining an example of a micro electromechanical device. FIG. 6 illustrates an example of a microstructure. The figure explaining the strain gauge to which the microstructure is applied. The figure explaining the strain gauge to which the microstructure is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Substrate 101 Lower electrode layer 102 Filling material layer 103 Upper electrode layer 104 Structure layer 110 Hollow part 120 Organic film 121 Metal film 122 Resist mask 123 Metal mask 131 Lower electrode layer 132 Filling material layer 133 Upper electrode layer 134 Structure layer 136 Lower electrode Layer 137 Filling material layer 138 Upper electrode layer 139 Structure layer 201 Insulating substrate 202 Underlayer film 204 Semiconductor layer 206 Gate insulating film 207 Gate electrode layer 209 Side wall 210 High-concentration N-type impurity region 211 P-type impurity region 212 N-type impurity region 213 N-type semiconductor element 214 P-type semiconductor element 215 Interlayer insulating layer 216 Contact hole 217 Conductive layer 218 Filling material layer 219 Conductive layer 220 Structural layer 230 Controller 231 Semiconductor device 232 Electrical circuit section 233 Structure body section 234 Control circuit 235 Interface 236 Sensor 237 Actuator 238 Conductive layer 239 Conductive layer 301 Insulating substrate 302 Underlying film 304 Organic semiconductor film 306 Gate insulating film 307 Gate electrode layer 316 Drain electrode layer 318 Filling material layer 319 Upper electrode layer 320 Structural layer 322 Protective film 401 Insulating substrate 402 Base film 404 Organic semiconductor film 406 Gate insulating film 407 Gate electrode layer 416 Drain electrode layer 418 Filling material layer 419 Upper electrode layer 420 Structure layer 422 Protective film 500 Substrate 501 Filling material layer 502 Conductive layer 503 Structure layer 510 Gauge 511 Resistance element 512 Resistance element 513 Resistance element

Claims (8)

A microelectromechanical device having a microstructure,
The microstructure includes a lower electrode layer provided on an insulating surface, a filling material layer provided on the lower electrode layer, and an upper electrode facing the lower electrode layer provided on the filling material layer And a structural layer provided on the upper electrode layer,
The structural layer has a structure movable in a direction toward the lower electrode layer or a direction away from the lower electrode layer,
The micro electromechanical device, wherein the filling material layer is an insulating material having elasticity. A microelectromechanical device having a microstructure,
The microstructure has a filler material layer provided on an insulating surface, an upper electrode layer provided on the filler material layer, and a structure layer provided on the upper electrode layer,
The structural layer has a structure movable in the thickness direction of the filler material layer,
The micro electromechanical device, wherein the filling material layer is an insulating material having elasticity. In claim 1 or claim 2,
A micro electro mechanical device characterized in that the insulating material is an elastomer or a thermoplastic elastomer. Forming a lower electrode layer on the insulating surface;
Forming a filling material layer made of an insulating material having elasticity on the lower electrode layer;
Forming an upper electrode layer on the filler material layer;
A method of manufacturing a microelectromechanical device, wherein a structural layer is formed on the upper electrode layer. Forming a lower electrode layer on the insulating surface;
A film made of an insulating material having elasticity covering the lower electrode layer is formed on the entire surface,
A metal mask is selectively formed on the film made of an insulating material having elasticity,
Etching a film made of an insulating material having elasticity using the metal mask to form a filling material layer,
Forming an upper electrode layer on the filler material layer;
A method of manufacturing a microelectromechanical device, wherein a structural layer is formed on the upper electrode layer. In claim 4 or claim 5,
The method for manufacturing a microelectromechanical device, wherein the insulating material having elasticity is an elastomer or a thermoplastic elastomer. In claim 6,
The method for manufacturing a microelectromechanical device, wherein the insulating material having elasticity is formed by being dissolved in a solvent. In claim 7,
The method for manufacturing a microelectromechanical device, wherein the insulating material having elasticity is formed by a spin coating method.

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