JP2009129477A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of storing pseudo binary data or multivalued data in a memory cell depending on a writing unit. <P>SOLUTION: The nonvolatile semiconductor storage device is capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell. In a first write operation that processes data in the first unit, the logic of either of the higher-order bit or the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data are stored in the one memory cell, and parity data for error correction in the second unit are stored in the memory cell. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, for example, a flash memory including a memory cell capable of storing multilevel data.

  In general, a nonvolatile semiconductor memory device typified by a NOR flash memory has a word write operation capable of writing to a memory cell in units of one word (16 bits) and a plurality of words written in order to shorten the write time. There is a page write operation that enables it.

  In recent years, with the increase in capacity and cost of flash memory, multi-level storage in which a plurality of bits of data is held in one memory cell has been advanced (for example, see Patent Document 1).

When the memory cell of the NOR type flash memory is multi-valued, the number of words that can be written by one page write operation is very large, for example, 512 words from the conventional 8 words, 16 words, and 32 words. It has become to. This is due to speeding up of writing, ECC (Error-Correcting Code) support for improving reliability, and the like (see, for example, Patent Document 2).
JP 2005-108303 A Japanese Patent Laid-Open No. 2001-210082

  The present invention provides a nonvolatile semiconductor memory device capable of storing pseudo binary data or multi-value data in a memory cell in accordance with a writing unit.

  The nonvolatile semiconductor memory device according to one aspect of the present invention provides multivalued data obtained by selecting an upper bit from one of the data sets of the first unit and a lower bit from the other as a threshold value of each memory cell. A non-volatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by allocating to a voltage, and in a first write operation that processes data in the first unit, By fixing the logic of either the bit or the lower bit and assigning two multi-value data that maximizes the difference in threshold voltage, one bit is assigned to one memory cell as a pseudo binary state. In a second write operation that stores input data and processes the data in a second unit that is larger than the first unit, multiple bits are stored in one memory cell as a multi-valued state. Stores the force data, and to store the parity data for error correction in said second unit to said memory cell.

  The nonvolatile semiconductor memory device according to one embodiment of the present invention can store pseudo binary data or multilevel data in a memory cell in accordance with a writing unit.

  For example, for each threshold value of the memory cell, the erase state is (11), and multi-value data is sequentially assigned as (10), (00), (01) from the lowest threshold value. It is necessary to control the interval between adjacent threshold values of memory cells that store multilevel data in a narrower range than when binary data is stored.

  Therefore, the multi-value data stored in the memory cell is generally guaranteed by an ECC circuit by providing parity data in order to improve reliability. A large amount of data such as 512 words (8192 bits) is batched by a page write operation at the time of multi-value data write in order to increase the repair efficiency for parity data and to speed up the write time. Need to be processed.

  In the page write operation, for example, a unit including 512-word main data, parity data associated with the main data, and flag data described later is written in the memory cell. When a page write operation is performed on a memory cell that stores multilevel data, 512 words (8192 bits) of main data are stored and held in 4096 memory cells.

  On the other hand, when a word write operation for performing data processing in units of one word is realized as a multi-value, an IO compression method for compressing data in a closed form in units of one word is adopted as a data compression method for multi-value data. When the parity data is generated in units of main data of 512 words as described above, it is necessary to update the parity data every time one word worth of data is newly added.

  However, in the flash memory, generally, the erase unit is set larger than the data write unit. Therefore, there is a problem that the parity data cannot be updated as described above for writing in units of one word. .

  In the nonvolatile semiconductor memory device according to the following embodiment which is an aspect of the present invention, pseudo binary data or multi-value data is stored in a memory cell in accordance with a writing unit while solving the above-described problem.

  Each embodiment will be described below with reference to the drawings. In the following embodiments, an example in which the present invention is applied to a NOR flash memory as a nonvolatile semiconductor memory device will be described.

  FIG. 1 is a diagram illustrating a configuration of a NOR flash memory 100 according to a first embodiment which is an aspect of the present invention.

As shown in FIG. 1, a NOR flash memory 100 includes a memory cell array 1, a decoder 2, a sense amplifier 3, a control circuit 4, an address buffer 5, an input / output buffer 6, a data latch circuit 7, A data compression circuit 8, a parity generation circuit 9, a burst circuit 10, an ECC correction circuit 11, and a multiplexer 12 are provided.

  The memory cell array 1 has a plurality of memory cells arranged in a matrix. The control gate electrodes of the plurality of memory cells arranged in the selected row direction are commonly connected to the word line, and the drain regions of the plurality of memory cells arranged in the selected column direction are common to the bit lines via the bit line contacts. It is connected.

  A memory cell group connected to one word line includes a plurality of memory cells used as a data area for storing main body data (write data input from the outside), parity data associated with the main body data, and a later-described data cell. This corresponds to a plurality of memory cells used as a parity / flag area in which flag data is stored. In this embodiment, the memory cell group connected to one word line is a unit processed by one page write operation.

  Hereinafter, the word write operation is, for example, a batch processing operation (first write operation) of 16-bit input data, and the page write operation is a plurality of words, that is, input data of at least 2 words (32 bits) or more. This means a batch processing operation (second writing operation).

  The decoder 2 performs bit line selection, word line selection, and driving of the memory cell array 1 in accordance with a control signal output from the control circuit 4.

  The sense amplifier 3 is connected to a bit line of the memory cell array 1 and reads and outputs data stored in the memory cell.

  Address buffer 5 receives an external address signal and generates an internal address signal. The internal address signal generated by the address buffer 5 is supplied to the control circuit 4, the data latch circuit 7, and the burst circuit 10.

  The input / output buffer 6 is connected to, for example, a data input / output terminal (not shown) capable of inputting / outputting data of 16 bits (one word) simultaneously in one transfer cycle. The supplied data is supplied to the data latch circuit 7 and the control circuit 4. Further, when reading data, the input / output buffer 6 receives the read data via the burst circuit 10 and outputs the input data to the outside.

  The control circuit 4 receives a chip enable signal CEB, a write enable signal WEB and an output enable signal OEB inputted from the outside, and also receives an internal address signal and a data signal. The control circuit 4 outputs various control signals for controlling the operation of each internal circuit based on these input signals.

  The data latch circuit 7 receives the internal address signal and the input data signal, latches the input data in the area indicated by the internal address signal, and outputs the latched input data to the data compression circuit 8 and the parity generation circuit 9. For example, it is assumed that the data latch circuit 7 can hold at least 256 bits of data.

  The data compression circuit 8 performs address compression on the flag data output from the control circuit 4, the main body data output from the data latch circuit 7, and the parity data output from the parity generation circuit 9.

  Here, FIG. 2 is a diagram for explaining the address compression method in the present embodiment. FIG. 3A is a diagram showing a relationship between each threshold value of the memory cell to which the compressed multi-value data is allocated and the cell distribution frequency.

  In this embodiment, the multi-value data compression method is not an IO compression method closed in units of one word, but data in units of one word input in different transfer cycles is processed as a set (multi-value compression pair). Use address compression. Here, for example, a case where a multi-value compression pair is configured in units of 256 bits is assumed. Of the 256-bit input data held in the data latch circuit 7, for example, the first 128 bits (8 words) are the upper bit “m (m = 0, 1)” side data, and the latter 128 bits (8 words). Is the lower bit “n (n = 0, 1)” side data, and multi-value data “mn” is configured.

  Hereinafter, in the page write operation, the input data on the upper bit side is referred to as pages 0, 1,... 7 for each word unit. Also, the input data on the lower bit side is called pages 8, 9... 15 for each word unit. Each page has a data capacity of 16 bits (1 word).

  A set of data having the same order in page 0 to page 7 on the upper bit side and page 8 to page 15 on the lower bit side, for example, a set of page 0 and page 8 is a multi-value compression pair. Therefore, the set of page 1 and page 9 is also a multi-value compression pair, and the set of page 2 and page 10 is also a multi-value compression pair.

  A multi-value compression pair, for example, page 0 and page 8 is 16-bit data, and is composed of 16 binary bits IO <0>, IO <1>,..., IO <15>. It shall be. Here, each IO <i> (i = 0,..., 15) represents a binary bit input from the i-th input / output terminal.

  As shown in FIG. 2, for example, data positioned at the same IO address IO <i> of two pages (for example, page 0 and page 8) that are a multi-value compression pair are associated and assigned to each threshold value of the memory cell. Thus, multi-value data is stored (FIG. 3A).

  Note that the two pages that form the multi-value compression pair are not necessarily limited to the above relationship, and different pages may be used as the multi-value compression pair. In addition, if bits between different pages are compressed, it is not always necessary to associate data positioned at the same IO address.

  FIG. 3B is a diagram showing a relationship between each threshold value of the memory cell to which the compressed pseudo binary data is allocated and the cell distribution frequency. FIG. 3C is a diagram showing allocation of data written by the word write operation.

  In this embodiment, when writing data in units of one word, the two states (11) and (01) with the widest difference in threshold voltage are used, and data is written into the memory cell as pseudo binary data (see FIG. 3B). This ensures data reliability without generating parity data.

  When writing the pseudo binary data, for example, the bit of the page 0IO <0> on the page 0IO <0> on the lower bit side is forcibly fixed to “1”. ) Is written into the memory cell as (11) or (01) data. That is, for example, the lower bit data consisting of page 8 to page 15 is forcibly fixed to “1”, for example, regardless of the external input. This halves the effective address space (FIG. 3C).

  As shown in FIG. 1, the parity generation circuit 9 generates parity data for ECC correction of this data according to the data output from the data latch circuit 7. The parity data is generated in units of 512 words (8192 bits) processed by one page write operation, for example.

  The ECC correction circuit 11 corrects the read data output from the sense amplifier 3 based on the parity data, and outputs corrected data (hereinafter referred to as corrected data).

  The multiplexer 12 receives the correction data output from the ECC correction circuit 11 and the flag data described later. The multiplexer 11 outputs the correction data to the burst circuit 10. Further, the multiplexer 1 outputs the flag data to the burst circuit 10 in response to an input of a control signal that requests output of the flag data output from the control circuit 4.

  The burst circuit 10 continuously outputs addresses of data to be read to the decoder 2 in synchronization with the external clock signal CLK according to the internal address signal. The burst circuit 10 outputs the data signal output from the multiplexer 12 to the input / output buffer 6 in synchronization with the external clock signal CLK (burst read operation).

  As described above, it is possible to control the memory cell in a multi-value state or a pseudo binary state in an address space of, for example, 512 words, which is a parity generation unit.

  However, since the parity data is generated in units of 512 words as described above, the multi-value data cannot be overwritten when the 512-word region is in the multi-value state, for example. Also, when the 512-word area is in a multilevel state, the pseudo binary state is overwritten, and when the 512-word area is in a pseudo binary state, the multilevel state is overwritten. But you can't do it as well.

  Further, when the 512-word area is in a pseudo binary state, for example, data cannot be written to page 8 forcibly fixing the data to “1”. That is, the lower bits masked by “1” data must be excluded from the valid address space.

  Because of this limitation, for example, whether the address space in units of 512 words is controlled as a multi-value state, a pseudo binary state, or an initial erase state is stored. It is necessary to keep it. The above control must be performed according to these states.

  Therefore, in this embodiment, flag data for determining the state is provided for every 512 words (unit processed by one page write operation), which is a parity generation unit.

  Here, FIG. 4 is a diagram showing allocation of the number of bits of parity data and flag data provided accompanying the main body data. FIG. 5 is a diagram showing an example of the allocation of the number of memory cells of parity data and flag data provided accompanying the main body data. FIG. 6 is a diagram showing the association between the logic stored in the memory cell and the state indicated by the flag data.

  As shown in FIG. 4, in this embodiment, for example, pseudo binary flag data (first flag data) indicating a pseudo binary state, multi-value, together with parity data generated every 512 word unit. Multi-value flag data (second flag data) indicating a state is provided. Hereinafter, when it is simply referred to as flag data, it means both flag data.

  As shown in FIG. 5, for example, multilevel flag data and pseudo binary flag data are stored in two memory cells in a pseudo binary state that does not require ECC relief. That is, as shown in FIGS. 1 and 5, the main body data, the accompanying flag data, and the accompanying parity data are also the minimum erasing unit to be erased at one time, and are a plurality of memories connected to one word line. Stored in the cell.

  Further, as shown in FIG. 6, for example, flag data is defined as (11) in the erased state, (01) in the multi-valued state, (10) in the pseudo binary state, and (00) in the write-inhibited state. And stored in the memory cell. When storing the pseudo binary flag data, the logic of the corresponding bit is rewritten from “1” to “0”, for example. When storing multi-level flag data, the logic of the corresponding bit is rewritten from “1” to “0”, for example.

  FIG. 7 is a diagram showing another example of allocation of memory cells for parity data and flag data provided in association with main body data. FIG. 8 is a diagram showing still another example of allocation of parity data and flag data memory cells provided in association with main body data.

  As shown in FIG. 7, the multilevel flag data and the pseudo binary flag data may be stored in one memory cell in a multilevel state.

  When pseudo binary flag data is written, the data is not ECC-corrected and parity data is not necessary. Therefore, when controlling the address space in units of 512 words as a pseudo binary state, pseudo binary flag data may be stored in a memory cell for storing parity data, as shown in FIG. . Thereby, the number of memory cells can be reduced and the circuit area can be reduced.

  Here, a word write operation and a page write operation using the flag data (pseudo binary flag data, multi-level flag data) in the NOR flash memory 100 will be described.

  First, an example of a flow of word write operation will be described. FIG. 9 is a flowchart illustrating an example of a word write operation of the NOR flash memory 100 according to the present embodiment.

  First, the control circuit 4 recognizes writing in units of words according to the input of the internal address signal and the data signal. Then, the control circuit 4 outputs a control signal for reading the flag to the decoder 2 (step S1).

  Next, the decoder 2 selects a bit line and a word line in the memory cell array 1 according to the control signal, and drives a memory cell corresponding to the designated address. As a result, flag data indicating the state of the address space in 512 word units including the designated address is read from the memory cell array 1, and the flag data is input to the control circuit 4 via the sense amplifier 3 (step S2). ).

  Next, the control circuit 4 determines whether or not the input flag data indicates a multi-value state (step S3).

  For example, if the control circuit 4 determines in step S3 that the flag data indicates a multi-valued state, as described above, the main body data is stored in the multi-valued state and cannot be written in word units. Therefore, the write operation is terminated.

  On the other hand, if the control circuit 4 determines in step S3 that the flag data does not indicate a multi-valued state, the control circuit 4 is in the erased state or the main body data is stored in a pseudo binary state. Is determined to be possible, and the process proceeds to step S4.

  Then, the control circuit 4 determines whether or not the designated address is an address of a page whose data is fixed to “1”, for example, in order to set the pseudo binary state (step S4).

  For example, if the control circuit 4 determines that the designated address is, for example, the address of a page whose data is fixed to “1”, the logic of the stored data is fixed and writing is impossible. Since there is, the write operation is terminated.

  On the other hand, if the control circuit 4 determines that the designated address is not, for example, the address of a word whose data is fixed at “1”, the process proceeds to step S5.

  When the designated address is not the address of a word in which data is fixed, writing in units of words is possible. Therefore, the control circuit 4 sets flag data indicating a binary state, outputs the flag data to the data compression circuit 8, and outputs a control signal for writing the flag data to the decoder 2.

  Then, the data compression circuit 8 outputs flag data after data compression. Then, the decoder 2 selects the bit line and the word line of the memory cell array 1 according to the control signal and the output of the data compression circuit 8, drives the memory cell corresponding to the designated address, and stores the flag data. Write (step S5).

  Next, a verify operation for the flag data is performed (step S6).

  Next, the control circuit 4 determines whether the verification is completed based on the output of the sense amplifier 3 (step S7).

  If the verification is not completed, the process returns to step S5, and the verify operation is performed again.

  On the other hand, when the verification is completed, the process proceeds to step S8.

  Next, the control circuit 4 outputs to the decoder 2 a control signal for writing the main body data at the designated address. Then, the data compression circuit 8 outputs the main data subjected to data compression. Then, the decoder 2 selects a bit line and a word line of the memory cell array 1 according to the control signal and the output of the data compression circuit 8, drives the addressed memory cell, and writes the main body data (step) S8).

  Next, a verify operation of the main body data is performed (step S9).

  Next, the control circuit 4 determines whether the verification is completed based on the output of the sense amplifier 3 (step S10).

  If the verification is not completed, the process returns to step S8, and the verify operation is performed again.

  On the other hand, when the verification is completed, the write operation is terminated.

  The word write operation is performed by the operation of the NOR flash memory 100 described above.

  As described above, in the flow shown in FIG. 9, after inputting the write command in units of words, the flag data is read during the initial operation to determine whether the main body data is in a multi-value state or a pseudo binary state.

  Here, if flag data indicating a pseudo binary state has already been written at the time of writing in word units, an operation for writing a flag indicating a pseudo binary state is not performed, but the specified address is immediately set. Write body data. As a result, the writing time in units of words can be shortened.

  Hereinafter, another example of the above-described word unit write operation will be described.

  FIG. 10 is a flowchart showing another example of the word unit write operation of the NOR flash memory 100 according to this embodiment.

In FIG. 10, the operations from step S1 to step S4 are the same as the operations from step S1 to step S4 shown in FIG. Further, the operation from the step S5 to the step S10 of the NOR flash memory 100 is the same as the operation from the step S5 to the step S10 shown in FIG. 9. In step S4, the control circuit 4 determines that the designated address is data Is determined not to be the address of the page fixed to “1”, the process proceeds to step S4a.

  In step S4a, the control circuit 4 determines whether or not the input flag data indicates a pseudo binary state.

  For example, if it is determined in step S4a that the flag data indicates a pseudo binary state, the control circuit 4 does not need to write flag data indicating the pseudo binary state again. Proceed to

  On the other hand, if it is determined in step S3 that the flag data does not indicate a pseudo binary state, the control circuit 4 needs to write flag data indicating a pseudo binary state. Proceed to

  The subsequent flow is the same as the flow shown in FIG.

  By the operation of the NOR flash memory 100 described above, the write operation time in units of words can be shortened.

  Next, an example of a flow of a write operation (page write operation) in units of a plurality of words (for example, 512 words) will be described.

  FIG. 11 is a flowchart showing an example of the page write operation of the NOR flash memory according to this embodiment.

  First, the control circuit 4 recognizes page-by-page writing in response to input of an internal address signal and a data signal. Then, the control circuit 4 outputs a control signal for reading the flag to the decoder 2 (step S11).

  Next, the decoder 2 selects a bit line and a word line of the memory cell array 1 according to the control signal, and drives a memory cell at a designated address. As a result, flag data indicating the state of the designated 512-word unit address space is read from the memory cell array 1, and the flag data is input to the control circuit 4 via the sense amplifier 3 (step S12).

  Next, the control circuit 4 determines whether or not the input flag data indicates a multilevel state (step S13).

  For example, if the control circuit 4 determines in step S13 that the flag data indicates a multi-valued state, as described above, the main body data is stored in the multi-valued state, and writing in units of multiple words is possible. Since this is not possible, the write operation is terminated.

  On the other hand, if the control circuit 4 determines in step S13 that the flag data does not indicate a multi-valued state, it determines that the flag data is in an erased state or the main body data is stored in a pseudo binary state. Is done.

  Therefore, the control circuit 4 determines whether or not the input flag data indicates a pseudo binary state (step S14).

  For example, if it is determined in step S14 that the flag data indicates a pseudo binary state, the control circuit 4 cannot write in units of a plurality of words, and ends the write operation.

  On the other hand, if the control circuit 4 determines in step S14 that the flag data does not indicate a pseudo binary state, it is determined that the state is an erased state.

  Here, when the designated 512-word unit address space is in the erased state, writing in units of a plurality of words is possible. Therefore, the control circuit 4 sets flag data indicating a multi-value state, outputs it to the data compression circuit 8, and outputs a control signal for writing the flag data to the decoder 2.

  Then, the data compression circuit 8 outputs flag data after data compression. The decoder 2 selects the bit line and the word line of the memory cell array 1 in accordance with the control signal and the output of the data compression circuit 8, drives the addressed memory cell, and writes the flag data (step) S15).

  Next, a verify operation for the flag data is performed (step S16).

  Next, the control circuit 4 determines whether the verification is completed based on the output of the sense amplifier 3 (step S17).

  If the verification is not completed, the process returns to step S15, and the verify operation is performed again.

  On the other hand, if the verification is completed, the process proceeds to step S18.

  Next, the control circuit 4 outputs to the decoder 2 a control signal for writing the main body data at the designated address. Then, the data compression circuit 8 outputs the main data subjected to data compression. The decoder 2 selects the bit line and the word line of the memory cell array 1 according to the control signal and the output of the data compression circuit 8, drives the addressed memory cell, and writes the body data (step) S18). Note that the parity data associated with the main body data is similarly written to a predetermined memory cell.

  Next, the verify operation of the main data and parity data is performed (step S19).

  Next, the control circuit 4 determines whether the verification is completed based on the output of the sense amplifier 3 (step S10).

  If the verification is not completed, the process returns to step S8, and the verify operation is performed again.

  On the other hand, when the verification is completed, the write operation is terminated.

  The page write operation is performed by the operation of the NOR flash memory 100 described above.

  Here, a read operation (burst read operation) of the NOR flash memory 100 will be described.

  In FIG. 1, when receiving an internal address signal for reading, the burst circuit 10 continuously outputs addresses for designating data to be read to the decoder 2 in synchronization with the external clock signal CLK. The decoder 2 selects a bit line and a word line of the memory cell array 1 according to the output of the burst circuit 10 and drives the addressed memory cell. As a result, the read flag data is input to the burst circuit 10, and the main data, flag data, and parity data read are input to the ECC correction circuit 11.

  When a dedicated command (flag output command) is input from the address buffer 5 and the input / output buffer 6, the control circuit 4 outputs a flag output command to the multiplexer 12. The multiplexer 12 outputs the flag data together with the correction data to the burst circuit 10 in response to the flag output command. Then, the burst circuit 10 outputs the input correction data and the flag data to the input / output buffer 6 as output data in synchronization with the external clock signal CLK.

  As a result, it is possible to output information indicating whether the designated 512-word unit address space is in a multilevel state or a pseudo binary state. Therefore, the external system that controls the NOR type flash memory determines whether the address space in units of 512 words is controlled as a multi-value state, a pseudo binary state, or an initial erase state. It becomes possible to manage.

  Further, as described above, when data in 512-word units is read, for example, multi-value flag data indicating a multi-value state in 512-word units and pseudo-binary flag data indicating a pseudo binary state are collectively displayed. Read out.

  The ECC correction circuit 11 performs ECC relief when multi-level flag data is input. On the other hand, the ECC correction circuit 11 does not perform ECC relief unless multi-level flag data is input.

  FIG. 12 is a diagram illustrating an example of a burst read operation of the NOR flash memory 100 according to the first embodiment which is an aspect of the present invention.

  As shown in FIG. 12, when multi-value flag data indicating a multi-value state is input, the burst circuit 10 outputs all read data in synchronization with the external clock CLK.

  Further, when the pseudo binary flag data indicating the pseudo binary state is input, the burst circuit 10 corresponds to the address of the page for which the logic is forcibly fixed to form the pseudo binary data. Data may be output as the fixed logic (for example, “1”) regardless of the read main data. Thereby, even if the data held in the memory cell in the page whose logic is fixed to “1” is defective from “1” to “0”, it does not appear as a defect outside.

  Furthermore, if a flag indicating a pseudo binary state is input to the burst circuit 10, the data corresponding to the address of the page for which the logic is forcibly fixed is invalid. Therefore, as shown in FIG. Skip data corresponding to address space. The burst circuit 10 outputs only the data corresponding to the remaining valid address space.

  That is, when the pseudo binary flag data is stored, the data stored in the other page is not read out, but the data stored in the other page is not read out. Thereby, the substantial data reading speed can be improved.

  As described above, according to the NOR flash memory 100 according to the present embodiment, pseudo binary data or multi-value data can be stored in the memory cell according to the write unit.

(Application example)
Hereinafter, an example in which the NOR flash memory 100 having the above configuration and function is mounted on a semiconductor chip will be described.

  FIG. 13 is a cross-sectional view showing an example of a semiconductor chip (multi-chip package: MCP) 1000 including the NOR flash memory 100 according to the first embodiment which is an aspect of the present invention.

  As shown in FIG. 13, a semiconductor chip 1000 includes a NAND flash memory 1002, a spacer 1003, a NOR flash memory 100, a spacer 1004, a PSRAM (Pseudo Static Random Access Memory) 1005, and a controller, which are sequentially stacked on a substrate 1001. 1006 is mounted in the same package.

  The NAND flash memory 1002 has, for example, a plurality of memory cells that can store multi-value data. Further, the semiconductor chip 1000 may be configured to use SDRAM (Synchronous Dynamic Random Access Memory) instead of PSRAM.

  Among the above memories, the NAND flash memory 1002 is used as a data storage memory, for example, depending on the use by the memory system. The NOR flash memory 100 is used as a program storage memory, for example. The PSRAM 1005 is used as a work memory, for example.

  The controller 1006 mainly performs data input / output control and data management for the NAND flash memory 1002. The controller 1006 includes an ECC correction circuit (not shown), adds an error correction code (ECC) when writing data, and analyzes and processes the error correction code when reading data.

  The NAND flash memory 1002, the NOR flash memory 100, the PSRAM 1005, and the controller 1006 are bonded to the substrate 1001 with wires 1007.

  Each solder ball 1008 provided on the back surface of the substrate 1001 is electrically connected to a wire 1007. As the package shape, for example, a surface mount type BGA (Ball Grid Array) in which each solder ball 1008 is two-dimensionally arranged is adopted.

  The ECC correction circuit 11 in the first embodiment may be provided in the NOR flash memory 100 as described above, or may be provided in the controller 1006. In this case, the NAND flash memory 1002 and the ECC correction circuit may be shared, and the NAND flash memory 1002 and the NOR flash memory 100 may have different ECC correction circuits. Further, the ECC correction circuit 11 may be provided outside the controller 1002 independently.

  Next, a case where the semiconductor chip 1000 is applied to a mobile phone which is an example of an electronic device will be described.

  FIG. 14 is a diagram showing a mobile phone in which the semiconductor chip 1000 is mounted. As shown in FIG. 14, the mobile phone 2000 includes a main body upper part 2002 having a main screen 2001 and a main body lower part 2004 having a keypad 2003. The mobile phone 2000 is equipped with a semiconductor chip 1000.

  A CPU (not shown) mounted on the mobile phone 2000 accesses the semiconductor chip 1000 via an interface (not shown) and transfers data and the like. The cellular phone 2000 uses, for example, the NAND flash memory 1002 as a user data storage area and the NOR flash memory 100 as a program storage area such as firmware.

  In such a memory system, the NOR flash memory 100 is required to perform a high-speed write operation in units of one word. On the other hand, the amount of program data to be stored is increasing as the application software becomes more sophisticated.

  As described above, the NOR flash memory 100 according to the first embodiment which is an aspect of the present invention stores data input in a word write operation in a pseudo binary state and is input in a page write operation. By storing data in a multi-valued state, it is possible to solve both of the two conflicting problems.

  The semiconductor chip 1000 can be applied to various electronic devices such as a personal computer, a digital still camera, and a PDA in addition to the mobile phone.

1 is a diagram illustrating a configuration of a flash memory according to a first embodiment which is an aspect of the present invention. FIG. It is a figure for demonstrating the address compression in Example 1 which is 1 aspect of this invention. It is a figure which shows the relationship between each threshold value of the memory cell to which the compressed multi-value data is allocated, and the cell distribution frequency. It is a figure which shows the relationship between each threshold value of the memory cell to which the compressed pseudo binary data is allocated, and the cell distribution frequency. It is a figure which shows allocation of the data written in the word unit. It is a figure which shows allocation of the bit number of the parity data and flag data provided accompanying main body data. It is a figure which shows an example of allocation of the memory cell of the parity data and flag data provided accompanying main body data. It is a figure which shows correlation with the state which flag stored in the logic memorize | stored in a memory cell. It is a figure which shows the other example of allocation of the memory cell of the parity data and flag data which are provided accompanying the main body data. It is a figure which shows the further another example of allocation of the memory cell of the parity data and flag data which are provided accompanying the main body data. 6 is a flowchart illustrating an example of a word write operation of the NOR flash memory according to the first embodiment which is an aspect of the present invention. 12 is a flowchart illustrating another example of the word write operation of the NOR flash memory according to the first embodiment which is an aspect of the present invention. 3 is a flowchart illustrating an example of a page write operation of the NOR flash memory according to the first embodiment which is an aspect of the present invention. FIG. 3 is a diagram illustrating an example of a burst read operation of the NOR flash memory 100 according to the first embodiment which is an aspect of the present invention. It is sectional drawing which shows an example of the semiconductor chip provided with the NOR type flash memory which concerns on Example 1 which is 1 aspect of this invention. It is a figure which shows the mobile telephone which stores the semiconductor chip provided with the NOR type flash memory which concerns on Example 1 which is 1 aspect of this invention.

Explanation of symbols

1 memory cell array 2 decoder 3 sense amplifier 4 control circuit 5 address buffer 6 input / output buffer 7 data latch circuit 8 data compression circuit 9 parity generation circuit 10 burst circuit 11 ECC correction circuit 12 multiplexer 100 flash memory 1000 semiconductor chip 1001 substrate 1002 NAND flash memory 1003, 1004 Spacer 1005 PSRAM
1006 Controller 1007 Wire 1008 Solder ball 2000 Mobile phone 2001 Main screen 2002 Main body upper part 2003 Keypad 2004 Lower main body

Claims (5)

By assigning multi-level data obtained by selecting the upper bit from one of the data sets of the first unit and the lower bit from the other to each threshold voltage of the memory cell, a plurality of bits are assigned to one memory cell. A non-volatile semiconductor memory device capable of storing data,
In the first write operation for processing data in the first unit, the logic of either the upper bit or the lower bit is fixed, and two multi-value data that maximizes the threshold voltage difference are allocated. Thus, 1-bit input data is stored in one of the memory cells as a pseudo binary state,
In a second write operation for processing data in a second unit larger than the first unit, a plurality of bits of input data are stored in one memory cell as a multi-value state, and the second unit is used in the second unit. A non-volatile semiconductor memory device, wherein parity data for error correction is stored in the memory cell. Controlling the address space of the second unit as the pseudo binary state or the multi-value state,
When the memory cell is in the pseudo binary state, the first flag data is stored for each of the second units, while when the memory cell is in the multi-value state, Second flag data is stored for each second unit,
When both the first flag data and the second flag data are not stored, both data processing by the first write operation and the second write operation is possible.
When the first flag data is stored and the second flag data is not stored, data processing by the first write operation is possible, and data by the second write operation Processing is prohibited,
When the second flag data is stored and the first flag data is not stored, both data processing by the first write operation and the second write operation is prohibited. The nonvolatile semiconductor memory device according to claim 1. When data processing is performed by the first write operation, the first flag data and the second flag data corresponding to a designated address space are read, and the pseudo binary state is determined. The nonvolatile semiconductor memory device according to claim 2, wherein the first flag is not written and data processing is performed. Storing the first flag data in the memory cell in which the parity data is stored in the second write operation;
4. The nonvolatile semiconductor memory device according to claim 2, wherein the second flag data is stored in one of the memory cells as the pseudo binary state. 5. When the first flag data is stored, data corresponding to an address space whose logic is fixed is not read, and input data corresponding to an address space whose logic is not fixed is read. The nonvolatile semiconductor memory device according to claim 2.

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