JP2009129301A - Self-diagnostic circuit and self-diagnostic method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems that in a configuration having a counter prepared for each diagnostic item, a circuit scale of an integrated circuit is increased, diagnostic items are increased as a function is enhanced and a circuit scale of a self-diagnostic unit is also increased. <P>SOLUTION: A self-diagnostic circuit 103 has a counter configured such that a plurality of types of error detection signals generated in an integrated circuit can be input thereto. The self-diagnostic circuit has also a setting unit 110 for determining a type of an error detection signal input to the counter out of the plurality of types of error detection signals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a self-diagnosis circuit and a self-diagnosis method for detecting an error in an integrated circuit.

  The integrated circuit is required to have high reliability depending on the equipment to be mounted. Therefore, in order to improve reliability, a self-diagnosis circuit may be mounted in the integrated circuit. The self-diagnosis circuit monitors the operation in the integrated circuit and detects a failure or performance degradation of the integrated circuit. A technique related to a semiconductor device having such a self-diagnosis circuit is disclosed in Patent Document 1.

In the technique described in Patent Document 1, a digital controller is disclosed in which a counter for the number of retries is provided for each diagnostic item in an integrated circuit, and an error with a large number of retries is determined as a serious error.
JP-A-4-245309

  However, since the technique described in Patent Document 1 has a configuration in which a counter is provided for each diagnostic item, the number of diagnostic items increases as the circuit scale of the integrated circuit increases and the functionality increases, and the circuit scale of the self-diagnosis unit also increases. There was a problem of doing.

  A self-diagnosis circuit according to an aspect of the present invention includes a counter to which a plurality of types of error detection signals generated in an integrated circuit are input, and an error detection signal to be input to the counter with respect to the plurality of types of error detection signals. A setting unit for determining the type.

  The self-diagnosis circuit of the present invention can detect an arbitrary failure with a simple configuration.

  FIG. 1 is a block diagram illustrating a system having an integrated circuit 100 and an integrated circuit 200 that incorporate a self-diagnostic circuit. As shown in FIG. 1, an integrated circuit 100 includes a CPU 101, a memory 102, a self-diagnosis circuit (hereinafter referred to as a test circuit) 103, a direct memory access controller (DMA) 104, a communication unit 105, an audio processing unit (AUDIO) 106, A video processing unit (VIDEO) 107 and an input / output control unit (I / O unit) 108 are provided. Here, the CPU 101 is a circuit that performs various processes based on, for example, a program stored in a ROM or the like in the memory 102. The memory 102 includes a ROM, a RAM, and the like, and is a storage unit that holds a program executed by the CPU and temporarily saves data being processed. The DMA 104 controls access when the CPU 101 or another functional block accesses the memory. The communication unit 105 is a control unit that controls communication when the integrated circuit 100 communicates with another integrated circuit (for example, the integrated circuit 200). The AUDIO 106 processes audio data processed by the integrated circuit 100. The VIDEO 107 processes video data processed by the integrated circuit 100. The I / O unit 108 controls input / output data of the integrated circuit 100.

  In addition, the integrated circuit 200 has only a configuration that does not include the audio processing unit 106, the video processing unit 107, and the test circuit 103 with respect to the configuration of the integrated circuit 100, and the other configurations are the same. Therefore, the same reference numerals are given to the same components as those of the integrated circuit 100, and the description thereof is omitted. The configuration shown in FIG. 1 is merely an example of an integrated circuit that configures the microcomputer, and the microcomputer can be configured with various functional blocks according to the function to be realized.

  Here, the test circuit 103 included in the integrated circuit 100 is a circuit that determines failure or deterioration of the integrated circuit 100 based on various signals output from other circuits included in the integrated circuit 100. The test circuit 103 according to the present embodiment is a circuit that counts various error flags output from other circuits and outputs the number of errors. FIG. 2 shows the test circuit 103 of the present embodiment in more detail.

  As shown in FIG. 2, the test circuit 103 according to the present embodiment includes a setting register 11, a plurality of AND circuits 12 </ b> A to 12 </ b> D, an OR circuit 13, and a counter 14. The setting register 11 is a register for setting an error flag to be counted based on a signal output from another circuit block or a signal input from the outside. The error to be counted can be set by control software input from the outside at the time of a test or a control program stored in an internal ROM. In addition, the setting can be changed by a signal given from the outside during the test. Therefore, in the present embodiment, the setting register 110 and the AND circuit 12 constitute a setting unit 110 that sets an error to be counted.

  In the AND circuits 12A to 12D, a setting value output from the setting register is input to one side, and error signals output from various points of the integrated circuit 100 are input to the other side. The AND circuit outputs the error flag input based on the output of the setting register to the subsequent stage. That is, when “L” level is input as the output value of the setting register, it operates as a mask circuit for masking the error flag. Here, the error flag output from another functional block of the integrated circuit 100 is a signal indicating that a minor error has occurred. Although it depends on the functions realized by the integrated circuit 100, a minor error is assumed to occur several times when the integrated circuit 100 operates, such as an error that can be corrected by ECC (Error Correction Code), bus access retry, or communication retry. This is an error. That is, here, if an error occurs during the operation of the integrated circuit 100, the error is considered to be a minor error as long as the error does not cause a malfunction as a system operation using the microcomputer of the integrated circuit 100. On the other hand, when an error occurs during the operation of the integrated circuit 100, a serious error is caused when the error causes a malfunction as a system operation using the microcomputer of the integrated circuit 100.

  The OR circuit 13 is connected to outputs of the AND circuits 12A to 12D. The OR circuit 13 inputs the error flag to the counter 14 when an error flag is output from any of the AND circuits 12A to 12D. The counter 14 counts the number of input error signals and outputs the count value.

  FIG. 3 is a flowchart showing the operation of the self-diagnosis circuit 103 configured as described above. Hereinafter, the operation in which the self-diagnosis circuit of the present embodiment detects a minor error will be described with reference to FIG.

  In step S1 shown in FIG. 3, a reset signal is input to the counter 14, and the value of the counter is initialized.

  Thereafter, in step S2 shown in FIG. 3, the setting register 11 is set to a state in which all minor errors are counted. In this embodiment, in order not to mask the error signal input to the AND circuits 12A to 12D, for example, in the case of a 4-bit setting register, “1” is written in all bits. Since the setting register 11 outputs “1” to all the AND circuits 12A to 12D, the AND circuits 12A to 12D output the input error signal as it is to the OR circuit. The OR circuit 13 collectively outputs the error signals output from the AND circuits 12A to 12D to the counter 14. In order to count minor errors that occur per unit time, this register is all rewritten to “0” after the unit time has elapsed.

  In step S3, the number of errors counted by the counter in step S2 is compared with a presumed allowable error number range. That is, it is determined whether Emin ≦ E ≦ Emax, where E is the number of errors, Emin is the minimum value of the assumed error number range, and Emax is the maximum value of the assumed error number range. If Emin ≦ E ≦ Emax, the process returns to step S1, and if E <Emin or Emax <E, the process proceeds to the next step S4.

  In step S4, the setting register 11 is set to a state where specific minor errors are counted. In this embodiment, the error signal input to the AND circuit 12A is not masked, and the error signal input to the AND circuits 12B to 12D is masked. For example, in the case of a 4-bit setting register, “1” is written only in the bit corresponding to the AND circuit 12A. Since “0” is written in the bits corresponding to the other AND circuits 12B to 12D, the error signal is masked, and the error counted by the counter 14 via the OR circuit is only a specific error. As described above, in order to count errors that occur per unit time, this register is all rewritten to “0” after the unit time has elapsed.

  In step S5, the specific error number counted by the counter in step S4 is compared with the allowable error number range related to the specific error assumed in advance. That is, when ES is the number of errors, ESmin is the minimum value of the assumed error number range, and ESmax is the maximum value of the assumed error number range, it is determined whether ESmin ≦ ES ≦ ESmax. Here, if it is within the range of ESmin ≦ ES ≦ ESmax, the value of the setting register is rewritten in step S7 and the process returns to step S4. If ES <Emin or ESmax <ES, the portion related to the specific error counted fails. In step S6, the self-diagnosis is terminated.

  As described above, in the present embodiment, all minor errors are counted, and when the count value exceeds the allowable range, it is possible to identify which error has occurred and the failure has occurred.

Embodiment 2
FIG. 4 is a diagram showing the self-diagnostic test circuit 103 according to the second embodiment of the present invention. The test circuit according to the second embodiment is a test circuit 103 capable of detecting an infinite loop due to a program error in addition to the above-described minor error. 4, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In this embodiment, in addition to the AND circuits 12A to 12D to which the minor error signal is input in the first embodiment, the input signal is increased in order to count other items. In addition, AND circuits 12E to 12H are added so that other items can be masked.

  When detecting an infinite loop, a signal input to an AND circuit 12G to which an instruction execution flag is input and an AND circuit 12H to which a cache miss flag is input is used. Note that the mask functions of the AND circuits 12A to 12H can be performed with the values set in the setting register as in the first embodiment. FIG. 5 is a flowchart showing an operation for diagnosing whether or not an infinite loop is entered in the present embodiment. The determination operation regarding the presence or absence of an infinite loop in the present embodiment will be described below with reference to FIG.

  In step S51 shown in FIG. 5, the counter is reset, and the counter value is initialized. In this state, the setting register is set so that only the instruction execution count is counted, and the error count is not counted.

  In step S52, the integrated circuit 100 is caused to execute a plurality of instructions that do not fall into an infinite loop. Here, it is assumed that the number and contents of instructions to be executed are predetermined. The instruction performed here is, for example, an addition instruction that does not enter a branch.

  In step S53, the value of the counter is read, and it is compared whether the number of executed instructions matches the value counted by the counter. If the number of instructions executed above matches the count value of the counter, the integrated circuit 100 correctly executes the instructions, and proceeds to the following step S54 assuming that the number is also correctly counted by the self-diagnostic test circuit. If the instruction execution count does not match the count value, it is determined that there is an error in the instruction execution unit such as the CPU 101 or the instruction transmission system.

  In step S54, the setting register is set to a value that does not count other than the number of cache misses, and the instruction used above is again executed by the integrated circuit.

  In step S55, the value of the counter is read to check whether there is a cache miss. In this case, if a cache miss has occurred to some extent, the test circuit assumes that the cache miss has been correctly counted and proceeds to the following steps.

  In step S56, the setting value is written in the setting register so as to measure only the instruction execution number. Thereafter, the integrated circuit 100 is caused to execute a program for confirming the presence or absence of an infinite loop.

  In step S57, the count value of the counter is read and the number of instruction executions is confirmed.

  In step S58, a setting value is written in the setting register so that only the number of cache misses is measured. Thereafter, the integrated circuit is caused to execute a program for confirming the presence or absence of the infinite loop again.

  In step S59, the count value of the counter is read and the number of cache misses is confirmed.

  Here, if the target program includes an infinite loop, the number of instruction executions becomes extremely large, and cache misses are reduced because instructions remain in the cache memory. For this reason, the count value in step S56 increases and the count value in step S58 decreases. In the present embodiment, steps S55 to S58 are performed a plurality of times, and if the difference between the instruction execution number and the cache miss is extremely large in any case, it is determined that the target program includes an infinite loop.

  In the test circuit of this embodiment, the test circuit 103 can further detect a case where the DMA 104 is deadlocked. FIG. 6 is a flowchart showing an operation for diagnosing whether or not DMA is in a deadlock in this embodiment. Hereinafter, the determination operation regarding the presence or absence of deadlock in the present embodiment will be described with reference to FIG.

  In step S61 shown in FIG. 6, the counter is initialized. A setting value for counting only the number of DMA transfers is written in the setting register.

  In step S62, data transfer using DMA is performed at least once. Note that the number of DMA transfers performed here is not necessarily one, and a predetermined number of DMA transfers may be performed.

  In step S63, the counter value is read. If the number of DMA transfers held by the counter is equal to the number of DMA transfers set in advance in step S62, it is determined that the test circuit is operating correctly and accurately counting the number of DMA transfers. If it is different from the preset value, it is determined that there is some error in the part from the DMA 104 to the test circuit or in the test circuit, and the test is interrupted.

In step S64, the counter is initialized. A setting value for counting only the number of accesses to the memory is written in the setting register.
In step S65, the counter value is read and the number of accesses to the memory is confirmed. If the number of accesses to the memory is equal to the preset number of DMA transfers, it is determined that the test circuit operates correctly and accurately counts the number of DMA transfers.

  After that, a value that sets all items to be counted by the counter to the setting register is written.

  In step S66, a program to be evaluated is executed.

  In step S67, the state is again set to count the number of DMA transfers, and in step S68, the count value of the number of DMA transfers after a certain time is confirmed. If the DMA is deadlocked here, the number of transfers from the DMA is zero.

  In step S69, memory access is counted as in step S68. In step S610, the counter value is checked after a predetermined time. From the fact that the number of memory accesses is small, it can be seen that some kind of failure has occurred. In this state, the memory access count of the individual bus master is checked. If the error is reproduced, it is determined in step S611 that the number of memory accesses is less than the expected number in the DMA.

  Further, according to the test circuit of the present embodiment, it is possible to detect more than the integrated circuit 200 that is the communication partner in the integrated circuit 100 that performs communication. FIG. 7 is a flowchart showing a flow when detecting the above-mentioned integrated circuits to be communicated. Hereinafter, an operation of detecting an abnormality in the communication target integrated circuit 200 will be described with reference to FIG.

  In step S71, the counter is initialized. In addition, the setting register is set so that only the occurrence of communication is counted.

  In step S72, communication between the integrated circuits 100 and 200 is executed a preset number of times.

  In step S73, the value of the counter is read out, and it is checked whether the path of the test circuit operates correctly after execution of communication. Here, when the value of the counter matches the number of times set in step S72, it is determined that the path from the communication unit to the counter is operating normally.

  In step S74, a value that sets all items to be counted by the counter to the setting register is written.

  In step S75, a program to be evaluated is executed.

  In step S76, the total number of errors is confirmed. If it is outside the normal range, it can be detected that there is an abnormality.

  In step S77, the setting register is switched to a mode for counting the number of communications per unit time. In step S78, the count value of the number of communications per unit time is confirmed. Here, when the communication part has an abnormality, an unexpected value is shown as the number of communication.

  In step S79, the integrated circuit to be communicated is changed and the same test is repeated.

  In step S710, when the integrated circuit to be communicated is changed to a normal value, it is determined that the integrated circuit 200 to be communicated is abnormal. If an abnormal value is indicated even if the integrated circuit to be communicated is changed, it is determined that the integrated circuit 100 itself is abnormal in the communication unit.

Embodiment 3
In the first embodiment and the second embodiment, an example in which an error location of the integrated circuit itself is specified is shown. However, the test circuit of the present invention can also detect deterioration of the integrated circuit body. FIG. 8 shows a circuit for detecting deterioration of the integrated circuit itself by the inventors. As shown in FIG. 8, the circuit that detects the deterioration of the integrated circuit includes a main body circuit 81, an evaluation circuit 82, and a deterioration detection unit 83. In FIG. 8, a normal operation clock CLK1 is input to the main body circuit 81, and a clock CLK2 having a frequency higher than that of the normal operation clock is input to the evaluation circuit 82. The evaluation circuit 82 that operates with the clock CLK2 having a higher frequency than the clock CLK1 that operates the main circuit 81 deteriorates faster than the main circuit 81. This deterioration appears in the delay of the output signal of the evaluation circuit 82. The deterioration of the evaluation circuit 3 is detected by detecting it using the deterioration detecting unit 83 that detects this delay.

  A plurality of evaluation circuits 82 and deterioration detectors 83 can be provided at arbitrary locations in the circuit. Therefore, as shown in FIG. 9, by inputting a plurality of deterioration detection signals to the input to the test circuit and narrowing down the deterioration portions by the setting register as appropriate, it is possible to specify the portion where the circuit is likely to deteriorate.

It is a block diagram which shows the system with which the self-diagnosis circuit of this invention is applied. It is a figure which shows the structure of the self-diagnosis circuit of this invention. It is a flowchart which shows operation | movement of the self-diagnosis circuit of this invention. It is a figure which shows the structure of the self-diagnosis circuit in the case of detecting an infinite loop. It is a flowchart which shows operation | movement in the case of detecting an infinite loop. It is a flowchart which shows the operation | movement in the case of detecting a DMA deadlock. It is a flowchart which shows the operation | movement in the case of detecting a communication abnormality. It is a figure which shows the structure of the microcomputer etc. in the case of detecting circuit degradation. It is a figure which shows the structure of the self-diagnosis circuit in the case of detecting circuit degradation.

Explanation of symbols

11 Setting register 12A-12D Circuit 12B-12H Mask circuit (AND circuit)
13 OR circuit 14 Counter 81 Body circuit 82 Evaluation circuit 83 Degradation detector 100 Integrated circuit 102 Memory 103 Self-diagnosis circuit (test circuit)
105 Communication Unit 106 Audio Processing Unit 107 Video Processing Unit 108 Input / Output Control Unit 110 Setting Unit 200 Integrated Circuit CLK1 Clock CLK1 Operation Clock CLK2 Clock

Claims (9)

A counter to which a plurality of types of error detection signals generated in the integrated circuit are input;
A self-diagnosis circuit comprising: a setting unit that determines types of error detection signals input to the counter with respect to the plurality of types of error detection signals.   The self-diagnosis circuit according to claim 1, wherein the setting unit includes a mask circuit that masks an error signal input to the counter, and a setting register that sets an operation of the mask circuit.   The self-diagnosis circuit according to claim 2, wherein the mask circuit is an AND circuit.   The self-diagnosis circuit according to any one of claims 1 to 3, wherein the self-diagnosis circuit determines whether or not there is a failure in the integrated circuit based on the number of errors per unit time.   5. The self-diagnosis circuit according to claim 4, wherein the self-diagnosis circuit determines the type of error detection signal masked by the mask circuit based on the number of errors per unit time. The integrated circuit further includes an evaluation circuit to which a clock having a frequency higher than the normal operation clock of the integrated circuit is provided, and a deterioration detection unit that outputs a deterioration detection signal indicating the deterioration of the circuit based on the output of the evaluation circuit. And
6. The self-diagnosis circuit according to claim 1, wherein the deterioration detection signal is input to the counter. A counter to which a plurality of types of error detection signals generated in the integrated circuit are input;
A self-diagnosis method for performing a self-diagnosis of the integrated circuit by a self-diagnosis circuit having a setting unit that determines the type of error detection signal input to the counter with respect to the plurality of types of error detection signals,
Let the integrated circuit execute the program to be evaluated,
Executing setting for extracting instruction execution to the setting unit, obtaining the number of instruction executions executed by the integrated circuit by the counter;
Execute the setting to extract an access miss to the cache memory in the setting unit, obtain the number of access misses to the cache memory by the counter,
A self-diagnosis method for determining the presence or absence of an infinite loop in the evaluation target program based on the number of instructions executed by the integrated circuit and the number of access misses to the cache memory. A counter to which a plurality of types of error detection signals generated in the integrated circuit are input;
A self-diagnosis method for performing a self-diagnosis of the integrated circuit by a self-diagnosis circuit having a setting unit that determines the type of error detection signal input to the counter with respect to the plurality of types of error detection signals,
Data transfer is performed using the direct memory access processing unit in the integrated circuit,
The setting unit is configured to extract the number of accesses to the memory in the integrated circuit, and the counter counts the number of accesses to the memory in the integrated circuit,
A self-diagnosis method for determining an abnormality of a direct memory access processing unit based on a difference between the number of times of data transfer and the number of accesses to the memory. A counter to which a plurality of types of error detection signals generated in the integrated circuit are input;
A self-diagnosis method for performing a self-diagnosis of the integrated circuit by a self-diagnosis circuit having a setting unit that determines the type of error detection signal input to the counter with respect to the plurality of types of error detection signals,
Execute predetermined communication with the target circuit to be the communication target of the integrated circuit,
Based on the evaluation target program, execute communication with the communication target,
Perform setting to extract the number of communication with the communication target based on the evaluation target program in the setting unit, obtain the communication frequency with the communication target based on the evaluation target program by the counter,
A self-diagnosis method for detecting an abnormality of a target circuit or the integrated circuit itself from the number of times of communication with the communication target based on the evaluation target program.

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