JP2009099847A - Thin-film transistor, its manufacturing method, and display device - Google Patents

Thin-film transistor, its manufacturing method, and display device Download PDF

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JP2009099847A
JP2009099847A JP2007271316A JP2007271316A JP2009099847A JP 2009099847 A JP2009099847 A JP 2009099847A JP 2007271316 A JP2007271316 A JP 2007271316A JP 2007271316 A JP2007271316 A JP 2007271316A JP 2009099847 A JP2009099847 A JP 2009099847A
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Tomohiro Watanabe
智大 渡邊
Katsumi Abe
勝美 安部
Susumu Hayashi
享 林
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Canon Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an a-IGZO-based thin-film transistor further stable against electrical stress, and to provide a display device using the same. <P>SOLUTION: The thin-film transistor has an active layer formed of an amorphous oxide prepared by containing In and Zn. In the thin-film transistor, energy for stabilizing an electric characteristic is provided to the active layer after forming the active layer, and the active layer provided with the energy desorbs Zn more than 1.05 times as much as the active layer without being provided with energy, at 200-700°C by a temperature programmed desorption method. The method of manufacturing the thin-film transistor having an active layer formed of an amorphous oxide containing In and Zn includes a step of providing energy for stabilizing an electric characteristic to the active layer after a step of forming the active layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、薄膜トランジスタとその製造方法及び表示装置に係わり、特に、活性層がIn、Znを含み構成されたアモルファス酸化物である薄膜トランジスタとその製造方法及び表示装置に関する。   The present invention relates to a thin film transistor, a manufacturing method thereof, and a display device, and more particularly to a thin film transistor whose active layer is an amorphous oxide including In and Zn, a manufacturing method thereof, and a display device.

近年、有機発光ダイオード(Organic Light Emitting Diode、以下OLEDという)を発光素子とするディスプレイの研究・開発が盛んに行われている。   In recent years, research and development of displays using organic light emitting diodes (Organic Light Emitting Diodes, hereinafter referred to as OLEDs) as light emitting elements have been actively conducted.

OLEDの駆動に用いられている薄膜トランジスタ(Thin Film Transistor、以下TFTという)として、アモルファスSi(Amorphous Si、以下a−Siという)TFTを用いることができる。a−SiTFTは、液晶ディスプレイ(Liquid Crystal Display、以下LCDという)で一般的に用いられている素子であるため、その技術を流用できる利点がある。また、a−SiTFTは、多結晶Si(Poly−crystal Si、以下p−Siという)TFTに比べ、安価で作成可能、かつ、大型化も容易であり、アモルファスであるため均一性が高い。   As a thin film transistor (hereinafter referred to as TFT) used for driving the OLED, an amorphous Si (Amorphous Si; hereinafter referred to as a-Si) TFT can be used. Since the a-Si TFT is an element generally used in a liquid crystal display (hereinafter referred to as LCD), there is an advantage that the technology can be used. Further, the a-Si TFT can be produced at a lower cost and can be easily increased in size and is more uniform because it is amorphous compared to a polycrystalline Si (Poly-crystal Si, hereinafter referred to as p-Si) TFT.

また、近年、透明酸化物半導体(Transparent Oxide Semiconductor、以下TOSという)を活性層として用いたTFTの開発も盛んになってきている。   In recent years, TFTs using transparent oxide semiconductors (Transparent Oxide Semiconductors, hereinafter referred to as TOS) as active layers have been actively developed.

例えば、Zn−Sn−Oを活性層に用いたTFTでは、活性層の成膜後に、400〜600℃にてポストアニールすることで、電界効果移動度が20cm/Vs以上のTFTが得られることが報告されている(非特許文献1)。この特性変化は、Zn−Sn−Oがアモルファスから多結晶に変化することで起きる、と考えられている。 For example, in a TFT using Zn—Sn—O as an active layer, a TFT having a field effect mobility of 20 cm 2 / Vs or more can be obtained by post-annealing at 400 to 600 ° C. after the formation of the active layer. (Non-Patent Document 1). This characteristic change is considered to occur when Zn—Sn—O changes from amorphous to polycrystalline.

ここで、400〜600℃という温度は、ガラス基板の耐熱温度付近で、ディスプレイ向けのTFTとしては扱いにくい。また、プラスチック基板を用いたフレキシブルディスプレイへの適用は困難である。   Here, the temperature of 400 to 600 ° C. is near the heat-resistant temperature of the glass substrate and is difficult to handle as a TFT for display. In addition, it is difficult to apply to a flexible display using a plastic substrate.

また、TFTの活性層向けの別のTOSとして、アモルファスIn−Ga−Zn−O(Amorphous In−Ga−Zn−O、以下a−IGZOという)が提案されている。a−IGZOは、結晶化温度が500℃以上のTOSである。さらに、a−IGZOを活性層として用いたTFTは、室温で成膜したアモルファス状態でも、10cm/Vs程度の高い電界効果移動度と、充分なオン・オフ比が得られている(特許文献1、非特許文献2)。そして、a−IGZOを活性層として用いたTFTは、アモルファス状態であることから、曲げにも強く、フレキシブルディスプレイ用のTFTとしても好適である。
特開2006−165527号公報 R.L. Hoffman, Solid-State Electronics, 2006, Vol. 50, pp. 500-503 Donghun Kang, Chang Jung Kim, Hyuck Lim, Sunil Kim, Jaechul Park, Ihun Song, Eunha Lee, Jaecheol Lee, and Youngsoo Park, TAOS2006, 2006, P2
As another TOS for the active layer of a TFT, amorphous In—Ga—Zn—O (Amorphous In—Ga—Zn—O, hereinafter referred to as a-IGZO) has been proposed. a-IGZO is TOS having a crystallization temperature of 500 ° C. or higher. Furthermore, a TFT using a-IGZO as an active layer has a high field-effect mobility of about 10 cm 2 / Vs and a sufficient on / off ratio even in an amorphous state formed at room temperature (Patent Literature). 1, Non-Patent Document 2). Since a TFT using a-IGZO as an active layer is in an amorphous state, it is resistant to bending and is suitable as a TFT for a flexible display.
JP 2006-165527 A RL Hoffman, Solid-State Electronics, 2006, Vol. 50, pp. 500-503 Donghun Kang, Chang Jung Kim, Hyuck Lim, Sunil Kim, Jaechul Park, Ihun Song, Eunha Lee, Jaecheol Lee, and Youngsoo Park, TAOS2006, 2006, P2

薄膜トランジスタの課題として、電気的ストレスに対する大きなしきい値電圧シフトがある。
アクティブマトリックス(Active Matrix、以下AMという)型OLEDディスプレイ向けのTFTは、AM型LCDに比べ、電気的ストレスに対する安定性がより要求される。
これに対し、a−Si TFTは、長時間の電気的ストレスにより、特性、特にしきい値電圧が大きく変化することがよく知られている。従って、AM型LCDならば問題がなくても、AM型OLEDディスプレイでa−Si TFTを用いるには、この問題を解決することが求められる。
A problem of a thin film transistor is a large threshold voltage shift with respect to electrical stress.
TFTs for active matrix (Active Matrix, hereinafter referred to as AM) type OLED displays are more required to have stability against electrical stress than AM type LCDs.
On the other hand, it is well known that the characteristics, particularly the threshold voltage, of the a-Si TFT changes greatly due to long-term electrical stress. Therefore, even if there is no problem in an AM type LCD, it is required to solve this problem in order to use an a-Si TFT in an AM type OLED display.

一方、a−IGZO系TFTについては、最近研究開発が始まったばかりである。これまでの報告例としては、TFTに室温で3μAの一定電流を100時間かけ続けた場合、しきい値電圧のシフト量が1.6V以下であることが報告されている(非特許文献2)。   On the other hand, the research and development of a-IGZO TFT has just started. As a report example so far, it has been reported that when a constant current of 3 μA is continuously applied to a TFT at room temperature for 100 hours, the threshold voltage shift amount is 1.6 V or less (Non-patent Document 2). .

本発明の薄膜トランジスタは、活性層がIn、Znを含み構成されたアモルファス酸化物である薄膜トランジスタであって、
前記活性層の形成後に前記活性層に電気特性を安定化させるためのエネルギーを付与し、
前記エネルギーを付与した活性層が、前記エネルギーを付与しない活性層に対して、昇温脱離分析により、温度範囲200℃から700℃において1.05倍よりも多いZnを脱離することを特徴とする薄膜トランジスタである。
The thin film transistor of the present invention is a thin film transistor whose active layer is an amorphous oxide composed of In and Zn,
Providing the active layer with energy for stabilizing electrical characteristics after the formation of the active layer;
The active layer imparted with energy desorbs more than 1.05 times Zn in a temperature range of 200 ° C. to 700 ° C. by temperature-programmed desorption analysis with respect to the active layer not imparted with energy. The thin film transistor.

エネルギーは加熱処理により付与されることが望ましい。そして、この加熱処理は大気中で行われ、加熱温度は150℃より高く、281℃未満の温度とすることができる。また、加熱処理は真空中で行われ、加熱温度は150℃より高く、300℃未満の温度とすることができる。   It is desirable to apply energy by heat treatment. And this heat processing is performed in air | atmosphere, and heating temperature can be made into the temperature higher than 150 degreeC and less than 281 degreeC. The heat treatment is performed in a vacuum, and the heating temperature can be higher than 150 ° C. and lower than 300 ° C.

また活性層は、In、Zn及びGaを含むアモルファス酸化物であることが望ましい。   The active layer is preferably an amorphous oxide containing In, Zn, and Ga.

本発明の薄膜トランジスタの製造方法は、活性層がIn,Znを含むアモルファス酸化物で構成された薄膜トランジスタの製造方法であって、前記活性層を形成する工程の後に前記活性層に電気特性を安定化させるためのエネルギーを付与する工程を含むことを特徴とする薄膜トランジスタの製造方法である。   The method of manufacturing a thin film transistor of the present invention is a method of manufacturing a thin film transistor in which an active layer is composed of an amorphous oxide containing In and Zn, and stabilizes electrical characteristics in the active layer after the step of forming the active layer. A method of manufacturing a thin film transistor, comprising a step of applying energy for causing the thin film transistor to be applied.

エネルギーを付与する工程は、活性層の上に接する絶縁層を形成する工程よりも後に行うことが望ましい。また、エネルギーは加熱処理により付与され、加熱温度は前記エネルギーを付与する工程以外の工程での熱処理温度よりも高いことが望ましい。   The step of applying energy is desirably performed after the step of forming the insulating layer in contact with the active layer. Moreover, it is desirable that energy is applied by heat treatment, and the heating temperature is higher than the heat treatment temperature in a process other than the process of applying the energy.

加熱処理は大気中で行われ、加熱温度は150℃より高く、281℃未満の温度とすることができる。また、加熱処理は真空中で行われ、加熱温度は150℃より高く、300℃未満の温度とすることができる。   The heat treatment is performed in the air, and the heating temperature can be higher than 150 ° C. and lower than 281 ° C. The heat treatment is performed in a vacuum, and the heating temperature can be higher than 150 ° C. and lower than 300 ° C.

本発明によれば、電気的ストレス耐性が良好な薄膜トランジスタを実現することができる。 According to the present invention, a thin film transistor having good electrical stress resistance can be realized.

以下に本発明の実施の形態について説明するが、本発明はこれらによって何ら限定されるものではない。   Embodiments of the present invention will be described below, but the present invention is not limited to these embodiments.

本発明者らが、a−IGZO系の半導体を活性層に用いたTFTの電気的ストレス耐性の向上を目的として各種安定化処理を検討した結果、Znがこの特性に深く関与していることを示す実験事実を見出した。   As a result of studying various stabilization treatments for the purpose of improving the electrical stress resistance of a TFT using an a-IGZO-based semiconductor as an active layer, the present inventors have found that Zn is deeply involved in this characteristic. We found experimental facts to show.

実施例1にて、より具体的に説明するが、a−IGZO膜を活性層に用いたTFTにおいて、活性層を大気中で温度範囲200℃から250℃で加熱処理(安定化処理)した場合、200℃未満または250℃より高い温度で安定化処理した場合に対して電気的ストレス耐性が向上する。また、大気中あるいは真空中で200℃から250℃において加熱処理(安定化処理)したa−IGZO単膜は、昇温脱離分析の結果から、200℃未満および250℃より高い温度で加熱処理した場合に対してZnの脱離量が多い。すなわち、電気的ストレス耐性とZnの脱離量とが同じ200℃から250℃で極値をとり、これらの間に相関が認められる。   As will be described in more detail in Example 1, in a TFT using an a-IGZO film as an active layer, when the active layer is heat-treated (stabilized) in the temperature range of 200 ° C. to 250 ° C. The resistance to electrical stress is improved when the stabilization treatment is performed at a temperature lower than 200 ° C. or higher than 250 ° C. In addition, the a-IGZO single film heat-treated (stabilized) at 200 ° C. to 250 ° C. in the air or in vacuum is subjected to heat treatment at temperatures below 200 ° C. and higher than 250 ° C. from the results of thermal desorption analysis. The amount of desorbed Zn is larger than that of the case. That is, the electrical stress resistance and the amount of Zn desorption take the extreme values from 200 ° C. to 250 ° C., and a correlation is observed between these values.

しかし以下に説明するように、大気中では、150℃より高く、281℃未満の温度であれば、電気的ストレスに対する改善が見られ、真空中では150℃より高く、300℃未満の温度であれば電気的ストレスに対する改善が見られる。   However, as will be explained below, in the atmosphere, if the temperature is higher than 150 ° C. and lower than 281 ° C., improvement against electrical stress can be seen. In vacuum, the temperature is higher than 150 ° C. and lower than 300 ° C. For example, improvement against electrical stress can be seen.

Znの脱離量が増加するということは、不安定なZnが多いことを示しており、a−IGZO膜の構造変化に由来しているものと考えられる。   An increase in the amount of desorbed Zn indicates that there is a large amount of unstable Zn, which is considered to be derived from the structural change of the a-IGZO film.

図5にa−IGZO単膜からの、HO分子の昇温脱離分析の結果を示す。膜表面に吸着したHO分子の脱離が200℃程度までに起こり、それ以上、500℃程度までの温度域において、膜中あるいは基板との界面からのHO分子の脱離が起きている。後者の膜中あるいは基板との界面からのHO分子の脱離は、310℃程度に脱離の極大を持っている。 FIG. 5 shows the results of temperature programmed desorption analysis of H 2 O molecules from the a-IGZO single film. Occur desorption of H 2 O molecules adsorbed on the film surface up to about 200 ° C., more, in a temperature range of up to about 500 ° C., occurs desorption of H 2 O molecules from the interface between the film or substrate ing. The desorption of H 2 O molecules from the latter film or from the interface with the substrate has a maximum of desorption at about 310 ° C.

脱離するHO分子の大部分は、膜中あるいは基板との界面ではOH基の形態で存在し、金属イオンに結合していると考えられる。加熱処理を行うと、OH基と金属イオンの結合が切断され、OH基のうちの一部は他のOH基等との反応を経てHO分子として脱離するとともに、残された金属イオンはダングリングボンドを持ち有効電荷の小さな不安定な状態になる。In、GaおよびZnの中ではZnが最も蒸気圧が高いため、昇温脱離分析中において脱離すると推測される。
TFTの電気的ストレスによる特性変化は、本実施形態のTFTを含め、主に、しきい値電圧の変化として現れる。一般的に、TFTのしきい値電圧の変化は、活性層、あるいは、活性層と絶縁膜の界面における電荷状態が変化することに起因する。
Most of the desorbed H 2 O molecules exist in the form of OH groups in the film or at the interface with the substrate, and are considered to be bonded to metal ions. When the heat treatment is performed, the bond between the OH group and the metal ion is cleaved, and a part of the OH group is desorbed as a H 2 O molecule through a reaction with another OH group, and the remaining metal ion. Has a dangling bond and an unstable state with a small effective charge. Since Zn has the highest vapor pressure among In, Ga and Zn, it is presumed to be desorbed during temperature programmed desorption analysis.
The characteristic change due to the electrical stress of the TFT mainly appears as a change in the threshold voltage including the TFT of this embodiment. In general, the change in the threshold voltage of the TFT is caused by a change in the charge state at the active layer or at the interface between the active layer and the insulating film.

従って、a−IGZO膜を活性層とするTFTにおいても、しきい値電圧の変化は、活性層や界面に元々あるトラップ準位や、電気的ストレスにより形成されるトラップ準位にキャリア電子が捕獲されることで生じる、と考えられる。つまり、安定化処理は、トラップ準位を低減する、あるいは、トラップ準位の形成を抑えることで、しきい値電圧の変化を抑制する効果を得ていることになる。さらに、昇温脱離分析の結果から、a−IGZO膜の構造変化がトラップ準位を低減する、あるいは、トラップ準位の形成を抑えることを実現している、と考えられる。   Therefore, even in a TFT having an a-IGZO film as an active layer, the threshold voltage changes due to trapping of carrier electrons in the trap level originally formed in the active layer or the interface or in the trap level formed by electrical stress. It is thought that it is caused by being done. That is, the stabilization process has an effect of suppressing a change in threshold voltage by reducing the trap level or suppressing the formation of the trap level. Furthermore, from the results of temperature programmed desorption analysis, it is considered that the structural change of the a-IGZO film achieves the reduction of trap levels or the suppression of trap level formation.

本実施形態において、エネルギー付与(安定化処理)には必ずしも加熱を必要としない。本実施形態においては、加熱処理の結果としてa−IGZO膜に構造変化を起こさせているが、電気的ストレス耐性が向上するのであれば、その他の処理を用いることができる。活性層にエネルギーを付与する(安定化処理)方法としては、例えば、ホットプレート、炉、レーザー照射および赤外線照射のような加熱を用いる場合や、紫外線照射やX線照射のような加熱を用いない場合が考えられる。   In the present embodiment, heating is not necessarily required for energy application (stabilization treatment). In the present embodiment, the a-IGZO film is structurally changed as a result of the heat treatment, but other treatments can be used as long as the electrical stress resistance is improved. As a method for imparting energy to the active layer (stabilization treatment), for example, heating such as hot plate, furnace, laser irradiation and infrared irradiation is used, or heating such as ultraviolet irradiation and X-ray irradiation is not used. There are cases.

どのような処理であっても、安定化処理を施した活性層が、安定化処理を施さない活性層に対して、昇温脱離分析により、温度範囲200℃から700℃において、1.05倍よりも多くのZnを脱離するような処理であれば良い。   Whatever the treatment, the active layer subjected to the stabilization treatment is compared with 1.05 in the temperature range of 200 ° C. to 700 ° C. by the temperature programmed desorption analysis with respect to the active layer not subjected to the stabilization treatment. Any treatment that desorbs more than twice as much Zn may be used.

実施例1に示すように、安定化処理の手段として温度を用いる場合、安定化処理を施さない場合の1.05倍よりも多くのZnを脱離するのは、150℃よりも高い温度において加熱処理を行う時である。安定化処理を150℃において行ったTFTの電気的ストレス耐性の向上の効果は200℃、250℃における効果に対して1桁程度小さくなっている。また、a−IGZO膜からのZnの脱離量は、安定化処理を施さない膜に比較して、大気中において150℃で加熱処理した場合、脱離量の増加は1.05倍である。さらに、真空中において、150℃で加熱処理した場合、脱離量の増加は1.04倍である(図2および図3)。昇温脱離分析におけるZnの脱離量の精度は多くて5%程度の誤差を含む。従って、150℃において加熱処理したa−IGZO膜からのZnの脱離量よりも脱離量が多い場合に本実施形態の効果を得ることができると考えられる。   As shown in Example 1, when temperature is used as a means for stabilization treatment, more than 1.05 times more Zn is desorbed at a temperature higher than 150 ° C. than when stabilization treatment is not performed. It is time for heat treatment. The effect of improving the electrical stress resistance of the TFT subjected to the stabilization treatment at 150 ° C. is about an order of magnitude smaller than the effect at 200 ° C. and 250 ° C. In addition, the amount of Zn desorbed from the a-IGZO film is 1.05 times the increase in the amount of desorbed when heat-treated at 150 ° C. in the atmosphere as compared to the film not subjected to stabilization treatment. . Furthermore, when heat treatment is performed at 150 ° C. in vacuum, the increase in desorption amount is 1.04 times (FIGS. 2 and 3). The accuracy of Zn desorption amount in temperature programmed desorption analysis includes an error of about 5% at most. Therefore, it is considered that the effect of the present embodiment can be obtained when the amount of desorption is larger than the amount of desorption of Zn from the a-IGZO film heat-treated at 150 ° C.

電気特性の安定化処理として温度を用いる場合、このZnの脱離量が得られる温度範囲で効果が得られるということになる。前記のことから、温度範囲の下限が「150℃よりも高い温度」であることが分かるが、上限を決める必要がある。後の実施例1において詳細を記すが、大気中300℃において加熱処理を行ったa−IGZO膜からのZnの脱離量は、安定化処理を施さない膜に比較して0.64倍であり、250℃における脱離量1.62倍の1/2以下に激減している。また、安定化処理を大気中300℃において行ったTFTの電気的ストレス耐性の向上の効果は250℃における効果に対して低下している。従って、250℃と300℃の間を直線近似し、Znの脱離量が安定化処理を施さない膜と同じになる温度を、電気特性の安定化処理の温度範囲の上とする。計算すると、この温度は281℃になる。すなわち、電気特性の安定化処理として大気中での熱処理を用いる場合、150℃より高く、281℃未満の温度で効果を得ることができる。また、200℃から250℃の温度がより好ましい。   When temperature is used for the stabilization process of the electrical characteristics, the effect is obtained in a temperature range in which the amount of Zn desorption can be obtained. From the above, it can be seen that the lower limit of the temperature range is “temperature higher than 150 ° C.”, but it is necessary to determine the upper limit. As will be described in detail later in Example 1, the amount of Zn desorbed from the a-IGZO film that was heat-treated at 300 ° C. in the atmosphere was 0.64 times that of the film that was not subjected to stabilization treatment. Yes, it is drastically reduced to ½ or less of 1.62 times the desorption amount at 250 ° C. In addition, the effect of improving the electrical stress resistance of the TFT subjected to the stabilization treatment at 300 ° C. in the atmosphere is lower than the effect at 250 ° C. Therefore, the temperature at which 250 ° C. and 300 ° C. are linearly approximated and the amount of Zn desorption is the same as that of the film not subjected to the stabilization treatment is set above the temperature range of the electrical property stabilization treatment. When calculated, this temperature is 281 ° C. That is, when heat treatment in the atmosphere is used as a stabilization process for electrical characteristics, an effect can be obtained at a temperature higher than 150 ° C. and lower than 281 ° C. Moreover, the temperature of 200 to 250 degreeC is more preferable.

一方、真空中300℃において加熱処理を行ったa−IGZO膜からのZnの脱離量は、安定化処理を施さない膜に比較して1.12倍であり、270℃における脱離量1.16倍に比較して減少しているが、安定化処理を施さない膜よりは増加している。従って、安定化処理を施さない膜と同じ脱離量に減少する温度が300℃よりも高いことが分かる。また、300℃よりも高い温度で熱処理する場合、活性層から酸素が脱離し、キャリア濃度が増加することから、TFTが常時オンの状態になる問題が生じる。したがって、真空中で安定化処理を施す場合、300℃を電気特性の安定化処理の温度範囲の上とする。すなわち、電気特性の安定化処理として真空中での熱処理を用いる場合、150℃より高く、300℃未満の温度で効果を得ることができる。また、200℃から250℃の温度がより好ましい。   On the other hand, the desorption amount of Zn from the a-IGZO film subjected to the heat treatment at 300 ° C. in vacuum is 1.12 times that of the film not subjected to the stabilization treatment, and the desorption amount at 270 ° C. is 1 Although it is reduced compared to 16 times, it is higher than that of the film not subjected to the stabilization treatment. Therefore, it can be seen that the temperature at which the desorption amount is the same as that of the film not subjected to the stabilization treatment is higher than 300 ° C. Further, when heat treatment is performed at a temperature higher than 300 ° C., oxygen is desorbed from the active layer and the carrier concentration is increased, which causes a problem that the TFT is always on. Therefore, when the stabilization process is performed in a vacuum, 300 ° C. is set above the temperature range of the stabilization process of the electrical characteristics. That is, when heat treatment in vacuum is used as a stabilization process for electrical characteristics, an effect can be obtained at a temperature higher than 150 ° C. and lower than 300 ° C. Moreover, the temperature of 200 to 250 degreeC is more preferable.

電気特性の安定化処理工程は、活性層を成膜した直後に真空中で行われるか、あるいは活性層を成膜した後から表示装置作製中に行われる。   The electrical property stabilization process is performed in a vacuum immediately after the active layer is formed, or is performed during the manufacture of the display device after the active layer is formed.

素子構成はトップゲートおよびボトムゲートのいずれでも良く、また、それぞれについてトップコンタクトおよびボトムコンタクトのいずれでも良い。したがって、前記電気特性の安定化処理工程を行うタイミングは、前記活性層を成膜した後であれば良く、ソース電極、ドレイン電極、ゲート絶縁膜、ゲート電極、保護膜等の形成後にも行うことができる。   The element configuration may be either a top gate or a bottom gate, and each may be either a top contact or a bottom contact. Accordingly, the timing of performing the electrical property stabilization process may be after the active layer is formed, and also after the source electrode, drain electrode, gate insulating film, gate electrode, protective film, and the like are formed. Can do.

ただし、発明者等の知見に拠れば、薄膜トランジスタの製造工程で電気特性の安定化処理を行う場合、活性層の上に接する絶縁層を形成する工程よりも後に行うことが望ましい。活性層上に絶縁層を形成する際、形成条件によっては活性層に大きなダメージを与えることがある。スパッタ法による保護層の形成の例では中性、並びにイオン化したスパッタ粒子、スパッタガスなどによる衝撃が活性層に与えられるため、形成条件によっては電気特性を含む活性層の特性が大きく変化することが分かっている。安定化処理後に活性層の大きな特性変化が発生し、この変化に伴い電気的ストレスに対する不安定性が発生する場合があるからである。   However, according to the knowledge of the inventors, when the stabilization process of the electrical characteristics is performed in the manufacturing process of the thin film transistor, it is preferable to perform it after the process of forming the insulating layer in contact with the active layer. When an insulating layer is formed on the active layer, the active layer may be greatly damaged depending on the formation conditions. In the example of forming the protective layer by the sputtering method, the active layer is impacted by neutrality and ionized sputtered particles, sputtering gas, etc., and the characteristics of the active layer including electrical characteristics may change greatly depending on the forming conditions. I know it. This is because a large characteristic change of the active layer occurs after the stabilization process, and instability to electrical stress may occur with this change.

また本発明者らの知見によれば、安定化処理を加熱処理により行う場合、該加熱処理における加熱温度は当該安定化処理を行う工程以外の工程での熱処理温度よりも高いことが好ましい。即ち、半導体素子(例えばTFT)を形成する全工程の中で安定化処理工程における加熱温度が最も高いことが好ましい。これは、安定化処理工程時の温度よりも高い温度で熱処理される他の工程が存在すると、安定化処理の効果が低下する場合があるからである。但し、安定化処理時の加熱温度よりも高い温度で処理される工程が他に存在したとしても、当該処理時間が短く、実質的に本発明の活性層に影響を与えない場合には許容される。   Further, according to the knowledge of the present inventors, when the stabilization treatment is performed by heat treatment, the heating temperature in the heat treatment is preferably higher than the heat treatment temperature in steps other than the step of performing the stabilization treatment. That is, it is preferable that the heating temperature in the stabilization process is the highest among all processes for forming a semiconductor element (for example, TFT). This is because if there is another process that is heat-treated at a temperature higher than the temperature during the stabilization process, the effect of the stabilization process may be reduced. However, even if there is another process that is processed at a temperature higher than the heating temperature during the stabilization process, the process time is short, and it is acceptable if it does not substantially affect the active layer of the present invention. The

特許文献1では、a−IGZO膜を、酸素を含む雰囲気中において、0℃から300℃、より好ましくは100℃から200℃の熱処理により、酸素欠損量、つまり、キャリア密度を1018(/cm)以下に制御することが開示されている。 In Patent Document 1, an a-IGZO film is subjected to a heat treatment at 0 ° C. to 300 ° C., more preferably 100 ° C. to 200 ° C. in an oxygen-containing atmosphere, whereby the amount of oxygen vacancies, that is, the carrier density is 10 18 (/ cm 3 ) The following control is disclosed.

a−IGZO膜に、大気中で120℃から350℃の熱処理を行った時の導電率の変化を図4に示す。   FIG. 4 shows the change in conductivity when the a-IGZO film is heat-treated at 120 ° C. to 350 ° C. in the atmosphere.

ここで、図4の横軸は加熱温度、縦軸は導電率である。また、非熱処理膜の導電率を、加熱温度が50℃の点に示す。   Here, the horizontal axis in FIG. 4 is the heating temperature, and the vertical axis is the conductivity. In addition, the electrical conductivity of the non-heat-treated film is shown at the point where the heating temperature is 50 ° C.

測定に用いた試料の作製法を以下に示す。基板として熱Si酸化膜が表面に形成された単結晶Siを用いた。単結晶Siは、リンが高濃度でドープされ、n型に低抵抗化してある。また、熱Si酸化膜は、膜厚約100nmである。次に、a−IGZOの酸化物半導体膜をRFスパッタ装置にて成膜した。成膜時の基板温度は室温であり、ターゲットにはIn:Ga:Zn:Oの組成比が1:1:1:4のものを用いた。成膜時のRFパワーを200Wとし、O2分圧5%のAr雰囲気中で、圧力0.5Paでスパッタを行った。成膜時間を調整することで、膜厚を20nmとした。別に、同じ条件で成膜した薄膜の薄膜X線回折測定(入射角 0.5度)を行ったところ、明瞭な回折ピークは認められなかったことから、作製したIn-Ga-Zn-O系薄膜はアモルファスであるといえる。 A method for preparing the sample used for the measurement is shown below. Single-crystal Si having a thermal Si oxide film formed on the surface was used as the substrate. Single-crystal Si is doped with phosphorus at a high concentration and has a low resistance to n-type. The thermal Si oxide film has a thickness of about 100 nm. Next, an oxide semiconductor film of a-IGZO was formed using an RF sputtering apparatus. The substrate temperature during film formation was room temperature, and a target having an In: Ga: Zn: O composition ratio of 1: 1: 1: 4 was used. Sputtering was performed at a pressure of 0.5 Pa in an Ar atmosphere with an RF power of 200 W during film formation and an O 2 partial pressure of 5%. The film thickness was set to 20 nm by adjusting the film formation time. Separately, when a thin film X-ray diffraction measurement (incidence angle of 0.5 degree) of a thin film formed under the same conditions was performed, no clear diffraction peak was observed, so the produced In-Ga-Zn-O thin film was It can be said that it is amorphous.

上記成膜法の成膜時間を変えることで、膜厚20nmと40nmのa−IGZO膜が得られた。   By changing the film formation time of the film formation method, a-IGZO films having a film thickness of 20 nm and 40 nm were obtained.

続いて、メタルマスクを用いて、電極をパターニングした。電極材料としてはAuを用い、電子ビーム真空蒸着法によりTiを約5nm成膜後、Auを約40nm成膜した。
作成した膜の電気導電率の測定には、電極のコンタクト性の影響を受けず、a−IGZO膜自体の特性を得るため、4つの電極を用いた4端子測定を用いた。電極の幅は0.4mm、長さは6mm、電極間の間隔は、0.4mmである。
Subsequently, the electrode was patterned using a metal mask. Au was used as the electrode material, and after depositing about 5 nm of Ti by electron beam vacuum deposition, about 40 nm of Au was deposited.
In measuring the electrical conductivity of the prepared film, 4-terminal measurement using four electrodes was used in order to obtain the characteristics of the a-IGZO film itself without being affected by the contact property of the electrodes. The width of the electrodes is 0.4 mm, the length is 6 mm, and the distance between the electrodes is 0.4 mm.

導電率の測定は、すべて、室温、大気中、暗所で行った。   All conductivity measurements were performed at room temperature, in the air, and in the dark.

導電率を測定後、加熱処理する。加熱温度は120℃、加熱時間は20分である。加熱後、4端子測定により、導電率測定を行った。さらに、加熱温度を、150℃、200℃、250℃、300℃、350℃とし、同様に導電率測定を行った。   After measuring the conductivity, heat treatment is performed. The heating temperature is 120 ° C. and the heating time is 20 minutes. After heating, the conductivity was measured by 4-terminal measurement. Furthermore, the heating temperature was set to 150 ° C., 200 ° C., 250 ° C., 300 ° C., and 350 ° C., and the conductivity was measured in the same manner.

非熱処理膜の膜厚20nmの導電率が9.4×10−7(S/cm)、40nmの導電率が4.5×10−7(S/cm)であった。 The conductivity of the non-heat-treated film at a thickness of 20 nm was 9.4 × 10 −7 (S / cm), and the conductivity at 40 nm was 4.5 × 10 −7 (S / cm).

加熱温度が120℃、150℃の場合、導電率の変化は1桁程度であった。
加熱温度が200℃になると、膜厚20nm、40nm共に、3桁以上の急激な導電率の増加が見られた。導電率は、どちらの膜厚でも、4×10−2(S/cm)となった。
When the heating temperature was 120 ° C. and 150 ° C., the change in conductivity was about one digit.
When the heating temperature reached 200 ° C., a rapid increase in conductivity of 3 digits or more was observed for both film thicknesses of 20 nm and 40 nm. The conductivity was 4 × 10 −2 (S / cm) regardless of the film thickness.

250℃加熱処理を行うと、膜厚20nmでは導電率が2桁程度低下する。膜厚40nmの場合、さらに1桁増加し、4×10−1(S/cm)という最大値をとった。
300℃以上の加熱処理を行うと、膜厚20nm、40nmのどちらにおいても、導電率が低下し、非処理膜の導電率の違いは、2桁以下と小さくなった。
以上のように、加熱処理による導電率変化に膜厚依存性があることから、上記導電率変化は、半導体と大気との界面付近の変化ではなく、膜全体での酸素欠損量の変化に起因していると考えられる。
一方、本実施形態のTFTにおいて200℃から250℃の安定化処理を行うと、電気的ストレスによるTFTの特性変化が減少し、電気的ストレスに対する耐性が向上する。これは、前述の考察より、活性層、あるいは界面のトラップ準位が減少する、あるいはトラップ準位の形成が抑制されるため、と考えられる。TFTの作製方法および測定手段については後述の実施例に示すものである。
When heat treatment is performed at 250 ° C., the conductivity decreases by about two orders of magnitude at a film thickness of 20 nm. In the case of a film thickness of 40 nm, it increased by an order of magnitude and took the maximum value of 4 × 10 −1 (S / cm).
When heat treatment at 300 ° C. or higher was performed, the conductivity decreased at both the film thickness of 20 nm and 40 nm, and the difference in conductivity of the non-processed film was as small as two digits or less.
As described above, since the change in conductivity due to heat treatment is dependent on the film thickness, the above change in conductivity is not due to a change near the interface between the semiconductor and the atmosphere, but due to a change in the amount of oxygen vacancies in the entire film. it seems to do.
On the other hand, when the stabilization process at 200 ° C. to 250 ° C. is performed on the TFT of this embodiment, the change in TFT characteristics due to electrical stress is reduced, and resistance to electrical stress is improved. This is presumably because the trap level at the active layer or the interface is reduced or the formation of the trap level is suppressed from the above consideration. The TFT production method and measurement means will be described in the examples described later.

また、活性層であるa−IGZO単膜の導電率が同程度の、安定化処理を施さないTFTと、大気中において300℃の安定化処理を施したTFTとにおいて、単膜の導電率が同程度あることから、2つのTFTのa−IGZO膜のキャリア密度、つまり酸素欠損量が同程度であると考えられる。しかし、300℃の安定化処理を施したTFTでは、電気的ストレス前後のしきい値変化が、安定化処理を行わないTFTの1/10程度となる。これは、酸素欠損量が同程度でも、安定化処理の有無により、電気的ストレスに対する耐性が異なることを示している。
従って、キャリアの起源の酸素欠損と、電気的ストレスによる特性変化の起源のトラップ準位は、同一のものでない、と結論づけられる。
In addition, the conductivity of the a-IGZO single film that is the active layer is about the same as that of the TFT that is not subjected to stabilization treatment and the TFT that is subjected to stabilization treatment at 300 ° C. in the atmosphere. From the same level, it is considered that the carrier density of the a-IGZO films of the two TFTs, that is, the amount of oxygen vacancies is the same level. However, in the TFT subjected to the stabilization process at 300 ° C., the threshold change before and after the electrical stress is about 1/10 of that of the TFT not subjected to the stabilization process. This shows that the resistance to electrical stress varies depending on the presence or absence of the stabilization treatment even when the amount of oxygen deficiency is similar.
Therefore, it can be concluded that the oxygen deficiency of the carrier origin and the trap level of the origin of the characteristic change due to electrical stress are not the same.

また、本実施形態において、大気中200℃、真空中200℃のいずれの安定化処理においても、TFTの電気的ストレスに対する耐性の向上に有効である。この場合、温度が有効なのであって、酸素を含む雰囲気は必ずしも必要としない。よって、大気中、真空中、減圧下の雰囲気中、Ar雰囲気等の非酸化雰囲気中で安定化処理をおこなってもよい。大気中、Ar雰囲気等の非酸化雰囲気中又は減圧下の雰囲気で安定化処理を行う場合には、150℃より高く、281℃未満の温度とすることが好ましい。
また、今回の結果を含め、一般に、酸素欠損の存在はトラップ準位の原因となる可能性はあるが、TFTの導電率と電気的ストレス耐性の傾向が一致しないことから、本実施形態の安定化処理は、酸素欠損をコントロールしているものではない。さらに、最も好ましい温度範囲が特許文献1に示されている温度範囲と異なることも、酸素欠損と電気的ストレス耐性の向上の起源が異なることを傍証するものである。
以上より、本実施形態の安定化処理は、特許文献1で行われている酸素欠損量の制御とは直接の因果関係がないと考えられる。
In this embodiment, any stabilization treatment at 200 ° C. in the air or 200 ° C. in a vacuum is effective in improving the resistance of the TFT to electrical stress. In this case, the temperature is effective, and an atmosphere containing oxygen is not necessarily required. Therefore, the stabilization treatment may be performed in the air, in a vacuum, in an atmosphere under reduced pressure, or in a non-oxidizing atmosphere such as an Ar atmosphere. When the stabilization treatment is performed in air, a non-oxidizing atmosphere such as an Ar atmosphere, or an atmosphere under reduced pressure, the temperature is preferably higher than 150 ° C. and lower than 281 ° C.
In addition, including the results of this time, the presence of oxygen vacancies generally may cause trap levels, but the TFT conductivity and the tendency of electrical stress resistance do not match, so the stability of this embodiment is stable. The chemical treatment does not control oxygen deficiency. Furthermore, the fact that the most preferable temperature range is different from the temperature range shown in Patent Document 1 also proves that the origin of improvement in oxygen deficiency and electrical stress resistance is different.
From the above, it is considered that the stabilization process of the present embodiment does not have a direct causal relationship with the control of the oxygen deficiency amount performed in Patent Document 1.

活性層の材料としてはInとZnを含む酸化物であれば良いが、In、Zn及びGaを含み構成される酸化物が好ましい。また、室温成膜が可能であり、素子間のバラつきが少なく、フレキシブルディスプレイへの適用が期待できることから、アモルファスであることが好ましい。   The active layer may be made of an oxide containing In and Zn, but an oxide containing In, Zn and Ga is preferable. In addition, since it can be formed at room temperature, there is little variation between elements, and application to a flexible display can be expected, it is preferably amorphous.

また、活性層は透明であることが好ましい。この場合、トランジスタの各構成部材に同じく透明な材料を用いることで、透明トランジスタとすることができ、ディスプレイに適用する際の開口率を向上させることができる。
また、前記活性層をアモルファスとするとともに、高分子基板等のフレキシブル基板を用い、さらにトランジスタの各構成部材に同じくアモルファス材料を用いることで、フレキシブルトランジスタを構成することができる。
The active layer is preferably transparent. In this case, by using the same transparent material for each component of the transistor, a transparent transistor can be obtained, and the aperture ratio when applied to a display can be improved.
In addition, a flexible transistor can be formed by making the active layer amorphous, using a flexible substrate such as a polymer substrate, and further using an amorphous material for each component of the transistor.

トランジスタの各構成部材の成膜手法としては、スパッタ法、真空蒸着法、イオンプレーティング法、ディップ法、CVD法、MOCVD法、PCVD法等がある。この内、本実施形態が特に効果的であるのは、300℃以下の低温において成膜を行う場合であり、均一大面積成膜に適しているスパッタ法が好ましい。   As a method for forming each component of the transistor, there are a sputtering method, a vacuum deposition method, an ion plating method, a dip method, a CVD method, an MOCVD method, a PCVD method, and the like. Among these, this embodiment is particularly effective when the film is formed at a low temperature of 300 ° C. or lower, and a sputtering method suitable for uniform large-area film formation is preferable.

絶縁層として好ましいのは、Al2O3、SiO2、SiON、SiN、Si3N4の内の少なくとも1つ、または少なくとも1つを含む複合酸化物または複合酸窒化物である。また、比誘電率が高い、Sc2O3、TiO2、ZnO、Ga2O3、SrO、Y2O3、ZrO2、In2O3、SnO、BaO、La2O3、Pr2O3、Gd2O3、Yb2O3、HfO2、Ta2O3、PbO、Bi2O3の内の少なくとも1つを絶縁層として用いることも好ましい形態である。 The insulating layer is preferably a composite oxide or a composite oxynitride containing at least one of Al 2 O 3 , SiO 2 , SiON, SiN, and Si 3 N 4 , or at least one. Also, the relative dielectric constant is high, Sc 2 O 3 , TiO 2 , ZnO, Ga 2 O 3 , SrO, Y 2 O 3 , ZrO 2 , In 2 O 3 , SnO, BaO, La 2 O 3 , Pr 2 O It is also preferable to use at least one of 3 , Gd 2 O 3 , Yb 2 O 3 , HfO 2 , Ta 2 O 3 , PbO, and Bi 2 O 3 as an insulating layer.

基板としては、例えば、石英ガラスやSi基板、セラミックス等があるが、例えば、ポリイミド、ポリエステル、その他の高分子材料、ガラス類、布類、紙類等をフレキシブル基板として使用することもできる。本実施形態が特に効果的であるのは、基板の材質の変質や、成膜中の活性層や絶縁層との熱膨張差等が問題となり、300℃以下の低温で成膜する場合である。   Examples of the substrate include quartz glass, Si substrate, and ceramics. For example, polyimide, polyester, other polymer materials, glass, cloth, paper, and the like can be used as the flexible substrate. This embodiment is particularly effective in the case where the film is formed at a low temperature of 300 ° C. or lower due to problems such as a change in the material of the substrate and a difference in thermal expansion from the active layer or the insulating layer during the film formation. .

電極としては、Au、Ti、Ni、In、Sn、Zn、Cu、Ag等やこれらの内少なくとも1つを含む合金や酸化物がある。
素子構成はトップゲートおよびボトムゲートのいずれでも良く、また、それぞれについてトップコンタクトおよびボトムコンタクトのいずれでも良い。
Examples of the electrode include Au, Ti, Ni, In, Sn, Zn, Cu, and Ag, and alloys and oxides including at least one of them.
The element configuration may be either a top gate or a bottom gate, and each may be either a top contact or a bottom contact.

以上のように電気特性の安定化処理を施した薄膜トランジスタは、電気的ストレスに対する安定性が向上し、そのソース電極またはドレイン電極を表示素子の電極に接続することで経時安定性に優れた表示装置とすることができる。   As described above, the thin film transistor subjected to the stabilization process of electrical characteristics has improved stability against electrical stress, and the display device has excellent temporal stability by connecting the source electrode or the drain electrode to the electrode of the display element. It can be.

また、前記のとおり、最もその効果が期待できるのは、表示装置がOLED素子を用いたディスプレイの場合である。   Further, as described above, the effect can be most expected when the display device is a display using an OLED element.

以下に本発明の実施例について図面を用いて説明するが、本発明はこれらによって何ら限定されるものではない。   Embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited thereto.

本発明の第1の実施例について、以下に説明する。   A first embodiment of the present invention will be described below.

本実施例において、図1に示すように、TFTの作成には、基板1として熱Si酸化膜2が表面に形成された単結晶Siを用いた。単結晶Siは、リンが高濃度でドープされ、n型に低抵抗化してある。TFTにおいて、前記低抵抗化された単結晶Siがゲート電極となる。また、熱Si酸化膜は、膜厚約100nmであり、TFTのゲート絶縁膜となる。   In this embodiment, as shown in FIG. 1, single-crystal Si having a thermal Si oxide film 2 formed on the surface was used as the substrate 1 for the production of the TFT. Single-crystal Si is doped with phosphorus at a high concentration and has a low resistance to n-type. In the TFT, the low-resistance single crystal Si serves as a gate electrode. Further, the thermal Si oxide film has a thickness of about 100 nm and becomes a gate insulating film of the TFT.

次に、活性層3としてa−IGZOの酸化物半導体膜をRFスパッタ装置にて成膜した。成膜時の基板温度は室温であり、ターゲットにはIn:Ga:Zn:Oの組成比が1:1:1:4のものを用いた。これは、カチオン比でIn:Zn:Ga=1:1:1のターゲットとなる。基板は、パワーを200Wとし、O2分圧5%のAr雰囲気中で、圧力0.5Paでスパッタを行った。成膜時間を調整することで、膜厚を20nmとした。ここで、本例とは別に、同じ条件で成膜した薄膜の薄膜X線回折測定(入射角 0.5度)を行ったところ、明瞭な回折ピークは認められなかったことから、作製したIn-Ga-Zn-O系薄膜はアモルファスであるといえる。 Next, an a-IGZO oxide semiconductor film was formed as the active layer 3 using an RF sputtering apparatus. The substrate temperature during film formation was room temperature, and a target having an In: Ga: Zn: O composition ratio of 1: 1: 1: 4 was used. This is a target with a cation ratio of In: Zn: Ga = 1: 1: 1. The substrate was sputtered at a pressure of 0.5 Pa in an Ar atmosphere with a power of 200 W and an O 2 partial pressure of 5%. The film thickness was set to 20 nm by adjusting the film formation time. Here, apart from this example, thin film X-ray diffraction measurement (incident angle 0.5 degree) of a thin film formed under the same conditions was performed, and no clear diffraction peak was observed. It can be said that the -Zn-O thin film is amorphous.

その後、ウェットエッチングにより、a−IGZO膜をパターニングした。   Thereafter, the a-IGZO film was patterned by wet etching.

まず、レジスト成膜・乾燥後、フォトリソグラフィーによりパターンを開口した。本工程で開口するのは、a−IGZO膜を取り去る領域である。その後、希塩酸によりウェットエッチングして、必要とする領域以外のa−IGZO膜を取り去った。これにより、活性層となるa−IGZO膜がパターニングできた。   First, after the resist film was formed and dried, a pattern was opened by photolithography. Opening in this step is a region where the a-IGZO film is removed. Thereafter, wet etching was performed with dilute hydrochloric acid to remove the a-IGZO film other than the necessary region. Thereby, the a-IGZO film used as an active layer was patterned.

本工程までの最高温度は、乾燥温度120℃であった。
ここで、a−IGZO膜の安定化処理として、大気中での加熱処理を実施した。加熱処理時間は20分とした。ただし、安定化の効果の違いを得るために、温度を150℃、200℃、250℃、300℃の4点条件振りを行った。
The maximum temperature up to this step was a drying temperature of 120 ° C.
Here, heat treatment in the atmosphere was performed as stabilization treatment of the a-IGZO film. The heat treatment time was 20 minutes. However, in order to obtain a difference in stabilization effect, the temperature was changed at four points of 150 ° C., 200 ° C., 250 ° C., and 300 ° C.

次に、ソース、ドレイン電極10、11をリフトオフ法により形成した。   Next, the source and drain electrodes 10 and 11 were formed by a lift-off method.

まず、レジスト成膜・乾燥後、フォトリソグラフィーにより、ソース、ドレイン電極に相当するパターンを開口した。その後、Ti層4、Au層5をこの順番で電子ビーム真空蒸着法により成膜した。Tiの膜厚は約5nm、Auの膜厚は約40nmであった。この後、レジストを剥離し、不必要なTi、Au膜を取り去ることで、ソース、ドレイン電極が形成できた。   First, after forming and drying the resist, patterns corresponding to the source and drain electrodes were opened by photolithography. Thereafter, a Ti layer 4 and an Au layer 5 were formed in this order by an electron beam vacuum deposition method. The film thickness of Ti was about 5 nm, and the film thickness of Au was about 40 nm. Thereafter, the resist was peeled off, and unnecessary Ti and Au films were removed to form source and drain electrodes.

安定化処理を除く、すべての工程における最高温度は、成膜中の基板温度、並びに乾燥温度であり、約120℃であった。   The maximum temperature in all steps except the stabilization treatment was the substrate temperature during film formation and the drying temperature, which was about 120 ° C.

以上のプロセスにより、図1に示すような、a−IGZO膜を活性層とするボトムゲート−トップコンタクト型のTFTが形成できた。   Through the above process, a bottom gate-top contact type TFT having an a-IGZO film as an active layer as shown in FIG. 1 was formed.

以下での電気的測定は、すべて、室温、大気雰囲気中、暗所で行った。   The following electrical measurements were all performed at room temperature, in an air atmosphere and in the dark.

本実施例におけるTFT(W/L=180μm/30μm)の初期特性は、Vds=12Vにおいて、電界効果移動度が7.1cm/Vs、しきい値電圧が6.4Vであった。 The initial characteristics of the TFT in this example (W / L = 180 μm / 30 μm) were a field effect mobility of 7.1 cm 2 / Vs and a threshold voltage of 6.4 V when Vds = 12 V.

上記のTFTに電気的ストレスを印加して、そのストレスに対する耐性を調べた。電気的ストレスの条件は、2つある。条件1は、ゲート電極に12V、ドレイン電極に6Vを800秒間印加する条件とし、条件2は、ゲート電極に20V、ドレイン電極に20Vを800秒間印加する条件とした。   An electrical stress was applied to the TFT and the resistance to the stress was examined. There are two conditions for electrical stress. Condition 1 was a condition in which 12V was applied to the gate electrode and 6V was applied to the drain electrode for 800 seconds, and condition 2 was a condition in which 20V was applied to the gate electrode and 20V was applied to the drain electrode for 800 seconds.

これら2つのストレス印加を行う前後での、TFTのしきい値電圧変化より、ストレス耐性を調べた。その結果を図6に示す。ここで、(しきい値電圧変化)=(ストレス後のしきい値電圧)−(ストレス前のしきい値電圧)とする。   The stress tolerance was examined from the change in the threshold voltage of the TFT before and after applying these two stresses. The result is shown in FIG. Here, (threshold voltage change) = (threshold voltage after stress) − (threshold voltage before stress).

この結果、条件1、2によらず、後述する比較例の120℃から、200℃までの加熱処理では、徐々に電気的ストレスに対する耐性が増加し、200℃から250℃の加熱処理により、最も耐性が高い状態になった。一方、300℃の加熱処理を行うと耐性が下がった。
従って、200℃から250℃の加熱処理(安定化処理)を加えることで、電気的ストレスに対する耐性が高いTFTを獲得することができた。
As a result, irrespective of the conditions 1 and 2, in the heat treatment from 120 ° C. to 200 ° C. in the comparative example described later, the resistance to electrical stress gradually increases, and the heat treatment from 200 ° C. to 250 ° C. High tolerance. On the other hand, when the heat treatment at 300 ° C. was performed, the resistance decreased.
Therefore, by applying a heat treatment (stabilization treatment) at 200 ° C. to 250 ° C., it was possible to obtain a TFT having high resistance to electrical stress.

上記温度範囲は、ガラス基板の耐熱温度に比べ十分低いため、ガラス基板上のTFTの安定化処理として適用することが可能である。また、プラスチック基板でも、ポリイミドなどを用いた基板では、耐熱温度以下となり、適用できる。さらに、ステンレス製基板を用い、トップエミッション型のOLEDディスプレイを構成する場合にも、本処理は適用することが可能である。   Since the above temperature range is sufficiently lower than the heat resistant temperature of the glass substrate, it can be applied as a stabilization process for TFTs on the glass substrate. Further, even a plastic substrate can be used because it is lower than the heat-resistant temperature in a substrate using polyimide or the like. Furthermore, this process can be applied to the case where a top emission type OLED display is configured using a stainless steel substrate.

TFTの作製とは別に、a−IGZO系の酸化物半導体をRFスパッタ装置にて熱Si酸化膜が表面に形成された単結晶Si基板上に成膜した。成膜条件はTFTの活性層と同じ条件を用いた。成膜時間を調整することで、膜厚を20nmとした。   Separately from the fabrication of the TFT, an a-IGZO-based oxide semiconductor was formed on a single crystal Si substrate having a thermal Si oxide film formed on the surface by an RF sputtering apparatus. The same film formation conditions as those for the active layer of the TFT were used. The film thickness was set to 20 nm by adjusting the film formation time.

成膜後に大気中において加熱処理を行い、その後に昇温脱離測定を行った。加熱温度としては、150℃、200℃、250℃、300℃とし、それぞれ別の基板を20分間加熱した。   After film formation, heat treatment was performed in the atmosphere, and then temperature programmed desorption measurement was performed. The heating temperatures were 150 ° C., 200 ° C., 250 ° C., and 300 ° C., and each of the different substrates was heated for 20 minutes.

昇温脱離測定は基板表面に接触させた熱電対の温度で約50℃から700℃まで、毎分60℃の昇温測定を行った。   Thermal desorption measurement was performed at a temperature of 60 ° C. per minute from about 50 ° C. to 700 ° C. at the temperature of a thermocouple brought into contact with the substrate surface.

脱離したガス種の内、Znに関する図を、図7に示す。比較のために非熱処理膜、120℃および350℃で20分間熱処理した膜の結果も加えた。ここで、横軸は前記の基板表面に接触させた熱電対の温度であり、縦軸は四重極質量分析計によって測定した質量数64のイオン強度である。   FIG. 7 shows a diagram relating to Zn among the desorbed gas species. For comparison, the results of a non-heat-treated film and a film heat-treated at 120 ° C. and 350 ° C. for 20 minutes were also added. Here, the horizontal axis represents the temperature of the thermocouple brought into contact with the substrate surface, and the vertical axis represents the ionic strength of mass number 64 measured by a quadrupole mass spectrometer.

脱離したガス種がZnであるか否かは、質量数64、66および68のZnのイオン強度が同位対比に応じ、同期して変化していることから確認できた。 Whether or not the desorbed gas species is Zn can be confirmed from the fact that the ion intensity of Zn + of mass numbers 64, 66 and 68 changes synchronously according to the isotope ratio.

図7から、Znは260℃程度で脱離を開始し、600℃付近で脱離が終了していることが分かった。600℃以上の温度においては、脱離が認められなかった。また、260℃以下にもわずかな脱離が認められた。   From FIG. 7, it was found that Zn started to desorb at about 260 ° C. and desorbed at about 600 ° C. Desorption was not observed at a temperature of 600 ° C. or higher. In addition, slight desorption was observed at 260 ° C. or lower.

Znの脱離量の積分イオン強度を、安定化処理を施さない膜を1とし、加熱処理温度に対してプロットした図を図8に示す。また、安定化処理を施さない膜からのZnの脱離量を、加熱温度が20℃の点に示す。   FIG. 8 shows a plot of the integrated ionic strength of the desorption amount of Zn with respect to the heat treatment temperature, assuming that the film not subjected to the stabilization treatment is 1. In addition, the amount of Zn desorbed from the film not subjected to the stabilization treatment is shown at the point where the heating temperature is 20 ° C.

加熱温度が150℃の場合、Znの脱離の積分イオン強度は、安定化処理を施さない膜に対して1.05倍であった。   When the heating temperature was 150 ° C., the integrated ionic strength of Zn desorption was 1.05 times that of the film not subjected to the stabilization treatment.

加熱温度が200℃に上昇すると、Znの脱離量は急増し、1.48倍となった。   When the heating temperature was increased to 200 ° C., the amount of Zn desorbed increased rapidly and became 1.48 times.

加熱温度が250℃に上昇すると、さらにZnの脱離量が増加し、1.62倍となった。   When the heating temperature was increased to 250 ° C., the amount of Zn desorbed further increased to 1.62 times.

しかしながら、加熱温度が300℃に上昇すると、Znの脱離量は急減し、0.64倍となった。   However, when the heating temperature increased to 300 ° C., the amount of Zn desorbed rapidly decreased to 0.64 times.

加熱温度が350℃に上昇すると、さらにZnの脱離量が減少し、0.42倍となった。   When the heating temperature was raised to 350 ° C., the amount of Zn desorbed further decreased and became 0.42 times.

すなわち、このZnの脱離量の加熱温度依存性は、前記の導電率の加熱温度依存性と同様に、150℃から200℃で急増し、250℃から300℃で急減していることが分かった。
[比較例1]
本発明の比較例1を以下に説明する。
That is, it is understood that the heating temperature dependence of the amount of desorbed Zn increases rapidly from 150 ° C. to 200 ° C. and decreases rapidly from 250 ° C. to 300 ° C., similar to the heating temperature dependence of the conductivity. It was.
[Comparative Example 1]
Comparative Example 1 of the present invention will be described below.

本比較例において、安定化処理を行っていない以外は、実施例1と同様の方法により作製したTFTを使用した。   In this comparative example, a TFT manufactured by the same method as in Example 1 was used except that the stabilization treatment was not performed.

すべての工程における最高温度は、成膜中の基板温度、並びに乾燥温度であり、共に約120℃であった。   The maximum temperature in all steps was the substrate temperature during film formation and the drying temperature, both of which were about 120 ° C.

以下での電気的測定は、すべて、室温、大気雰囲気中、暗所で行った。   The following electrical measurements were all performed at room temperature, in an air atmosphere and in the dark.

本比較例におけるTFT(W/L=180μm/30μm)の初期特性は、Vds=12Vにおいて、電界効果移動度が7.1cm/Vs、しきい値電圧が6.4Vであった。 The initial characteristics of the TFT (W / L = 180 μm / 30 μm) in this comparative example were a field effect mobility of 7.1 cm 2 / Vs and a threshold voltage of 6.4 V at Vds = 12V.

実施例1と同様に、上記のTFTに電気的ストレスを印加して、そのストレスに対する耐性を調べた。電気的ストレスの条件は、実施例1と同様である。
これら2つのストレス印加を行う前後での、TFTのしきい値電圧変化より、ストレス耐性を調べた。その結果を図6に示す。ただし、本比較例は、TFT形成プロセスの最高温度が120℃であるため、120℃の点にデータをプロットした。条件1および条件2の内容は実施例1と同じである。また、しきい値電圧変化の定義は、実施例1と同じである。
[比較例2]
本比較例において、比較例1と同様の方法により作製したTFTを使用した。ただし、本比較例におけるa−IGZO膜の膜厚は40nmとした。
In the same manner as in Example 1, an electrical stress was applied to the TFT, and the resistance to the stress was examined. The conditions for electrical stress are the same as in Example 1.
The stress tolerance was examined from the change in the threshold voltage of the TFT before and after applying these two stresses. The result is shown in FIG. However, since the maximum temperature of the TFT forming process is 120 ° C. in this comparative example, the data is plotted at a point of 120 ° C. The contents of condition 1 and condition 2 are the same as those in the first embodiment. The definition of the threshold voltage change is the same as in the first embodiment.
[Comparative Example 2]
In this comparative example, a TFT manufactured by the same method as in Comparative Example 1 was used. However, the film thickness of the a-IGZO film in this comparative example was 40 nm.

以下での電気的測定は、すべて、室温、暗所で行った。   All electrical measurements below were performed at room temperature in the dark.

本比較例の大気雰囲気中でのTFT(W/L=300μm/50μm)の初期特性は、Vds=12Vにおいて、電界効果移動度が8.5cm/Vs、しきい値電圧が7.1Vであった。 The initial characteristics of the TFT (W / L = 300 μm / 50 μm) in the air atmosphere of this comparative example are as follows: when Vds = 12 V, the field-effect mobility is 8.5 cm 2 / Vs, and the threshold voltage is 7.1 V. there were.

本比較例において、TFT作成後、比較例1と同様な手法にて、電気的ストレス耐性を測定した。本比較例で与えた電気的ストレスは、ゲート電極に6V、ドレイン電極に6Vを800秒間印加、とした。さらに、雰囲気による効果を見るため、大気雰囲気と真空雰囲気にて測定を行った。大気雰囲気での電気的ストレス耐性の測定を測定1、真空雰囲気での測定を測定2とした。   In this comparative example, the electrical stress resistance was measured by the same method as in Comparative Example 1 after the TFT was created. The electrical stress applied in this comparative example was 6 V applied to the gate electrode and 6 V applied to the drain electrode for 800 seconds. Furthermore, in order to see the effect of the atmosphere, the measurement was performed in an air atmosphere and a vacuum atmosphere. The measurement of the electrical stress resistance in the air atmosphere was measured 1, and the measurement in the vacuum atmosphere was measured 2.

電気的ストレス耐性を評価した結果を図9に示す。しきい値電圧変化の定義は、実施例1と同じである。   The result of evaluating the electrical stress resistance is shown in FIG. The definition of the threshold voltage change is the same as in the first embodiment.

この結果、雰囲気によらず、ストレスによるしきい値電圧変化が1V弱有ることが分かった。   As a result, it was found that the threshold voltage change due to stress is less than 1 V regardless of the atmosphere.

本実施例は、比較例2のTFTに対し、真空雰囲気で200℃の安定化処理を1時間加えたものである。   In this example, the TFT of Comparative Example 2 was subjected to a stabilization treatment at 200 ° C. in a vacuum atmosphere for 1 hour.

以下での電気的測定は、すべて、室温、暗所で行った。   All electrical measurements below were performed at room temperature in the dark.

安定化処理の効果は、比較例2と同様に、TFTに電気的ストレスを与える前後での、TFTの特性変化を調べることで評価した。本実施例で与えた電気的ストレスは、比較例2と同様、ゲート電極に6V、ドレイン電極に6Vを800秒間印加、とした。   As in Comparative Example 2, the effect of the stabilization treatment was evaluated by examining the change in TFT characteristics before and after applying electrical stress to the TFT. As in the comparative example 2, the electrical stress applied in this example was 6 V applied to the gate electrode and 6 V applied to the drain electrode for 800 seconds.

さらに、雰囲気による効果を見るため、真空雰囲気と大気雰囲気にて測定を行った。安定化処理後の真空雰囲気での測定を測定3とし、安定化処理後の大気雰囲気での測定を測定4とする。   Furthermore, in order to see the effect of the atmosphere, measurements were performed in a vacuum atmosphere and an air atmosphere. The measurement in the vacuum atmosphere after the stabilization treatment is taken as measurement 3, and the measurement in the air atmosphere after the stabilization treatment is taken as measurement 4.

図9に、前記2つの測定におけるしきい値電圧の変化を示す。しきい値電圧変化の定義は、実施例1と同じである。   FIG. 9 shows changes in the threshold voltage in the two measurements. The definition of the threshold voltage change is the same as in the first embodiment.

この結果、安定化処理後には、雰囲気によらず、しきい値電圧変化を0.2V以下に抑えることができることがわかった。   As a result, it was found that the threshold voltage change can be suppressed to 0.2 V or less after the stabilization process regardless of the atmosphere.

従って、真空雰囲気中で200℃の安定化処理を加えることで、しきい値電圧変化を1V弱から0.2V以下に抑えることができ、電気的ストレスに対する耐性を向上させることできた。   Therefore, by applying a stabilization treatment at 200 ° C. in a vacuum atmosphere, the threshold voltage change can be suppressed from less than 1 V to 0.2 V or less, and resistance to electrical stress can be improved.

上記温度は、ガラス基板の耐熱温度に比べ十分低いため、ガラス基板上のTFTの安定化処理として適用することが可能である。また、プラスチック基板でも、ポリイミドなどの耐熱性の高い基板の場合には耐熱温度以下となり、適用できる。さらに、ステンレス製基板を用い、トップエミッション型のOLEDディスプレイを構成する場合にも、本処理は適用することが可能である。   Since the above temperature is sufficiently lower than the heat-resistant temperature of the glass substrate, it can be applied as a stabilization process for TFTs on the glass substrate. In addition, even a plastic substrate can be used because it has a heat resistant temperature or lower in the case of a substrate having high heat resistance such as polyimide. Furthermore, this process can be applied to the case where a top emission type OLED display is configured using a stainless steel substrate.

本実施例のAM型OLEDディスプレイについて以下に説明する。   The AM type OLED display of this embodiment will be described below.

図10は、本実施例に用いるガラス基板上の逆スタガー(ボトムゲート)型TFT素子である。本TFT素子の作成方法を以下に示す。   FIG. 10 shows an inverted staggered (bottom gate) TFT element on a glass substrate used in this example. A method for producing this TFT element will be described below.

まず、ガラス基板11にスパッタ法を用い透明伝導膜IZOを150nm成膜後、フォトリゾグラフィー法と塩酸を用いたウェットエッチング法により、ゲート電極12を形成する。   First, a transparent conductive film IZO having a thickness of 150 nm is formed on the glass substrate 11 by sputtering, and then the gate electrode 12 is formed by photolithography and wet etching using hydrochloric acid.

続いて、スパッタ法によりa−SiOによる第1の絶縁膜13を200nm成膜する。その際、スパッタターゲットにはSiOターゲットを用い、スパッタガスにArガスを用いる。 Subsequently, a first insulating film 13 made of a-SiO x is formed to a thickness of 200 nm by sputtering. At that time, a SiO 2 target is used as the sputtering target, and Ar gas is used as the sputtering gas.

次に、室温においてスパッタ法で活性層14として用いるa−IGZOの酸化物半導体膜を20nm成膜する。ここで、a−IGZO膜の安定化処理として、大気中で250℃において20分の安定化処理を行う。その後、活性層のパターニングを、フォトリゾグラフィー法と塩酸を用いたウェットエッチングにて行う。   Next, an a-IGZO oxide semiconductor film used as the active layer 14 is formed by sputtering at room temperature to a thickness of 20 nm. Here, as the stabilization process of the a-IGZO film, the stabilization process is performed in the atmosphere at 250 ° C. for 20 minutes. Thereafter, the active layer is patterned by photolithography and wet etching using hydrochloric acid.

次に、活性層の保護とエッチングストップ機能のため、第2の絶縁膜15として、スパッタ法によりa−SiOによる絶縁層を100nm成膜する。その際、スパッタガスとしてO/Ar混合ガス比50%の酸化性雰囲気を用いる。その後、第2の絶縁膜のパターニングを、フォトリソグラフィー法とCFガスによるドライエッチングを用いて行う。 Next, for the protection of the active layer and the etching stop function, an insulating layer made of a-SiO x is formed to a thickness of 100 nm as the second insulating film 15 by sputtering. At that time, an oxidizing atmosphere having an O 2 / Ar mixed gas ratio of 50% is used as a sputtering gas. Thereafter, patterning of the second insulating film is performed using photolithography and dry etching with CF 4 gas.

次に、透明伝導膜ITOを150nmスパッタ法により成膜後、フォトリソグラフィー法と市販のITOエッチング液を用いたウェットエッチング法によりソース電極16、ドレイン電極17を形成する。   Next, after forming a transparent conductive film ITO by a 150 nm sputtering method, a source electrode 16 and a drain electrode 17 are formed by a photolithography method and a wet etching method using a commercially available ITO etching solution.

こうして、図10に示す逆スタガー(ボトムゲート)型透明TFT素子を形成することができる。   Thus, the inverted staggered (bottom gate) type transparent TFT element shown in FIG. 10 can be formed.

前記ゲート電極、ソース電極及びドレイン電極としてIZO、ITOなどの透明導電性酸化膜はもちろん、Ni、Cr、Rh、Mo、Nd、Ti、W、Ta、Pb、Alなどの金属や、これらを含む合金又はシリサイドも用いることができる。また、ゲート電極、ソース電極及びドレイン電極をそれぞれ別の材料で形成する、あるいは各電極の1部を別の材料で形成することも可能である。   The gate electrode, source electrode and drain electrode include not only transparent conductive oxide films such as IZO and ITO, but also metals such as Ni, Cr, Rh, Mo, Nd, Ti, W, Ta, Pb and Al, and the like. Alloys or silicides can also be used. In addition, the gate electrode, the source electrode, and the drain electrode can be formed using different materials, or a part of each electrode can be formed using different materials.

図10に示したTFTを用いて、AM型OLEDディスプレイの基本構成要素である画素を形成することができる。図11に、図10に示したTFTとOLED素子を含む構成例を示す。図10の構成部材と同一構成部材については同一符号を付して説明を省略する。   A pixel which is a basic component of an AM type OLED display can be formed using the TFT shown in FIG. FIG. 11 shows a configuration example including the TFT and the OLED element shown in FIG. Constituent members that are the same as those shown in FIG.

図11において、アノード電極18はソース電極と接続され、貫通電極及び透明電極を構成する。アノード電極18の透明電極部分とカソード電極21との間に有機発光層20が設けられる。カソード電極21は例えば炭酸セシウムとアルミニウムとで構成される。19は平坦化膜を示す。   In FIG. 11, the anode electrode 18 is connected to the source electrode, and constitutes a through electrode and a transparent electrode. An organic light emitting layer 20 is provided between the transparent electrode portion of the anode electrode 18 and the cathode electrode 21. The cathode electrode 21 is made of, for example, cesium carbonate and aluminum. Reference numeral 19 denotes a planarizing film.

本実施例のAM型OLEDディスプレイは、TFTに対し、250℃の安定化処理行っているため、電気的ストレス耐性が高い。従って、長時間でも駆動可能なAM型OLEDディスプレイが実現できる。   The AM type OLED display of this example has high electrical stress resistance because the TFT is stabilized at 250 ° C. Therefore, an AM type OLED display that can be driven for a long time can be realized.

又、本実施例では、ガラス基板上に作成するが、耐熱が250℃程度あるプラスチック基板でも同様に作成可能である。その場合、フレキシブルディスプレイも可能となる。   In the present embodiment, it is formed on a glass substrate, but a plastic substrate having a heat resistance of about 250 ° C. can be similarly formed. In that case, a flexible display is also possible.

さらに、本実施例の図10に示したTFTは、AM型OLEDディスプレイと同様に、AM型LCDや、他のAM型ディスプレイ、例えばAM型電気泳動素子反射ディスプレイにも用いることができる。   Further, the TFT shown in FIG. 10 of the present embodiment can be used for an AM type LCD and other AM type displays such as an AM type electrophoretic element reflective display as well as the AM type OLED display.

本発明は、電気的ストレス耐性が良好な薄膜トランジスタに適用可能で、AM型OLEDディスプレイ、AM型LCDや、他のAM型ディスプレイ、例えばAM型電気泳動素子反射ディスプレイに用いることができる。   The present invention can be applied to a thin film transistor having good electrical stress resistance, and can be used for an AM type OLED display, an AM type LCD, and other AM type displays such as an AM type electrophoretic element reflective display.

本発明の第1実施例、並びに第1の比較例に係わる、薄膜トランジスタの構成を示す図である。It is a figure which shows the structure of the thin-film transistor concerning 1st Example of this invention and a 1st comparative example. 真空中で熱処理したa−IGZO膜の質量数64(Zn)の昇温脱離測定結果を示す図である。It is a figure which shows the thermal desorption measurement result of mass number 64 (Zn <+> ) of the a-IGZO film heat-processed in the vacuum. 昇温脱離分析における、真空中での加熱処理温度に対する質量数64(Zn)の積分イオン強度を示す図である。It is a figure which shows the integral ion intensity | strength of mass number 64 (Zn <+> ) with respect to the heat processing temperature in a vacuum in a thermal desorption analysis. a−IGZO膜の導電率の熱処理温度依存性を示す図である。It is a figure which shows the heat processing temperature dependence of the electrical conductivity of an a-IGZO film. a−IGZO膜からの、質量数18(H)の昇温脱離測定結果を示す図である。from a-IGZO film is a diagram showing a temperature-programmed desorption measurement results of the mass number 18 (H 2 O +). 本発明の第1の実施例と第1の比較例に係わる、電気的ストレスによるしきい値電圧変化の安定化処理温度依存性を示す図である。It is a figure which shows the stabilization process temperature dependence of the threshold voltage change by the electrical stress concerning the 1st Example of this invention and a 1st comparative example. 本発明の第1の実施例に係わる、大気中で熱処理したa−IGZO膜の質量数64(Zn)の昇温脱離測定結果を示す図である。It is a figure which shows the thermal desorption measurement result of mass number 64 (Zn <+> ) of the a-IGZO film heat-processed in air | atmosphere concerning the 1st Example of this invention. 本発明の第1の実施例に係わる、昇温脱離分析における、大気中での加熱処理温度に対する質量数64(Zn)の積分イオン強度を示す図である。It is a figure which shows the integral ion intensity | strength of mass number 64 (Zn <+> ) with respect to the heat processing temperature in air | atmosphere in the thermal desorption analysis concerning the 1st Example of this invention. 本発明の第2の比較例と第2の実施例に係わる、安定化処理前後の電気的ストレスによるしきい値電圧変化を示す図である。It is a figure which shows the threshold voltage change by the electrical stress before and behind the stabilization process concerning the 2nd comparative example and 2nd Example of this invention. 本発明の第3の実施例に係わる、薄膜トランジスタの構成を示す図である。It is a figure which shows the structure of the thin-film transistor concerning the 3rd Example of this invention. 本発明の第3の実施例に係わる、薄膜トランジスタと有機EL素子の構成を示す図である。It is a figure which shows the structure of the thin-film transistor and organic electroluminescent element concerning the 3rd Example of this invention.

符号の説明Explanation of symbols

12 ゲート電極
13 第1の絶縁層
14 a−IGZO活性層
15 第2の絶縁層
16 ソース電極
17 ドレイン電極
18 アノード電極(透明電極かつ貫通電極)
19 平坦化膜
20 有機発光層
21 カソード電極(炭酸セシウム+アルミ)
12 Gate electrode
13 First insulating layer
14 a-IGZO active layer
15 Second insulation layer
16 Source electrode
17 Drain electrode
18 Anode electrode (transparent electrode and through electrode)
19 Planarization film
20 Organic light emitting layer
21 Cathode electrode (cesium carbonate + aluminum)

Claims (13)

活性層がIn、Znを含み構成されたアモルファス酸化物である薄膜トランジスタであって、
前記活性層の形成後に前記活性層に電気特性を安定化させるためのエネルギーを付与し、
前記エネルギーを付与した活性層が、前記エネルギーを付与しない活性層に対して、昇温脱離分析により、温度範囲200℃から700℃において1.05倍よりも多いZnを脱離することを特徴とする薄膜トランジスタ。
A thin film transistor whose active layer is an amorphous oxide composed of In and Zn,
Providing the active layer with energy for stabilizing electrical characteristics after the formation of the active layer;
The active layer imparted with energy desorbs more than 1.05 times Zn in a temperature range of 200 ° C. to 700 ° C. by temperature-programmed desorption analysis with respect to the active layer not imparted with energy. A thin film transistor.
前記エネルギーは加熱処理により付与されることを特徴とする請求項1に記載の薄膜トランジスタ。   The thin film transistor according to claim 1, wherein the energy is applied by heat treatment. 前記加熱処理は大気中で行われ、加熱温度は150℃より高く、281℃未満の温度であることを特徴とする請求項2に記載の薄膜トランジスタ。   The thin film transistor according to claim 2, wherein the heat treatment is performed in the atmosphere, and the heating temperature is higher than 150 ° C and lower than 281 ° C. 前記加熱処理は真空中で行われ、加熱温度は150℃より高く、300℃未満の温度であることを特徴とする請求項2に記載の薄膜トランジスタ。   The thin film transistor according to claim 2, wherein the heat treatment is performed in a vacuum, and the heating temperature is higher than 150 ° C. and lower than 300 ° C. 4. 前記活性層が、Inと、Zn及びGaを含むアモルファス酸化物であることを特徴とする請求項1から4のいずれか1項に記載の薄膜トランジスタ。   5. The thin film transistor according to claim 1, wherein the active layer is an amorphous oxide containing In and Zn and Ga. 6. 前記活性層が、カチオン比でIn:Zn:Ga=1:1:1のターゲットを使用して、スパッタ装置により成膜されたアモルファス酸化物であることを特徴とする請求項1から5のいずれか1項に記載の薄膜トランジスタ。   6. The active layer is an amorphous oxide formed by a sputtering apparatus using a target having a cation ratio of In: Zn: Ga = 1: 1: 1. 2. A thin film transistor according to item 1. 表示素子の電極に、請求項1から6のいずれか1項に記載の薄膜トランジスタのソース電極又はドレイン電極が接続されていることを特徴とする表示装置。   A display device, wherein the source electrode or the drain electrode of the thin film transistor according to any one of claims 1 to 6 is connected to an electrode of the display element. 請求項7に記載の表示装置の表示素子が有機発光ダイオードであることを特徴とする表示装置。   A display device according to claim 7, wherein the display element is an organic light emitting diode. 活性層がInと、Znと、を含むアモルファス酸化物で構成された薄膜トランジスタの製造方法であって、前記活性層を形成する工程の後に前記活性層に電気特性を安定化させるためのエネルギーを付与する工程を含むことを特徴とする薄膜トランジスタの製造方法。   A method of manufacturing a thin film transistor in which an active layer is composed of an amorphous oxide containing In and Zn, and energy is applied to the active layer to stabilize electrical characteristics after the step of forming the active layer A process for producing a thin film transistor, comprising the step of: 前記エネルギーを付与する工程を、活性層の上に接する絶縁層を形成する工程よりも後に行うことを特徴とする請求項9に記載の薄膜トランジスタの製造方法。   10. The method for manufacturing a thin film transistor according to claim 9, wherein the step of applying energy is performed after the step of forming an insulating layer in contact with the active layer. 前記エネルギーは加熱処理により付与され、該加熱処理における加熱温度は前記エネルギーを付与する工程以外の工程での熱処理温度よりも高いことを特徴とする請求項9又は10に記載の薄膜トランジスタの製造方法。   11. The method of manufacturing a thin film transistor according to claim 9, wherein the energy is applied by a heat treatment, and a heating temperature in the heat treatment is higher than a heat treatment temperature in a step other than the step of applying the energy. 前記加熱処理は大気中で行われ、加熱温度は150℃より高く、281℃未満の温度であることを特徴とする請求項9から11のいずれか1項に記載の薄膜トランジスタの製造方法。   The method for manufacturing a thin film transistor according to any one of claims 9 to 11, wherein the heat treatment is performed in the atmosphere, and the heating temperature is higher than 150 ° C and lower than 281 ° C. 前記加熱処理は真空中で行われ、加熱温度は150℃より高く、300℃未満の温度であることを特徴とする請求項9から11のいずれか1項に記載の薄膜トランジスタの製造方法。   The method for manufacturing a thin film transistor according to any one of claims 9 to 11, wherein the heat treatment is performed in a vacuum, and the heating temperature is higher than 150 ° C and lower than 300 ° C.
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