JP2009094674A - Synchronization tracking circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronization tracking circuit capable of high-speed and highly precise tracking operation by increasing and decreasing an estimation bit cycle when imperfect synchronization is detected. <P>SOLUTION: The synchronization tracking circuit is provided with: a synchronization acquisition circuit 120 for establishing synchronization with respect to a received IQ signal; a bit cycle storage circuit 130 for storing a bit cycle estimated when acquiring synchronization; a symbol clock regeneration circuit 140 for using the estimated bit cycle to notify the symbol clock and timing before and after that; secondary sampling circuits 150 and 151 for performing the secondary sampling of the received IQ signal with output timing from the symbol clock regeneration circuit 140; a correlation operation circuit 160 for performing correlation operation with a reference signal by using the secondary sampling data to output the correlation value; a comparison circuit 170 for comparing correlation values of the symbol timing and timing before and after that to output timing with which a maximum correlation value is given; and a data determination circuit 180 for performing data determination on the basis of the correlation value of the correlation operation circuit 160. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a synchronous tracking circuit used in a demodulation circuit such as a communication device.

  In communication, in order for a receiver to demodulate a signal sent from a transmitter, it is necessary to synchronize the received signal on the receiver side. There are two types of synchronization: synchronization acquisition, which detects that the expected signal has arrived and starts demodulation, and synchronization tracking, which performs synchronization correction at any time by monitoring synchronization deviation during demodulation. Both are important factors that affect the performance of the receiver.

  FIG. 9 is a configuration diagram of a conventional synchronization tracking circuit.

  In FIG. 9, reference numeral 10 denotes an A / D conversion circuit that samples, quantizes and outputs a baseband analog signal. Reference numeral 20 denotes a clock recovery circuit that outputs a reproduction clock, an early clock that is one clock earlier than the reproduction clock, and a late clock that is one clock later than the reproduction clock when capturing synchronization. Reference numeral 30 denotes a phase shift circuit that shifts the phases of the three clock signals output from the clock recovery circuit 20. Reference numeral 40 denotes a secondary sampling circuit that performs secondary sampling of data output from the A / D conversion circuit 10 using a clock output from the phase shift circuit 30. Reference numeral 50 denotes a phase shift detection circuit that compares the amplitude of each clock timing signal output from the secondary sampling circuit 40, detects a phase shift, and outputs a control signal corresponding to the detected phase shift. Reference numeral 60 denotes a demodulation circuit that inputs data that is secondarily sampled by the reproduction clock among the data output from the secondary sampling circuit 40 and demodulates the data.

  The conventional synchronization tracking operation described above will be described.

  First, at the time when synchronization acquisition is successful for an effective baseband signal, the clock recovery circuit 20 starts to output a recovered clock, an early clock, and a late clock. These clocks continue to be output at a constant interval (chip interval) until reception ends. The phase shift circuit 30 outputs each input clock as it is without performing phase shift. In the secondary sampling circuit 40, the output from the A / D conversion circuit 10 is subjected to secondary sampling with each clock output from the phase shift circuit 30 and output. Assuming that the synchronization is accurately established, the data sampled by the reproduction clock among the signals output from the secondary sampling circuit 40 has the highest SN ratio and becomes reliable data.

  The demodulation circuit 60 performs demodulation using this data. However, over time, the synchronization with the received signal gradually shifts due to the master clock shift between the transceivers. For example, when the amount of deviation reaches a higher S / N ratio than the data secondarily sampled by the early clock output from the phase shift circuit 30 than the data secondarily sampled by the reproduction clock, the demodulator circuit The data input to 60 is preferably data sampled with an early clock rather than data secondarily sampled with a recovered clock. At this time, the phase shift detection circuit 50 detects the phase shift and outputs a signal notifying the phase shift. When this signal is transmitted to the phase shift circuit 30, the phase shift circuit 30 shifts the phase so that the current early clock becomes a new reproduction clock. At this time, the new early clock and the new late clock become a clock one clock earlier than the new reproduction clock and a clock one clock later than the new reproduction clock, respectively.

By performing such an operation, in the secondary sampling circuit 40, the data that has been sampled with the early clock until then is sampled with the new reproduction clock. Therefore, it is possible to perform demodulation using high data. An example of performing the synchronous follow-up operation while shifting the reproduction clock by one clock in this way is, for example, a method shown in (Patent Document 1).
JP-A-8-335892

  However, in the above-described conventional configuration, the reproduction clock is output at regular intervals, so the clock accuracy of the transmitter is not very good (for example, about several percent to 20%). Communication (for example, RFID (Radio Frequency IDentification)) ) Has a problem that it is extremely difficult to make the received signal follow the received signal operation.

  The present invention is a circuit configuration that estimates a bit period from a received signal, adjusts timing based on the estimated bit period, and outputs a recovered clock. When a synchronization shift is detected, the estimated bit period is increased or decreased. It is an object of the present invention to provide a synchronous tracking circuit that can perform a high-speed and highly accurate tracking operation.

  The present invention relates to a synchronization acquisition circuit that establishes synchronization with a received IQ signal, a bit period storage circuit that stores a bit period estimated at the time of synchronization acquisition, a symbol clock using the estimated bit period, and timings before and after the symbol clock. A symbol clock recovery circuit for notifying a signal, a secondary sampling circuit for performing secondary sampling of the received IQ signal at a timing output from the symbol clock recovery circuit, and secondary sampling data output from the secondary sampling circuit. From a correlation calculation circuit that performs correlation calculation with a reference signal and outputs a correlation value, a comparison circuit that compares the correlation values of the symbol timing and the timing before and after it, and outputs a timing that gives the maximum correlation value, and a correlation calculation circuit And a data determination circuit that performs data determination based on the output correlation value. .

  As a result, it is possible to provide a synchronous tracking circuit that can perform a high-speed and high-accuracy tracking operation even in communications where the clock accuracy is not very good.

  According to the present invention, since synchronization tracking is performed by increasing or decreasing the estimated bit period, a high-speed and high-accuracy synchronization tracking circuit can be realized even in communication with poor clock accuracy.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the following embodiments can be mutually used for related portions.

(Embodiment 1)
In this embodiment, a case where the present invention is applied to an RFID reader / writer will be described as an example.

  In the RFID system, the reader / writer reads the information stored in the tag and performs article management. However, because the tag is manufactured with a circuit as simple as possible at low cost, the clock accuracy of the tag is largely allowed by the standard. ing. Compared to other wireless communications, for example, the clock accuracy in the IEEE802.11b standard wireless LAN is limited to within ± 25 ppm, but the EPC global Class1 Generation 2 which is the RFID standard allows a maximum of ± 22% clock deviation. These differences are almost 1000 times. Accordingly, the receiver circuit of the RFID reader / writer is required to have a far wider range of synchronization acquisition / follow-up performance than other wireless communications, and this embodiment can be adapted to this.

  FIG. 1 is a configuration diagram of a demodulation circuit including a synchronization tracking circuit according to Embodiment 1 of the present invention.

  In FIG. 1, reference numeral 110 denotes a threshold value determination circuit that determines a threshold value for detecting a desired signal. Reference numeral 120 denotes a synchronization acquisition circuit that receives a received IQ signal and a threshold value, acquires initial synchronization for the received signal, and outputs an estimated bit period and symbol timing. A bit period storage circuit 130 stores the estimated bit period and can increase or decrease the value of the stored bit period when a control signal is input. A symbol clock recovery circuit 140 outputs a symbol clock based on the timing signal output from the synchronization acquisition circuit 120 and the estimated bit period stored in the bit period storage circuit 130.

  Reference numerals 150 and 151 denote secondary sampling circuits that sample the I and Q signals with the recovered symbol clock output from the symbol clock recovery circuit 140. Reference numeral 160 denotes a correlation calculation circuit that performs a correlation calculation on the data sampled by the secondary sampling circuits 150 and 151. Reference numeral 170 denotes a comparison circuit that compares the correlation values output from the correlation calculation circuit 160 and outputs the result. Reference numeral 180 denotes a data determination circuit that performs data determination based on the correlation value output from the correlation calculation circuit 160 and outputs demodulated data.

  The operation of the circuit shown in FIG. 1 configured as described above will be described.

  First, when the reader / writer shifts to the reception mode, the threshold value determination circuit 110 determines a threshold value, and the synchronization acquisition circuit 120 acquires initial synchronization. If the encoding for transmission from the tag to the reader / writer is set to the mirror subcarrier code, the leading portion of the IQ signal received by the reader / writer has a positive and negative repetitive waveform. The initial synchronization is captured by detecting. An example of the synchronization acquisition circuit is shown in FIG.

  FIG. 2 is a configuration diagram of the synchronization supplement circuit according to the first embodiment of the present invention.

In FIG. 2, reference numeral 210 denotes a synthesis circuit that synthesizes received IQ signals. As this synthesis formula, | I (n) | + | Q (n) |, or I (n) ² + Q (n) ² , or | I (n) + I (n + 1) | + | Q (n) + Q (n + 1) | or (I (n) + I (n + 1)) ² + (Q (n) + Q (n + 1)) ² is considered (n is a natural number indicating the number of the oversampled sample).

  Note that a calculation formula that can evaluate the amplitude even if the phase of the IQ signal changes is sufficient, and the synthesis formula used for the synthesis circuit 210 is not limited to the calculation formula shown here.

  The peak detection circuit 220 detects the peak value of the signal output from the synthesis circuit 210. The comparison circuit 230 evaluates whether or not the peak value detected by the peak detection circuit 220 is greater than the threshold value input from the threshold value determination circuit 110. If it is larger than the threshold value, the counter 240 is notified.

  Here, the threshold value needs to be a value with which a signal from the tag can be detected, and the threshold value determination circuit 110 is, for example, a noise level in a no-signal period immediately before a tag response is returned. And a circuit that sets a value larger than the maximum value as a threshold value can be realized. Alternatively, it can be realized by detecting a level of a received signal from each tag and configuring a circuit that sets a threshold corresponding to the level each time. Alternatively, it can be realized by configuring a circuit that monitors the signal level of the burst portion of the preamble signal in the received signal from each tag for an arbitrary period and sets a value smaller than the maximum value of the period as a threshold value. Alternatively, a pilot tone is added to the tag response, the signal level of the pilot tone is monitored for an arbitrary period, and a value smaller than the maximum value (for example, one half of the maximum value) is set as a threshold value. This can be realized by configuring a circuit that performs the above. Alternatively, it is realized by configuring a circuit that detects the value of an arbitrary number of peaks in the burst portion of the preamble signal in the received signal from each tag and sets a value smaller than the average value of the plurality of peaks as a threshold value. it can. Alternatively, a pilot tone is added to the tag response, the value of an arbitrary number of peaks in the pilot tone portion is detected, and a value smaller than the average value of the plurality of peak values (for example, two minutes of the average value of the peak values). This can be realized by configuring a circuit that sets 1) as a threshold value. Note that if the reader / writer controls multiple antennas, the noise caused by the change of antennas should be re-detected at least every time antennas are switched and the threshold is reset. Can respond to changes in In addition, if a response from the tag is not received for a certain period of time, the noise level is detected again, and the threshold value is reset to avoid a communication failure due to an incorrect threshold setting. .

  The counter 240 counts and outputs the peak interval of the IQ composite signal. The synchronization detection circuit 250 determines that a desired signal has arrived when two or more consecutive peak intervals output from the counter 240 are within a certain range, and detects synchronization. For example, if the peak interval at a certain point in time is 15 clocks long, and the peak interval arrives two or more consecutively within the range of 15 ± 1 clock immediately after that, the desired signal comes. The initial synchronization is established by estimating and outputting the bit period from the peak interval.

  At this time, an enable signal notifying the timing of the symbol clock is also output. The length of the estimated bit period varies depending on the setting value M of the mirror subcarrier.

  The set value M is defined by the EPC global Class 1 Generation 2 standard and is a value set by the reader / writer. FIG. 3 shows the correspondence between the set value M and the mirror subcarrier code.

  FIG. 3 is an explanatory diagram of a mirror subcarrier code according to Embodiment 1 of the present invention.

  As shown in FIG. 3, since the peak interval corresponds to the symbol length, the bit period is 4 times the symbol length when M = 2, 8 times the symbol length when M = 4, and M = 8. Is 16 times the symbol length. The synchronization detection circuit 250 estimates the bit period from a plurality of peak intervals according to the value of the set value M.

  When initial synchronization is established, synchronization tracking is started so that synchronization is not lost. The detailed operation of the synchronization tracking will be described below.

  After receiving the enable signal from the synchronization acquisition circuit 120, the symbol clock recovery circuit 140 outputs a symbol clock at a calculated interval using the estimated bit period stored in the bit period storage circuit 130. The interval at which the symbol clock is output is an interval obtained by dividing the estimated bit period by 4, 8, and 16 for the set values M = 2, 4, and 8, respectively. At this time, if the result of division cannot be divided, the surplus clocks are distributed as evenly as possible.

  The secondary sampling circuits 150 and 151 sample the IQ signal at the symbol clock and the timing before and after the symbol clock based on the regenerated symbol clock. The correlation calculation circuit 160 performs a correlation calculation for the three timings of the symbol clock and the timings before and after the symbol clock, and outputs the calculation result. This arithmetic expression is required to show a larger correlation value as the synchronization is more accurate. At the same time, it is desirable to contribute to data determination. For example, as shown in FIG. 3, focusing on the fact that the phase of the mirror subcarrier code is inverted by 180 degrees between the first half and the second half of the bit as shown in FIG. And the latter half of the bit are obtained, the data is determined based on the positive / negative of the inner product, and the synchronization accuracy can be evaluated with the absolute value.

When M = 2 (I1-I2) (I3-I4) + (Q1-Q2) (Q3-Q4)
When M = 4 (I1-I2 + I3-I4) (I5-I6 + I7-I8) + (Q1-Q2 + Q3-Q4) (Q5-Q6 + Q7-Q8)
When M = 8 (I1-I2 + I3-I4 + I5-I6 + I7-I8) (I9-I10 + I11-I12 + I13-I14 + I15-I16)
+ (Q1-Q2 + Q3-Q4 + Q5-Q6 + Q7-Q8) (Q9-Q10 + Q11-Q12 + Q13-Q14 + Q15-Q16)
The above I1 to I16 and Q1 to Q16 are IQ data subjected to secondary sampling, and the state of the secondary sampling is shown in FIGS.

  4 to 6 are explanatory diagrams of secondary sampling according to Embodiment 1 of the present invention. FIG. 4 shows a case where the set value M = 2, FIG. 5 shows a case where the set value M = 4, and FIG. Indicates the case where the set value M = 8.

  The case where M = 2 will be described with reference to FIG. 4. The combined vector of the first half of the bit is (I1-I2, Q1-Q2), and the combined vector of the second half of the bit is (I3-I4, Q3-Q4). In the case of data 0, the first half of the bits are (2A, 2A), the second half of the bits are (2A, 2A), and the first half of the bits are (2A, 2A). The second half of the bit is (-2A, -2A). Looking at the difference between the combined vector data 0 and data 1, the phase difference between the first half and the second half is 0 degrees in the case of data 0, whereas the first half and the second half are combined in the case of data 1. The phase difference of the vector is 180 degrees. Actually, the phase difference takes various values due to the influence of synchronization shift or noise. However, as data judgment, if the phase difference is less than 90 degrees, data 0 is assumed, and if it is greater than 90 degrees, data 1 is assumed. Good. Whether the phase difference between the two vectors is smaller or larger than 90 degrees can be evaluated by whether the inner product of the two vectors is positive or negative.

That is, the data determination circuit 180 determines data 0 if the correlation calculation result is positive, and data 1 if the result is negative. In the above example, the inner product in the case of data 0 is 8A ² , and the inner product in the case of data 1 is −8A ² . The data can be similarly determined for M = 4 and M = 8.

  Next, synchronous tracking when M = 2 will be described with reference to FIG.

  FIG. 7 is an explanatory diagram of the secondary sampling in the first embodiment of the present invention, and shows a state in which oversampling is performed 5 times the symbol rate. The oversampling may be any number as long as it is a natural number of 2 or more.

  In order to perform synchronization tracking, correlation calculation is performed using IQ data secondarily sampled with a symbol clock and clocks before and after the symbol clock.

  In FIG. 7, assuming that the symbol clock is reproduced at the timing of the regenerated symbol clock (a), the IQ data sampled by the regenerated symbol clock is (I1, Q1), (I2, Q2), (I3). , Q3), (I4, Q4). Also, the IQ data at a timing one sample earlier than the reproduction symbol clock is (I1E1, Q1E1), (I2 E1, Q2E1), (I3E1, Q3E1), (I4E1, Q4E1). The IQ data at the later sampling timing is (I1L1, Q1L1), (I2L1, Q2L1), (I3L1, Q3L1), (I4L1, Q4L1),.

  The correlation calculation circuit 160 performs the correlation calculation of these three timings, and the comparison circuit 170 compares the absolute values of the correlation values at each timing. When the reproduced symbol clock is the reproduced symbol clock (a) in FIG. 7, the absolute value of each IQ data at the timing before and after that is smaller than that sampled by the reproduced symbol clock. As a result of comparison, the correlation value at the timing of the regenerated symbol clock is determined to be the largest. At this time, it is determined that the timing of the recovered symbol clock is correct, and the sampling of the next bit inherits the timing of the recovered symbol clock.

  However, if the reproduced symbol clock is shifted, for example, as reproduced symbol clock (b) in FIG. 7, the comparison circuit 170 has the largest correlation value at a timing delayed by one sample timing from the reproduced symbol clock. This is notified to the bit cycle storage circuit 130.

  Also, if the recovered symbol clock is shifted, for example, as shown in the recovered symbol clock (c) of FIG. 7, the comparison circuit 170 has the largest correlation value at a timing one sample timing earlier than the recovered symbol clock. Is notified to the bit cycle storage circuit 130.

  When the bit cycle storage circuit 130 is informed that the correlation value at the timing delayed by one sample timing from the reproduction symbol clock is the largest, the stored bit cycle is increased and the timing one sample timing earlier than the reproduction symbol clock. When it is notified that the correlation value is the largest, the stored bit period is reduced. The symbol clock recovery circuit 140 performs synchronization tracking by recovering the symbol clock based on the increased or decreased bit period.

  Next, a mechanism that can perform synchronous tracking by increasing or decreasing the bit period will be described.

  FIG. 7 shows a case where the estimated bit period is estimated to be 20 sample clocks, and a reproduced symbol clock is generated every 5 sample clocks.

  Assuming that the reproduced symbol clock is output at the timing of the reproduced symbol clock (b), the bit period storage circuit 130 increases the stored bit period by the above-described circuit operation. For example, if the estimated bit period is increased by 1 sample clock to 21 sample clocks, among 4 reproduced symbol clocks in 1 bit, 3 times generate 5 symbol clocks and 1 time generate 6 symbol clocks. To.

  Further, assuming that the reproduced symbol clock is output at the timing of the reproduced symbol clock (c), the bit period storage circuit 130 reduces the stored bit period by the above-described circuit operation. For example, if the estimated bit period is reduced by 1 sample clock to 19 sample clocks, among 4 reproduced symbol clocks in 1 bit, 3 times generate 5 symbol clocks and 1 time generate 4 symbol clocks. To. By operating in this way, the symbol clock is adjusted and synchronization tracking is performed.

  Also, for example, in the case where a symbol clock is generated with 5 sample clocks in 2 times and 6 sample clocks in 2 times out of 4 playback symbol clocks in 1 bit, distribution of the sample clocks in 1 bit Since 5 → 5 → 6 → 6 causes a bias in the symbol clock within one bit, 6 → 5 → 5 → 6 or 5 → 6 → 6 → 5 so as to be symmetrical. With such an allocation, there is no bias, and a more ideal symbol clock can be generated.

  The correction amount at the time of correcting the bit period may be a correction amount set in advance, or may be a correction amount corresponding to the shift amount by measuring the synchronization shift amount.

  Furthermore, by shifting the timing at which the sample clock starts to be counted simultaneously with the increase / decrease of the estimated bit period, faster synchronization tracking can be performed. For example, immediately before the estimated bit period is increased by one sample clock, the timing to start counting the sample clock is delayed by one sample timing, or immediately before the estimated bit period is decreased by one sample clock, the timing to start counting the sample clock is advanced by one sample timing. To do. The shifting timing is not limited to one clock.

  In addition, if the estimated bit period is continuously increased more than the predetermined number of times, there is a possibility of malfunction due to noise, etc., so stop increasing the estimated bit period and then follow the synchronous tracking from the next timing. Try to resume. It is allowed to decrease the estimated bit period when the estimated bit period is not increased.

  In addition, if the estimated bit period is continuously reduced more than the predetermined number of times, there is a possibility of malfunction due to noise, etc., so once the estimated bit period has been reduced, synchronization tracking is performed from the next timing. Try to resume. It is permissible to increase the estimated bit period when the reduction of the estimated bit period is stopped.

  Also, if you delay the timing to start counting the bit period continuously more than the predetermined number of times, there is a possibility of malfunction due to noise etc., so stop delaying the timing to start counting the bit period, and then Restart from the timing. It is acceptable to advance the timing at which the bit period starts to be counted while stopping the delay at the timing at which the bit period starts to be counted.

  In addition, if the timing to start counting the bit period continuously more than the predetermined number of times is advanced, there is a possibility of malfunction due to noise etc., so stop the timing to start counting the bit period once and then Restart from the timing. It is permissible to delay the timing to start counting the bit period when the timing to start counting the bit period is stopped earlier.

  In addition, synchronization tracking is performed while increasing / decreasing the estimated bit period for a certain period after the bit period is estimated first, and then the estimated bit period is fixed until reception is completed, and the timing to start counting the bit period is adjusted ( = If the synchronization tracking is performed by adjusting the phase of the reproduced symbol clock), even if a large noise enters after the estimation of the bit period is stabilized, the synchronization tracking can be performed without being influenced by it. . When the bit period is fixed, an average of the bit periods estimated so far may be calculated and used. Further, if the above-described fixed period is taken until the preamble arrives, the accuracy of bit period estimation can be improved by the fixed waveform immediately before the preamble.

  It should be noted that the synchronization tracking accuracy can be improved by providing a filter at the output of the comparison circuit 170 and removing the jitter of the timing signal giving the maximum correlation value output from the comparison circuit 170. A random walk filter may be adopted as this filter.

  Even when M = 4 or M = 8, synchronous tracking can be performed by the same operation as described above.

(Embodiment 2)
FIG. 8 is a configuration diagram of a demodulation circuit including a synchronization tracking circuit according to the second embodiment of the present invention.

  In FIG. 8, reference numeral 810 denotes a threshold value storage circuit that stores a threshold value for detecting a desired signal. Reference numeral 820 denotes a synchronization acquisition circuit that receives received I and Q signals and a threshold value, acquires initial synchronization for the received signal, and outputs an estimated bit period and symbol timing. A bit period storage circuit 830 stores the estimated bit period and can increase or decrease the value of the stored bit period when a control signal is input. A symbol clock recovery circuit 840 outputs a symbol clock based on the timing signal output from the synchronization acquisition circuit 820 and the estimated bit period stored in the bit period storage circuit.

  Reference numerals 850 and 851 denote secondary sampling circuits that sample the I and Q signals with the recovered symbol clock output from the symbol clock recovery circuit 840. Reference numeral 860 denotes a correlation calculation circuit that performs a correlation calculation on the data sampled by the secondary sampling circuits 850 and 851. Reference numeral 870 denotes a comparison circuit that compares the correlation values output from the correlation calculation circuit 860 and outputs the result. Reference numeral 880 denotes a data determination circuit that performs data determination based on the correlation value output from the correlation calculation circuit 860 and outputs demodulated data.

  The detailed operation of the circuit shown in FIG. 8 configured as described above will be described.

  First, when the reader / writer shifts to the reception mode, the synchronization acquisition circuit 820 captures the initial synchronization using the threshold value stored in advance in the threshold value storage circuit 810. If the transmission from the tag to the reader / writer is set to the mirror subcarrier system, the leading part of the received IQ signal at the reader / writer has a positive and negative repetitive waveform. Capture initial synchronization. The synchronization acquisition circuit is the same as that shown in the first embodiment.

  When initial synchronization is established, synchronization tracking is started so that synchronization is not lost. The detailed operation of the synchronization tracking will be described below.

  After receiving the enable signal from the synchronization acquisition circuit 820, the symbol clock recovery circuit 840 outputs a symbol clock at intervals calculated using the estimated bit period stored in the bit period storage circuit 830. The interval at which the symbol clock is output is an interval obtained by dividing the estimated bit period by 4, 8, and 16 for M = 2, 4, and 8, respectively. At this time, if the result of division cannot be divided, the surplus clocks are distributed as evenly as possible.

  The secondary sampling circuits 850 and 851 sample the IQ signal at the symbol clock and the timing before and after the symbol clock based on the regenerated symbol clock. The correlation calculation circuit 860 performs correlation calculation for the three timings of the symbol clock and the timing before and after the symbol clock, and outputs the calculation result. This arithmetic expression is required to be the same as that shown in the first embodiment. In the data determination circuit 880, data determination is performed as in the first embodiment. The comparison circuit 870 also compares the absolute values of the correlation values at each timing as in the case of the first embodiment, and outputs a control signal notifying which timing has the largest correlation.

  For example, if the reproduced symbol clock is shifted as shown in the reproduced symbol clock (b) of FIG. 7, the comparison circuit 870 has the largest correlation value at a timing delayed by one sample timing from the reproduced symbol clock. Is notified to the bit cycle storage circuit 830.

  If the reproduced symbol clock is shifted as shown in the reproduced symbol clock (c) of FIG. 7, the comparison circuit 870 indicates that the correlation value at the timing one sample timing earlier than the reproduced symbol clock is the largest. The bit cycle storage circuit 830 is informed. When the bit cycle storage circuit 830 is informed that the correlation value at the timing delayed by one sample timing from the reproduction symbol clock is the largest, the stored bit cycle is increased and the timing one sample timing earlier than the reproduction symbol clock. When it is notified that the correlation value is the largest, the stored bit period is reduced.

  The symbol clock recovery circuit 840 performs synchronization tracking by recovering the symbol clock based on the increased or decreased bit period. The mechanism for performing synchronous tracking by increasing or decreasing the bit period is the same as that shown in the first embodiment.

  As described above, the synchronization tracking circuit and the demodulation circuit including the circuit shown in each embodiment estimate the bit period from the received signal and synchronize to obtain a large amount between the transmitter and the receiver. Even if there is a clock shift (about 0 to 20%), synchronization acquisition and synchronization tracking can be realized with high accuracy.

  The symbol clock recovery circuit can regenerate the symbol clock from the estimated bit period by substantially equally distributing the estimated bit period by the number of symbols per bit and outputting the symbol clock at the allocated interval.

  Also, in the symbol clock recovery circuit, if the number of clocks representing the estimated bit period is not divisible by the number of symbols per bit, the symbol clock is output by allocating the surplus clock so as to be centrally symmetric within one bit. By doing so, the shift of the symbol clock in one bit can be minimized.

  Also, the symbol clock recovery circuit can follow the received signal synchronously by adjusting the phase of the recovered symbol clock based on the signal that gives the timing for giving the maximum correlation value output from the comparison circuit. .

  Also, based on the timing signal giving the maximum correlation value notified by the comparison circuit, the symbol clock timing is adjusted by increasing / decreasing the bit period estimated by the bit period storage circuit, and the received IQ signal is followed. Can follow a wide range of synchronization.

  Also, synchronization tracking is performed while increasing / decreasing the estimated bit period for a fixed time after synchronization acquisition is completed, and then the bit period is fixed until reception is completed, and the phase of the recovered symbol clock is adjusted. Thus, it is possible to prevent the estimated bit period from being shaken due to noise or the like.

  In addition, synchronization tracking is performed while increasing or decreasing the estimated bit period until the preamble arrives, and then the bit period is fixed until reception is completed, and the phase of the recovered symbol clock is adjusted, so that the estimated bit period is It can be prevented from being shaken by the influence of noise or the like.

  In addition, after synchronization is established, synchronization tracking is performed while averaging the estimated bit period, the estimated bit period is fixed when the degree of increase / decrease of the bit period falls within a certain range, and then reception ends. Until then, it is possible to prevent the estimated bit period from being shaken by the influence of noise or the like by adjusting the phase of the reproduced symbol clock.

  When the estimated bit period is increased, the symbol clock is delayed by a preset time, and when the estimated bit period is reduced, the symbol clock is advanced by a preset time, so that the symbol clock adjustment range is preset. By doing so, the circuit can be simplified.

  In addition, the amount of synchronization deviation is monitored, the bit period correction amount corresponding to the degree of the deviation is obtained, and when the estimated bit period is increased, the symbol clock is delayed by the obtained correction amount, and the estimated bit period is reduced. In this case, it is possible to perform synchronization tracking with higher accuracy by performing correction in accordance with the amount of synchronization deviation, such as by advancing the correction amount obtained for the symbol clock.

  Further, by providing a filter such as a random walk filter at the output of the comparison circuit and removing the jitter of the timing signal that gives the maximum correlation value output from the comparison circuit, more accurate synchronization tracking can be realized.

  In addition, the synchronization acquisition circuit detects a peak value exceeding a preset threshold value for the synthesized signal of the received IQ signal, and synchronization is established when the adjacent peak interval is within a certain range. Therefore, by outputting the peak value timing and the estimated bit period, the arrival of the desired signal can be detected, and the synchronization tracking and demodulation operation can be started.

  In addition, the synchronization acquisition circuit detects a peak value exceeding a preset threshold value with respect to the synthesized signal of the received IQ signal, and synchronization is achieved when a plurality of continuous peak intervals are within a certain range. By assuming that it is established and outputting the timing of the peak value and the estimated bit period, the arrival of the desired signal can be detected, and the synchronization tracking and demodulation operation can be started.

  In addition, the synchronization acquisition circuit automatically sets a threshold value for the synthesized signal of the received IQ signal, detects a peak value exceeding the threshold value, and the adjacent peak interval is within a certain range. Sometimes it is considered that synchronization has been established, and by outputting the timing of the peak value and the estimated bit period, the arrival of the desired signal can be detected, and the synchronization tracking and demodulation operation can be started.

  In addition, the synchronization acquisition circuit automatically sets a threshold value for the synthesized signal of the received IQ signal, detects a peak value exceeding the threshold value, and a plurality of continuous peak intervals are within a certain range. It is assumed that synchronization has been established and the peak value timing and the estimated bit period are output, so that the arrival of the desired signal can be detected and the synchronization tracking and demodulation operation can be started.

  Further, the combined signal of the received IQ signal is set to | I (n) | + | Q (n) | or | I (n) + I (n + 1) | + | Q (n) + Q (n + 1) | The synchronization can be acquired with a simple circuit regardless of the phase of the received IQ signal.

Further, by combining the received IQ signal with I (n) ² + Q (n) ² or (I (n) + I (n + 1)) ² + (Q (n) + Q (n + 1)) ² , Synchronization can be accurately captured regardless of the phase of the received IQ signal.

  In addition, the noise level in the no-signal period immediately before the tag response returns is detected, and a value larger than the maximum value is automatically set as a threshold value, thereby reducing the influence of noise on synchronization acquisition. be able to.

  Further, by detecting the noise level every time the antenna is switched, the influence of noise on the synchronization acquisition can be reduced.

  Further, when the response from the tag cannot be received for a certain period, the noise level is detected again, thereby reducing the influence of noise on the synchronization acquisition.

  In addition, by detecting the received signal level from each tag and automatically setting a threshold value corresponding to the level each time, it is possible to reduce the influence of noise on synchronization acquisition.

  In addition, the signal level of the burst part of the preamble signal in the received signal from each tag is monitored for an arbitrary period, and a value smaller than the maximum value of that period is automatically set as a threshold value, depending on the received signal strength By setting a threshold value, synchronization acquisition can be performed with high accuracy.

  In addition, a pilot tone is added to the tag response, the signal level of the pilot tone is monitored for an arbitrary period, and a value smaller than the maximum value of the period is automatically set as a threshold value, thereby improving the received signal strength. By setting a threshold value accordingly, synchronization acquisition can be performed with high accuracy.

  Further, by setting the threshold value to ½ of the maximum value of the received signal detected by monitoring, the threshold value can be set according to the received signal strength, so that synchronization can be accurately captured.

  In addition, by detecting the value of any number of peaks in the burst part of the preamble signal in the received signal from each tag, and automatically setting a value smaller than the average value of these peaks as a threshold value, By setting the threshold value according to the signal strength, synchronization acquisition can be performed with high accuracy.

  Also, by adding a pilot tone to the tag response, detecting the value of an arbitrary number of peaks in the pilot tone portion, and automatically setting a value smaller than the average value of these peaks as a threshold value. By setting a threshold value according to the received signal strength, synchronization acquisition can be performed with high accuracy.

  Further, by setting the threshold value to ½ of the average value of a plurality of detected peaks, setting the threshold value according to the received signal strength enables accurate synchronization acquisition.

  When following the mirror subcarrier set value M = 2, four sets of (I, Q) data in one bit sampled by the secondary sampling circuit are used, and the correlation equation used by the correlation calculation circuit is calculated. By using the inner product of the first two sets of combined vectors and the second two sets of combined vectors, the calculation of synchronization tracking and data demodulation can be performed simultaneously using the absolute value and sign of the correlation value.

  Further, when following the mirror subcarrier set value M = 4, eight sets of (I, Q) data in one bit sampled by the secondary sampling circuit are used, and the correlation equation used by the correlation calculation circuit is By using the inner product of the first four sets of combined vectors and the second four sets of combined vectors, it is possible to simultaneously perform operations of synchronization tracking and data demodulation using the absolute value and sign of the correlation value.

  Further, when following the mirror subcarrier set value M = 8, 16 sets of (I, Q) data in 1 bit sampled by the secondary sampling circuit are used, and the correlation equation used by the correlation calculation circuit is calculated. By using the inner product of the first eight sets of combined vectors and the second eight sets of combined vectors, the calculation of synchronization tracking and data demodulation can be performed simultaneously using the absolute value and sign of the correlation value.

  In addition, if the regenerated symbol clock is advanced a certain number of times, the regenerative symbol clock is corrected incorrectly by stopping the regenerative clock from being advanced at the regenerative symbol clock correction time for the next or subsequent fixed period. Can be prevented.

  Also, if the reproduction symbol clock is delayed for a certain number of times, erroneous correction of the reproduction symbol clock is prevented by stopping delaying the reproduction clock at the reproduction symbol clock correction time for the next or subsequent fixed period. be able to.

  In addition, if the estimated bit period is increased for a certain number of times, the estimated bit period is incorrect by stopping increasing the estimated bit period at the estimated bit period correction time for the next or subsequent fixed period. Correction can be prevented.

  Also, if the estimated bit period is reduced a certain number of times, the estimated bit period is incorrect by stopping reducing the estimated bit period at the estimated bit period correction time for the next or subsequent fixed period. Correction can be prevented.

  The synchronization tracking circuit according to the present invention is configured to estimate the bit period from the received signal, adjust the timing based on the estimated bit period, and output the recovered clock. Increase or decrease the bit period. This has the effect that a high-speed and high-precision tracking operation can be performed, and is applied to a demodulation circuit such as a receiver used for communication.

Configuration diagram of a demodulation circuit including a synchronous tracking circuit according to the first embodiment of the present invention Configuration diagram of synchronization supplementary circuit in Embodiment 1 of the present invention Explanatory drawing of mirror subcarrier code in Embodiment 1 of the present invention Explanatory drawing of the secondary sampling in Embodiment 1 of this invention Explanatory drawing of the secondary sampling in Embodiment 1 of this invention Explanatory drawing of the secondary sampling in Embodiment 1 of this invention Explanatory drawing of the secondary sampling in Embodiment 1 of this invention Configuration diagram of a demodulation circuit including a synchronization tracking circuit according to the second embodiment of the present invention Configuration diagram of conventional synchronous tracking circuit

Explanation of symbols

110 Threshold decision circuit 120, 820 Synchronization supplement circuit 130, 830 Bit period storage circuit 140, 840 Symbol clock recovery circuit 150, 151, 850, 851 Secondary sampling circuit 160, 860 Correlation operation circuit 170, 870 Comparison circuit 180, 880 Data judgment circuit 810 Threshold memory circuit

Claims (34)

A synchronization acquisition circuit for establishing synchronization with the received IQ signal;
A bit period storage circuit for storing a bit period estimated at the time of synchronization acquisition;
A symbol clock recovery circuit for notifying the symbol clock and the timing before and after that using the estimated bit period;
A secondary sampling circuit for performing secondary sampling of the received IQ signal at a timing output from the symbol clock recovery circuit;
A correlation calculation circuit for performing a correlation calculation with a reference signal using the secondary sampling data output from the secondary sampling circuit and outputting a correlation value;
A comparison circuit that compares the correlation values of the symbol timing and the timing before and after the symbol timing and outputs a timing that gives the maximum correlation value;
A synchronization follow-up circuit, comprising: a data determination circuit that performs data determination based on a correlation value output from the correlation calculation circuit. 2. The synchronization tracking circuit according to claim 1, wherein the symbol clock recovery circuit distributes the estimated bit period substantially evenly by the number of symbols per bit and outputs a symbol clock at the allocated intervals. In the symbol clock recovery circuit, when the number of clocks representing the estimated bit period is not divisible by the number of symbols per bit, the remainder clock is allocated so as to be centrally symmetric in one bit and the symbol clock is output. The synchronous follow-up circuit according to claim 2. 4. The symbol clock recovery circuit adjusts the phase of a recovered symbol clock based on a signal for notifying a timing for giving a maximum correlation value output from the comparison circuit. 2. The synchronous tracking circuit according to item 1. Based on the timing signal giving the maximum correlation value notified by the comparison circuit, the bit period storage circuit adjusts the symbol clock timing by increasing or decreasing the estimated bit period, and follows the received IQ signal. The synchronous tracking circuit according to any one of claims 1 to 4. Synchronous tracking is performed while increasing or decreasing the estimated bit period for a predetermined time after synchronization acquisition is completed.After that, the bit period is fixed until reception is completed, and synchronization tracking is performed by adjusting the phase of the recovered symbol clock. 6. The synchronization tracking circuit according to claim 5, wherein the synchronization tracking circuit is performed. Until the preamble arrives, the synchronization tracking is performed while increasing or decreasing the estimated bit period, and then the synchronization is performed by fixing the bit period and adjusting the phase of the regenerated symbol clock until reception ends. The synchronous tracking circuit according to claim 5. After synchronization is established, synchronization tracking is performed while averaging the estimated bit period, and the estimated bit period is fixed when the degree of increase / decrease of the bit period falls within a certain range, and then until reception is completed 6. The synchronization tracking circuit according to claim 5, wherein synchronization tracking is performed by adjusting a phase of a reproduction symbol clock. 9. The symbol clock is delayed by a preset time when the estimated bit period is increased, and the symbol clock is advanced by a preset time when the estimated bit period is reduced. 2. The synchronous tracking circuit according to item 1. The amount of synchronization deviation is monitored, the bit period correction amount corresponding to the degree of the deviation is obtained, and when the estimated bit period is increased, the symbol clock is delayed by the obtained correction amount, and when the estimated bit period is reduced. 9. The synchronization tracking circuit according to claim 1, wherein the symbol clock is advanced by a correction amount obtained. 11. The synchronous follow-up circuit according to claim 1, further comprising a filter at an output of the comparison circuit to remove jitter of a timing signal that gives a maximum correlation value output from the comparison circuit. The synchronous tracking circuit according to claim 11, wherein a random walk filter is used as a filter for removing jitter. The synchronization acquisition circuit detects a peak value exceeding a preset threshold value for a synthesized signal of the received IQ signal, and synchronization is established when the adjacent peak interval is within a certain range. 13. The synchronous follow-up circuit according to claim 1, wherein the synchronous follow-up circuit outputs a peak value timing and an estimated bit period. The synchronization acquisition circuit detects a peak value exceeding a preset threshold value with respect to a synthesized signal of the received IQ signal, and synchronization is established when a plurality of consecutive peak intervals are within a certain range. The synchronous follow-up circuit according to any one of claims 1 to 12, wherein the synchronous tracking circuit outputs a timing of a peak value and an estimated bit period. The synchronization acquisition circuit sets a threshold value for the synthesized signal of the received IQ signal, detects a peak value exceeding the threshold value, and synchronizes when the adjacent peak interval is within a certain range. The synchronous follow-up circuit according to claim 1, wherein the timing of the peak value and the estimated bit period are output. The synchronization acquisition circuit sets a threshold value for a synthesized signal of the received IQ signal, detects a peak value exceeding the threshold value, and a plurality of continuous peak intervals are within a certain range. The synchronization follow-up circuit according to any one of claims 1 to 12, wherein synchronization is established, and the timing of the peak value and the estimated bit period are output. The combined signal of the received IQ signals is | I (n) | + | Q (n) |, I (n) ² + Q (n) ² , | I (n) + I (n + 1) | + | Q (n) Any one of + Q (n + 1) | and (I (n) + I (n + 1)) ² + (Q (n) + Q (n + 1)) ² The synchronous tracking circuit described. 18. A noise level in a no-signal period immediately before a response from a communication partner is returned, and a value larger than the maximum value is set as a threshold value. The synchronous follow-up circuit described in 1. 19. The synchronous tracking circuit according to claim 18, wherein the noise level is detected each time the antenna is switched. 19. The synchronous follow-up circuit according to claim 18, wherein when the response from the communication partner cannot be received for a certain period, the noise level is detected again. 18. The synchronous follow-up circuit according to claim 15, wherein the level of a received signal from a communication partner is detected, and a threshold value corresponding to the level is set. 22. The synchronous follow-up circuit according to claim 21, wherein the signal level of the burst portion of the preamble signal in the received signal from the communication partner is monitored for an arbitrary period, and a value smaller than the maximum value of the period is set as a threshold value. . The pilot tone is added to a response from a communication partner, the signal level of the pilot tone is monitored for an arbitrary period, and a value smaller than the maximum value of the period is set as a threshold value. Synchronous tracking circuit. 24. The synchronous tracking circuit according to claim 22, wherein the threshold value is set to ½ of the maximum value of the received signal detected by monitoring. 22. The value of an arbitrary number of peaks in a burst portion of a preamble signal in a received signal from a communication partner is detected, and a value smaller than the average value of the plurality of peaks is set as a threshold value. Synchronous tracking circuit. A pilot tone is added to a response from a communication partner, an arbitrary number of peak values of the pilot tone portion are detected, and a value smaller than the average value of the plurality of peaks is set as a threshold value. The synchronous tracking circuit according to claim 25. 27. The synchronous follow-up circuit according to claim 25 or 26, wherein the threshold value is ½ of an average value of a plurality of detected peaks. When following the mirror subcarrier set value M = 2, four sets of (I, Q) data in one bit sampled by the secondary sampling circuit are used, and a correlation equation used by the correlation calculation circuit is obtained. The synchronous tracking circuit according to any one of claims 1 to 27, wherein the synchronous tracking circuit is an inner product of two combined vectors of the first half and two combined vectors of the second half. When following the mirror subcarrier set value M = 4, 8 sets of (I, Q) data in 1 bit sampled by the secondary sampling circuit are used, and a correlation equation used by the correlation calculation circuit is obtained. 28. The synchronous tracking circuit according to claim 1, wherein the synchronous tracking circuit is an inner product of the combined vector of the first half 4 and the combined vector of the latter 4 sets. When following the set value M = 8 of the mirror subcarrier, 16 sets of (I, Q) data in 1 bit sampled by the secondary sampling circuit are used, and a correlation equation used by the correlation calculation circuit is obtained. The synchronous tracking circuit according to any one of claims 1 to 27, wherein the synchronous tracking circuit is an inner product of the combined vector of the first half 8 and the combined vector of the second half 8. 31. When the reproduction symbol clock is advanced a predetermined number of times, the advancement of the reproduction clock is stopped at the time of reproduction symbol clock correction for the next or subsequent fixed period. 2. The synchronous tracking circuit according to item 1. 32. When the reproduction symbol clock is delayed for a certain number of times, delaying the reproduction clock at the reproduction symbol clock correction time is stopped for the next or subsequent fixed period. The synchronous follow-up circuit described in 1. 35. The increase in the estimated bit period is stopped at the estimated bit period correction time point when the estimated bit period is increased a predetermined number of times, for the next or subsequent fixed period. The synchronization tracking circuit according to any one of the preceding claims. 34. The reduction of the estimated bit period is stopped at the estimated bit period correction time point when the estimated bit period is reduced a predetermined number of times, for the next or subsequent fixed period. The synchronization tracking circuit according to any one of the preceding claims.

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