JP2009088368A - Method of manufacturing low-resistance chip resistor - Google Patents

Method of manufacturing low-resistance chip resistor Download PDF

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JP2009088368A
JP2009088368A JP2007258289A JP2007258289A JP2009088368A JP 2009088368 A JP2009088368 A JP 2009088368A JP 2007258289 A JP2007258289 A JP 2007258289A JP 2007258289 A JP2007258289 A JP 2007258289A JP 2009088368 A JP2009088368 A JP 2009088368A
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electrode film
film
surface electrode
layer
resistor
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Hideki Hayashi
英樹 林
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Kamaya Electric Co Ltd
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Kamaya Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a low-resistance chip resistor with which reliability can be obtained as an electrode by sufficiently ensuring an overlapping portion of a surface electrode film and an end face electrode film, furthermore, an insulating substrate can be relatively easily divided along a dividing groove and in division, burrs hardly occur. <P>SOLUTION: In a chip resistor 10, the surface electrode film 12 is formed in a triple-layer structure comprising a lower layer 12a, an intermediate layer 12b and an upper layer 12c. The surface electrode film 12 is constituted of a material with copper as a main component. The lower layer 12a is formed so as to be spaced apart from a dividing groove 11b in a secondary direction over a dividing groove 11a in a primary direction, the intermediate layer 12b is formed so as to be spaced apart from the dividing grooves 11a, 11b in the primary and secondary directions and to be thicker than the surface electrode film lower layer 12a and further, the upper layer 12c is formed so as to be spaced apart from the dividing grooves 11a, 11b in the primary and secondary direction and, by providing an end face electrode film 16 and an electrode plating film 17 herein, to be higher than a resistor film 13 and a protecting film 14. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、低抵抗チップ抵抗器の製造方法に関し、特に、フェースダウン実装される低抵抗のチップ抵抗器の製造方法に関する。   The present invention relates to a method for manufacturing a low resistance chip resistor, and more particularly to a method for manufacturing a low resistance chip resistor to be face-down mounted.

チップ抵抗器を製造する慣用の方法として、最初に、分割溝が刻設されたアルミナ製の絶縁基板において分割溝を跨ぐように表電極膜を形成し、次に、両表電極膜間を接続するように抵抗膜を形成するものがある。ここで、表電極膜は、銀粉、ガラス粉、ビヒクル及び溶剤等が混練されてなる銀ペーストを用いて、スクリーン印刷法でアルミナ基板に印刷し、これを乾燥させた後にピーク温度850℃程度で焼成して形成する。また抵抗膜は、銀粉、パラジウム粉、ガラス粉、ビヒクル及び溶剤等が混練されてなる抵抗ペーストを用いて、表電極膜と同様に、スクリーン印刷、乾燥、焼成を行うことにより形成する。   As a conventional method of manufacturing a chip resistor, first, a surface electrode film is formed so as to straddle the dividing groove on an insulating substrate made of alumina in which the dividing groove is engraved, and then the surface electrode films are connected to each other. Some of them form a resistance film. Here, the surface electrode film is printed on an alumina substrate by a screen printing method using a silver paste in which silver powder, glass powder, a vehicle, a solvent and the like are kneaded, and after drying this, the peak temperature is about 850 ° C. It is formed by firing. The resistance film is formed by screen printing, drying, and baking in the same manner as the surface electrode film, using a resistance paste in which silver powder, palladium powder, glass powder, a vehicle, a solvent, and the like are kneaded.

しかしながら、上述の製造方法により、50mΩ以下でTCR300×10-6/℃のチップ抵抗器を製造することは容易ではない。これを実現するために、面積抵抗0.1Ω/□である抵抗ペーストを使用し、焼成後の抵抗膜の膜厚を20μm程度に形成することが考えられるが、この方法では、低抵抗チップ抵抗器の厚さが規定の寸法より厚くなってしまうという問題があった。さらに電極部の抵抗値を小さくする必要がある。 However, it is not easy to manufacture a chip resistor having a TCR of 300 × 10 −6 / ° C. at 50 mΩ or less by the above manufacturing method. In order to realize this, it is conceivable to use a resistance paste having a sheet resistance of 0.1Ω / □ and to form a fired resistive film with a thickness of about 20 μm. There is a problem that the thickness of the vessel becomes thicker than the prescribed dimension. Furthermore, it is necessary to reduce the resistance value of the electrode portion.

このような課題を解決するために、表電極膜及び抵抗膜に銅系厚膜を適用することが考えられている。
例えば、膜厚12μmで面積抵抗2mΩ/□を実現しようとするとき、銅系厚膜を適用する場合、そのペーストの組成は、例えば、銅粉75〜85%、ガラス粉1〜5%、ビヒクル及び溶剤10〜24%になる。これに対し、従来の銀系厚膜を適用する場合、そのペーストの組成は、例えば、銀粉70%、ガラス粉9%、ビヒクル及び溶剤21%になる。
両者を比較すると、銅系厚膜では、ガラス粉の含有率が5%程度少なくなる一方で、導電粉(銅粉又は銀粉)の含有率が5%程度多くなる。したがって、銅系厚膜を適用することにより、上述したチップ抵抗器の製造方法と同様に、絶縁基板の分割溝を跨ぐ表電極膜を形成した場合には、銀系厚膜に比べて、分割溝に沿った絶縁基板の切断が容易でなくなるという問題が生じてしまう。
In order to solve such a problem, it is considered to apply a copper-based thick film to the surface electrode film and the resistance film.
For example, when a copper-based thick film is applied to achieve a sheet resistance of 2 mΩ / □ with a film thickness of 12 μm, the composition of the paste is, for example, 75% to 85% copper powder, 1% to 5% glass powder, vehicle And 10-24% of solvent. On the other hand, when a conventional silver-based thick film is applied, the composition of the paste is, for example, 70% silver powder, 9% glass powder, 21% vehicle and solvent.
When both are compared, in the copper-based thick film, the content of glass powder decreases by about 5%, while the content of conductive powder (copper powder or silver powder) increases by about 5%. Therefore, by applying a copper-based thick film, the surface electrode film straddling the dividing groove of the insulating substrate is formed as compared with the silver-based thick film, as in the above-described chip resistor manufacturing method. There arises a problem that it becomes difficult to cut the insulating substrate along the groove.

ところで、低抵抗かつ低TCRのチップ抵抗器を実現する際に阻害要因となる、端面電極の抵抗値の影響を低減するため、抵抗膜の在る面を回路基盤の部品搭載面に向けて実装されるチップ抵抗器が知られており、このようなフェースダウン実装されるチップ抵抗器において、抵抗膜を、銅/ニッケル合金を主成分とする材料から構成するものが特許文献1及び2に記載されている。   By the way, in order to reduce the influence of the resistance value of the end face electrode, which becomes a hindrance when realizing a low resistance and low TCR chip resistor, the surface on which the resistance film exists is mounted toward the circuit board component mounting surface. A chip resistor is known, and in such a face-down mounted chip resistor, a resistor film made of a material mainly composed of a copper / nickel alloy is described in Patent Documents 1 and 2. Has been.

特許文献1のチップ抵抗器は、セラミック基板下面の長手方向両端部に一対の嵩上げ下地部が設けられ、これらの嵩上げ下地部の少なくとも一部を覆うように一対の第1電極層が設けられ、一対の第1電極層どうしを橋絡するように銅/ニッケル合金を主成分とする抵抗体が形成され、一対の第1電極層を覆うようにそれぞれ第2電極層が形成され、さらに、抵抗体を覆うように保護層が設けられたものである。またセラミック基板の両端面には、基板上面に設けられた上部電極層と、第1電極層及び第2電極層とを接続すべく、それぞれ端面電極が形成され、この端面電極がめっき層により覆われている。   The chip resistor of Patent Document 1 is provided with a pair of raised base portions at both longitudinal ends of the lower surface of the ceramic substrate, and a pair of first electrode layers so as to cover at least a part of these raised base portions, A resistor mainly composed of a copper / nickel alloy is formed so as to bridge the pair of first electrode layers, a second electrode layer is formed so as to cover the pair of first electrode layers, and a resistance A protective layer is provided to cover the body. Further, on both end faces of the ceramic substrate, end face electrodes are respectively formed to connect the upper electrode layer provided on the upper face of the substrate with the first electrode layer and the second electrode layer, and these end face electrodes are covered with a plating layer. It has been broken.

また特許文献2には、低抵抗かつ低TCRな銅/ニッケル合金を主成分とする抵抗体がセラミック基板の下面に形成され、この抵抗体の長手方向両端部を覆うように第1電極層及び第2電極層が2層構造で設けられ、抵抗体を覆うように絶縁性の保護層が設けられ、セラミック基板の上面両端には上部電極層が設けられたチップ抵抗器が記載されている。この上部電極層と、第1電極層及び第2電極層とは、それぞれセラミック基板の両端面に設けられた端面電極により接続されている。
特開2007−88161号公報 特開2007−88162号公報
In Patent Document 2, a resistor mainly composed of a copper / nickel alloy having a low resistance and a low TCR is formed on the lower surface of the ceramic substrate, and the first electrode layer and the first electrode layer are formed so as to cover both longitudinal ends of the resistor. A chip resistor is described in which a second electrode layer is provided in a two-layer structure, an insulating protective layer is provided so as to cover the resistor, and upper electrode layers are provided at both ends of the upper surface of the ceramic substrate. The upper electrode layer, the first electrode layer, and the second electrode layer are connected to each other by end face electrodes provided on both end faces of the ceramic substrate.
JP 2007-88161 A JP 2007-88162 A

特許文献1の第0018段落には、「第1および第2電極層4,6は各チップ領域の周縁と重なり合わないように印刷されるため、これら両電極層4,6が大判基板の分割用ブレイク溝に入り込む虞は少ない」と記載されており、また特許文献2の第0017段落にも同様な記載がある。
このように分割用ブレイク溝に電極層の材料が入り込んでない場合、例えば、銅を主成分とする材料から電極層を構成したとしても、一次分割して短冊状基板を形成したときに、バリを生じないという利点が得られる。
しかしながら、分割用ブレイク溝に電極層の材料が全く入り込んでない短冊状基板の両端面に対し、スパッタリングを施して端面電極膜を形成した場合には、第1電極層及び第2電極層の端辺と、端面電極膜との重なり部分が少なくなってしまう虞がある。このように十分な重なり部分が得られない場合、この重なり部分における抵抗値が高くなってしまい、チップ抵抗器の低抵抗化が困難になる。
In paragraph 0018 of Patent Document 1, “the first and second electrode layers 4 and 6 are printed so as not to overlap with the periphery of each chip region. There is little risk of entering the break groove for use ", and there is a similar description in paragraph 0017 of Patent Document 2.
In this way, when the electrode layer material does not enter the dividing break groove, for example, even if the electrode layer is made of a material mainly composed of copper, burrs are not generated when the strip-shaped substrate is formed by primary division. The advantage of not occurring is obtained.
However, when the end face electrode films are formed by sputtering the both end faces of the strip-shaped substrate in which the material of the electrode layer does not enter the breaking break grooves, the edges of the first electrode layer and the second electrode layer are formed. Then, there is a possibility that the overlapping portion with the end face electrode film is reduced. When a sufficient overlapping portion cannot be obtained in this way, the resistance value at the overlapping portion becomes high, and it is difficult to reduce the resistance of the chip resistor.

本発明は、上記課題を解決しようとするものであり、その目的は、表電極膜と端面電極膜との重なり部分が十分に確保されて電極としての信頼性が得られ、しかも、銅を主成分とする材料により表電極膜を構成した場合であっても、分割溝に沿った絶縁基板の分割が比較的容易であり、分割したときにバリが生じ難くい低抵抗チップ抵抗器の製造方法を提供することである。   An object of the present invention is to solve the above-mentioned problems. The object of the present invention is to sufficiently secure an overlapping portion between the surface electrode film and the end face electrode film, to obtain reliability as an electrode, and to mainly use copper. A method of manufacturing a low-resistance chip resistor in which the insulating substrate along the dividing groove is relatively easy to divide even when the surface electrode film is composed of the component material, and burrs are not easily generated when divided. Is to provide.

本発明では、以下に記載する(1)及び(2)の手段により上記課題が解決される。   In the present invention, the above problems are solved by means (1) and (2) described below.

(1)矩形に区画するように一次方向及び二次方向の分割溝が表裏面に刻設された絶縁基板の表面に、前記一次方向の分割溝を跨ぎ、且つ前記二次方向の分割溝から離間するように表電極膜下層を形成する表電極膜下層形成工程と、当該表電極膜下層上において前記絶縁基板の一次及び二次方向の分割溝から離間し、且つ前記表電極膜下層よりも厚く表電極膜中間層を形成する表電極膜中間層形成工程と、当該表電極膜中間層どうしを接続し、これらの一部を覆う抵抗体膜を形成する抵抗体膜形成工程と、前記表電極膜中間層上において前記絶縁基板の一次及び二次方向の分割溝から離間し、前記抵抗体膜に接触せず、且つ前記抵抗体膜よりも高くなるように表電極膜上層を形成する表電極膜上層形成工程と、前記抵抗体膜の抵抗値調整のためのトリミング溝を刻設するトリミング溝刻設工程と、前記抵抗体膜を覆うように保護膜を形成する保護膜形成工程と、前記絶縁基板を一次方向の分割溝に沿って短冊状に分割する一次分割工程と、前記絶縁基板の左右端面を覆い裏電極膜及び表電極膜下層のそれぞれ一部に重畳するように、スパッタ法により端面電極膜を形成する端面電極膜形成工程と、前記絶縁基板を二次方向の分割溝に沿ってチップ状に分割する二次分割工程と、前記裏電極膜、表電極膜下層、表電極膜中間層、表電極膜上層及び端面電極膜を覆うように電極めっき膜を形成する電極めっき膜形成工程とを備え、前記表電極膜下層、表電極膜中間層、表電極膜上層及び前記抵抗体膜は、少なくともCu及びSiO2を含むガラス粉からなるペースト材料の焼成により形成することを特徴とする低抵抗チップ抵抗器の製造方法。 (1) From the surface of the insulating substrate in which the primary and secondary dividing grooves are engraved on the front and back surfaces so as to divide into rectangles, straddling the primary dividing grooves and from the secondary dividing grooves A surface electrode film lower layer forming step of forming a surface electrode film lower layer so as to be spaced apart, and spaced apart from the division grooves in the primary and secondary directions of the insulating substrate on the surface electrode film lower layer, and more than the surface electrode film lower layer A surface electrode film intermediate layer forming step for forming a thick surface electrode film intermediate layer, a resistor film forming step for connecting the surface electrode film intermediate layers to each other, and forming a resistor film covering a part of these, A front electrode film upper layer is formed on the electrode film intermediate layer so as to be separated from the primary and secondary dividing grooves of the insulating substrate, not to contact the resistor film, and to be higher than the resistor film. The electrode film upper layer forming step and the resistance value adjustment of the resistor film A trimming groove engraving step for engraving the trimming groove, a protective film forming step for forming a protective film so as to cover the resistor film, and dividing the insulating substrate into strips along the division grooves in the primary direction. A primary division step, an end face electrode film forming step of forming an end face electrode film by a sputtering method so as to cover the left and right end faces of the insulating substrate and overlap each part of the back electrode film and the lower layer of the front electrode film, and the insulating substrate A secondary dividing step of dividing the electrode into a chip shape along the dividing groove in the secondary direction, and an electrode so as to cover the back electrode film, the front electrode film lower layer, the front electrode film intermediate layer, the front electrode film upper layer and the end face electrode film An electrode plating film forming step of forming a plating film, wherein the surface electrode film lower layer, the surface electrode film intermediate layer, the surface electrode film upper layer, and the resistor film are made of glass powder containing at least Cu and SiO 2 Formed by firing A method of manufacturing a low resistance chip resistor.

(2)前記表電極膜下層は5〜10μmの膜厚に形成し、前記表電極膜中間層は15〜20μmの膜厚に形成することを特徴とする前記(1)に記載の低抵抗チップ抵抗器の製造方法。   (2) The low resistance chip according to (1), wherein the surface electrode film lower layer is formed to a thickness of 5 to 10 μm, and the surface electrode film intermediate layer is formed to a thickness of 15 to 20 μm. Manufacturing method of resistors.

本発明において、表電極膜下層の膜厚は、絶縁基板の表面における一次方向の分割溝の深さ及び幅と比較して薄く形成すれば良く、これにより、絶縁基板は一次方向の分割溝に沿って分割し易くなり、且つ端面に生じるバリを抑制することができる。
例えば、絶縁基板の汎用品として用いられているものに、表面の一次方向の分割溝の深さが170〜230μm程度、分割溝の最大幅が10〜30μm程度に形成されたのものがあり、このような絶縁基板を用いる場合、表電極膜下層の膜厚は、前記(2)の製造方法における5〜10μm程度を推奨することができる。
なお、スクリーン印刷法により表電極膜下層を形成する場合、その膜厚を薄くしすぎると、印刷したパターンにカスレが発生する可能性があり、これを考慮して上述のように5〜10μm程度の厚膜にすることが好ましい。
In the present invention, the thickness of the lower layer of the surface electrode film may be formed thinner than the depth and width of the primary direction dividing grooves on the surface of the insulating substrate, whereby the insulating substrate is formed into the primary direction dividing grooves. It becomes easy to divide along, and the burr | flash which arises in an end surface can be suppressed.
For example, the insulating substrate used as a general-purpose product is one in which the depth of the dividing groove in the primary direction of the surface is about 170 to 230 μm and the maximum width of the dividing groove is about 10 to 30 μm. When such an insulating substrate is used, the thickness of the lower layer of the surface electrode film can be recommended to be about 5 to 10 μm in the production method (2).
In addition, when forming the surface electrode film lower layer by the screen printing method, if the film thickness is too thin, there is a possibility that the printed pattern may be blurred. Considering this, about 5 to 10 μm as described above. It is preferable to use a thick film.

本発明の低抵抗チップ抵抗器の製造方法において、表電極膜下層は、絶縁基板上に刻設された一次方向の分割溝を跨ぐように形成する一方で、表電極膜中間層及び表電極膜上層は、一次及び二次方向の分割溝から離間するように形成するものであるため、これら三層構造の表電極膜は銅を主成分とする材料から形成されるものであるにも拘わらず、一次方向の分割溝に沿った絶縁基板の分割は容易になり、この分割端面に生じるバリを抑制することも可能になり、さらに、三層構造からなる表電極膜における導体抵抗を低減し、チップ抵抗器の低抵抗化を可能にする。
また本発明の製造方法によれば、三層構造からなる表電極膜のうち、表電極膜下層は、表電極膜中間層及び表電極膜上層よりも薄く形成され、一次分割された後も一次方向の分割溝であった面にそのまま残されるため、端面電極は、表電極膜下層に対して十分な重なり面を確保することができて、電極としての信頼性の低下を防止することができる。
In the method for manufacturing a low resistance chip resistor of the present invention, the surface electrode film lower layer is formed so as to straddle the primary direction dividing grooves formed on the insulating substrate, while the surface electrode film intermediate layer and the surface electrode film Since the upper layer is formed so as to be separated from the dividing grooves in the primary and secondary directions, the surface electrode film having the three-layer structure is formed from a material mainly composed of copper. In addition, it becomes easy to divide the insulating substrate along the dividing grooves in the primary direction, it is possible to suppress burrs generated on the dividing end faces, and further reduce the conductor resistance in the surface electrode film having a three-layer structure, The resistance of the chip resistor can be reduced.
According to the production method of the present invention, the surface electrode film lower layer of the surface electrode film having a three-layer structure is formed thinner than the surface electrode film intermediate layer and the surface electrode film upper layer, and is primary even after the primary division. Since the end surface electrode is left as it is on the surface that was the dividing groove in the direction, the end surface electrode can secure a sufficient overlapping surface with respect to the lower layer of the surface electrode film, and can prevent a decrease in reliability as an electrode. .

以下、図面を参照して本発明の実施の形態について説明するが、本発明はこれに限定されるものではない。
図1は本発明により製造されるチップ抵抗器10の断面図である。
チップ抵抗器10は、アルミナ等から成る絶縁基板11の表面の両端に、銅を主成分とする表電極膜12が下層12a、中間層12b及び上層12cの三層から形成され、両端の表電極膜12間に銅を主成分とする抵抗体膜13が形成され、抵抗体膜13にはトリミング溝13aが設けられ、抵抗体膜13の上にエポキシ樹脂材料を主成分とする保護層14が形成され、絶縁基板11の裏面の両端に裏電極膜15が形成され、裏電極膜15と表電極膜下層12aとを接続するように絶縁基板11の両端面に端面電極膜16が形成され、銅、ニッケル及びスズからなる電極めっき膜17が端面電極膜16、裏電極膜15及び表電極膜12を被覆するように形成されている。
Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
FIG. 1 is a cross-sectional view of a chip resistor 10 manufactured according to the present invention.
In the chip resistor 10, a surface electrode film 12 mainly composed of copper is formed from three layers of a lower layer 12a, an intermediate layer 12b and an upper layer 12c on both ends of the surface of an insulating substrate 11 made of alumina or the like. A resistor film 13 mainly composed of copper is formed between the films 12, a trimming groove 13 a is provided in the resistor film 13, and a protective layer 14 mainly composed of an epoxy resin material is formed on the resistor film 13. The back electrode film 15 is formed on both ends of the back surface of the insulating substrate 11, and the end face electrode films 16 are formed on both end surfaces of the insulating substrate 11 so as to connect the back electrode film 15 and the front electrode film lower layer 12a. An electrode plating film 17 made of copper, nickel and tin is formed so as to cover the end face electrode film 16, the back electrode film 15 and the front electrode film 12.

次に、図2乃至図4を参照して本発明のチップ抵抗器の製造方法について説明する。
図2(a)〜(c)は絶縁基板の表側から見た平面図であり、図2(d)〜(f)は図2(a)におけるA−A部分を切断した断面図である。
最初に、図2(a)(d)に示したように、絶縁基板11の表面に表電極膜下層12aを形成する。
絶縁基板11の表裏面には、矩形に区画するように一次方向及び二次方向に分割溝11a,11bが刻設され、特に、一次方向の分割溝11aは200μm程度の深さに形成される。また表電極膜下層12aの材料としては、Cu及びSiO2を含むペーストを使用することが可能であり、さらに詳細には、Cu粉が75〜85%、SiO2を含むガラス粉が1〜5%、ビヒクル及び溶剤が10〜24%程度の割合で混練りされたペーストを使用することができる。
このようなペーストをスクリーン印刷法により、図2(a)(d)に示したパターン、すなわち、一次方向の分割溝11aを跨ぎ、且つ二次方向の分割溝11bから離間するようなパターンで絶縁基板11に印刷し、窒素雰囲気中においてピーク温度900℃程度で焼成し、膜厚5〜10μm程度の表電極膜下層12aを形成する。この表電極膜下層12aの膜厚は、一次方向の分割溝11aの深さ200μmに比較して極めて薄いものであるため、表電極膜下層12aは、図2(d)に示したように分割溝11aの表面に沿った断面形状で形成される。
Next, a manufacturing method of the chip resistor of the present invention will be described with reference to FIGS.
2A to 2C are plan views as viewed from the front side of the insulating substrate, and FIGS. 2D to 2F are cross-sectional views taken along line AA in FIG.
First, as shown in FIGS. 2A and 2D, the surface electrode film lower layer 12 a is formed on the surface of the insulating substrate 11.
Split grooves 11a and 11b are formed on the front and back surfaces of the insulating substrate 11 in a primary direction and a secondary direction so as to be divided into rectangles. In particular, the split grooves 11a in the primary direction are formed to a depth of about 200 μm. . Moreover, as a material of the surface electrode film lower layer 12a, it is possible to use a paste containing Cu and SiO 2. More specifically, 75 to 85% of Cu powder and 1 to 5 of glass powder containing SiO 2 are used. %, Vehicle and solvent can be used in a proportion of about 10 to 24%.
The paste is insulated by the screen printing method with the pattern shown in FIGS. 2A and 2D, that is, a pattern that straddles the dividing groove 11a in the primary direction and is separated from the dividing groove 11b in the secondary direction. The substrate 11 is printed and fired at a peak temperature of about 900 ° C. in a nitrogen atmosphere to form a surface electrode film lower layer 12a having a thickness of about 5 to 10 μm. Since the thickness of the surface electrode film lower layer 12a is extremely thin compared to the depth 200 μm of the dividing groove 11a in the primary direction, the surface electrode film lower layer 12a is divided as shown in FIG. It is formed in a cross-sectional shape along the surface of the groove 11a.

次に、表電極膜下層12aの上に表電極膜中間層12bを形成する。
表電極膜中間層12bは、表電極膜下層12aと同じペースト材料を使用し、スクリーン印刷法により、図2(b)(e)に示したパターン、つまり、一次方向の分割溝11a及び二次方向の分割溝11bから離間するようなパターンで印刷し、窒素雰囲気中においてピーク温度900℃程度で焼成し、膜厚15〜20μm程度に形成する。表電極膜中間層12bは、チップ抵抗器10の抵抗値に応じて両端の表電極膜12の間隔を調節する機能を有するものである。
表電極膜中間層12bは、表電極膜下層12aよりも大きな膜厚で形成されるものであるが、どの程度まで厚くするかは、表電極膜12自体の抵抗値として許容される範囲に応じて適宜決められる。
Next, the surface electrode film intermediate layer 12b is formed on the surface electrode film lower layer 12a.
The surface electrode film intermediate layer 12b uses the same paste material as that of the surface electrode film lower layer 12a, and the pattern shown in FIGS. 2B and 2E, that is, the dividing grooves 11a and the secondary in the primary direction are formed by screen printing. It prints with the pattern which leaves | separates from the direction division | segmentation groove | channel 11b, and it bakes at the peak temperature of about 900 degreeC in nitrogen atmosphere, and forms it by about 15-20 micrometers in film thickness. The surface electrode film intermediate layer 12 b has a function of adjusting the distance between the surface electrode films 12 at both ends in accordance with the resistance value of the chip resistor 10.
The surface electrode film intermediate layer 12b is formed with a film thickness larger than that of the surface electrode film lower layer 12a. The thickness of the surface electrode film intermediate layer 12b depends on the allowable range of the resistance value of the surface electrode film 12 itself. As appropriate.

次に、抵抗体膜13を、図2(c)(f)に示したように形成する。
抵抗体膜13の材料としては、例えば、銅粉、ニッケル粉の混合粉や合金粉と鉛フリーのガラス、ビヒクル、溶剤からなるペーストを使用することができる。このようなペーストをスクリーン印刷法により、図2(c)(f)に示したパターン、すなわち、表電極膜下層12a及び二次方向の分割溝11bから離間し、表電極膜中間層12bの一部を覆い、且つ表電極膜中間層12bの間の絶縁基板11上を覆うようなパターンで印刷し、窒素雰囲気中においてピーク温度900℃で焼成することにより形成する。
Next, the resistor film 13 is formed as shown in FIGS.
As the material of the resistor film 13, for example, a paste made of a mixed powder or alloy powder of copper powder or nickel powder and lead-free glass, vehicle, or solvent can be used. Such a paste is separated from the pattern shown in FIGS. 2C and 2F by the screen printing method, that is, from the surface electrode film lower layer 12a and the dividing groove 11b in the secondary direction, to form one surface electrode film intermediate layer 12b. And is printed by a pattern that covers the insulating substrate 11 between the surface electrode film intermediate layers 12b and baked at a peak temperature of 900 ° C. in a nitrogen atmosphere.

抵抗体膜13を形成した後、図3(a)に示したように、表電極膜中間層12bの上に表電極膜上層12cを形成する。表電極膜上層12cは、表電極膜下層12aと同じペースト材料を使用し、スクリーン印刷法により、一次方向の分割溝11a及び二次方向の分割溝11bから離間し、かつ抵抗体膜13からも離間する配置で印刷し、窒素雰囲気中においてピーク温度900℃程度で焼成し、膜厚10〜15μm程度に形成する。
ここで、表電極膜上層12cを抵抗体膜13から離間した理由は、これらが重なることにより表電極膜上層12cの表面に高低差ができることを防止し、チップ抵抗器10をフェースダウン実装に適した形状にするためである。
また表電極膜上層12cは、チップ抵抗器10を回路基盤にフェースダウン実装するときに、部品搭載面に接触するものであるため、これに適応できるように、電気めっき層形成後、保護膜14より高く形成するための補助として形成される。これは、電気めっき層のみにより保護膜14より高く形成しようとすると、チップ抵抗器10の横方向の寸法が規定した値を超える可能性があるからである。
以上のように表電極膜下層12a、表電極膜中間層12b及び表電極膜上層12cの三層構造から表電極膜12が構成され、この表電極膜12は、抵抗体膜13及び保護膜14よりも膜厚が10〜25μm程度薄く形成されるものであるが、ここに膜厚が15〜30μmである電気めっき層17を形成することにより、この電気めっき層17を保護膜14よりも高く形成することができる。また一次方向の分割溝11aには比較的薄く形成された表電極膜上層12cのみが重畳されるため、表電極膜12が銅を主成分とする材料から形成されるものであるにも拘わらず、絶縁基板11は一次方向に分割し易いものとなる。
表電極膜上層12cを形成した後、抵抗値を計測しながら、抵抗体膜13の表面をトリミングして溝13aを形成し、抵抗体膜13を所望の抵抗値に調整する。
After the resistor film 13 is formed, as shown in FIG. 3A, a surface electrode film upper layer 12c is formed on the surface electrode film intermediate layer 12b. The surface electrode film upper layer 12c uses the same paste material as the surface electrode film lower layer 12a, is separated from the primary direction division grooves 11a and the secondary direction division grooves 11b by the screen printing method, and also from the resistor film 13 Printing is performed in a distant arrangement, and firing is performed at a peak temperature of about 900 ° C. in a nitrogen atmosphere to form a film thickness of about 10 to 15 μm.
Here, the reason why the surface electrode film upper layer 12c is separated from the resistor film 13 is to prevent the surface of the surface electrode film upper layer 12c from having a height difference due to the overlap, and the chip resistor 10 is suitable for face-down mounting. This is to make it a different shape.
Further, since the surface electrode film upper layer 12c is in contact with the component mounting surface when the chip resistor 10 is face-down mounted on the circuit board, the protective film 14 is formed after the electroplating layer is formed so as to adapt to this. It is formed as an auxiliary to form higher. This is because the lateral dimension of the chip resistor 10 may exceed a prescribed value if it is formed higher than the protective film 14 only by the electroplating layer.
As described above, the surface electrode film 12 is composed of the three-layer structure of the surface electrode film lower layer 12a, the surface electrode film intermediate layer 12b, and the surface electrode film upper layer 12c. The surface electrode film 12 includes the resistor film 13 and the protective film 14. The thickness of the electroplating layer 17 is lower than that of the protective film 14 by forming the electroplating layer 17 having a thickness of 15 to 30 μm. Can be formed. Moreover, since only the relatively thinly formed surface electrode film upper layer 12c is superimposed on the dividing groove 11a in the primary direction, the surface electrode film 12 is formed from a material mainly composed of copper. The insulating substrate 11 can be easily divided in the primary direction.
After the surface electrode film upper layer 12c is formed, the surface of the resistor film 13 is trimmed to form the groove 13a while measuring the resistance value, and the resistor film 13 is adjusted to a desired resistance value.

次に、図3(b)に示したように、保護膜14及び裏電極膜15を形成する。
保護膜14は、エポキシ樹脂を主成分とするペースト材料を使用し、スクリーン印刷法により、トリミング溝13aの形成された抵抗体膜13を覆い、両端の表電極膜上層12cの間を埋めるような配置で印刷し、ほぼ200℃程度で焼付ける。保護膜14は、トリミング溝13aを覆うために十分な膜厚が必要であり、2層印刷を行う。これにより保護膜14のほうが表電極上層12cよりも10〜25μm程度高く形成される。
また裏電極膜15は、銀を主成分とする導電性樹脂ペースト材料を使用し、スクリーン印刷法により、一次方向及び二次方向の分割溝11a,11bを跨ぐような配置で印刷し、ほぼ200℃程度で焼付けをする。銅系厚膜に比べ、分割時のバリが少なく、割れ性が良好であるという理由から、裏電極膜15は、一次方向及び二次方向の分割溝11a,11bを跨ぐような配置で形成される。
Next, as shown in FIG. 3B, the protective film 14 and the back electrode film 15 are formed.
The protective film 14 uses a paste material mainly composed of an epoxy resin, covers the resistor film 13 with the trimming grooves 13a formed by screen printing, and fills the gaps between the upper surface electrode film layers 12c at both ends. Print in place and bake at around 200 ° C. The protective film 14 needs to have a sufficient film thickness to cover the trimming groove 13a, and two-layer printing is performed. Thereby, the protective film 14 is formed higher by about 10 to 25 μm than the upper surface electrode layer 12c.
The back electrode film 15 is printed using a conductive resin paste material containing silver as a main component and arranged in such a manner as to straddle the dividing grooves 11a and 11b in the primary direction and the secondary direction by screen printing. Bake at around ℃. The back electrode film 15 is formed so as to straddle the dividing grooves 11a and 11b in the primary direction and the secondary direction because there are few burrs at the time of division and good cracking property compared to the copper-based thick film. The

保護膜14及び裏電極膜15を形成した後、絶縁基板11を一次方向の分割溝11aに沿って分割することにより、短冊状の中間加工品を形成する。このとき、一次方向の分割溝11aには比較的薄く形成された表電極膜下層12aのみが重畳されているため、この表電極膜下層12aが銅を主成分とする材料から形成されたものであるにも拘わらず、絶縁基板11の一次方向の分割は容易に行うことができて、しかも、バリの発生が抑制される。
短冊状中間加工品の短辺方向の断面が図4(a)であり、これに示したように、表電極膜下層12aが一次方向の分割溝11aであった面にまで回り込んで付着している。
After forming the protective film 14 and the back electrode film 15, the insulating substrate 11 is divided along the dividing grooves 11 a in the primary direction, thereby forming a strip-shaped intermediate processed product. At this time, only the relatively thinly formed surface electrode film lower layer 12a is superposed on the dividing groove 11a in the primary direction, and therefore the surface electrode film lower layer 12a is formed of a material mainly composed of copper. Nevertheless, the primary substrate can be easily divided in the primary direction, and the generation of burrs is suppressed.
The cross section in the short side direction of the strip-shaped intermediate processed product is shown in FIG. 4A. As shown in this figure, the surface electrode film lower layer 12a wraps around and adheres to the surface that was the dividing groove 11a in the primary direction. ing.

次に、短冊状中間加工品の長手方向の両端面に、スパッタ法により、クロム膜とニッケル膜との二層構造からなる端面電極16を形成する。この端面電極16の形成後の断面が図4(b)である。   Next, end face electrodes 16 having a two-layer structure of a chromium film and a nickel film are formed by sputtering on both end faces in the longitudinal direction of the strip-shaped intermediate processed product. FIG. 4B shows a cross section after the end face electrode 16 is formed.

端面電極16を形成した後、二次方向の分割溝11bに沿って分割することによりチップ状中間加工品に形成し、さらに、このチップ状中間加工品にCu、Ni及びSnの三層構造からなる電気めっき層17を形成すればチップ抵抗器10が完成する。Cu、Ni、Snの電気めっき層17は、保護膜14よりも5〜20μm程度高くなるように形成され、チップ抵抗器10を回路基板にフェースダウン実装したときに、保護膜14と回路基板面との間に隙間ができるようにされる。   After the end face electrode 16 is formed, the chip-shaped intermediate processed product is formed by dividing along the secondary-direction dividing groove 11b. Further, the chip-shaped intermediate processed product is formed from a three-layer structure of Cu, Ni, and Sn. When the electroplating layer 17 is formed, the chip resistor 10 is completed. The electroplating layer 17 of Cu, Ni, Sn is formed so as to be about 5 to 20 μm higher than the protective film 14, and when the chip resistor 10 is mounted face-down on the circuit board, the protective film 14 and the circuit board surface A gap is made between them.

本発明により製造されるチップ抵抗器の断面図である。It is sectional drawing of the chip resistor manufactured by this invention. (a)〜(c)は本発明のチップ抵抗器の製造方法を構成する各工程を示す平面図であり、(d)〜(f)は、これら各工程における断面図である。(A)-(c) is a top view which shows each process which comprises the manufacturing method of the chip resistor of this invention, (d)-(f) is sectional drawing in these each process. (a)(b)は、図2に引き続いて行われる各工程を示す断面図である。(A) and (b) are sectional drawings which show each process performed following FIG. (a)〜(c)は、図3に引き続いて行われる各工程を示す断面図である。(A)-(c) is sectional drawing which shows each process performed following FIG.

符号の説明Explanation of symbols

10 チップ抵抗器
11 絶縁基板
12 表電極膜
12a 表電極膜下層
12b 表電極膜中間層
12c 表電極膜上層
13 抵抗体膜
13a トリミング溝
14 保護層
15 裏電極膜
16 端面電極膜
17 電極めっき膜
DESCRIPTION OF SYMBOLS 10 Chip resistor 11 Insulating substrate 12 Front electrode film 12a Front electrode film lower layer 12b Front electrode film intermediate layer 12c Front electrode film upper layer 13 Resistor film 13a Trimming groove 14 Protective layer 15 Back electrode film 16 End face electrode film 17 Electrode plating film

Claims (2)

矩形に区画するように一次方向及び二次方向の分割溝が表裏面に刻設された絶縁基板の表面に、前記一次方向の分割溝を跨ぎ、且つ前記二次方向の分割溝から離間するように表電極膜下層を形成する表電極膜下層形成工程と、
当該表電極膜下層上において前記絶縁基板の一次及び二次方向の分割溝から離間し、且つ前記表電極膜下層よりも厚く表電極膜中間層を形成する表電極膜中間層形成工程と、
当該表電極膜中間層どうしを接続し、これらの一部を覆う抵抗体膜を形成する抵抗体膜形成工程と、
前記表電極膜中間層上において前記絶縁基板の一次及び二次方向の分割溝から離間し、前記抵抗体膜に接触せず、且つ前記抵抗体膜よりも高くなるように表電極膜上層を形成する表電極膜上層形成工程と、
前記抵抗体膜の抵抗値調整のためのトリミング溝を刻設するトリミング溝刻設工程と、
前記抵抗体膜を覆うように保護膜を形成する保護膜形成工程と、
前記絶縁基板を一次方向の分割溝に沿って短冊状に分割する一次分割工程と、
前記絶縁基板の左右端面を覆い裏電極膜及び表電極膜下層のそれぞれ一部に重畳するように、スパッタ法により端面電極膜を形成する端面電極膜形成工程と、
前記絶縁基板を二次方向の分割溝に沿ってチップ状に分割する二次分割工程と、
前記裏電極膜、表電極膜下層、表電極膜中間層、表電極膜上層及び端面電極膜を覆うように電極めっき膜を形成する電極めっき膜形成工程とを備え、
前記表電極膜下層、表電極膜中間層、表電極膜上層及び前記抵抗体膜は、少なくともCu及びSiO2を含むガラス粉からなるペースト材料の焼成により形成することを特徴とする低抵抗チップ抵抗器の製造方法。
The dividing grooves in the primary direction and the secondary direction so as to be divided into rectangles are straddled on the surface of the insulating substrate in which the front and back surfaces are engraved, and are separated from the dividing grooves in the secondary direction. A surface electrode film lower layer forming step of forming a surface electrode film lower layer on the surface;
A surface electrode film intermediate layer forming step of forming a surface electrode film intermediate layer that is spaced apart from the primary and secondary dividing grooves on the surface electrode film lower layer and thicker than the surface electrode film lower layer;
A resistor film forming step of connecting the surface electrode film intermediate layers and forming a resistor film covering a part of these,
On the surface electrode film intermediate layer, the surface electrode film upper layer is formed so as to be separated from the primary and secondary dividing grooves of the insulating substrate, not to contact the resistor film, and to be higher than the resistor film. A surface electrode film upper layer forming step,
A trimming groove engraving step for engraving a trimming groove for adjusting the resistance value of the resistor film;
A protective film forming step of forming a protective film so as to cover the resistor film;
A primary dividing step of dividing the insulating substrate into strips along a dividing groove in a primary direction;
An end face electrode film forming step of forming an end face electrode film by a sputtering method so as to cover the left and right end faces of the insulating substrate and to overlap each of the back electrode film and the front electrode film lower layer;
A secondary division step of dividing the insulating substrate into chips along the division grooves in the secondary direction;
An electrode plating film forming step of forming an electrode plating film so as to cover the back electrode film, the surface electrode film lower layer, the surface electrode film intermediate layer, the surface electrode film upper layer and the end face electrode film,
The low resistance chip resistor, wherein the surface electrode film lower layer, the surface electrode film intermediate layer, the surface electrode film upper layer, and the resistor film are formed by firing a paste material made of glass powder containing at least Cu and SiO 2. Manufacturing method.
前記表電極膜下層は5〜10μmの膜厚に形成し、前記表電極膜中間層は15〜20μmの膜厚に形成することを特徴とする前記請求項1に記載の低抵抗チップ抵抗器の製造方法。   2. The low resistance chip resistor according to claim 1, wherein the lower layer of the surface electrode film is formed to a thickness of 5 to 10 μm, and the intermediate layer of the surface electrode film is formed to a thickness of 15 to 20 μm. Production method.
JP2007258289A 2007-10-02 2007-10-02 Method of manufacturing low-resistance chip resistor Pending JP2009088368A (en)

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