JP2009080866A - Readout voltage generation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that power consumption cannot be reduced for securing reliability of a nonvolatile memory device by controlling a readout margin. <P>SOLUTION: In the readout voltage generation device, a readout voltage is set so that a readout load element is at a prescribed load value corresponding to the content of data to be substantially simultaneously stored when the data are stored in the nonvolatile memory device. According to such constitution, there is no need for starting a circuit for increasing the readout margin during a data holding period of the stored data so that the power consumption can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a read voltage generator for generating a read voltage for reading data stored in a nonvolatile memory device.

The nonvolatile memory device stores data by accumulating electric charges in a charge accumulation film. EEPROM (Electronically Erasable and Programmable Read Only Memory: electrically rewritable non-volatile memory) is roughly divided into two structures with different types of charge storage films.
One is an FG (Floating Gate) in which a conductor called a floating gate serving as a charge storage film is surrounded by an oxide film and electrically insulated on a gate insulating film, and charges are stored in the floating gate. Floating gate) type. The other is a MNOS (Metal-Nitride-Oxide) which has a charge storage film in which a plurality of insulating films are stacked, and stores information by controlling the amount of charge stored in a charge trap in the charge storage film. -Silicon) type and MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type.

The threshold voltage in the state where electrons are stored in the charge storage film, that is, in the state where write data is stored, is Vtw, and the threshold voltage in the state where holes are stored in the charge storage film, that is, where erase data is stored The voltage is Vte, and the threshold voltage in a state where neither electrons nor holes are accumulated in the charge storage film, that is, the thermal equilibrium state threshold voltage is called V0.
Here, when the value of the voltage Vcg applied to the gate electrode of the memory element when reading the data stored in the memory element is set so that the relationship of Vte <Vcg <Vtw is established, the drain current of the memory element is Since it does not flow in a state where data is stored but flows in a state where erase data is stored, it is possible to discriminate between write data and erase data.

  However, the values of Vtw and Vte are not always constant. The memory element gradually approaches a thermal equilibrium state that is a stable state of energy with the passage of time. That is, since the charge accumulated in the charge storage film is released over time, the values of Vtw and Vte approach V0, and finally Vtw = Vte = V0.

  If the relationship of Vte <Vcg <Vtw does not hold in the process in which the values of Vtw and Vte approach V0, data cannot be read correctly.

Among the above, the difference between the values of Vtw and Vcg or the difference between the values of Vte and Vcg is called a read margin.
Several proposals are being seen as a method of coping with the case where the read margin is reduced with the passage of time (see, for example, Patent Document 1).

  Next, it demonstrates using drawing. FIG. 4 is a block diagram illustrating a configuration of a microcomputer including the semiconductor memory device described in the prior art disclosed in Patent Document 1, and is a diagram rewritten without departing from the gist thereof for easy explanation. .

  In FIG. 4, 1000 is a microcomputer, 200 is a semiconductor memory device, 300 is a processor, 210 is a non-volatile memory, 220 is a first sense amplifier, 230 is detection means, 340 is control means, and 350 is storage means.

  The detection unit 230 includes a second sense amplifier 231, a third sense amplifier 232, and a detection circuit 233. The control unit 340 includes a verify unit 341.

The operation at the time of data reading in the prior art disclosed in Patent Document 1 will be described.
A read signal output from the nonvolatile memory 210 is supplied to the first sense amplifier 220. The first sense amplifier 220 compares the level of the read signal with the first reference level and outputs a first logic value corresponding to the level of the read signal.
The first logical value is output from the semiconductor memory device 200 as stored data.

Next, a description will be given of a coping operation in the case where the read margin is reduced with the passage of time.
The enable signal output from the storage unit 350 is supplied to the detection unit 230, and the second sense amplifier 231, the third sense amplifier 232, and the detection circuit 233 constituting the detection unit 230 are activated.

  A read signal output from the nonvolatile memory 210 is supplied to the first sense amplifier 220, the second sense amplifier 231, and the third sense amplifier 232.

The first sense amplifier 220 compares the level of the read signal with the first reference level and outputs a first logic value corresponding to the level of the read signal.
The second sense amplifier 231 compares the level of the read signal with a second reference level that is higher than the first reference level, and outputs a second logical value corresponding to the level of the read signal.
The third sense amplifier 232 compares the level of the read signal with a third reference level that is smaller than the first reference level, and outputs a third logical value corresponding to the level of the read signal.
The first to third logic values are supplied to the detection circuit 233.

The detection circuit 233 outputs a detection signal when all of the first to third logic values do not match.
If all of the first to third logic values match, it can be determined that there is still a sufficient read margin to correctly read the stored data, and the coping operation ends here.

The detection signal and the first logical value output from the detection circuit 233 are supplied to the control unit 340.
The control unit 340 supplies the nonvolatile memory 210 with an access control signal for executing rewriting with the same content as the read signal in the storage area of the nonvolatile memory 210 corresponding to the detection signal.

In the verifying means 341 provided in the control means 340, it is verified whether or not rewriting has been executed normally.
If rewriting is performed normally, the first logical value to the third logical value all match, and therefore the detection signal from the detection circuit 233 is not supplied.

  When the verifying unit 341 verifies that the rewrite has not been executed normally, the control unit 340 generates an access control signal for prohibiting access to the storage area of the nonvolatile memory 210 corresponding to the detection signal. Supply to the memory 210.

The prior art disclosed in Patent Document 1 can detect that the read margin has become smaller than a predetermined value by providing the detection unit 230, and the processor 300 can detect the read margin from the predetermined value. The reliability of the semiconductor memory device 200 is improved by taking measures against rewriting data or prohibiting access to the storage area of the nonvolatile memory 210 that has become smaller.

Japanese Patent Laying-Open No. 2005-141827 (page 6-8, FIG. 1)

  In the prior art disclosed in Patent Document 1, in order to reliably detect that the read margin has become small, the detection means 230 is not limited to the time of reading stored data, but always in the retention period of stored data. It is necessary to keep it activated, and there is a problem that power is constantly consumed.

  Furthermore, in order to rewrite data to the storage area of the non-volatile memory 210 with a small read margin, it is necessary to generate a high voltage as a write voltage, which also consumes a large amount of power. There's a problem.

  In addition, when access to the storage area of the nonvolatile memory 210 is prohibited, it is necessary to provide a spare storage area for storing data in place of the storage area where access is prohibited, resulting in poor space efficiency. There's a problem.

  The present invention has been made to solve such a problem, and improves the reliability of the nonvolatile memory device without starting up the circuits in and around the nonvolatile memory device during the retention period of the stored data. The purpose is to do.

  In order to solve the above problems, the present invention adopts the following configuration.

A read voltage generator for generating a read voltage for reading data stored in a nonvolatile memory device,
The non-volatile memory device has a non-volatile memory element and a read load element. When data is written to the non-volatile memory element, the read load element has a predetermined load value corresponding to the content of the data substantially simultaneously. When the read voltage is set and the data stored in the nonvolatile memory device is read, the read voltage is applied to the read load element.

  A voltage generation unit that generates a predetermined voltage; and a conversion unit that converts the predetermined voltage into a read voltage. The conversion unit includes a nonvolatile storage unit and a voltage adjustment resistor. Has a first sense level shift nonvolatile memory element and a second sense level shift nonvolatile memory element, and the first sense level shift nonvolatile memory element and the voltage adjustment resistor are connected in series. The second sense level shift nonvolatile memory element is connected in parallel with the first sense level shift nonvolatile memory element. When data is written to the nonvolatile memory element, the same data as the first sense level shift nonvolatile memory is written at substantially the same time. The predetermined voltage is converted into the read voltage by storing data in the second memory element and data opposite to the data in the second nonvolatile memory element for sense level shift. And outputting Te.

  The nonvolatile memory element and the nonvolatile storage means have the same structure.

  The non-volatile memory means has a laminated film formed by laminating a plurality of insulating films.

  The read voltage generating device according to the present invention stores the data to set the read voltage so that the load value of the read load element becomes a value for increasing the read margin substantially simultaneously when data is written to the nonvolatile memory element. In the data holding period, it is not necessary to activate the circuit in order to increase the read margin, and the power consumption can be reduced.

  Furthermore, since the reliability of the nonvolatile memory device is improved by increasing the read margin, it is not necessary to rewrite data, and not only does not consume power by applying a high voltage as a write voltage, but also high There is an effect that a device for generating a voltage is not necessary.

  In addition, since the reliability of the nonvolatile memory device is improved by increasing the read margin, it is not necessary to deal with the prohibition of access to a part of the storage area of the nonvolatile memory element, and the access is prohibited. Since there is no need to provide a spare storage area for storing data in place of the storage area, there is an effect that the space can be used effectively.

  In addition, there is an effect that the detection means for constantly monitoring the size of the read margin, the processor for controlling the handling of the non-volatile memory element having a small read margin, and these complicated circuits are not required.

[Overall description of read voltage generator: FIG. 1]
FIG. 1 is a block diagram for explaining a read voltage generator according to the present invention.
In FIG. 1, 10 is a nonvolatile memory means, 11 is a first sense level shift nonvolatile memory element, 12 is a second sense level shift nonvolatile memory element, 20 is a voltage adjusting resistor, and 21 is a constant resistance. , 30 is a conversion unit, 40 is a voltage generation unit, and 100 is a read voltage generation device having them. Reference numeral 50 denotes a nonvolatile memory device, 51 denotes a nonvolatile memory element, 52 denotes a read load element, and 53 denotes a comparator.
A predetermined voltage output from the voltage generation unit 40 and input to the conversion unit 30 is Va, and a read voltage output from the conversion unit 30 and input to the nonvolatile memory device 50 is V10. The predetermined voltage Va is a voltage that is used to adjust the voltage in the conversion unit 30 and generate the read voltage V10.

  The conversion unit 30 includes a nonvolatile storage unit 10, a voltage adjustment resistor 20, and a constant resistor 21. The nonvolatile memory means 10 includes a first sense level shift nonvolatile memory element 11 and a second sense level shift nonvolatile memory element 12.

The first sense level shift nonvolatile memory element 11 and the voltage adjusting resistor 20 are connected in series, and the second sense level shift nonvolatile memory element 12 is connected in parallel thereto.
The constant resistor 21 is provided between the read voltage V10 and the ground potential.

  The non-volatile memory device 50 is connected to a read load element 52 and a non-volatile memory element 51 that receive a read voltage V10 and whose load value is determined according to the read voltage V10. ing. The output of the comparator 53 becomes output data X corresponding to the data stored in the nonvolatile memory element 51.

Here, one bit of the first sense level shift nonvolatile memory element 11 and one bit of the second sense level shift nonvolatile memory element 12 correspond to one bit of the nonvolatile memory element 51. ing. That is, although not shown, when M is a natural number and the nonvolatile memory element 51 is M bits, the first sense level shift nonvolatile memory element 11 and the second sense level shift nonvolatile memory element 12 Are M bits.

[Description of Operation: FIG. 1]
Next, the operation of the read voltage generator of the present invention will be described with reference to FIG.
When the write data is stored in the nonvolatile memory element 51, the same data as the write data to the first sense level shift nonvolatile memory element 11, that is, the write data is supplied to the second sense level shift nonvolatile memory substantially simultaneously. Data opposite to the write data, that is, erase data is stored in the element 12. By storing data in this way, the value of the read voltage V10 is set to V11 (not shown).

When reading the write data stored in the nonvolatile memory element 51, a predetermined voltage Va is input to the conversion unit 30. In the first sense level shift nonvolatile memory element 11, current does not flow because write data is stored, and in the second sense level shift nonvolatile memory element 12, erase data is stored. Flows. Therefore, since the predetermined voltage Va input to the conversion unit 30 is output from the conversion unit 30 without changing the value, the value of the read voltage V10 is
V11 = Va
It becomes.

  By applying V11 to the read load element 52, the load value of the read load element 52 is determined. The data stored in the nonvolatile memory element 51 is determined using the determined load value, and the result is output to the outside of the nonvolatile memory device 50 via the comparator 53.

  When erasing data is stored in the non-volatile memory element 51, the same data as the erasing data, that is, the erasing data is transferred to the first sense level shifting non-volatile memory element 11 almost simultaneously. Data opposite to the erase data, that is, write data is stored in the element 12. By storing data in this way, the value of the read voltage V10 is set to V12 (not shown).

When the erase data stored in the nonvolatile memory element 51 is read, a predetermined voltage Va is input to the conversion unit 30. The first sense level shift nonvolatile memory element 11 stores current because erase data is stored, and the second sense level shift nonvolatile memory element 12 stores current because write data is stored. Not flowing. Therefore, the predetermined voltage Va input to the conversion unit 30 varies in value due to a voltage drop when a current flows through the voltage adjusting resistor 20 and is output from the conversion unit 30.
When the value of the voltage adjusting resistor 20 is R10 and the value of the constant resistor 21 is Ra, the value of the read voltage V10 is
V12 = (Ra / (Ra + R10)) Va
It becomes.

  By applying V12 to the read load element 52, the load value of the read load element 52 is determined. The data stored in the nonvolatile memory element 51 is determined using the determined load value, and the result is output to the outside of the nonvolatile memory device 50 via the comparator 53.

[Explanation of Sense Level Shift and Read Margin: FIGS. 2 and 3]
Next, changes in the sense level and the read margin caused by setting the read voltage V10 to V11 or V12 will be described.

  FIG. 2 is an explanatory diagram showing the relationship between the read voltage V10 applied to the read load element 52 in FIG. 1 and the sense level of the nonvolatile memory device 50. The horizontal axis represents the read voltage value, and the vertical axis represents the sense level value.

As shown in FIG. 2, there is a feature that the sense level decreases as the read voltage increases.
Here, the sense level when the read voltage is V11 is S1, and the sense level when the read voltage is V12 is S2.

  FIG. 3 is an explanatory diagram showing the relationship between the change of the threshold voltage value of the nonvolatile memory element 51 in FIG. 1 over time and the sense level. The horizontal axis represents the passage of time since the data was stored, and the vertical axis represents the threshold voltage value.

  Here, the threshold voltage when writing data is stored is Vtw, the threshold voltage when erasing data is stored is Vte, and neither writing data nor erasing data is stored, that is, thermal equilibrium. The threshold voltage of the state is V0. The difference between the threshold voltage and the sense level is the read margin.

When reading the write data, as already described with reference to FIGS. 1 and 2, the read voltage is V11 and the sense level is S1.
As shown in FIG. 3, when the sense level becomes S1, the read margin with respect to the threshold voltage Vtw in the state where the write data is stored becomes large, and the stored data is correctly read even after a lapse of time. be able to.

When reading the erased data, as already described with reference to FIGS. 1 and 2, the read voltage is V12 and the sense level is S2.
As shown in FIG. 3, when the sense level becomes S2, the read margin with respect to the threshold voltage Vte in the state where the erased data is stored becomes large, and the stored data is correctly read out even after a lapse of time. be able to.

The threshold voltage Vtw in the state in which the write data is stored and the threshold voltage Vte in the state in which the erase data are stored approach the threshold voltage V0 in the thermal equilibrium state with the passage of time. For,
S1 <V0 <S2
With this setting, both the write data and the erase data can be read correctly even after a lapse of time.

As already described with reference to FIGS. 1 and 2, the values of the sense levels S1 and S2 are determined by the values of the read voltages V11 and V12, and the values of the read voltages V11 and V12 are determined. The predetermined voltage Va generated by the voltage generator 40, the value R10 of the voltage adjusting resistor 20, and the value Ra of the constant resistor 21 are present.
In other words, in view of the characteristics of the nonvolatile memory element 51, by making the values of Va, R10, and Ra suitable, it is possible to read data stored in the nonvolatile memory device correctly even if time passes. The read voltage generator of the present invention that outputs a voltage is realized.

[Description of structure of memory element]
The already described nonvolatile memory element 51 and the nonvolatile memory means 10 can be memory elements having the same structure. That is, the first sense level shift nonvolatile memory element 11 and the second sense level shift nonvolatile memory element 12 constituting the nonvolatile memory element 51 and the nonvolatile memory means 10 are memory elements having the same structure. be able to.
Although these memory elements are not particularly limited, a memory element having a stacked film formed by stacking a plurality of insulating films, for example, a MONOS type or MNOS type memory element can be used.

Since the non-volatile memory element 51 and the non-volatile memory means 10 are memory elements having the same structure, the manufacturing process can be made the same, which has the advantage of reducing the manufacturing cost and the manufacturing process time. is there.
In addition, since the memory elements having the same structure can have the same writing voltage and erasing voltage, the means for generating these voltages can be made the same, which also reduces the cost. Contributes to shortening of time.

Furthermore, by using a memory element of MONOS type or MNOS type, the threshold voltage Vtw in the state in which write data is stored in FIG. 3 and the threshold voltage Vte in the state in which erase data is stored are Can be expressed by the following mathematical formula.
Vtw = A · log (T) + B
Vte = C · log (T) + D
Here, A is the slope of Vtw in FIG. 3, B is the value of Vtw immediately after storing the write data, C is the slope of Vte in FIG. 3, D is the value of Vte immediately after storing the erased data, and T is the figure. 3 is the value on the horizontal axis, that is, the time elapsed since the data was stored.

In a MONOS type or MNOS type memory element, A and C are constant values that do not depend on the passage of time.
Therefore, even if it does not wait for a long time until Vtw = Vte to obtain the value of the threshold voltage V0 in the thermal equilibrium state, the change in the value of Vtw and Vte is read in a short time immediately after storing the data. , A, B, C, and D, the value of the threshold voltage V0 in the thermal equilibrium state can be easily estimated.
Therefore, there is also an advantage that the sense levels S1 and S2 for increasing the read margin can be reliably set in a short time.

  The read voltage generator of the present invention can improve the reliability of the nonvolatile memory device by increasing the read margin, and it is not necessary to activate the circuit during the retention period of the stored data. Since electric power can be reduced, it is suitable for portable electronic devices and computer devices that require high reliability and low power consumption.

1 is a block diagram for explaining a read voltage generator according to the present invention. FIG. It is a figure explaining the relationship between the read voltage applied to a read load element, and the sense level of a non-volatile memory device. It is a figure explaining the relationship between the threshold voltage of a non-volatile memory element, and a sense level. It is a block diagram explaining the prior art shown in patent document 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Nonvolatile memory | storage means 11 1st non-volatile memory element for 1st sense level shifts 12 2nd non-volatile memory element for 2nd sense level shifts 20 Resistance for voltage adjustment 21 Constant resistance 30 Conversion part 40 Voltage generation part 50 Nonvolatile memory apparatus 51 Nonvolatile memory element 52 Read load element 53 Comparator 100 Read voltage generator Ra Constant resistance value R10 Voltage adjustment resistor value S1, S2 Sense level value V10 Read voltage V11, V12 Read voltage value Va Predetermined voltage Vtw Write Threshold voltage Vte when data is stored Vte Threshold voltage V0 when erase data is stored V0 Thermal equilibrium threshold voltage X Output data

Claims (4)

A read voltage generator for generating a read voltage for reading data stored in a nonvolatile memory device,
The nonvolatile memory device includes a nonvolatile memory element and a read load element,
When writing data to the non-volatile memory element, the read voltage is set so that the read load element has a predetermined load value corresponding to the content of the data substantially simultaneously,
A read voltage generation device, wherein when the data stored in the nonvolatile memory device is read, the read voltage is applied to the read load element. A voltage generator that generates a predetermined voltage; and a converter that converts the predetermined voltage into the read voltage;
The conversion unit has a nonvolatile storage means and a voltage adjustment resistor,
The nonvolatile memory means includes a first sense level shift nonvolatile memory element and a second sense level shift nonvolatile memory element,
The first sense level shift nonvolatile memory element and the voltage adjusting resistor are connected in series, and the second sense level shift nonvolatile memory element is connected in parallel with the first sense level shift nonvolatile memory element,
When writing data to the non-volatile memory element, the same data as the data is stored in the first sense level shifting non-volatile memory element substantially simultaneously, and data opposite to the data is stored in the second sense level. The read voltage generator according to claim 1, wherein the predetermined voltage is converted into the read voltage and output by being stored in a shift nonvolatile memory element.   3. The read voltage generator according to claim 2, wherein the nonvolatile memory element and the nonvolatile memory means have the same structure.   4. The read voltage generator according to claim 2, wherein the nonvolatile memory means has a laminated film formed by laminating a plurality of insulating films.

Images