JP2009070967A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with a plurality of chips laminated and capable of supplying a uniform power supply. <P>SOLUTION: A first semiconductor integrated circuit chip and a second semiconductor integrated circuit chip are laminated and mutually connected by an inter-chip connection electrode. A core power supply voltage is supplied to a core circuit formed in the first semiconductor integrated circuit chip through the core power terminal of the second semiconductor integrated circuit chip and the inter-chip connection electrode. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which a first semiconductor integrated circuit chip and a second semiconductor integrated circuit chip are stacked on each other and are electrically connected via inter-chip connection electrodes.

  A semiconductor integrated circuit device includes a semiconductor integrated circuit chip and a semiconductor package for storing the semiconductor integrated circuit chip.

  On the semiconductor integrated circuit chip, there are a core region formed by a logic circuit, an input / output buffer, and an input / output pad region formed by input / output and power supply pad electrodes. In general, the input / output pad region is arranged on the outer periphery of the semiconductor integrated circuit chip from the viewpoint of easy connection by bonding with a lead frame or a circuit board (interposer substrate) provided in the semiconductor package.

  In addition, since the operating power supply voltage is different between the logic circuit and the input / output buffer circuit, there is a problem that if both are formed on the same semiconductor integrated circuit chip, the cost increases.

Therefore, one semiconductor integrated circuit chip includes a logic circuit that operates at a low power supply voltage, and the other semiconductor integrated circuit chip includes an input / output circuit that operates at a high power supply voltage, an electrostatic protection circuit, and a pad electrode. A semiconductor integrated circuit in which a semiconductor integrated circuit chip is bonded is proposed (for example, see Patent Document 1).
JP 2005-129881 A

  In recent years, the size of semiconductor integrated circuit chips tends to increase as the degree of integration and multifunction of semiconductor integrated circuits increase. When the size of the semiconductor integrated circuit chip is increased, the power supply voltage is supplied from the power supply pad disposed on the outer periphery of the semiconductor integrated circuit chip to the core circuit disposed in the center of the semiconductor integrated circuit chip. The problem is that the voltage drops.

  Patent Document 1 mentioned above does not mention measures against this problem.

  In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit capable of uniformly supplying power to a semiconductor integrated circuit chip.

The semiconductor integrated circuit of the present invention that achieves the above object is a semiconductor integrated circuit in which a first semiconductor integrated circuit chip and a second semiconductor integrated circuit chip are laminated together and electrically connected via an inter-chip connection electrode. In
In the first semiconductor integrated circuit chip, a core circuit having a plurality of input terminals and a plurality of output terminals and operating upon supply of a core power supply voltage is formed,
The second semiconductor integrated circuit chip operates by receiving a buffer power supply voltage higher than the core power supply voltage, and a signal input from the outside of the semiconductor integrated circuit is applied to a corresponding input terminal of the core circuit. An input buffer to be supplied; an output buffer that operates in response to supply of the buffer power supply voltage; and outputs a signal output from a corresponding output terminal of the core circuit to the outside of the semiconductor integrated circuit; and A core power supply terminal for receiving the supply of the core power supply voltage from the outside is formed;
The core power supply voltage is supplied to the core circuit through the core power supply terminal and the inter-chip connection electrode.

  In the semiconductor integrated circuit of the present invention, the core power supply voltage supplied from the outside is applied to the first semiconductor integrated circuit chip via the core power supply terminal formed on the second semiconductor integrated circuit chip and the inter-chip connection electrode. It is the structure which supplies to the formed core circuit. Therefore, the core power supply voltage to the core circuit is compared with the conventional technique of supplying power from the power supply pad arranged on the outer periphery of the semiconductor integrated circuit chip to the core circuit arranged at the center of the semiconductor integrated circuit chip. It is possible to increase the uniformity of the supply.

  Here, the second semiconductor integrated circuit chip includes a signal input to the input terminal of the core circuit, a signal output from the output terminal, a signal output from the input buffer, or an output buffer. It is preferable that a level shifter for converting the signal level with the signal input to is formed.

  The first semiconductor integrated circuit chip is provided with mesh-shaped power supply wiring for supplying the core power supply voltage to the core circuit, and the mesh-shaped power supply wiring is provided with the first semiconductor integrated circuit chip. It is preferable that the core power supply voltage is supplied through the corresponding core power supply terminal and the inter-chip connection electrode in both the peripheral portion and the central portion.

  As described above, when the core power supply voltage is supplied via the inter-chip connection electrodes in both the peripheral portion and the central portion of the first semiconductor integrated circuit chip, the core power supply voltage can be supplied more uniformly to the core circuit.

  Further, the second semiconductor integrated circuit chip includes an input / output buffer cell including a transistor capable of forming the output buffer, a transistor capable of forming the input buffer, and a terminal region capable of forming the core power supply terminal. It is preferable that the input buffer, the output buffer, and the core power supply terminal are formed in a plurality of regularly arranged input / output buffer cells.

  This makes it easy to design the second semiconductor integrated circuit chip.

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of uniformly supplying power to a semiconductor integrated circuit chip.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view of a semiconductor integrated circuit according to an embodiment of the present invention.

  In the semiconductor integrated circuit 1, a first semiconductor integrated circuit chip 10 and a second semiconductor integrated circuit chip 20 are stacked. The stacked semiconductor integrated circuit chips are stored in a BGA package. That is, a laminated chip in which the first semiconductor integrated circuit chip 10 and the second semiconductor integrated circuit chip 20 are laminated is laminated with an interposer substrate 30 provided with solder balls 31 that serve as terminals of the package, The interposer substrate is electrically connected.

  The first semiconductor integrated circuit chip 10 has a core circuit layer 11 and a wiring layer 12 on the surface side of the semiconductor substrate 13. A large number of transistors (not shown) are formed in the core circuit layer 11. The transistors are connected to each other by a wiring formed in the wiring layer 12 to form a core circuit having various logic functions. Further, a through electrode 14 is formed in the substrate 13, and thereby an electrical connection with the second semiconductor integrated circuit chip 20 is made. That is, in the embodiment shown in FIG. 1, the through electrode 14 functions as an inter-chip connection electrode that electrically connects the first semiconductor integrated circuit chip 10 and the second semiconductor integrated circuit chip 20.

  The second semiconductor integrated circuit chip 20 has a buffer circuit layer 21 and a wiring layer 22 on the surface side of the semiconductor substrate 23. A number of transistors (not shown) are formed in the buffer circuit layer 21. The transistors are connected to each other by a wiring (not shown) formed in the wiring layer 22 to form an input / output buffer (an input buffer and an output buffer). A through electrode 24 is formed in the substrate 23. The through electrode 24 is used to connect the stacked semiconductor integrated circuit chips to the interposer substrate 30 constituting the BGA package. That is, the through electrode 24 functions as a package connection electrode that connects the stacked semiconductor integrated circuit chips to the package.

  In FIG. 2, a signal input from the outside of the semiconductor integrated circuit 1 is input to a core circuit formed in the first semiconductor integrated circuit chip 10 via an input buffer formed in the second semiconductor integrated circuit chip 20. FIG. 2 is a diagram schematically illustrating a path through which a signal output from the core circuit and a signal output from the core circuit are output to the outside of the semiconductor integrated circuit 1 through an output buffer formed in the second semiconductor integrated circuit chip 20; is there. FIG. 2 also shows a path for supplying a power supply voltage to the core circuit and input / output buffers (input buffer and output buffer).

  In the semiconductor integrated circuit 1 of the embodiment of FIG. 2, the core circuit 100 formed in the first semiconductor integrated circuit chip 10 includes AND gates 11_1, 12_2, OR gates 11_3, 11_4, and various logic gates and flip-flops not shown. The logic circuit 11_5 is a combination of the above. The core circuit 100 has a plurality of input terminals including input terminals of the AND gate 11_1 and the OR gate_11_3, and also has a plurality of output terminals including output terminals of the AND gate 11_2 and the OR gate 11_4. On the other hand, in the second semiconductor integrated circuit chip 20, an input buffer 21_1 and an output buffer 21_2 are formed.

The core circuit 100 operates upon receiving the supply of the core power supply voltage. Therefore, a signal input to or output from the core circuit has an amplitude (core signal amplitude) corresponding to the core power supply voltage (approximately equal to the core power supply voltage). The input / output buffer operates upon receiving the supply of the buffer power supply voltage. Therefore, a signal input to or output from the input / output buffer has an amplitude (buffer signal amplitude) corresponding to the buffer power supply voltage (approximately equal to the buffer power supply voltage). The core power supply voltage is lower than the buffer power supply voltage. Specifically, for example, the core power supply voltage is 1.2V and the buffer power supply voltage is 3.3V.
In addition to the input / output buffer, the second semiconductor integrated circuit chip 20 is also provided with a level shifter that converts the signal level between the signal having the core signal amplitude and the signal having the buffer signal amplitude. Specifically, a signal having a buffer signal amplitude received from the outside of the semiconductor integrated circuit 1 and passed through the input buffer 21_1 (output from the input buffer 21_1) is converted into an input signal having a core signal amplitude, and the core circuit 100, the input level shifter 21_2 supplied to the input terminal 100 and the output signal of the core signal amplitude output from the output terminal of the core circuit 100 are converted into a signal of the buffer signal amplitude and input to the output buffer 21_4. A side level shifter 21_3 is formed. Similarly to the input / output buffer, the level shifter is also formed by connecting a plurality of transistors provided in the buffer circuit layer of the second semiconductor integrated circuit chip 20 with wiring provided in the wiring layer 22. The level shifter operates by receiving both the core power supply voltage and the buffer power supply voltage.

  In such a stacked chip in which the first semiconductor integrated circuit chip 10 and the second semiconductor integrated circuit chip 20 are stacked, an input signal input to a terminal of a BGA package (not shown) is input to the interposer substrate 30 pad 30_1. And input to the input buffer 21_1 through the through electrode 24_1 provided on the substrate 23 of the second semiconductor integrated circuit chip 20 and the wiring formed in the wiring layer 22 of the second semiconductor integrated circuit chip 20. . The input signal that has passed through the input buffer 21_1 further passes through the input-side level shifter 21_2, and is transmitted to the pad 22_1 formed in the wiring layer 22 of the second semiconductor integrated circuit chip 20, so that the first semiconductor integrated circuit The AND gate 11_1, which is an input terminal of the core circuit 100, through the through electrode 14_1 provided on the substrate 13 of the circuit chip 10 and the wiring provided on the wiring layer 12 of the first semiconductor integrated circuit chip 10. It is supplied to one input terminal. Although not shown, the other input terminal of the AND gate 11_1 and the other input terminal of the core circuit 100 are also connected to the through electrode provided on the substrate 23 of the second semiconductor integrated circuit chip 20 and the input, respectively. An input signal is provided via a buffer and an input side level shifter, a pad formed on the wiring layer 22 of the second semiconductor integrated circuit chip 20, and a through electrode provided on the substrate 13 of the first semiconductor integrated circuit chip 10. Is supplied.

  The output signal output from the output terminal of the AND gate 11_2 is provided on the wiring formed in the wiring layer 12 of the first semiconductor integrated circuit chip 10 and the substrate 13 of the first semiconductor integrated circuit chip 10. The signal is transmitted to the pad 22_2 formed in the wiring layer 22 of the second semiconductor integrated circuit chip 20 through the through electrode 14_2. Then, this output signal passes through the output level shifter 21_3 and the output buffer 21_4, and is transmitted to the pad 30_2 of the interposer substrate 30 through the through electrode 24_2 provided on the substrate 23 of the second semiconductor integrated circuit chip 20. The signal is output to the outside of the semiconductor integrated circuit 1 from a terminal of a BGA package (not shown). Although illustration is omitted, output signals output from other output terminals of the core circuit 100 including the OR gate 11_4 are also connected to the through electrodes provided on the substrate 13 of the first semiconductor integrated circuit chip 10, Semiconductor integrated circuit through pads formed in the wiring layer 22 of the second semiconductor integrated circuit chip 20, output side level shifter and output buffer, and through electrodes provided in the substrate 23 of the second semiconductor integrated circuit chip 20. It is output outside the circuit 1.

  The first semiconductor integrated circuit chip 10 is supplied with a core power supply voltage necessary for the operation of the core circuit. That is, the core power supply voltage supplied to the terminal of the BGA package (not shown) is supplied to the second through the pad 30_3 of the interposer substrate 30 and the through electrode 24_3 provided on the substrate 23 of the second semiconductor integrated circuit chip 20. Is supplied to the core power supply pad 22_3 provided in the wiring layer 22 of the semiconductor integrated circuit chip 20. Further, the core circuit 100 is connected via the through electrode 14_3 provided on the substrate 13 of the first semiconductor integrated circuit chip 10 and the wiring 12_1 provided on the wiring layer 12 of the first semiconductor integrated circuit chip 10. The AND gates 11_1 and 11_3, the OR gates 11_2 and 11_4, and the logic circuit 11_5 are provided.

The core circuit 100 includes a core circuit ground power supply voltage, a through electrode provided on the substrate of the second semiconductor integrated circuit chip 20, a pad provided on the wiring layer 22, and the first semiconductor integrated circuit chip 10. It is supplied through a through electrode provided on the substrate, but the illustration is omitted.
As described above, the core power supply voltage (and the core circuit ground power supply voltage) is supplied to the core circuit 100 of the first semiconductor integrated circuit chip 10 through the through electrode 14. Accordingly, by appropriately setting the number and arrangement of the through electrodes for supplying the core power supply voltage, it is possible to supply the power supply voltage uniformly over the entire core circuit. In particular, as compared with the case where power is supplied from the pads provided in the peripheral portion of the chip to the core circuit in the central portion of the chip, the uniformity of the power supply voltage supply can be greatly improved.

  The core power supply voltage supplied to the core power supply pad 22_3 is also supplied to the level shifters 21_2 and 21_3 via the wiring 22_4 of the wiring layer 22 in the second semiconductor integrated circuit chip 20 as well. The second semiconductor integrated circuit chip 20 is also supplied with a buffer power supply voltage in addition to the core power supply voltage. That is, the buffer power supply voltage supplied to the terminal of the BGA package (not shown) includes the pad 30_4 of the interposer substrate 30, the through electrode 24_4 provided on the substrate 23 of the second semiconductor integrated circuit chip 20, and the second semiconductor integrated circuit. It is supplied to the input buffer 21_1, the output buffer 21_4, and the level shifters 21_2 and 21_3 through the wiring 22_5 provided in the wiring layer 22 of the circuit chip 20. The input buffer 21_1 and the output buffer 21_4 are similarly supplied with a buffer ground power supply voltage, but are not shown.

FIG. 3 is a diagram conceptually showing mesh power supply wirings formed in the wiring layer 12 of the first semiconductor integrated circuit chip 10 and the wiring layer 22 of the second semiconductor integrated circuit chip 20.
In the wiring layer 12 of the first semiconductor integrated circuit chip 10, mesh-shaped power supply wirings 12 a are formed over the entire surface of the first semiconductor integrated circuit chip 10. The mesh-shaped power supply wiring 12a includes a pad 30_3 (30_3a, 30_3b) of the interposer substrate 30 and a through electrode 24_3 (24_3a, 24_3b) provided in the second semiconductor integrated circuit chip 20 from a terminal of a BGA package (not shown). The core power supply voltage is supplied through the core power supply pads 22_3 (22_3a and 22_3b) and the through electrodes 14_3 (14_3a and 14_3b) provided in the first semiconductor integrated circuit chip 10. Then, the core power supply voltage is supplied to the core circuit formed in the first semiconductor integrated circuit chip 10 through the mesh power supply wiring 12a. That is, the wiring 12-1 of the wiring layer 12 of the first semiconductor integrated circuit chip 10 shown in FIG. 2 constitutes a part of the mesh-shaped power supply wiring 12a shown in FIG.

  Thus, by providing the mesh-shaped power supply wiring 12a, the uniformity of the core power supply voltage supply to the core circuit formed in the first semiconductor integrated circuit chip 10 can be improved. In the example shown in FIG. 3, the core power supply voltage is supplied to the mesh power supply wiring 12a through the core power supply pad 22_3a and the through electrode 14_3a in the central portion of the first semiconductor integrated circuit chip 10. In addition, the peripheral portion of the first semiconductor integrated circuit chip 10 is also performed via the core power supply pad 22_3b and the through electrode 14_3b. As described above, the core power supply voltage is supplied to the mesh-shaped power supply wiring 12a through the through electrode in both the central portion and the peripheral portion of the first semiconductor integrated circuit chip 10, thereby providing a core power supply for the core circuit. The uniformity of voltage supply can be further improved.

  FIG. 3 shows an example in which the core power supply voltage is supplied to the mesh power supply wiring 12a through one through electrode 14_3a and 14_3b in the central portion and the peripheral portion of the first semiconductor integrated circuit chip 10, respectively. Indicated. However, in reality, a large number of through electrodes 14 are provided on the entire surface including the central portion and the peripheral portion of the first semiconductor integrated circuit chip 10 to supply the core power supply voltage to the mesh power supply wiring 12a. Is preferred. Specifically, for example, the through electrodes 14 may be provided on the entire surface of the first semiconductor integrated circuit chip 10 at a constant density. Alternatively, in the first semiconductor integrated circuit chip 10, it is possible to provide the through electrodes 14 at a higher density than the other regions with respect to a region that consumes a large amount of power supply current. Although not shown, mesh power supply wiring for supplying a core circuit ground power supply voltage is also formed in the wiring layer 12 of the first semiconductor integrated circuit chip 10. The ground power supply voltage is also supplied to the mesh power supply wiring for the ground power supply voltage via the through electrodes 14 provided in both the central portion and the peripheral portion of the first semiconductor integrated circuit chip 10.

  In the example shown in FIG. 3, the core power supply voltage mesh-like power supply wiring 22 a for supplying the core power supply voltage is also formed in the wiring layer 22 of the second semiconductor integrated circuit chip 20. A core power supply voltage is supplied to the level shifter formed in the second semiconductor integrated circuit chip 20 through the mesh power supply wiring 22a. In the example shown in FIG. 3, the core power supply voltage is supplied to the mesh power supply wiring 22a through the through electrodes 24_3 (24_3a, 24_3b) provided on the substrate 23 of the second semiconductor integrated circuit chip 20. ing. That is, the mesh-shaped power supply wiring 22a provided on the second semiconductor integrated circuit chip 20 is also connected to the mesh portion of the second semiconductor integrated circuit chip 20 through the through electrodes 24_3a and 24_3b in both the central portion and the peripheral portion. The core power supply voltage is supplied.

  As described above, in the semiconductor integrated circuit 1 shown in FIG. 3, the core power supply voltage is first supplied from the terminal of the BGA package (not shown) through the interposer substrate 30 and the through-electrode 24_3 (24_3a, 24_3b). The power is supplied to the mesh power supply wiring 22 a of the integrated circuit chip 20, and is supplied from the mesh power supply wiring 22 a to the level shifter or other circuits formed in the second semiconductor integrated circuit chip 20. Further, the mesh-shaped power supply wiring 22a is supplied to the mesh-shaped power supply wiring 12a of the first semiconductor integrated circuit chip 10 through the through electrodes 14_3 (14_3a, 14_3b). To the core circuit formed in the semiconductor integrated circuit.

  In the example shown in FIG. 3, the first semiconductor is directly above the through electrode 24_3 (24_3a, 24_b) for supplying the core power supply voltage from the interposer substrate 30 to the mesh power supply wiring 22a of the second semiconductor integrated circuit chip 20. Through electrodes 14_3 (14_3a, 14_3b) for supplying a core power supply voltage to the mesh power supply wiring 12a of the integrated circuit 10 are arranged. However, in this way, the through electrode 14 for supplying the core power supply voltage to the first semiconductor integrated circuit chip 10 is disposed immediately above the through electrode 24 for supplying the core power supply voltage to the second semiconductor integrated circuit chip 20. Is not essential at least when the mesh-like power supply wiring 22a is formed in the second semiconductor integrated circuit chip 20. As long as the core power supply voltage can be supplied with the required uniformity to the mesh power supply wiring 12a of the second semiconductor integrated circuit chip 20 via the mesh power supply wiring 22a and the plurality of through electrodes 14, The position of the through electrode 24 that supplies the core power supply voltage to the second semiconductor integrated circuit chip 20 and the position of the through electrode 14 that supplies the core power supply voltage to the first semiconductor integrated circuit chip 10 can also be shifted from each other. It is.

  In the second semiconductor integrated circuit chip 20, when the circuit using the core power supply voltage is only the level shifter, the current supply amount of the core power supply required for the second semiconductor integrated circuit chip 20 is small. . For this reason, with respect to the second semiconductor integrated circuit chip 20, it is possible to omit the formation of the mesh-shaped power supply wiring 22a for supplying the core power supply voltage. Also in this case, disposing the through electrode 14 for supplying the core power supply voltage to the first semiconductor integrated circuit chip 10 immediately above the through electrode 24 for supplying the core power supply voltage to the second semiconductor integrated circuit chip 20 Not necessarily required. However, it is preferable to arrange them in close proximity.

  In the semiconductor integrated circuit 1 shown in FIG. 3, the second semiconductor integrated circuit chip 20 has a mesh power supply for supplying a buffer power supply voltage in addition to a mesh power supply wiring 22a for supplying a core power supply voltage. A wiring 22b is also formed. The mesh power supply wiring 22b is connected to a buffer power supply through a pad 30_4 of the interposer substrate 30 and a through electrode 24_4 provided on the substrate 23 of the second semiconductor integrated circuit chip 20 from a terminal of a BGA package (not shown). Voltage is supplied. Note that the through electrode 24_4 for supplying the buffer power supply voltage is also disposed on the entire surface of the second semiconductor integrated circuit chip 20 including both the central portion and the peripheral portion of the second semiconductor integrated circuit chip 20. preferable.

  As described above, in the embodiment of the present invention shown in FIGS. 1 to 3, the first semiconductor integrated circuit chip 10 in which the through electrode 14 is provided on the substrate 13 and the second semiconductor integrated circuit in which the through electrode 24 is provided on the substrate 23. The circuit chip 20 was stacked, and both the electrodes were electrically connected using the through electrode 14 provided on the substrate 13 of the first semiconductor integrated circuit chip 10 as an inter-chip connection electrode. That is, by connecting one end of the through electrode 14 exposed on the back surface side of the first semiconductor integrated circuit chip 10 to a pad provided on the wiring layer 22 of the second semiconductor integrated circuit chip 20, Electrical connection was made between the semiconductor integrated circuit chip and the second semiconductor integrated circuit chip. Then, the connection between the first and second semiconductor integrated circuit chips stacked and connected in this way and the package is performed by connecting one end of the through electrode 24 exposed on the back side of the second semiconductor integrated circuit chip 20, This was done by connecting to the pads of the interposer substrate 30. That is, the through electrode 24 (strictly speaking, one end of the through electrode 24 exposed on the back side of the second semiconductor integrated circuit chip 20) functions as a terminal for connecting the stacked chips to the package. For example, the through electrode 24_3 used for supplying the core power supply voltage functions as a core power supply terminal.

  However, in the semiconductor integrated circuit of the present invention, the connection between the first semiconductor integrated circuit chip 10 and the second semiconductor integrated circuit chip 20 and the connection with the package are not limited to this embodiment. Various embodiments are also possible.

  For example, the connection between the first semiconductor integrated circuit chip 10 and the second semiconductor integrated circuit chip 20 is used by using the through electrode 24 provided on the substrate 23 of the second semiconductor integrated circuit chip 20 as an inter-chip connection electrode. It is also possible to do this. That is, one end of the through electrode 24 exposed on the back surface side of the second semiconductor integrated circuit chip 20 is connected to a pad provided on the wiring layer 12 of the first semiconductor integrated circuit chip 10, thereby It is also possible to make electrical connection between the semiconductor integrated circuit chip and the second semiconductor integrated circuit chip. In this case, for example, a bump electrode is formed on a pad provided on the wiring layer 22 of the second semiconductor integrated circuit chip 20 and the package is connected to the interposer substrate via the bump electrode. This can be done by connecting to a pad. In this case, for example, a bump electrode used for supplying a core power supply voltage functions as a core power supply terminal. In this case, it is not necessary to provide a through electrode on the substrate 13 of the first semiconductor integrated circuit chip 10.

  Alternatively, the first semiconductor integrated circuit chip 10 and the second semiconductor integrated circuit chip 20 can be stacked so that the surface sides of both faces each other. In this case, bump electrodes are formed on the pads formed on the wiring layer 22 of the second semiconductor integrated circuit chip 20, and the bump electrodes are used as inter-chip connection electrodes. That is, the electrical connection is made by connecting the bump electrode to the pad provided on the wiring layer 12 of the first semiconductor integrated circuit chip 10. Conversely, a bump electrode can be formed on the pad provided on the wiring layer 12 of the first semiconductor integrated circuit chip 1 and connected to the pad provided on the wiring layer 22 of the second semiconductor integrated circuit chip 20. is there. For example, the through-electrode 24 is provided on the substrate 23 of the second semiconductor integrated circuit chip 20, and one end of the through-electrode 24 exposed on the back side of the substrate 23 is connected to the pad of the interposer substrate 30. Do by. In this case, for example, the through electrode 24 used for supplying the core power supply voltage functions as a core power supply terminal. Also in this case, it is not necessary to provide a through electrode on the substrate 13 of the first semiconductor integrated circuit chip 10.

  In any case, the second semiconductor integrated circuit chip 20 is supplied with a core power supply voltage to a core power supply terminal (through electrode or bump electrode) formed in the second semiconductor integrated circuit chip 20. The core power supply voltage supplied to the second semiconductor integrated circuit chip 20 is further provided on the inter-chip connection electrode (either the first semiconductor integrated circuit chip 10 or the second semiconductor integrated circuit chip 20). , Through electrode or bump electrode), the first semiconductor integrated circuit chip 10 is supplied. That is, the supply of the core power supply voltage to the first semiconductor integrated circuit chip 10 (or the core circuit 100 formed in the first semiconductor integrated circuit chip 10) is performed by the core formed in the second semiconductor integrated circuit chip. This is performed through the power supply terminal and the inter-chip connection electrode.

  Therefore, the core power supply voltage can be supplied uniformly throughout the entire core circuit 100 by appropriately setting the number and arrangement of the inter-chip connection electrodes.

  In the semiconductor integrated circuit of the present invention, in particular, when a level shifter for converting the signal level between the signal of the core circuit and the signal of the input / output buffer is formed on the second semiconductor integrated circuit chip, In the manufacture of the semiconductor integrated circuit chip, only the transistor operating with the core power supply voltage may be formed. Therefore, the first semiconductor integrated circuit chip can be manufactured at a low cost with a small number of steps. Further, the first semiconductor integrated circuit chip does not need to be provided with mesh power supply wiring for supplying the buffer power supply voltage and the buffer ground power supply voltage. Thereby, the chip area of the first semiconductor integrated circuit chip or the number of necessary wiring layers can be reduced, and further the manufacturing cost can be reduced.

  FIG. 4 is a diagram showing an example of a design flow of the semiconductor integrated circuit 1 of the present invention.

  First, in the first design process 61, a package pin arrangement request is obtained.

  Next, in the second design step 62, the second semiconductor integrated circuit chip (input / output chip) is taken into consideration in consideration of the above-described pin arrangement proposal, the output buffer operating simultaneously, the allowable current of the power supply wiring, and the like. Consider the arrangement (coordinates) of power supply terminals for supplying power (core power supply voltage, buffer power supply voltage, and ground power supply voltage corresponding to each).

  Further, in the third design step 63, the arrangement of user terminals (signal terminals, etc.) other than those for power supply of the input / output chip is examined in consideration of the pin arrangement request.

  In the fourth design process 64, the die size of the input / output chip and the coordinates of the terminal are determined.

  Next, in the fifth design step 65, the layout of the core circuit of the first semiconductor integrated circuit chip (core chip) and the layout of the input / output buffers of the second semiconductor integrated circuit chip 20 (input / output chip) are performed. Here, the arrangement of interchip connection electrodes between the first and second semiconductor integrated circuit chips 10 and 20 is also considered.

  FIG. 5 is a plan view conceptually showing one embodiment of the structure of the second semiconductor integrated circuit chip. In the second semiconductor integrated circuit chip shown in FIG. 5, a plurality of input / output buffer cells 25 having a fixed shape are regularly arranged. Specifically, in the example shown in FIG. 5, a plurality of buffer cells 25 are two-dimensionally arranged in a lattice pattern.

  Although not shown, each buffer cell 25 includes an input buffer region in which a transistor capable of forming an input buffer is formed in the buffer circuit layer 21 and a transistor capable of forming an output buffer. An output buffer region formed in the circuit layer 21, a transistor capable of forming an input side level shifter, an input side level shifter region formed in the buffer circuit layer 21, and a transistor capable of forming an output side level shift Are arranged in the buffer circuit layer 21, and an output side level shifter region and a terminal region are arranged. The terminal region of the input buffer region is a region for forming a package connection electrode and an inter-chip connection electrode.

  When the buffer cell 25 is used as an input cell for receiving an input signal from the outside of the semiconductor integrated circuit 1, the transistors formed in the input buffer region are connected by the wiring of the wiring layer 22, and the input buffer The transistors formed in the input side level shift region are connected by the wiring of the wiring layer 22 to form an input side level shifter. When the buffer cell 25 is used as an output cell for outputting an output signal to the outside of the semiconductor integrated circuit 1, the transistors formed in the output buffer region are connected by the wiring of the wiring layer 22 to form an output buffer. At the same time, the transistors formed in the output side level shift region are connected by the wiring of the wiring layer 22 to form an output side level shifter. In either case, a package connection electrode and an inter-chip connection electrode are formed in the terminal region. The package connection electrode is used as an input terminal for receiving an input signal or an output terminal for outputting an output signal.

  When the buffer cell 25 is used as a power supply cell for receiving supply of power supply voltage, a package connection electrode and an interchip connection electrode are formed. The package connection electrode is used as a power supply terminal for receiving supply of power supply voltage. For example, when used as a core power supply cell that receives a core power supply voltage, the package connection electrode is used as a core power supply terminal.

  In designing the semiconductor integrated circuit of the present invention, it is possible to assume a regular arrangement of the input / output buffer cells 25 as shown in FIG. That is, in the second to fourth design steps, the terminal coordinates can be determined on the assumption that the input / output buffer cells are arranged at a predetermined pitch. Thereby, the time required for the design can be shortened.

  However, it is not essential to adopt such a design method. Without assuming a predetermined arrangement of the input / output buffer cells, it is possible to execute the second to fourth design steps and determine the coordinates of the terminals.

It is sectional drawing of the semiconductor integrated circuit of one Embodiment of this invention. It is a figure which shows the signal path | route in the semiconductor integrated circuit of this invention, and a power supply path | route. It is a figure which shows notionally the mesh-shaped power supply wiring formed in the 1st and 2nd semiconductor integrated circuit chip | tip of this invention. It is a figure which shows an example of the design flow of the semiconductor integrated circuit of this invention. It is a top view which shows notionally one Embodiment of the structure of a 2nd semiconductor integrated circuit chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 10 1st semiconductor integrated circuit chip 11 Core circuit layer 12, 22 Wiring layer 13, 23 Substrate 12a, 22a, 22b Mesh-like power supply wiring 14, 24 Through-electrode 20 Second semiconductor integrated circuit chip 21 Buffer circuit Layer 30 interposer substrate

Claims (4)

In a semiconductor integrated circuit in which a first semiconductor integrated circuit chip and a second semiconductor integrated circuit chip are stacked on each other and electrically connected via an inter-chip connection electrode,
In the first semiconductor integrated circuit chip, a core circuit having a plurality of input terminals and a plurality of output terminals and operating by receiving supply of a core power supply voltage is formed,
The second semiconductor integrated circuit chip operates by receiving a buffer power supply voltage higher than the core power supply voltage, and inputs a signal input from the outside of the semiconductor integrated circuit to a corresponding input terminal of the core circuit. An input buffer to be supplied; an output buffer that operates in response to supply of the buffer power supply voltage; and outputs a signal output from a corresponding output terminal of the core circuit to the outside of the semiconductor integrated circuit; and A core power supply terminal receiving the supply of the core power supply voltage from the outside is formed;
The semiconductor integrated circuit, wherein the core power supply voltage is supplied to the core circuit through the core power supply terminal and the through electrode.   In the second semiconductor integrated circuit chip, a signal input to the input terminal of the core circuit or a signal output from the output terminal and a signal output from the input buffer or input to the output buffer 2. The semiconductor integrated circuit according to claim 1, further comprising a level shifter for converting a signal level between the first and second signals.   The first semiconductor integrated circuit chip is formed with mesh-shaped power supply wiring for supplying the core power supply voltage to the core circuit, and the mesh-shaped power supply wiring is connected to a peripheral portion of the first semiconductor integrated circuit chip. 3. The semiconductor integrated circuit according to claim 1, wherein the core power supply voltage is supplied through the corresponding core power supply terminal and the inter-chip connection electrode in both the central portion and the center portion.   The second semiconductor integrated circuit chip includes a plurality of input / output buffer cells including a transistor capable of forming the output buffer, a transistor capable of forming the input buffer, and a terminal region capable of forming the core power supply terminal. 4. The input buffer, the output buffer, and the core power supply terminal are formed in a regular arrangement, and the input buffer cell, the output buffer, and the core power supply terminal are formed in each of the plurality of input / output buffer cells. The semiconductor integrated circuit as described.

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