JP2009058690A - Storage location extracting apparatus and storage location extracting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To parallelize processes necessary for common portion extraction, and to speed up processing so as to enhance efficiency in entire processing. <P>SOLUTION: A common address extracting apparatus 10 performs a log addition processing of first round sieve processing to each byte and, for the value of each byte after the first round of log addition processing is completed, turns ON the parity bit attached to the address of the byte satisfying the condition. Then, the common address extracting apparatus 10 performs a log addition processing of second round sieve processing to each byte maintaining the state of holding the value of the parity bit. For each value held by the byte after the second round of sieve processing is completed, the common address extracting apparatus 10 turns OFF the parity bit attached to the address of the byte not satisfying the condition. After that, the common address extracting apparatus 10 extracts the address of the byte whose value of corresponding parity bit is 1 as the common portion of the memory address satisfying the condition. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a storage position extraction apparatus and a storage position extraction method for extracting a storage position of a calculation result that satisfies a predetermined condition from among calculation results stored in a plurality of calculation result storage areas.

  In recent years, due to the spread of the Internet and the like, there is an increasing need to perform settlement and personal authentication electronically through a network, but RSA cryptography is used as one of the basic technologies for maintaining the information security. The security of this RSA cipher is based on the difficulty of the prime factorization problem. In order to use this cipher safely, the security evaluation of the RSA cipher is performed precisely and the implementation parameters are set appropriately. It is important to evaluate

  For such an evaluation, it is necessary to determine how much the most efficient prime factorization algorithm known at present can be implemented, and the prime factorization algorithm is not limited to software aspects, but also to dedicated hardware. Evaluation by is indispensable.

  For example, among prime factorization algorithms that are important in evaluating the security of RSA cryptography, the most known method at present is the general number field sieving method. Specifically, the general number field sieving method includes four steps: a polynomial selection step, a relational expression search step, a matrix calculation step, and a square root calculation step (see Non-Patent Document 1).

  As a calculation amount necessary for the general number field sieving method, the most essential part of the above steps is a relational expression search step. This relational expression search step is further composed of two types of processes, ie, a sieving process part and a relational expression checking part, and it is known that sieving process is essential in terms of calculation amount.

  The sieving process is an operation for initializing a memory and a process that combines log addition and threshold determination. In this log addition process, a memory space having a data capacity of 1 byte (8 bits) is prepared, and the logarithmic value of the prime number is set for each of the prepared prime numbers for the address data satisfying a certain condition. Perform the addition process. In the threshold determination process, after the log addition process is performed on all prime numbers, a process of extracting an address of memory data that is equal to or greater than a predetermined threshold is performed (see Patent Document 1). And the process which calculates | requires the common part of the memory address each extracted, whenever this sieving process is implemented in multiple times is also important, and needs to be implemented efficiently.

  Conventionally, as a method for obtaining the common part of the memory address, when obtaining this common part, the addresses extracted for each of the plurality of sieving processes are temporarily stored in an external storage device, and these data are matched to each other. A method for obtaining a part is known.

  More specifically, as shown in FIG. 9, it is determined whether the value of each byte after the first sieving process is over the threshold “6”, and the value over the threshold “6”. Are transferred to a buffer outside the apparatus and held in the buffer. Subsequently, after the second sieving process is completed, the same process is performed to transfer the addresses “3” and “5” of the bytes holding the value of the threshold value “6” or more, which are also held in the buffer. Then, the common part “5” is extracted from the results held in the respective buffers. Here, the process of transferring data from the hardware to the buffer and the process of extracting the common part held in the buffer are sequential processes.

JP 2007-188263 A Tetsuya Izu, Yuji Kida “Current Status of Factoring”, Journal of the Japan Society for Applied Mathematics, Vol.13, No.2 (20030625) pp. 289-303, 2003.

  By the way, in the technique for extracting the common part of the memory address by performing the data transfer to the buffer as described above, when extracting the common part, since the output bus to the external storage device is usually single, Both extraction and common part extraction are difficult to parallelize, causing problems such as increased data transfer time due to sequential processing and increased processing time, reducing overall processing efficiency. There was a problem to do.

  Accordingly, the present invention has been made to solve the above-described problems of the prior art, and enables parallelization of processes required for common part extraction, thereby increasing the efficiency of the entire process and increasing the processing time. It aims to become.

  In order to solve the above-described problems and achieve the object, the present invention is a storage position extraction that extracts a storage position of a calculation result that satisfies a predetermined condition from each calculation result stored in each of a plurality of calculation result storage areas. A storage unit that stores first information indicating that the calculation result satisfies the predetermined condition in association with the calculation result storage area, and the predetermined information every time each calculation result is updated. Based on the change result changed by the change means, the change means for changing the first information corresponding to the calculation result that no longer satisfies the condition to the second information indicating that the predetermined condition is not satisfied Extraction means for extracting a storage position of a calculation result satisfying the predetermined condition.

  In the above invention, the present invention may further include setting means for setting the first information in association with the calculation result storage area of the calculation result satisfying the predetermined condition among the calculation results in the first calculation. The changing means changes the first information corresponding to the calculation result that does not satisfy the predetermined condition in the calculation after the first time to the second information indicating that the predetermined condition is not satisfied. It is characterized by that.

  In the above invention, the present invention further includes a setting unit that sets the first information in association with all the calculation result storage areas at the calculation start time, and the changing unit sets the predetermined condition as follows. The first information corresponding to the calculation result that is no longer satisfied is changed to second information indicating that the predetermined condition is not satisfied.

  In addition, the present invention is a storage position extraction method for extracting a storage position of a calculation result that satisfies a predetermined condition among the calculation results respectively stored in a plurality of calculation result storage areas, wherein the predetermined condition is satisfied A storage step of storing first information indicating that the calculation result is associated with the calculation result storage area, and a calculation result that does not satisfy the predetermined condition each time the calculation result is updated A change step for changing the first information to second information indicating that the predetermined condition is not satisfied, and a calculation result satisfying the predetermined condition based on the change result changed by the change step And an extraction step for extracting the position.

  According to the present invention, a parity bit is prepared for each address in the arithmetic unit, and the extracted address information is processed using the parity bit, thereby enabling parallel processing necessary for common part extraction. It is possible to increase the overall efficiency and increase the processing time.

  Embodiments of a storage location extraction apparatus and a storage location extraction method according to the present invention will be described below in detail with reference to the accompanying drawings.

  In the following embodiments, the outline and features of the common address extraction device according to the first embodiment, the configuration of the common address extraction device, and the flow of processing will be described in order, and finally the effects of the first embodiment will be described.

[Outline and Features of Common Address Extraction Device According to Embodiment 1]
First, the outline and characteristics of the common address extracting apparatus according to the first embodiment will be described with reference to FIG. FIG. 1 is a diagram for explaining the outline and features of the common address extracting apparatus according to the first embodiment.

  The common address extracting apparatus 10 according to the first embodiment outlines extracting a memory address of an operation result satisfying a predetermined condition from each operation result stored in each of a plurality of operation result storage areas. The common address extracting apparatus 10 is mainly characterized in that the processing is speeded up by improving the efficiency of the entire processing.

  The main feature will be described in detail. The common address extraction device 10 includes a 1-byte storage area for storing the log addition processing result for each address, and a flag indicating whether the log addition processing result meets the selection condition. Is stored in association with a 1-bit storage area (parity bit) for storing each address.

  Under such a configuration, the common address extraction apparatus 10 performs the first log addition process for the sieving process on each byte (see (1) in FIG. 1). Then, the common address extracting apparatus 10 turns on the parity bit attached to the address of the byte that satisfies the condition for the value of each byte after the first log addition processing is completed ((2 in FIG. 1). )reference). Specifically, the common address extraction apparatus 10 determines whether or not each value held by the byte after the first log addition processing is completed is equal to or greater than a threshold value, and as a result, retains a value equal to or greater than the threshold value. The parity bit of the byte address is set to “1”.

  Subsequently, the common address extraction apparatus 10 performs the second log addition process for the sieving process on each byte while maintaining the parity bit value (see (3) in FIG. 1). Then, the common address extracting apparatus 10 turns off the parity bit attached to the address of the byte that does not satisfy the condition for each value held by the byte after the second sieving process is completed ((( 4)). Specifically, the common address extraction apparatus 10 determines whether each value held by the byte after the second sieving process is completed is a value less than a threshold value, and as a result, determines a value less than the threshold value. The parity bit of the byte address to be held is set to 0.

  Thereafter, the common address extracting device 10 extracts and stores the address of the byte whose corresponding parity bit value is 1 as a common part of the memory address satisfying the condition (see (5) in FIG. 1). In addition, although the case where a sieving process is performed twice and a common part is extracted is described above, the sieving process may be performed twice or more to extract a common part.

  As described above, the common address extracting apparatus 10 can increase the efficiency of the entire processing and speed up the processing as described above, as a result of enabling parallel processing of the processing required for the common part extraction. Is possible.

[Configuration of Common Address Extractor 10]
Next, the configuration of the common address extracting apparatus 10 shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a block diagram illustrating the configuration of the common address extracting apparatus 10 according to the first embodiment. In the following description, a common address extraction device is applied to the FPGA.

  As shown in the figure, the common address extracting apparatus 10 includes operation units 11a to 11n, memories 12a to 12n, and a control unit 13, and is connected to factor basis databases 20a and 20b, respectively. Memories 12a to 12n are allocated to the arithmetic units 11a to 11n, respectively. The processing of each of these units will be described below.

  The factor basis databases 20a and 20b store a set of factor bases that are triple natural numbers (p, s, log). The factor basis is a natural number in which p is a prime number, s is a natural number of 0 or more and less than p, and a logarithm value log2 (p) of log p is rounded up. In the factor basis databases 20a and 20b, different sets of factor bases are stored, and the factor basis (p, s, log) stored in the factor basis database 20a is used in the first sieving process, and the factor basis database 20b The factor bases (p, s, log) stored in are used in the second sieving process. Each of the factor base databases 20a and 20b stores about 50 million as the total number of factor bases.

  The calculation unit 11 reads the factor base from the factor base database 20 and performs log addition processing using the factor base. Specifically, using the example of FIG. 3, first, the calculation unit 11 a initializes the value of each byte to 0 and reads (p, s, log) from the factor base database 20. Then, the arithmetic unit 11a determines whether or not s <S (that is, determines whether or not the value of s protrudes from the memory size). If s <S, the byte position in the memory space is determined. Read the memory value of s, add the value of log to that value, and write the value back to the same byte position.

  The calculation unit 11a then repeats the above process until s + p is changed to s, and the memory size of the memory 12a protrudes (that is, until the value of s + p becomes equal to or greater than S). Then, when the memory size exceeds the memory size, the calculation unit 11a sets s−S to s again and delivers (p, s, log) to the calculation unit 11b. After that, when all the arithmetic units 11a to 11n perform the above processing, the final arithmetic unit 11n will be described later that the first sieving process has been completed (or that the first and subsequent sieving processes have been completed). The threshold determination unit 13a is notified.

  Here, a calculation example of the log addition processing will be described with reference to FIG. In the example of FIG. 4, (3, 0, 2), (5, 0, 3), (7, 4, 3), (11, 4) are stored as factor bases (p, s, log) in the factor base database 20. , 4), (13, 6, 4), (17, 3, 5), (19, 2, 5) are stored, the arithmetic unit 11a sequentially reads out the factor bases and logs Addition processing is performed, and the total of log addition processing results performed using all factor bases is stored in the memory 12. In other words, in the example of FIG. 4, as the total of the log addition processing results, “5”, “0”, “5”, “7”, “7”, “3”, “6” Is stored. Thereafter, the control unit 13 to be described later determines whether or not each value held by the byte after the log addition processing is finished is equal to or greater than the threshold “6”, and as a result, retains a value equal to or greater than the threshold “6”. The parity bits of addresses “3”, “4”, and “6”, which are byte addresses, are set to 1.

Memory 12a~12n has S = 2 ¹⁹ bytes memory space in total, compatible 1 and byte storage area as a data capacity to store a log addition processing result for each address, the log addition process result selection conditions A 1-bit parity bit is stored for each address.

  The control unit 13 includes a threshold value determination unit 13a and a common address extraction unit 13b. The threshold value determination unit 13a determines whether or not the byte value of each of the memories 12a to 12n after the first sieving process is over the threshold value, and the parity attached to the byte address that is equal to or more than the threshold value. Turn on the bit. In addition, after the first sieving process, it is determined whether the value of each byte after the sieving process is less than the threshold value, and the parity bit attached to the address of the byte that is less than the threshold value is turned off. .

  Specifically, when the threshold determination unit 13a receives a notification that the first sieving process has been completed from the calculation unit 11n, is the threshold value greater than or equal to the threshold for each byte value after the sieving process is completed? As a result, the threshold value determination unit 13a sets the parity bit of the address of the byte holding a value equal to or greater than the threshold value to 1. In addition, when the common address extraction apparatus 10 receives a notification that the first and subsequent sieving processes have been completed from the arithmetic unit 11n, the common address extracting apparatus 10 sets a value less than the threshold for each byte value after the sieving process is completed. As a result, the parity bit of the address of the byte holding the value less than the threshold is set to 0.

  If it demonstrates using the example of FIG. 5, the threshold value determination part 13a is more than a threshold value (threshold "6" in the example of FIG. 5) with respect to the value of each byte after the 1st sieve process is complete | finished. The parity bits attached to the addresses “1” and “5” that are equal to or greater than the threshold are set to “1”. Thereafter, it is determined whether the value of each byte after the second sieving process is less than a threshold value. As a result, an address “1” having a parity bit “1” and less than the threshold value is determined. The parity bit attached to “0” is set to “0”. As a result, a common address 13b, which will be described later, is extracted as an address “5” having a parity bit “1” as a common part of the results of both the first and second sieving processes.

  The common address extraction unit 13b extracts the address of the byte whose corresponding parity bit value is 1 as the common part of the memory address equal to or greater than the threshold value. For example, referring to the example of FIG. 5 described above, the common address extraction unit 13b extracts the address “5” having the parity bit “1” as a common part of the memory address as shown in FIG.

[Processing by common address extractor]
Next, the overall processing flow by the common address extracting apparatus 10 according to the first embodiment will be described with reference to FIG. FIG. 6 is a flowchart illustrating the overall processing operation of the common address extracting apparatus 10 according to the first embodiment.

  As shown in the figure, the common address extracting device 10 initializes the value of each byte to 0 (step S101), and executes the first sieving process (detailed later using FIG. 7) (step S102). ). Then, the common address extraction device 10 determines whether or not each byte value after the first sieving process is equal to or greater than the threshold value, and turns on the parity bit attached to the byte address that is equal to or greater than the threshold value. (Step S103).

  Then, the common address extraction apparatus 10 initializes the value of each byte to 0 (step S104), and executes the second sieving process (step S105). Thereafter, after the second sieving process is completed, the common address extraction apparatus 10 determines whether the value of each byte after the sieving process is completed is less than the threshold value, and the address of the byte that is less than the threshold value Is turned off (step S106).

  Then, the common address extraction device 10 extracts the address of the byte whose corresponding parity bit value is 1 as the common part of the memory address equal to or greater than the threshold (step S107).

  Subsequently, the flow of the sieving process performed by the common address extracting apparatus 10 according to the first embodiment will be described with reference to FIG. FIG. 7 is a flowchart illustrating the sieving operation of the common address extracting apparatus 10 according to the first embodiment.

  As shown in the figure, the calculation unit 11a of the common address extraction device 10 reads the factor base (p, s, log) from the factor base database 20 (step S201). Then, the calculation unit 11a determines whether or not s <S (step S202). If s <S (Yes in step S202), the memory unit reads the memory value at the byte position s in the memory space, and determines the value. The value of log is added to and the value is written back to the same byte position (step S203).

  Then, the arithmetic unit 11a sets s + p to s (step S204), returns to step S202, determines whether s <S (that is, whether the value of s + p exceeds S), and s < The processes in steps S202 to S205 described above are repeated until it is determined not to be S. On the other hand, if it is determined in step S202 that s <S is not satisfied (No in step S202), s−S is changed to s, and (p, s, log) is transferred to the calculator 11b (step S202). S205). Here, the next factor base (p, s, log) stored in the factor base database 20 is read out simultaneously with the delivery to the calculation unit 11b, and the above-described factor base (p, s, log) is used to The same processing as in steps S202 to S205 is performed.

  After that, when the calculation unit 11b receives (p, s, log) from the calculation unit 11a, the calculation unit 11b performs the same processing as steps S202 to S205 described above, and delivers (p, s, log) to the next calculation unit 11c. (Steps S206 to S209), the processing is repeated up to the calculation unit 11n (Steps S210 to S212). Then, the arithmetic unit 11n performs log addition processing using all factor bases (p, s, log) stored in the factor base database 20, and then proceeds to step S103 described above. The first sieving process and the second sieving process shown in FIG. 6 perform the same process, but in the first sieving process, the factor basis (p, s, log) stored in the factor basis database 20a is used. ), And in the second sieving process, the log addition process is performed using the factor base (p, s, log) stored in the factor base database 20b.

[Effect of Example 1]
As described above, the common address extraction device 10 prepares a parity bit for each address in the arithmetic device, and processes the extracted address information using this parity bit, thereby performing processing necessary for common part extraction. Parallelization is possible, and the processing time can be increased by improving the efficiency of the entire processing.

  Also, according to the first embodiment, by realizing as hardware logic, threshold value determination and common term extraction processing can be executed in parallel, and further, common term extraction and memory initialization can be performed simultaneously with threshold value determination. As a result, the time required for the common term extraction process is greatly reduced, and the calculation efficiency of the entire sieving process in the prime factorization is remarkably improved. In addition, the memory logic element built in the FPGA (for example, Virtex 4) has a unit of 9 bits including 1-bit parity in each 1-byte element, which is particularly effective when this algorithm is implemented in hardware. is there.

  Although the embodiments of the present invention have been described so far, the present invention may be implemented in various different forms other than the embodiments described above. Therefore, another embodiment included in the present invention will be described below as a second embodiment.

(1) Parity bits In the present invention, all parity bits may be turned on at the start of processing, and parity bits attached to addresses that do not meet the conditions may be turned off after each calculation. Specifically, as shown in FIG. 8, the common address extraction device 10a initializes all the parity bits attached to each byte to 1 and initializes the value of each byte to 0 (see FIG. 8). 8, see (1)). Then, the common address extracting device 10a performs the first sieving process on each byte while keeping the value of the parity bit (see (2) in FIG. 8).

  Thereafter, the common address extraction device 10a determines the address of the byte that satisfies the condition (the value of the byte having a value of 6 or more that is a threshold value) for each byte value after the first sieving process is completed. For the address), the parity bit remains “1”, the parity bit attached to the address of the byte that does not satisfy the condition (the address of the byte that is also less than 6) is set to “0”, and all the bytes are simultaneously The value is initialized to 0 (see (3) in FIG. 8).

  Subsequently, the common address extraction device 10a performs the second sieving process on each byte while keeping the value of the parity bit (see (4) in FIG. 8). Then, the common address extracting device 10a, for each byte value after the second sieving process is completed, for the byte address satisfying the condition (a byte having a value of 6 or more which is a value determined as a threshold value). For (address), the parity bit attached to the address of the byte that does not satisfy the condition (the address of the byte that is also less than 6) is set to 0 without changing the parity bit, and all the byte values are initialized to 0 at the same time. (See (5) in FIG. 8). Thereafter, the address of the byte whose corresponding parity bit value is 1 is extracted.

  In this way, all parity bits are turned on at the start of processing, and after each operation, the parity bit attached to the address of the byte holding the value less than the threshold value is turned off, thus simplifying the circuit structure. Is possible.

(2) System Configuration The components of the illustrated devices are functionally conceptual and need not be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to that shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured. For example, the calculation unit 11 and the control unit 13 may be integrated.

  In addition, among the processes described in this embodiment, all or part of the processes described as being performed automatically can be performed manually, or the processes described as being performed manually can be performed. All or a part can be automatically performed by a known method. In addition, the processing procedure, control procedure, specific name, and information including various data and parameters shown in the above-described document and drawings can be arbitrarily changed unless otherwise specified.

(Supplementary Note 1) A storage position extraction device that extracts a storage position of a calculation result that satisfies a predetermined condition among calculation results stored in a plurality of calculation result storage areas,
Storage means for storing the first information indicating that the calculation result satisfies the predetermined condition in association with the calculation result storage area;
Changing means for changing the first information corresponding to the calculation result that does not satisfy the predetermined condition each time the calculation result is updated to second information indicating that the predetermined condition is not satisfied;
Extraction means for extracting a storage position of a calculation result that satisfies the predetermined condition based on a change result changed by the change means;
A storage position extraction apparatus comprising:

(Additional remark 2) It is further provided with the setting means which sets said 1st information in association with the calculation result storage area of the calculation result which satisfies the said predetermined condition among the calculation results in the first calculation,
The storage according to claim 1, wherein the changing unit changes the first information corresponding to the calculation result that no longer satisfies the predetermined condition in the calculation after the first time to the second information. Position extraction device.

(Additional remark 3) It is further provided with the setting means which sets said 1st information in correlation with all the calculation result storage areas at the time of calculation start,
The storage position extraction apparatus according to appendix 1, wherein the changing unit changes the first information corresponding to the calculation result that no longer satisfies the predetermined condition to the second information.

(Supplementary Note 4) The storage position extraction apparatus according to any one of Supplementary Notes 1 to 3, wherein the computation on the computation result storage area is performed in parallel.

(Additional remark 5) The said change means performs the process which updates said 1st information in parallel, The memory location extraction apparatus as described in any one of additional marks 1-4 characterized by the above-mentioned.

(Supplementary Note 6) The supplementary note 1 further includes computation result initialization means for initializing the computation result storage area at the same time when the first information is changed to the second information by the changing means. The memory position extraction device according to any one of?

(Supplementary note 7) The storage position extracting device according to any one of supplementary notes 1 to 6, wherein the storage means uses one byte as one unit as the calculation result storage area.

(Supplementary note 8) The storage means uses nine bytes as one unit, of which eight bits are used as the calculation result storage region, and one bit is used as a region for storing the first information. The memory position extraction device according to any one of the above.

(Supplementary note 9) A storage position extraction method for extracting a storage position of a calculation result satisfying a predetermined condition among calculation results stored in a plurality of calculation result storage areas,
A storage step of storing first information indicating that the calculation result satisfies the predetermined condition in association with the calculation result storage area;
A change step of changing the first information corresponding to the calculation result that does not satisfy the predetermined condition each time the calculation result is updated to second information indicating that the predetermined condition is not satisfied,
An extraction step for extracting a storage position of a calculation result that satisfies the predetermined condition based on the change result changed by the change step;
A memory location extraction method characterized by comprising:

(Supplementary Note 10) The method further includes a setting step of setting the first information in association with the calculation result storage area of the calculation result satisfying the predetermined condition among the calculation results in the first calculation,
The storage according to appendix 9, wherein the changing step changes the first information corresponding to the calculation result that no longer satisfies the predetermined condition in the calculation after the first time to the second information. Location extraction method.

(Supplementary Note 11) Further includes a setting step of setting the first information in association with all the calculation result storage areas at the calculation start time point,
The storage position extraction method according to appendix 9, wherein the changing step changes the first information corresponding to the calculation result that no longer satisfies the predetermined condition to the second information.

(Additional remark 12) The storage position extraction method according to any one of additional remarks 9 to 11, wherein the calculation on the calculation result storage area is performed in parallel.

(Additional remark 13) The said change process performs the process which updates said 1st information in parallel, The memory location extraction method as described in any one of additional remarks 9-12 characterized by the above-mentioned.

(Supplementary Note 14) The supplementary note further includes computation result initialization means for initializing the computation result storage area at the same time when the first information is changed to the second information by the changing step. The memory location extraction method according to any one of 9 to 13.

(Supplementary note 15) The storage location extraction method according to any one of supplementary notes 9 to 14, wherein the storage step uses one byte as one unit as the calculation result storage area.

(Supplementary note 16) Supplementary notes 9 to 15, wherein the storage step uses nine bytes as a unit, of which eight bits are used as the calculation result storage region, and one bit is used as a region for storing the first information. The memory location extraction method according to any one of the above.

  As described above, the storage position extraction apparatus and the storage position extraction method according to the present invention extract a storage position of a calculation result that satisfies a predetermined condition from each calculation result stored in each of a plurality of calculation result storage areas. In particular, it is possible to parallelize the processes required for common part extraction, and it is suitable for increasing the efficiency of the entire process and speeding up the process.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining an overview and features of a common address extraction device 10 according to a first embodiment. 1 is a block diagram illustrating a configuration of a common address extraction device 10 according to a first embodiment. It is a figure for demonstrating a log addition process. It is a figure for demonstrating the example of a calculation of log addition processing. It is a figure for demonstrating a threshold determination process. 3 is a flowchart illustrating an overall processing operation of the common address extracting apparatus 10 according to the first embodiment. 4 is a flowchart illustrating an operation of sieving processing of the common address extracting apparatus 10 according to the first embodiment. It is a figure for demonstrating the common address extraction apparatus 10a which concerns on Example 2. FIG. It is a figure for demonstrating the conventional sieve process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10a Common address extraction apparatus 11a-11n Operation part 12a-12n Memory 13 Control part 13a Threshold determination part 13b Common address extraction part 20a, 20b Factor base database

Claims (4)

A storage position extraction device that extracts a storage position of a calculation result that satisfies a predetermined condition among the calculation results stored in a plurality of calculation result storage areas,
Storage means for storing the first information indicating that the calculation result satisfies the predetermined condition in association with the calculation result storage area;
Changing means for changing the first information corresponding to the calculation result that does not satisfy the predetermined condition each time the calculation result is updated to second information indicating that the predetermined condition is not satisfied;
Extraction means for extracting a storage position of a calculation result that satisfies the predetermined condition based on a change result changed by the change means;
A memory location extraction apparatus. Of the calculation results in the first calculation, further comprising setting means for setting the first information in association with the calculation result storage area of the calculation results satisfying the predetermined condition,
2. The change unit according to claim 1, wherein the change unit changes the first information corresponding to the calculation result that no longer satisfies the predetermined condition in the calculation after the first time to the second information. Memory location extraction device. A setting means for setting the first information in association with all the calculation result storage areas at the calculation start time;
The storage position extraction apparatus according to claim 1, wherein the changing unit changes the first information corresponding to the calculation result that no longer satisfies the predetermined condition to the second information. A storage position extraction method for extracting a storage position of a calculation result that satisfies a predetermined condition among each calculation result stored in each of a plurality of calculation result storage areas,
A storage step of storing in the storage unit the first information indicating that the calculation result satisfies the predetermined condition in association with the calculation result storage area;
A change step of changing the first information corresponding to the calculation result that does not satisfy the predetermined condition each time the calculation result is updated to second information indicating that the predetermined condition is not satisfied,
An extraction step for extracting a storage position of a calculation result that satisfies the predetermined condition based on the change result changed by the change step;
Memory location extraction method.

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