JP2009042992A - Bus controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus controller configuring a bus to prevent enlargement of a chip area due to wiring congestion, and controlling the bus. <P>SOLUTION: In this bus controller 2, an arbitration part 21 arbitrates access requests from a plurality of masters 1-N (1-1 to 1-N). A slave access control part 23 performs access arbitrated by the arbitration part 21 to a slave 4. The bus controller 2 is connected with the plurality of masters 1-N (1-1 to 1-N) by a one-way read bus RD and one-way write buses WD1-WDN, and the write buses WD1-WDN are configured such that a bus width of each the write bus WD1-WDN becomes narrower than a bus width of the read bus RD. Accordingly, there is effect that it can be prevented that the chip area becomes large by the wiring congestion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technology for controlling a bus in a multiprocessor system, and in particular, a bus that controls a read bus and a write bus as separate one-way buses and configures the bus so as to prevent wiring congestion of the write bus. The present invention relates to a control device.

  In recent years, a multiprocessor system has been actively developed in order to improve the processing performance of the processor. In such a multiprocessor system, a common bus coupling is generally used so that a plurality of processors (hereinafter also referred to as masters) can access a shared main memory (hereinafter also referred to as slaves). .

  In such a shared bus connection, there are two types of bus connection methods. One method is to use a read bus and a write bus as one bidirectional bus, and control the bus so that read data and write data do not collide. In this method, the number of buses can be reduced, so that the chip area can be reduced.

  Another method is to make the read bus and the write bus separate unidirectional buses. In this method, the size at which the data transfer of each bus can be efficiently performed is determined, and the width is often equal to the line size of the cache. By making reading and writing independent, data writing can be performed even when data is being read from the slave, thereby improving processing performance. As a technique related to these, there is an invention disclosed in Patent Document 1 below.

The multiprocessor system disclosed in Patent Document 1 includes M CPU cards and a unidirectional inter-CPU card connection interface for connecting them. The inter-CPU card control circuit has a command transmission circuit and an arbitration circuit. The instruction sending circuit divides each of the N divided instructions into N cycles when receiving a plurality of instructions for the main memory from a plurality of processors, and divides the N divided instructions into N cycles to connect the CPU cards. To send. When the arbitration circuit receives a division command from the CPU card, the arbitration circuit arbitrates and serializes the division command, reproduces the command, and gives the command to the main memory control circuit.
JP 2000-268209 A

  As described above, when the read bus and the write bus are one bidirectional bus, there is an advantage that the number of buses can be reduced. However, data can be written when data is read from the slave. Therefore, there is a problem that the processing performance is lowered. Further, in order to increase the data transfer speed, it is necessary to perform high impedance control, and there is a problem that the processing speed cannot be improved by inserting a buffer.

  In addition, when the read bus and the write bus are separate one-way buses, there is an advantage that the processing performance can be improved, but one of the write data output from a plurality of masters is selected. When the bus width is wide, the selection logic becomes large, and there is a problem that the chip area becomes large or wiring becomes impossible due to wiring congestion.

  Further, the above-mentioned Patent Document 1 discloses that the read bus and the write bus are one bidirectional bus, and that the read bus and the write bus are separate unidirectional buses. The above-mentioned problems cannot be solved.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a bus control device that configures and controls a bus so as to prevent an increase in chip area due to wiring congestion. It is.

  According to an embodiment of the present invention, there is provided a bus control device that controls access requests from a plurality of masters to slaves in a multiprocessor system. The arbitration unit arbitrates access requests from a plurality of masters. The slave access control unit performs access arbitrated by the arbitration unit to the slave. The bus control device is connected to a plurality of masters by a one-way read bus and a write bus, and the bus width of the write bus is configured to be narrower than the bus width of the read bus.

  According to this embodiment, the bus control device is connected to a plurality of masters by a unidirectional read bus and a write bus, and the bus width of the write bus is configured to be narrower than the bus width of the read bus. There is an effect that it is possible to prevent an increase in the chip area due to wiring congestion.

(First embodiment)
FIG. 1 is a diagram showing a configuration example of a multiprocessor system including a bus control unit (hereinafter also referred to as a bus control device) in the first embodiment of the present invention. This multiprocessor system includes a plurality of masters 1 to N (1-1 to 1-N), a bus control unit 2, a slave control unit 3, and a slave 4.

  Each of the masters 1 to N (1-1 to 1-N) includes a CPU (Central Processing Unit) 11, an I cache 12 that holds instruction codes, and a D cache 13 that holds operands (data). Including. The line size of each cache is 128 bits, and access such as cache fill is performed in units of 128 bits.

  The masters 1 to N (1-1 to 1-N) output requests 1 to N when accessing the slave 4. Each request includes information accompanying the request, such as a request signal, a read / write signal, a byte control signal, and a burst (indicating that the access data is 128 bits) signal.

  Masters 1 to N (1-1 to 1-N) read data from slave 4 via a 128-bit RD bus. The masters 1 to N (1-1 to 1-N) write data to the slaves 4 via 32-bit WD1 to WDN, respectively.

  The bus control unit 2 receives requests 1 to N from a plurality of masters 1 to N (1-1 to 1-N), arbitrates which request is accepted, and receives a request from the master (hereinafter referred to as a request). A snoop processing request is made to a master other than the master other than the master that issued the data, and it is confirmed whether the D cache 13 of the other master has the data to be accessed. Then, the bus control unit 2 outputs the accepted access request to the slave control unit 3.

  The slave control unit 3 receives an access request from the bus control unit 2 and reads or writes data to the slave 4 via the shared bus 5. The slave control unit 3 can perform 128-bit data read and data write to the slave 4.

  In the system of the present invention, the instruction held in the I-cache 12 has an architecture that does not need to maintain coherency with the operand (the cache purge is essential when the instruction code is rewritten), and the coherency is reduced by the snoop process. All that needs to be maintained is between the D caches of each master. Although an instruction fetch request from each master and an operand access request are output with the same request signal, only operand (data) access related to snoop processing will be described below.

  The bus control unit 2 includes an arbitration unit 21, a snoop control unit 22, a slave access control unit 23, and a 128-bit write data buffer 24.

  When receiving a plurality of requests from the master, the arbitrating unit 21 performs arbitration, and asserts an ACK (acceptance) signal to the selected master. As an arbitration method, a round robin method or a random method is used.

  The snoop control unit 22 makes a snoop process request to a master other than the requested master in the next cycle arbitrated by the arbitration unit 21, and the D cache 13 of the other master has the data to be accessed. Check if it is. After the end of the snoop process, the slave access control unit 23 outputs an access request to the slave control unit 3.

  In the following, the snoop process will be described for each case. However, it is assumed that “no snoop hit” occurs when no other master has data of the same address. Further, if another master has data of the same address in an Exclusive state, a Shared state, or a Dirty state, it is assumed that a “snoop hit” occurs.

(1) When no snoop hit occurs The other master that has received the snoop processing request checks whether or not there is a line in the D cache 13 that matches the address indicated by the snoop request. If there is no matching line in its own D-cache 13, information indicating "none" is returned to the master that issued the request. Upon receiving information indicating “none” from all other masters, the snoop control unit 22 outputs the request from the arbitration unit 21 to the slave access control unit 23 as it is. Note that the line in the master D-cache 13 that issued the request is registered as Exclusive. That is, this line is only in the master D-cache 13 that issued the request.

(2) When another master has an exclusive state If there is a line that matches another master's D cache 13 and is in an exclusive state, information indicating "Exclusive" is sent to the master that issued the request. Return it. In the case of read, when the master that issued the request receives information indicating “Exclusive”, both masters register the line as Shared. That is, this line is shared by a plurality of master D-caches 13.

  In the case of a write, when the master that issued the request receives information indicating “Exclusive”, the write data is written into the D cache 13 of the master that has been in an exclusive state, and both masters are in the line. Is registered as Shared. Alternatively, only the master that issued the request may be registered as exclusive, by invalidating the line in the master D-cache 13 held in the exclusive state.

(3) When another master has a shared state If there is a line that matches the D cache 13 of another master and the shared state is present, information indicating “Shared” is sent to the master that issued the request. Return it. In the case of a read, when the master that issued the request receives information indicating “Shared”, the line in the D cache 13 is registered as Shared. That is, this line is shared by a plurality of master D-caches 13.

  In the case of a write, when the master that issued the request receives information indicating “Shared”, the write data is written into the D cache 13 of the master that has been in the Shared state, and these masters are in the line. Is registered as Shared. Alternatively, only the master that issued the request may be registered as an exclusive by invalidating the line of the master D cache 13 held in the shared state.

(4) When another master has a Dirty state There is a line that matches the D cache 13 of the other master and the Dirty state (this line has been updated and holds a value different from the contents of the main memory. Information indicating “Dirty” is returned. In the case of a read, the other master simultaneously writes the data back into the main memory. There are a case where the line of the D cache 13 is invalidated simultaneously with the data write back and a case where the line is left in the D cache 13 as a valid state only by making it Clean. Which of these is determined depends on the request state of the snoop request, the cache mode, and the like.

  When invalidating the line, only the D cache 13 of the master that issued the request has this line, and the master that issued the request registers this line with Exclusive. This is because a dirty line can only be held by the master D-cache, and is always held exclusively.

  On the other hand, when only the Clean is set, at least two master D caches 13 have this line and are registered in the D cache 13 as Shared.

  In the case of a write, when the master that issued the request receives information indicating “Dirty”, the write data is written into the D cache 13 of the master that had been in the Dirty state, and both masters Is registered as Shared. Alternatively, only the master that issued the request may be registered as Exclusive by invalidating the line in the master D-cache 13 held in the Dirty state. In either case, coherency for that line is preserved.

  If the request after arbitration is a read, the snoop control unit 22 outputs the access request to the slave 4 to the slave access control unit 23 after performing the above-described snoop process. When the slave access control unit 23 reads 128-bit data via the slave control unit 3, the slave access control unit 23 outputs the data to the RD bus.

  The snoop control unit 22 first performs the above-described snoop processing even when the request after arbitration is a write. Thereafter, since 32-bit write data is output from the requesting master, the arbitration unit 21 outputs one ACK (acceptance) signal to the requesting master in response to one write request. At this time, if the write data is 128 bits, four write requests are output from the master, and 32-bit data is sequentially written into the write data buffer 24.

  Since the 128-bit write data is data on the same line in the cache, the snoop process at the time of writing is performed only for the first write request, and the snoop process for the remaining three write requests is not performed.

  When write data for four times is written in the write data buffer 24, the slave access control unit 23 outputs a write request for the slave 4 to the slave control unit 3 and 128 bits written in the write data buffer 24. Are collectively output to the slave processing unit 3.

  FIG. 2 is a timing chart for explaining processing of the multiprocessor system according to the first embodiment of the present invention. In FIG. 2, a request 1 from the master 1 (1-1) is received by the arbitration unit 21 as a result of the arbitration.

  At T2, master 1 (1-1) asserts a request (request 1 signal). This request is a request to read data at address A1, and the RW1 signal is set to a high level (hereinafter, H level). The arbitration unit 21 asserts the ACK1 signal in response to the read request for the address A1.

  At T3, the snoop control unit 22 issues a snoop processing request corresponding to the read request of the address A1 to a master other than the master 1 (1-1), and the snoop processing is performed. At this time, the master 1 (1-1) asserts the next request (request 1 signal). This request is a write request of 32 bits or less to the address A2, and the RW1 signal is set to the low level (hereinafter, L level). Then, the master 1 (1-1) outputs write data WD2.

  At T4, the snoop control unit 22 issues a snoop process request corresponding to the write request at the address A2 to a master other than the master 1 (1-1), and the snoop process is performed. At this time, the master 1 (1-1) asserts the next request (request 1 signal). This request is a request to read the data at address A3, and the RW1 signal is set to the H level.

  At T5, the snoop control unit 22 issues a snoop processing request corresponding to the read request at the address A3 to a master other than the master 1 (1-1). At this time, the master 1 (1-1) sets the BURST1 signal to the H level and outputs a burst write request to the address A4, and also outputs the first 32-bit write data WD4-1. This data is written into the write data buffer 24.

  In cycle T5, data RD1 corresponding to the read request at address A1 is read from slave 4 and output to master 1 (1-1), and VLD1 signal indicating that the read data is valid is at H level. Is done. Also, write data WD2 to address A2 is output to slave 4.

  At T6, the snoop control unit 22 issues a snoop processing request corresponding to the write request at the address A4 to a master other than the master 1 (1-1). At this time, the master 1 (1-1) outputs the second 32-bit write data WD4-2 and writes it into the write data buffer 24. The snoop processing request corresponding to the write request at address A4 is made only in this cycle.

  At T7, the master 1 (1-1) outputs the third 32-bit write data WD4-3 and writes it into the write data buffer 24, and the data RD3 corresponding to the read request at the address A3 is received from the slave 4. Read out and output to the master 1 (1-1). At this time, the VLD1 signal indicating that the read data is valid is set to the H level.

  At T8, the master 1 (1-1) outputs the last 32-bit write data WD4-4 and writes it into the write data buffer 24.

  At T9, the 128-bit write data WD4 written in the write data buffer 24 is output to the slave 4 and written.

  FIG. 3 is a flowchart for explaining the processing procedure of the bus control unit 2 according to the first embodiment of the present invention. First, it is determined whether or not the request from the master is a write request (S11). If it is not a write request, it is determined that the request is a read request (S11, No), and the snoop control unit 22 issues a snoop process request to another master (S18), and the process proceeds to step S17.

  If the write request is determined (S11, Yes), the snoop control unit 22 issues a snoop process request to another master (S12). Then, the slave access control unit 23 refers to the BURST signal and determines whether or not the size of the write data is larger than 32 bits (S13).

  If the size of the write data is 32 bits or less (S13, No), the process proceeds to step S17. If the size of the write data is larger than 32 bits (S13, Yes), the value of the Count register is cleared to 0 (S14). Then, 32-bit data is written to the write data buffer 24, and the value of the Count register is incremented (S15).

  Next, it is determined whether or not the value of the Count register is smaller than 4 (S16). When the data size is larger than 32 bits, since the size is only 128 bits, if the value of the Count register is smaller than 4 (S16, Yes), the process returns to step S15 to repeat the data writing to the write data buffer 24. . If the value of the Count register is 4 (S16, No), since the 128-bit line data is ready, the process proceeds to step S17.

  In step S <b> 17, the slave control unit 3 executes access to the slave 4. In the case of read data, the slave control unit 3 outputs the data read from the slave 4 to the master that issued the request via the RD bus. In the case of write data, the slave control unit 3 writes 128-bit (or 32 bits or less) data written in the write data buffer 24 to the slave 4.

  In the above description, the write data bus width between the masters 1 to N (1-1 to 1-N) and the bus control unit 2 is 32 bits, and the read data bus width is 128 bits. However, it goes without saying that the same effect can be obtained if the bus width of the write data is narrower than the bus width of the read data.

  As described above, according to the bus control device of the present embodiment, the write data bus width (32 bits) between the masters 1 to N (1-1 to 1-N) is changed to the read data bus width. Since it is narrower than (128 bits), it is possible to prevent the chip area from being increased due to wiring congestion.

  When writing 128-bit data to the slave 4, the write data buffer 24 is written and connected to the write data buffer 24 four times and then written to the slave 4, so that the write data bus width It is possible to write data having a size equal to the line size of the D-cache 13 to the slave 4 at a time while reducing the size of the slave 4.

(Second Embodiment)
FIG. 4 is a diagram illustrating a configuration example of a multiprocessor system including a bus control unit according to the second embodiment of the present invention. Compared with the multiprocessor system in the first embodiment shown in FIG. 1, the only difference is that a snoop data buffer 25 into which data in the D-cache 13 is written when a snoop hit is added. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  The snoop control unit 22 makes a snoop processing request to a master other than the master that has been requested after arbitration by the arbitration unit 21, and whether or not the D cache 13 of another master has data to be accessed. To check. When a snoop hit occurs, the master writes data for one line in the 128-bit snoop data buffer 25.

  Masters 1 to N (1-1 to 1-N) can snoop by writing 32-bit data four times through WD1 to WDN in the same manner as when writing 128-bit data to the write data buffer 24. Data is written into the snoop data buffer 25.

(1) In the case where no snoop hit occurs When another master that has received a snoop processing request does not have a matching line in its own D-cache 13, information indicating "none" is returned to the master that issued the request. Upon receiving information indicating “none” from all other masters, the snoop control unit 22 outputs the request from the arbitration unit 21 to the slave access control unit 23 as it is. Then, the line of the master D cache 13 that has issued the request is registered as Exclusive.

(2) When another master has an exclusive state If there is a line that matches another master's D cache 13 and is in an exclusive state, information indicating "Exclusive" is sent to the master that issued the request. Return it. In the case of reading, another master simultaneously writes the data of the line into the snoop data buffer 25. When the master that issued the request receives information indicating “Exclusive”, the data of the line is read from the snoop data buffer 25. Both masters register the line as Shared.

  In the case of writing, when the requesting master receives information indicating “Exclusive”, the write data is written into the write data buffer 24 and the snoop data buffer 25 and the line is registered as Shared. The other master reads the data of the line from the snoop data buffer 25 and registers it as Shared. The data written to the write data buffer 24 is written to the slave 4 by the slave control unit 3. Alternatively, only the master that issued the request may be registered as exclusive, by invalidating the line in the master D-cache 13 held in the exclusive state.

(3) When another master has a shared state If there is a line that matches the D cache 13 of another master and the shared state is present, information indicating “Shared” is sent to the master that issued the request. Return it. In the case of reading, another master simultaneously writes the data of the line into the snoop data buffer 25. When the master that issued the request receives information indicating “Shared”, the data of the line is read from the snoop data buffer 25. Both masters register the line as Shared.

  In the case of writing, when the requesting master receives information indicating “Shared”, the write data is written into the write data buffer 24 and the snoop data buffer 25 and the line is registered as Shared. The other master reads the data of the line from the snoop data buffer 25 and registers it as Shared. The data written to the write data buffer 24 is written to the slave 4 by the slave control unit 3. Alternatively, only the master that issued the request may be registered as an exclusive by invalidating the line of the master D cache 13 held in the shared state.

(4) When another master has a Dirty state If there is a line that matches the D cache 13 of another master and the state is Dirty, information indicating "Dirty" is sent to the master that issued the request. Return it. In the case of reading, another master simultaneously writes the data of the line into the snoop data buffer 25. When the master that issued the request receives the information indicating “Dirty”, the data of the line is read from the snoop data buffer 25. Both masters register the line as Shared.

  In the case of writing, when the requesting master receives information indicating “Dirty”, the write data is written into the write data buffer 24 and the snoop data buffer 25 and the line is registered as Shared. The other master reads the data of the line from the snoop data buffer 25 and registers it as Shared. The data written to the write data buffer 24 is written to the slave 4 by the slave control unit 3. Alternatively, only the master that issued the request may be registered as Exclusive by invalidating the line in the master D-cache 13 held in the Dirty state.

  FIG. 5 is a timing chart for explaining processing of the multiprocessor system according to the second embodiment of the present invention. FIG. 5 shows a snoop hit in the D cache 13 of the master N (1-N) in the snoop process at the time of a read request for the address A1 from the master 1 (1-1).

  At T2, master 1 (1-1) asserts a request (request 1 signal). This request is a request to read data at address A1, and the RW1 signal is set to the H level. The arbitration unit 21 asserts the ACK1 signal in response to the read request for the address A1.

  At T3, the snoop control unit 22 issues a snoop processing request corresponding to the read request of the address A1 to a master other than the master 1 (1-1), and the snoop processing is performed. At this time, the master N (1-N) has the data of the line in the Dirty state, and the master N (1-N) writes the first 32-bit snoop data D1-1 to the snoop data buffer 25. Include.

  In this cycle T3, the master 1 (1-1) asserts the next request (request 1 signal). This request is a request to read the data at address A2, and the RW1 signal is set to the H level. This request is kept waiting until the snoop process corresponding to the read request at the address A1 is completed.

  At T4, the master N (1-N) writes the second 32-bit snoop data D1-2 into the snoop data buffer 25.

  At T5, the master N (1-N) writes the third 32-bit snoop data D1-3 into the snoop data buffer 25.

  At T6, the master N (1-N) writes the fourth 32-bit snoop data D1-4 to the snoop data buffer 25. The 128-bit snoop data R1 written in the snoop data buffer 25 is output to the RD bus, and the VLD1 signal is set to the H level. At this time, a read request for the data at the address A2 is accepted, and the arbitration unit 21 asserts the ACK1 signal.

  At T7, the snoop control unit 22 issues a snoop processing request corresponding to the read request of the address A2 to a master other than the master 1 (1-1), and the snoop processing is performed. At this time, the master 1 (1-1) asserts the next request (request 1 signal). This request is a read request for data at address A3.

  At T8, the snoop control unit 22 issues a snoop processing request corresponding to the read request at the address A3 to a master other than the master 1 (1-1). At this time, the data R2 of the address A2 is output to the RD bus, and the VLD1 signal is set to the H level.

  At T9, data R3 at address A3 is output to the RD bus, and the VLD1 signal is set to H level.

  As described above, according to the bus control device in the present embodiment, when a snoop hit occurs in the snoop process, after writing and coupling the 32-bit snoop data to the snoop data buffer 25 four times, Since the master reads the snoop data from the snoop data buffer 25, the bus width of the snoop data can be narrowed, and the chip area can be prevented from increasing due to wiring congestion.

  In addition, since writing to the write data buffer 24 and writing to the snoop data buffer 25 can be performed in parallel, the processing speed can be improved.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows the structural example of the multiprocessor system containing the bus control part in the 1st Embodiment of this invention. 3 is a timing chart for explaining processing of the multiprocessor system in the first embodiment of the present invention; It is a flowchart for demonstrating the process sequence of the bus control part 2 in the 1st Embodiment of this invention. It is a figure which shows the structural example of the multiprocessor system containing the bus control part in the 2nd Embodiment of this invention. It is a timing chart for demonstrating the process of the multiprocessor system in the 2nd Embodiment of this invention.

Explanation of symbols

  1-1 to 1-N master, 2 bus control unit, 3 slave control unit, 4 slave, 5 shared bus, 11 CPU, 12 I cache, 13 D cache, 21 arbitration unit, 22 snoop control unit, 23 slave access control Part, 24 write data buffer, 25 snoop data buffer.

Claims (7)

A bus control device that controls access requests from a plurality of processors to a slave in a multiprocessor system,
Arbitration means for arbitrating access requests from the plurality of processors;
Access control means for performing access arbitrated by the arbitration means to the slave,
The bus control device is configured such that the bus control device is connected to the plurality of processors by a one-way read bus and a write bus, and the bus width of the write bus is narrower than the bus width of the read bus. The bus control device further includes write data storage means for storing write data,
The access control means writes a plurality of write data output from the processor to the write data storage means via the write bus, and writes the write data written to the write data storage means to the slave at a time. The bus control device according to claim 1. The bus control device further includes snoop control means for issuing a snoop request corresponding to the access request arbitrated by the arbitration means to the plurality of processors;
Snoop data storage means for storing snoop data,
The snoop control means writes a plurality of snoop data output from a snoop hit processor to the snoop data storage means via the write bus, and writes the snoop data written to the snoop data storage means to the read bus 3. The bus control device according to claim 2, wherein the bus control device outputs the request to the processor that has issued an access request at a time.   The snoop control means writes a plurality of write data output from the processor that issued the access request to the snoop data storage means via the write bus, and writes the write data written to the snoop data storage means to the snoop data storage means. 4. The bus control device according to claim 3, wherein the bus control device outputs to a processor that has made a snoop hit at a time via a read bus.   5. The bus control device according to claim 3, wherein the snoop hit processor is a processor that holds data in a cache line in a dirty state.   6. The bus control device according to claim 3, wherein the writing to the write data storage means and the writing to the snoop data storage means are performed in parallel via different write buses by different processors.   6. The bus control device according to claim 3, wherein the writing to the write data storage unit and the writing to the snoop data storage unit are performed in parallel via the same write bus by the same processor.

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