JP2009038885A5 - - Google Patents

Description

Signal extracting device and reactive power compensator including the same

  The present invention relates to a signal extraction apparatus for extracting a desired frequency component from an AC signal having a plurality of frequency components.

  2. Description of the Related Art Conventionally, there has been proposed a power conversion device that is provided in, for example, a power distribution system and stabilizes system power supplied to the power distribution system. As a power converter, for example, a DC power stored by a rechargeable battery is converted into AC power by an inverter and supplied to a system (for example, refer to Patent Document 1), or a fluctuation in reactive current generated in a wiring system is suppressed. Reactive power compensation device (also referred to as “reactive power generation device”) for the purpose.

JP 2004-153957 A

  FIG. 12 is a diagram illustrating an exemplary configuration of the reactive power compensator.

  In this reactive power compensator, for example, an inverter 61 is connected to a system having a system power supply 63 via an inductive impedance 62. The output voltage of the inverter 61 is controlled by the voltage control circuit 64.

The voltage control circuit 64 includes three-phase / dq axis converters 65 and 66, a d axis filter 67 and a q axis filter 68, a d axis current control circuit 69 and a q axis current control circuit 70, subtracters 71 and 72, and an adder 73. is thus generally configured to 74, dq-axis / three-phase converter 75 and the pulse width modulation circuit 7 6.

In this voltage control circuit 64, the current detector 77 detects the output currents Ia, Ib, and Ic of the inverter 61, and the d-axis current Id and q-axis current Id that have been dq-axis converted by the three-phase / dq-axis converter 66 and Control signals Ucd and Ucq are generated by the d-axis current control circuit 69 and the q-axis current control circuit 70 from the difference from the determined reference currents Id ′ and Iq ′. The control signals Ucd and Ucq are obtained by converting the detection voltages Vsa, Vsb, and Vsc of the system into the dq axis by the three-phase / dq axis converter 65 and removing the harmonic component by the d axis filter 67 and the q axis filter 68. The voltage control signals Vcd and Vcq are generated by correcting the voltage Vsd2 and the q-axis voltage Vsq2. The output voltages Vca, Vcb, Vcc of the inverter 61 are controlled based on the voltage control signals Vcd, Vcq. As a result, the power factor of the grid power supplied to the grid is improved.

  In the voltage control circuit 64 configured as described above, when the output currents Ia, Ib, and Ic of the inverter 61 are controlled to the target values by feedback control, the d-axis voltage Vsd2 and the q-axis voltage Vsq2 are obtained from the system detection voltages Vsa, Vsb, and Vsc. Since the control signals Ucd and Ucq are corrected by the d-axis voltage Vsd2 and the q-axis voltage Vsq2 to generate the voltage control signals Vcd and Vcq, the update period of the voltage control signals Vcd and Vcq is the d-axis voltage. It will be influenced by the update period of Vsd2 and q-axis voltage Vsq2. That is, if the time until the d-axis voltage Vsd2 and the q-axis voltage Vsq2 are obtained from the system detection voltages Vsa, Vsb, and Vsc becomes longer, the period for updating the voltage control signals Vcd and Vcq becomes longer.

The d-axis filter 67 and the q-axis filter 68 provided for obtaining the d-axis voltage Vsd2 and the q-axis voltage Vsq2 remove harmonic components and unbalance components from the output of the dq-axis / three-phase converter 65 , basic frequency positive phase of (the frequency of the system. 50 Hz or 60Hz in Japan) (hereinafter, referred to as "fundamental wave positive phase component".) but is for extracting only the direct current, d-axis filter 67 and The q-axis filter 68 is configured by a digital low-pass filter such as a moving average filter, an FIR (Infinite Impulse Response) filter, or an IIR (Infinite Impulse Response) filter, for example.

  The moving average filter is configured to sample data of a frequency to be removed for at least one period, and to remove the frequency by calculating a moving average of the sampling data.

With this low-pass filter, a delay detection basic NamiTadashi phase as reactive power compensator, voltage control signal Vcd, there is a problem that a period for updating the generation of Vcq longer. That is, in this reactive power compensator, since this low-pass filter is used for the d-axis filter 67 and the q-axis filter 68, the response speed becomes slow.

  In order to stably control the output currents Ia, Ib, and Ic of the inverter 61 to the target values by feedback control, it is desirable to generate the voltage control signals Vcd and Vcq as fast as possible. Since the compensator uses the d-axis filter 67 and the q-axis filter 68 formed of a moving average filter, the output of the d-axis voltage Vsd2 and the q-axis voltage Vsq2 always has a delay of a certain time or more, and the voltage control signal Vcd, There is a limit to speeding up the generation of Vcq.

  This invention makes it the subject to provide the signal extraction apparatus which can suppress that the detection delays also with respect to a low-order frequency component. It is another object of the present invention to provide a reactive power compensator including the signal extraction device.

  In order to solve the above problems, the present invention takes the following technical means.

A signal extraction device provided by a first aspect of the present invention is a signal extraction device for extracting a fundamental frequency from a three-phase alternating current signal in which a harmonic of a predetermined order is superimposed on the fundamental frequency. The three-phase alternating current signal is converted into a two-phase signal in a first orthogonal coordinate system that rotates at a angular frequency having the same frequency as the fundamental frequency. A first three-phase / two-phase conversion means for converting to a two-phase signal of the first orthogonal coordinate system; and a first arithmetic operation means for converting the three-phase AC signal into the first three-phase / two-phase conversion means. Output from the first three-phase / two-phase conversion means, harmonic generation means for generating a two-phase signal identical to the harmonics of the predetermined order converted into a two-phase signal in the first orthogonal coordinate system by Two-phase signal and two-phase signal output from the harmonic generation means And a harmonic cancellation means for canceling out the harmonics of the predetermined order included in the output of the first three-phase / two-phase conversion means by calculating a difference from the signal (claim) Item 1).

According to the present invention, the first three-phase / two-phase conversion means converts the three-phase AC signal into a two-phase signal in the first orthogonal coordinate system that rotates at an angular frequency having the same frequency as the fundamental frequency. Since the three-phase AC signal includes harmonics of a predetermined order in addition to the fundamental frequency, the harmonics of the predetermined order are output from the first orthogonal coordinate system to the output of the first three-phase / two-phase conversion means. The one converted into a two-phase signal is also included. A two-phase signal identical to a predetermined-order harmonic is generated from the three-phase AC signal by the harmonic generation means and converted into the two-phase signal of the first orthogonal coordinate system by the first three-phase / two-phase conversion means. The Then, the harmonic cancellation means calculates the difference between the two-phase signal output from the first three-phase / two-phase conversion means and the two-phase signal output from the harmonic generation means, and the first three-phase / The two-phase signal of a predetermined order harmonic contained in the output of the two-phase conversion means is canceled.

  Arithmetic processing for converting the three-phase AC signal by the first three-phase / two-phase conversion means into the two-phase signal of the first orthogonal coordinate system, and the two of the first orthogonal coordinate system from the three-phase AC signal by the harmonic generation means The calculation processing for generating the phase signal is performed at the same time, and the cancellation processing of the two-phase signal of the harmonic of the predetermined order included in the output of the first three-phase / two-phase conversion means is performed in real time. The extraction delay when extracting only the fundamental frequency from the three-phase AC signal on which the harmonics of the order are superimposed can be suppressed, and the response of the signal extraction can be improved.

According to a preferred embodiment, the harmonic generation means converts the three-phase AC signal into a two-phase signal of a second orthogonal coordinate system that rotates at an angular frequency having the same frequency as the harmonic of the predetermined order. A second three-phase / two-phase conversion means for converting the three-phase AC signal into a two-phase signal in the second orthogonal coordinate system by a second three-phase / two-phase conversion calculation process; Filter means for removing an AC signal included in the two-phase signal of the second orthogonal coordinate system converted by the three-phase / two-phase conversion means; and the second orthogonal coordinate system with respect to the first orthogonal coordinate system A two-phase signal of the second orthogonal coordinate system output from the filter means is converted into a two-phase signal of the first orthogonal coordinate system by an arithmetic process of rotating the second orthogonal coordinate system at a relative angular frequency. And coordinate conversion means for converting to Claim 2).

  According to another preferred embodiment, the harmonic generation means includes at least a positive-phase component of a seventh-order harmonic that rotates in the same direction as the rotation direction of the three-phase AC signal of the fundamental frequency, or of the fundamental frequency. It is preferable to generate a two-phase signal corresponding to the opposite phase of the fundamental frequency and the fifth harmonic that rotates in the direction opposite to the rotation direction of the three-phase AC signal.

  According to another preferred embodiment, the filter means may be composed of a first low-pass filter having a predetermined response time constant of the fundamental frequency.

  Further, the filter means includes a second low-pass filter connected in parallel to the first low-pass filter and having a response time constant shorter than a response time constant of the first low-pass filter, and the second low-pass filter. Detecting means for detecting that the output value of the filter becomes a constant value and the constant value continues for a predetermined time or more, and detecting that the constant value continues for a predetermined time or more by the detecting means And an output changing means for changing the output value of the first low-pass filter to the output value of the second low-pass filter.

  A reactive power compensator provided by the second aspect of the present invention is provided between an AC power supply and a power system, and is provided in the power system in order to improve the power factor of AC power supplied from the AC power supply. A reactive power compensator that supplies a compensation current to a flowing load current, comprising: a load current detection circuit that detects the load current; and a compensation current detection circuit that detects the compensation current, the load current detection The circuit and the compensation current detection circuit use the signal extraction device provided by the first aspect of the present invention (Claim 6).

  The reactive power compensator provided by the third aspect of the present invention is provided between an AC power supply and a power system, and provides a reactive power to the power system to stabilize the system voltage. Compensation device comprising: a system voltage detection circuit for detecting the system voltage; and a compensation current detection circuit for detecting the compensation current, wherein the system voltage detection circuit and the compensation current detection circuit include The signal extraction device provided by the first aspect is used (claim 7).

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 is a diagram showing a configuration of a signal extraction device according to the present invention. The signal extraction apparatus 1 is an apparatus for extracting a signal having a desired frequency SuNaru fraction of the alternating current signal having a plurality of frequency components by digital processing. The signal extraction apparatus 1 shown in FIG. 1 receives a three-phase AC signal (U-phase, V-phase, W-phase digital signal) as an AC signal having a plurality of frequency components, and has a desired frequency component to be extracted. As shown, a positive phase component of a fundamental frequency (for example, 50 Hz) is output.

  The signal extraction device 1 includes a fundamental frequency rotation coordinate transformation circuit 2 (hereinafter referred to as “basic frequency transformation circuit 2”) that functions as the “first three-phase / two-phase transformation means” of the present invention, and the present invention. N (n: integer greater than or equal to 2) order harmonic positive phase generation circuit 3 (hereinafter referred to as “n order positive phase generation circuit 3”) and m order (m: 1) functioning as “harmonic generation means”. (Integer) harmonic anti-phase component generation circuit 4 (hereinafter referred to as “m-order anti-phase component generation circuit 4”) and canceling circuit 5 functioning as the “harmonic canceling means” of the present invention. .

  The fundamental frequency conversion circuit 2 performs dq conversion for the positive phase of the fundamental frequency included in the input three-phase AC signal. Note that the three-phase AC signal input to the fundamental frequency conversion circuit 2 is a signal obtained by detecting, for example, the three-phase AC voltage of the system, as described in the prior art. The positive phase component of the n-th order harmonics such as the minute, the third order, the fifth order,. Therefore, the fundamental frequency conversion circuit 2 outputs the dq conversion value (DC signal) for the positive phase of the fundamental frequency, and the output includes the negative phase component of the fundamental frequency, the positive phase component of the nth harmonic, and A dq conversion value (AC signal) such as a reverse phase component of the m-th harmonic is also included.

The n-th order positive phase generation circuit 3 has the same dq conversion value as the dq conversion value (AC signal) for the positive phase of the n-th order harmonic contained in the output of the fundamental frequency conversion circuit 2 from the input three-phase AC signal. (AC signal) is generated. The m-th order anti-phase component generation circuit 4 has the same dq as the dq conversion value (AC signal) of the anti-phase component of the m-order harmonic included in the output of the fundamental frequency conversion circuit 2 from the input three-phase AC signal. A conversion value (AC signal) is generated. In the case of m = 1, m order reverse phase generating circuit 4 is a circuit for generating the same dq conversion value and the dq conversion value of the reverse phase of the basic frequency in the output of the fundamental frequency conversion circuit 2 next, but not for the higher harmonics of the basic frequency, for convenience of explanation, the circuit is also included in the m-th order reversed phase generating circuit 4 for reversed phase of the basic frequency.

  The cancellation circuit 5 includes the basic frequency conversion circuit 2, the n-order positive phase component generation circuit 3, and the d-axis outputs of the m-order negative phase component generation circuit 4, as well as the basic frequency conversion circuit 2, the n-order positive phase component generation circuit 3, and The difference between the q-axis outputs of the m-th order antiphase component generation circuit 4 is calculated, and the positive phase component of the nth harmonic and the negative phase component of the mth harmonic included in the output signal of the fundamental frequency conversion circuit 2 are canceled out. Only the positive phase of the fundamental frequency is output to the subsequent stage.

That is, as shown in FIG. 2, the output of the fundamental frequency conversion circuit 2 includes the negative phase component of the fundamental frequency, the positive phase component of the nth harmonic and the negative phase component of the mth harmonic, as described above. AC components (see f ₁ , f ₂ , and f _{3 in} FIG. 2) generated by performing dq conversion for the fundamental frequency are converted into dq conversion values (see f ₀ (= 0) in FIG. 2) of the fundamental frequency component. They are superimposed (see FIG. 2 (a)). Therefore, in this signal extraction device 1, in the n-th order positive phase component generation circuit 3 and the m-th order negative phase generation circuit 4, the normal phase component of the n-order harmonic and the negative phase component of the m-order harmonic are used for the fundamental frequency. The AC components generated by performing the dq conversion are respectively generated (see FIG. 2B), and the generated AC components are canceled by the cancellation circuit 5 from the output of the basic frequency conversion circuit 2, whereby the fundamental frequency Only the dq conversion value (DC component) for the positive phase is extracted (see FIG. 2C).

  Note that one n-th order positive phase component generation circuit 3 and one m-th order negative phase generation circuit 4 are described, but, for example, when the harmonics are composed of a plurality of orders, circuits corresponding to the orders are respectively provided. Provided. The m-order antiphase component generation circuit 4 includes a circuit corresponding to the antiphase component of the fundamental frequency, for example, m = 1 (primary).

  For example, the signal extraction device 1 is applied to a reactive power compensator or the like for stabilizing system power as will be described later, but the system power has harmonic components unique to the system. The signal extraction device 1 needs to generate them in order to remove the harmonic components unique to the system, and the n-th order positive phase generation circuit 3 and the m-th order negative phase generation circuit 4 have their own harmonics. Provided for each component. For example, a fifth-order, seventh-order, eleventh-order, or thirteen-order normal phase generation circuit or negative phase generation circuit is provided as necessary. A fundamental wave antiphase component generation circuit is also provided.

  As shown in FIG. 3, the basic frequency conversion circuit 2 includes a three-phase / two-phase conversion unit 6 and a dq conversion unit 7. The three-phase / two-phase converter 6 converts a three-phase AC signal (U-phase, V-phase, W-phase digital signal) into a two-phase signal (α, β) in a stationary coordinate system (α axis, β axis). Is. For this conversion, for example, Equation 1 is used.

Here, if the three-phase AC signal (U phase, V phase, W phase) is composed only of the positive phase of the fundamental frequency f ₀ , the three-phase AC signal is U = Asin (ωt), V = Asin (ωt−2π / 3), W = Asin (ωt + 2π / 3). Incidentally, A is shows the amplitude of the three-phase AC signal, the omega angular frequency indicates a ω = 2π · f _0. Further, ωt represents the rotation angle for the fundamental wave positive phase. Substituting these U, V, and W values into Equation 1, the two-phase signal (α, β) can be expressed by Equation 2.

The two-phase signal (α, β) expressed by Equation 2 is input to the dq conversion unit 7. dq converter 7, the two-phase signals (alpha, beta) the converted AC signals in a stationary coordinate system (alpha axis, beta axis) the three-phase alternating current with the angular frequency ω that has the same frequency as basic frequency It is converted into a signal of a rotating coordinate system (d axis, q axis) that rotates in the same rotation direction (for example, counterclockwise) as the signal. For this conversion, Equation 3 is used.

  A signal expressed in the rotating coordinate system (d-axis, q-axis) can be expressed by Expression 4 using Expression 3.

  Thus, the dq conversion processing is performed by the fundamental frequency conversion circuit 2, whereby the positive phase component of the fundamental frequency of the three-phase AC signal can be converted into the d-axis and q-axis DC components.

  The three-phase AC signal (U phase, V phase, W phase) input to the fundamental frequency conversion circuit 2 includes components other than the positive phase component of the fundamental frequency (the negative phase component of the fundamental frequency and the nth harmonic). Of the positive phase or the reverse phase of the m-th harmonic), the fundamental frequency conversion circuit 2 obtains the d-axis obtained by applying the above formulas 1 to 3 to these components. The q-axis component (AC component) is also output.

  That is, when the positive phase component of the nth harmonic is included, the positive phase component of the nth harmonic is U = Asin (nωt), V = Asin (nωt−2π / 3), W = Asin (nωt + 2π). Therefore, when these U, V, and W values are applied to Equation 1 and Equation 3, the αβ conversion value becomes Equation 5 and the dq conversion value becomes Equation 6. Therefore, the positive phase component of the nth harmonic is output from the fundamental frequency conversion circuit 2 as an AC signal having the same frequency as the (n−1) th harmonic (n is an integer of 2 or more).

  In addition, when the antiphase component of the mth harmonic is included, the antiphase component of the mth harmonic is U = Asin (mωt), V = Asin (mωt + 2π / 3), W = Asin (mωt−2π). Therefore, when these U, V, and W values are applied to Equation 1 and Equation 3, the αβ conversion value becomes Equation 7 and the dq conversion value becomes Equation 8. Therefore, the negative phase component of the m-order harmonic is output from the fundamental frequency conversion circuit 2 as an AC signal having the same frequency as the (m + 1) -order harmonic (m is an integer of 1 or more).

  If m = 1 in Equations 7 and 8, the αβ conversion value for the negative phase of the fundamental frequency and the dq conversion value for the negative phase of the fundamental frequency output from the basic frequency conversion circuit 2 are obtained. 10 and so on. Therefore, the negative phase component of the fundamental frequency is output from the fundamental frequency conversion circuit 2 as an AC signal having a frequency twice the fundamental frequency.

  Returning to FIG. 1, the n-order positive phase component generation circuit 3 includes an n-order harmonic positive phase component rotation coordinate conversion circuit 11 (hereinafter referred to as “n-order positive phase component conversion circuit 11”) and a first low-pass filter 12. And a second low-pass filter 13 and an n-th order positive phase sub-conversion circuit 14.

  The nth-order positive phase conversion circuit 11 performs dq conversion processing for the positive phase of the nth-order harmonic, and has the same configuration as the basic frequency conversion circuit 2 described above. A phase converter 6 and a dq converter 7 are included (see FIG. 3).

In the three-phase / two-phase conversion unit 6 in the n-order positive phase component conversion circuit 11, the positive phase component of the n-order harmonic included in the three-phase AC signal is converted into a two-phase signal (α, β) that is a stationary coordinate system. Is done. Since the positive phase component of the n-th harmonic contained in the three-phase AC signal is expressed by U = Asin (nωt), V = Asin (nωt−2π / 3), W = Asin (nωt + 2π / 3), these When the values of U, V, and W are applied to Equation 1, the two-phase signal (α, β) is expressed by α = Asin (nωt) and β = −Acos (nωt) as shown in Equation 5 above. It becomes.

In the dq converter 7, the two-phase signal (α, β) = (Asin (nωt), −Acos (nωt)) is the same as the three-phase AC signal at the angular frequency of nω in the stationary coordinate system (α axis, β axis). To a rotation coordinate system (d-axis, q-axis) signal that is rotated in the rotation direction (for example, counterclockwise). In this conversion, the following formula 11 is used instead of the formula 3, and the dq conversion value is the same as the above formula 4. That is, d = 0, q = −A, and the positive phase component of the n-order harmonic of the three-phase AC signal is converted from the n-order positive phase component conversion circuit 11 to the DC component of the d-axis and the q-axis and output. The

  On the other hand, since the input signal of the n-th order positive phase conversion circuit 11 is the same as the input signal of the fundamental frequency conversion circuit 2, a signal other than the positive phase component of the nth harmonic (the positive frequency of the fundamental frequency) is included in the input signal. Phase component, anti-phase component and anti-phase component of s-order harmonic (s ≠ n), etc.). The d-axis and q-axis components (AC components) obtained by applying Formula 11 are also output.

  The positive phase component having a frequency different from that of the nth order harmonic input to the nth order positive phase conversion circuit 11 is expressed as U = Asin (sωt), V = Asin (sωt−2π / 3), W = Asin (sωt + 2π / 3). ) (S ≠ n) When these U, V, and W values are applied to Equation 1 and Equation 11, the αβ conversion value becomes Equation 12, and the dq conversion value becomes Equation 13. .

  Therefore, the positive phase component having a frequency different from that of the nth order harmonic is output from the nth order positive phase conversion circuit 11 as an AC signal having the same frequency as the (s−n) th order harmonic. The dq conversion value of the positive phase of the fundamental frequency input to the n-th order positive phase conversion circuit 11 can be obtained by setting s = 1 in Equation 13, d = −Asin {(n−1) ωt} , Q = −Acos {(n−1) ωt}.

Further, n-th harmonic to be input to the n TsugiTadashisho partial conversion circuit 11 and the same or different frequency reverse phase (in this frequency are also included basic frequency), U = Asin (pωt) , V = Asin (pωt + 2π / 3), W = Asin (pωt−2π / 3) (integer of p = 1, 2,...), These U, V, and W values are applied to Equation 1 and Equation 11. Then, the αβ conversion value is expressed by Equation 14, and the dq conversion value is expressed by Equation 15.

  Therefore, the negative phase component having the same or different frequency as the nth harmonic is output from the nth positive phase conversion circuit 11 as an AC signal having the same frequency as the (p + n) th harmonic. Note that the dq conversion value of the negative phase of the fundamental frequency input to the n-th order positive phase conversion circuit 11 can be obtained by setting p = 1 in Equation 15, and d = Asin {(n + 1) ωt}, q = Acos {(n + 1) ωt}.

  A first low-pass filter 12 is connected to the d-axis output of the n-th order positive phase conversion circuit 11, and a second low-pass filter 13 is connected to the q-axis output of the n-th order positive phase conversion circuit 11. As described above, since the dq conversion value of the signal other than the positive phase component of the nth order harmonic is output as an AC signal to the output of the nth order positive phase conversion circuit 11, the first low pass filter 12 and the first low pass filter 12 The filter 13 is provided to remove the AC component from the output of the n-th order positive phase conversion circuit 11.

  The 1st low-pass filter 12 and the 2nd low-pass filter 13 are comprised by the digital filter (for example, average moving filter). The first low-pass filter 12 receives the d-axis output of the n-th order positive phase conversion circuit 11 and the second low-pass filter 13 receives the q-axis output of the n-th order positive phase conversion circuit 11. The first low-pass filter 12 removes the AC component of, for example, Asin {(s−n) ωt} and Asin {(p + n) ωt} of the d-axis component output from the n-th order positive phase conversion circuit 11. Further, the AC component of the q-axis component output from the n-th order positive phase conversion circuit 11, for example, the AC component of −Acos {(s−n) ωt} or Acos {(p + n) ωt} is removed by the second low-pass filter 13. Is done. The outputs of the first and second low-pass filters 12 and 13 are connected to an n-th order positive phase sub-conversion circuit 14.

  The n-th order positive phase sub-conversion circuit 14 rotates the coordinates of the dq conversion value for the positive phase of the n-order harmonics output from the first low-pass filter 12 and the second low-pass filter 13 from the fundamental frequency conversion circuit 2. The output is converted into a dq conversion value (AC signal) that is the same as the dq conversion value (AC signal) for the positive phase of the n-th harmonic output.

The dq conversion value output from the fundamental frequency conversion circuit 2 is a rotation coordinate system that rotates a stationary αβ coordinate system counterclockwise at an angular frequency of ω (this rotation coordinate system is the “first coordinate of the present invention”). It corresponds to “orthogonal coordinate system”). On the other hand, the dq conversion value output from the n-th order positive phase component conversion circuit 11 is a rotating coordinate system that rotates a stationary αβ coordinate system counterclockwise at an angular frequency of nω (this rotating coordinate system is the present invention). (Corresponding to “second orthogonal coordinate system”). The rotation coordinate system of the dq conversion value output from the nth-order positive phase conversion circuit 11 has an angular frequency of (n−1) ω with respect to the rotation coordinate system of the dq conversion value output from the basic frequency conversion circuit 2. Since it rotates counterclockwise, the dq conversion value for the positive phase of the nth order harmonic output from the nth order positive phase conversion circuit 11 is rotated clockwise at an angular frequency of (n−1) ω. If converted into the rotating coordinate system, the dq conversion value in the rotating coordinate system of the fundamental frequency converting circuit 2 is obtained.

  Accordingly, in the n-th order positive phase sub-conversion circuit 14, the dq conversion value of the positive phase of the n-order harmonics output from the first low-pass filter 12 and the second low-pass filter 13 is expressed by the following equation 16 as the fundamental frequency conversion circuit 2. Are converted into values (d ′, q ′) in the rotating coordinate system.

  When only the dq conversion value for the positive phase of the n-th harmonic is output from the first low-pass filter 12 and the second low-pass filter 13, d = 0 and q = −A. , The converted values d ′ and q ′ are d ′ = Asin {(n−1) ωt} and q ′ = − Acos {(n−1) ωt}. The converted values d ′ and q ′ coincide with the dq converted values for the positive phase of the nth-order harmonic output from the fundamental frequency converting circuit 2 shown in Equation 6. The conversion values d ′ and q ′ output from the n-th order positive phase sub-conversion circuit 14 are input to the cancellation circuit 5.

The m-th order anti-phase component generation circuit 4 includes an m-order harmonic anti-phase component rotation coordinate conversion circuit 15 (hereinafter referred to as “m-order anti- phase component conversion circuit 15”), a third low-pass filter 16, and a fourth low-pass filter. The filter 17 and the m-th order antiphase sub-conversion circuit 18 are configured.

The m-th order anti-phase component conversion circuit 15 performs dq conversion processing for the anti-phase component of the m-th order harmonic, and has the same configuration as that of the basic frequency conversion circuit 2 as in the case of the n-th order positive phase conversion circuit 11. And includes a three-phase / two-phase converter 6 and a dq converter 7 (see FIG. 3).

  In the three-phase / two-phase converter 6 in the m-th order anti-phase component conversion circuit 15, the anti-phase component of the m-order harmonic contained in the three-phase AC signal is converted into a two-phase signal (α, β) that is a stationary coordinate system. Is done. Since the reverse phase components of the m-order harmonics included in the three-phase AC signal are represented by U = Asin (mωt), V = Asin (mωt + 2π / 3), and W = Asin (mωt−2π / 3). When the values of U, V, and W are applied to the above equation 1, the two-phase signal (α, β) is expressed as α = Asin (mωt), α = Acos (mωt) as shown in the equation 7. Become.

In the dq converter 7, the two-phase signal (α, β) = (Asin (mωt), Acos (mωt)) is the same as the three-phase AC signal in the stationary coordinate system (α axis, β axis) at the angular frequency of mω. It is converted into a signal of a rotating coordinate system (d axis, q axis) that rotates in the rotation direction (clockwise). In this conversion, the following Expression 17 is used instead of Expression 3, and the dq conversion values are d = 0 and q = A. Therefore, the reverse phase component of the m-order harmonic of the three-phase AC signal is also converted from the m-order reverse phase conversion circuit 15 into the d-axis and q-axis DC components and output.

  On the other hand, since the input signal of the m-th order anti-phase component conversion circuit 15 is also the same as the input signal of the fundamental frequency conversion circuit 2, the input signal is a signal other than the anti-phase component of the m-order harmonic (the positive phase of the fundamental frequency). And the negative phase component and the positive phase component of the k-th order harmonic (k ≠ m) are included. D-axis and q-axis components (AC components) obtained by applying 17 are also output.

m following reverse phase is inputted to the converting circuit 15 m harmonic same Wakashi Ku different frequencies positive phase of (the frequency are also included basic frequency), U = Asin (kωt) , V = Asin (kωt−2π / 3), W = Asin (kωt + 2π / 3) (k = 1, 2,...), And applying these U, V, and W values to Equation 1 and Equation 17, The αβ conversion value is the same as Equation 18, and the dq conversion value is as Equation 19.

Therefore, the positive phase component having the same or different frequency as the m-order harmonic is output from the m-order anti-phase component conversion circuit 15 as an AC signal having the same frequency as the (m + k) -order harmonic. Note that the dq conversion value of the positive phase of the fundamental frequency input to the m-th order anti-phase conversion circuit 15 can be obtained by setting k = 1 in Equation 19 , d = Asin {(m + 1) ωt}, q = −Acos {(m + 1) ωt}.

  Further, the negative phase components having a frequency different from that of the m-th order harmonic input to the m-order negative phase conversion circuit 15 are U = Asin (hωt), V = Asin (hωt + 2π / 3), W = Asin (hωt−2π / 3) When represented by (h ≠ m) and applying these U, V, and W values to Equation 1 and Equation 17, the αβ conversion value becomes Equation 20 and the dq conversion value becomes Equation 21. .

Therefore, the negative phase component having a frequency different from that of the m-th harmonic is output from the m-order negative phase conversion circuit 15 as an AC signal having the same frequency as the (m−h) -order harmonic. Note that the dq conversion value of the negative phase component of the fundamental frequency input to the m-th order negative phase conversion circuit 15 can be obtained by setting h = 1 in Equation 21, d = Asin {(m−1) ωt}, q = Acos {(m−1) ωt}.

  A third low-pass filter 16 is connected to the d-axis output of the m-th order anti-phase component conversion circuit 15, and a fourth low-pass filter 17 is connected to the q-axis output of the m-th order anti-phase component conversion circuit 15. As described above, since the dq conversion value of the signal other than the negative phase component of the m-th harmonic is also output as the AC signal to the output of the m-order negative phase conversion circuit 15, the third low-pass filter 16 and the fourth low-pass filter 16 The filter 17 is provided to remove the AC component from the output of the m-th order antiphase component conversion circuit 15.

The third low-pass filter 16 and the fourth low-pass filter 17 are configured by digital filters in the same manner as the first and second low-pass filters 12 and 13. The third low-pass filter 16 receives the d-axis output of the m-th order anti-phase component conversion circuit 15 and the fourth low-pass filter 17 receives the q-axis output of the m-order anti-phase component conversion circuit 15. The third low-pass filter 16 removes AC components of, for example, Asin {(m + k) ωt} and Asin {(m−h) ωt} of the d-axis component output from the m-th order antiphase component conversion circuit 15. Further, the fourth low-pass filter 17 removes the AC component of the q-axis component output from the m- order antiphase component conversion circuit 15, for example, -Acos {(m + k) ωt} or Acos {(m−h) ωt}. Is done. The outputs of the third and fourth low-pass filters 16 and 17 are connected to an m-th order antiphase sub-conversion circuit 18.

The m-th order anti-phase component sub-conversion circuit 18 rotates the coordinates of the d-q conversion value of the anti- phase component of the m-order harmonics output from the third low-pass filter 16 and the fourth low-pass filter 17 from the fundamental frequency conversion circuit 2. The output is converted into a dq conversion value (AC signal) that is the same as the dq conversion value (AC signal) of the reversed phase of the m-th harmonic output.

The dq conversion value output from the m-th order antiphase sub-conversion circuit 18 is a rotating coordinate system that rotates a stationary αβ coordinate system clockwise at an angular frequency of mω (this rotating coordinate system is the “ Equivalent to the “second orthogonal coordinate system”). Since the rotation coordinate system of the dq conversion value output from the fundamental frequency conversion circuit 2 rotates counterclockwise at the angular frequency of ω , the rotation of the dq conversion value output from the m-order antiphase component sub-conversion circuit 18 is performed. The coordinate system rotates clockwise at an angular frequency of (m + 1) ω with respect to the rotating coordinate system of the dq conversion value output from the basic frequency conversion circuit 2. Therefore, if the dq conversion value of the anti-phase component of the m- order harmonic output from the m-order anti-phase component sub-conversion circuit 18 is converted into a rotating coordinate system that rotates counterclockwise at an angular frequency of (m + 1) ω, This is the dq conversion value in the rotating coordinate system of the basic frequency conversion circuit 2.

  In the m-order anti-phase component sub-conversion circuit 18, the dq conversion value of the anti-phase component of the m-order harmonics output from the third low-pass filter 16 and the fourth low-pass filter 17 is the rotation of the fundamental frequency conversion circuit 2 according to the following Equation 22. It is converted into a value (d ′, q ′) in the coordinate system.

  Since d = 0 and q = A in the state where only the dq conversion value corresponding to the reverse phase of the m-th harmonic is output from the third low-pass filter 16 and the fourth low-pass filter 17, these values are expressed by Equation 22. If converted, the converted values d ′ and q ′ are d ′ = Asin {(m + 1) ωt} and q ′ = Acos {(m + 1) ωt}. The converted values d ′ and q ′ coincide with the dq converted value of the antiphase component of the m-order harmonic output from the fundamental frequency converting circuit 2 expressed by Equation 8. The conversion values d ′ and q ′ output from the m-th order negative phase sub-conversion circuit 18 are input to the cancellation circuit 5.

  The cancellation circuit 5 includes a first arithmetic circuit 19 that calculates a difference between the d-axis outputs of the fundamental frequency conversion circuit 2 and the n-th order positive phase generation circuit 3, and a first arithmetic circuit 19 and an m-th order negative phase generation circuit 4. A second arithmetic circuit 20 that calculates the difference between the d-axis outputs of the first, a third arithmetic circuit 21 that calculates a difference between the q-axis outputs of the fundamental frequency conversion circuit 2 and the n-th order positive phase generation circuit 3, and a third The fourth arithmetic circuit 22 calculates the difference between the q-axis outputs of the arithmetic circuit 21 and the m-th order negative phase generation circuit 4.

  That is, in the first arithmetic circuit 19, the n-th order positive phase generation circuit for the fundamental frequency component dq-transformed by the fundamental frequency conversion circuit 2 and the d-axis portion of the positive phase of the nth order harmonic superimposed thereon. The d-axis portion of the positive phase component of the nth harmonic generated in 3 is canceled. In the second arithmetic circuit 20, the d-axis component of the antiphase component of the m-order harmonic generated by the m-order antiphase component generation circuit 4 is canceled with respect to the output of the first arithmetic circuit 19. Therefore, only the d-axis component (direct current) corresponding to the positive phase of the fundamental frequency is output from the second arithmetic circuit 20.

Similarly, the third arithmetic circuit 21 generates the n- th order positive phase component for the q-axis portion of the fundamental frequency component dq-transformed by the fundamental frequency conversion circuit 2 and the positive phase component of the n- order harmonic superimposed thereon. The q-axis portion for the positive phase of the nth-order harmonic generated by the circuit 3 is canceled. In the fourth arithmetic circuit 22, the q-axis portion of the antiphase component of the m-order harmonic generated by the m-order antiphase component generation circuit 4 is canceled with respect to the output of the third arithmetic circuit 21. Therefore, only the q-axis component (direct current) corresponding to the positive phase of the fundamental frequency is output from the fourth arithmetic circuit 22.

  According to the above configuration, a signal (dq-converted alternating current) obtained by dq-converting the positive-phase component of the n-th harmonic (n; an integer of 2 or more) included in the three-phase alternating-current signal by the fundamental frequency conversion circuit 2 is output. Component) is generated by the n-th order positive phase generation circuit 3. Further, the same signal as the signal (dq-converted AC component) output by dq-converting m-order harmonics (m; an integer of 1 or 2 or more) included in the three-phase AC signal by the fundamental frequency conversion circuit 2 Is generated by the m-th order negative phase generation circuit 4.

Then, a signal (the same as the fundamental frequency) of the positive phase component of the nth order harmonic generated by the nth order positive phase generation circuit 3 and the negative phase component of the mth order harmonic generated by the mth order negative phase generation circuit 4 (An AC signal on the dq coordinate system that rotates counterclockwise at an angular frequency having a frequency of 2) is input to the cancellation circuit 5 and the difference from the output of the fundamental frequency conversion circuit 2 is calculated. Since the output of the fundamental frequency conversion circuit 2 includes the AC component on the dq coordinate system for the positive phase component of the nth harmonic and the antiphase component of the mth harmonic in addition to the positive phase component of the fundamental frequency. These AC components are canceled out by the positive phase component of the nth harmonic and the negative phase signal of the mth harmonic generated by the nth order positive phase generation circuit 3 and the mth order negative phase generation circuit 4. . As a result, only the dq conversion value (DC signal on the dq coordinate system) for the positive phase of the fundamental frequency is output from the cancellation circuit 5.

  As described above, in the signal extraction device 1 of the present embodiment, when extracting the positive phase component of the fundamental frequency, unnecessary n-order harmonic components are removed from the moving average filter, FIR filter, IIR filter, and the like as in the conventional configuration. Rather than removing by using the moving average calculation, a signal (basic frequency) other than the positive phase component of the basic frequency included in the output when the positive phase component of the basic frequency is dq converted by the basic frequency conversion circuit 2 The same signal as the dq conversion value (AC signal) of the negative phase component, the positive phase component of the nth harmonic or the negative phase component of the mth harmonic) A method is used in which the signal is separately generated by the phase generation circuit 4 and the separately generated signal is subtracted from the output of the basic frequency conversion circuit 2.

  According to this method, in synchronization with the dq conversion processing of the fundamental frequency conversion circuit 2, the fundamental frequency conversion of signals other than the positive phase component of the fundamental frequency is performed by the n-th order positive phase generation circuit 3 and the m-order negative phase generation circuit 4. A process for generating the same signal as the dq conversion value in the circuit 2 is performed, and the dq conversion value (AC signal) of the signal other than the positive phase component of the fundamental frequency included in the output of the fundamental frequency conversion circuit 2 is canceled with the signal. Since the operation to be performed is performed in real time, the positive phase component of the fundamental frequency can be quickly extracted. That is, when a low-pass filter composed of a conventional moving average filter is used, a time lag of one period or more of the frequency occurs although the filtering effect of the frequency to be removed occurs. In the method of this embodiment, the time lag is There is almost no signal responsiveness.

  FIG. 4 is a diagram illustrating a simulation input waveform of a three-phase AC signal in the signal extraction device 1. The figure shows the positive phase component (three-phase alternating current) of the fundamental frequency (frequency 50 Hz) whose amplitude is “1” at time 0 in the state in which the second harmonic (amplitude A = 0.1, frequency 100 Hz) is always input. ) Is shown. That is, as the input signal to the signal extraction device 1, the positive phase component (three-phase alternating current) of the fundamental frequency of amplitude “1.0” obtained by superimposing the second harmonic of amplitude “0.1” at time 0 is input. The signal waveform when it is done is shown.

  FIG. 5 is a diagram showing a simulation output waveform in the signal extraction apparatus 1. In the figure, a waveform indicated by a solid line indicates an output waveform from the signal extraction device 1 according to the present embodiment, and a one-dot chain line indicates a low-pass filter composed of a conventional moving average filter (hereinafter referred to as “moving average low-pass” as necessary). The output waveform is shown when the second harmonic is removed using a filter.

  As shown in the figure, in the conventional configuration, when the positive phase component of the fundamental frequency on which the second-order harmonic is superimposed at time 0 is input, the second-order harmonic dq conversion value (AC component) is thereafter input. On the other hand, since the moving average calculation is performed, the amplitude of the dq conversion value is gradually reduced, and a complete filtering effect is produced from the time when one period (200 msec) of the second harmonic has elapsed, and the amplitude becomes zero. Accordingly, the dq conversion value for the positive phase of the fundamental frequency on which the second harmonic is superimposed is only the dq conversion value (DC component) of the positive phase component DC of the fundamental frequency from time 0.02.

  On the other hand, in the signal extraction device 1 according to the present embodiment, the dq conversion value of the second harmonic is started at the same time as the dq conversion processing for the positive phase of the fundamental frequency on which the second harmonic is superimposed at time 0. Since the (alternating current component) canceling process is performed, the dq conversion value for the positive phase of the fundamental frequency on which the secondary harmonics are superimposed is the dq conversion value (DC component) of the positive phase component DC of the fundamental frequency from time zero. It can be seen that there is no time lag of 200 msec as in the conventional configuration.

In FIG. 5, the output waveform of the signal extraction device 1 slightly fluctuates from time 0 to near time 0.04. This is because the first and second low-pass filters of the n-th order positive phase generation circuit 3. Since the moving average low-pass filters are used as the third and fourth low-pass filters 16 and 17 of the 12, 13 and m-th order anti-phase component generation circuit 4, n in the period of time lag until the filtering effect of these low-pass filters occurs. This is because a component other than the same signal as the dq conversion value in the fundamental frequency conversion circuit 2 of the second harmonic is output to the output from the second-order positive phase generation circuit 3 or the m-th order negative phase generation circuit 4. .

  By the way, since the n-order harmonic contained in the three-phase AC signal is a harmonic with respect to the fundamental frequency, if the fundamental frequency fluctuates due to some factor, the n-order harmonic will fluctuate accordingly. . Accordingly, when the positive phase component of the fundamental frequency input to the n-th order positive phase component generation circuit 3 and the m-th order negative phase component generation circuit 4 varies, the basic component superimposed on the positive phase component of the fundamental frequency according to the variation. The negative phase component of the frequency, the positive phase component of the nth harmonic, and the negative phase component of the mth harmonic also vary. Needless to say, the signal itself superimposed on the positive phase of the fundamental frequency fluctuates.

  As described above, the n-th order positive phase component generation circuit 3 includes the first and second moving average low-pass filters for removing components (AC components) obtained by dq conversion of signals other than the positive phase components of the n-th order harmonics. Although the second low-pass filters 12 and 13 are provided, signals other than the positive-phase component of the n-th order harmonic input to the n-order positive-phase component generation circuit 3 fluctuate in accordance with the fluctuation of the fundamental frequency for the positive phase. Even in this case, in order to effectively remove the signal, it is necessary to set the response time constants of the first and second low-pass filters 12 and 13 to be relatively long. The same applies to the third and fourth low-pass filters 16 and 17 including the moving average low-pass filter of the m-th order antiphase component generation circuit 4.

  However, if the response time constants of the first and second low-pass filters 12 and 13 of the n-th order positive phase generation circuit 3 are fixed to a long response time constant, for example, the response time constants of the first and second low-pass filters 12 and 13 are used. When the fluctuation of the positive phase of the fundamental frequency converges during this period, and even if a sufficient filtering effect is obtained at that time, the filtering effect cannot be obtained until the fixed response time constant period elapses Occurs.

For example, if the response time constants of the first and second low-pass filters 12 and 13 are set to 10 periods (200 msec) of the basic frequency, the frequency range to be removed by the first and second low-pass filters 12 and 13 and the attenuation effect are improved. However, a response time of 200 msec is required until a sufficient filtering effect occurs. Therefore, after the moving average calculation process is started by the first and second low-pass filters 12 and 13, for example, the fluctuation of the fundamental frequency converges at 100 msec, and the response time constants of the first and second low-pass filters 12 and 13 are If it is 100 msec , even if the filtering effect is sufficiently produced at the time when 100 msec has passed, the filtering effect is not sufficiently produced unless 200 msec has passed from the first and second low-pass filters 12 and 13. . Such an inconvenience applies to the third and fourth low-pass filters 16 and 17 of the m-th order antiphase component generation circuit 4 as well.

  Therefore, in the present embodiment, the first to fourth low-pass filters 12, 13, 16, and 17 are configured as follows in order to eliminate the above-described inconvenience.

  FIG. 6 is a diagram illustrating an internal configuration of the first to fourth low-pass filters 12, 13, 16, and 17. The low-pass filters 12, 13, 16, and 17 have the same internal configuration. The first to fourth low-pass filters 12, 13, 16, and 17 are configured by digital low-pass filters that are so-called moving average filters, and the internal configuration shown in FIG. 6 does not show a specific hardware configuration. Rather, it shows a software concept when digital arithmetic processing is performed.

Each of the low-pass filters 12, 13, 16, and 17 includes a low-pass filter (hereinafter referred to as “low-pass filter (large)”) 23 having a relatively large response time constant and a low-pass filter (hereinafter referred to as “low-pass filter (large)”) having a relatively small response time constant. The low-pass filter (small) ”) 24 and a fluctuation detection unit 25 for detecting that the fluctuation of the three-phase AC signal has converged. A low-pass filter (large) 23, functions as a "first B-pass filter" of the present invention, a low-pass filter (small) 24 functions as a "second B-pass filter" of the present invention. Further, the fluctuation detecting unit 25 functions as “detecting means” and “output changing means” of the present invention.

  If the response time constant of the low-pass filter (large) 23 is at least one period (20 msec) of the fundamental frequency, frequencies above the fundamental frequency can be removed, but the attenuation rate of the low-pass filter (large) 23 is increased. Therefore, for example, it is set to 200 msec. The response time constant of the low-pass filter (small) 24 is, for example, 10 msec. The low-pass filter (large) 23 has a data area 23 a for storing data, and the low-pass filter (small) 24 is a data area in which the number of stored data is smaller than the data area 23 a of the low-pass filter (large) 23. 24a.

  In the first to fourth low-pass filters 12, 13, 16, and 17, the output value of the low-pass filter (large) 23 is normally used in order to improve response characteristics when the input three-phase AC signal fluctuates. Yes. When the fluctuation detector 25 detects that the three-phase AC signal fluctuates and the fluctuation has converged, the output value of the low-pass filter (small) 24 is used as the output value of the low-pass filter (large) 23. Yes.

FIG. 7 is a diagram showing data transition states in the data regions 23a and 24a of the low-pass filter (large) 23 and the low-pass filter (small) 24 and the moving average value associated therewith. FIG. 8 shows the low-pass filter (large). 23 is a flowchart showing the operation of the low-pass filter 23 and the low-pass filter (small) 24.

  Here, it is assumed that the low-pass filter (small) 24 has a data area 24a for storing five data, and the low-pass filter (large) 23 has a data area 23a for storing 50 data (see FIG. 7 (a)). When the sampling period is τ, the response time constant of the low-pass filter (small) 24 is represented by 5 × τ, and the response time constant of the low-pass filter (large) 23 is represented by 50 × τ.

The low-pass filter (small) 24 calculates the average of five data in the data area 24a every sampling time, and the low-pass filter (large) 23 calculates the average of 50 data in the data area 23a . It is assumed that data “0” is stored in the data areas 23a and 24a in the initial state. Therefore, the moving average value in the initial state of both the low-pass filter (small) 24 and the low-pass filter (large) 23 is “0” (see FIG. 7A). In FIG. 7, data input as d-axis output and q-axis output from the n-th order positive phase conversion circuit 11 and the m-th order negative phase conversion circuit 15 is indicated by “1”.

  Referring to the flowchart of FIG. 8, when d-axis output data and q-axis output data from the n-th order positive phase conversion circuit 11 and the m-th order negative phase conversion circuit 15 are input, the low-pass filter (large) 23 is The data is stored in the data area 23a (S1). The low-pass filter (small) 24 also stores the data in the data area 24a (S2).

  Next, filtering is performed in the low-pass filter (small) 24 and the low-pass filter (large) 23 (S3). Specifically, moving average values in the low-pass filter (small) 24 and the low-pass filter (large) 23 are calculated. That is, in the first sampling, as shown in FIG. 7 (b), the first region (the numbers described in the upper part of each region (hereinafter referred to as the numbers below)) of the low-pass filter (small) 24 and the low-pass filter (large) 23. (Referred to as “region number”) (see 0)), if “1” is stored, the moving average value of the low-pass filter (small) 24 becomes 1/5 = 0.2, and the moving average of the low-pass filter (large) 23 The value is 1/50 = 0.02.

  FIG. 7C shows a case where data is stored at the second sampling. In this case, if “1” is stored in each second area (refer to area number 1) of the data areas 24a and 23a of the low-pass filter (small) 24 and the low-pass filter (large) 23 in the second sampling, the data Since “1” is two, the moving average value of the low-pass filter (small) 24 is 2/5 = 0.4, and the moving average value of the low-pass filter (large) 23 is 2/50 = 0.04. .

  Thereafter, sampling is performed sequentially. As shown in FIG. 7 (d), in the fifth sampling, the fifth regions (regions) of the data regions 24a and 23a of the low-pass filter (small) 24 and the low-pass filter (large) 23 are obtained. When “1” is stored in the number 4), the data “1” in the first to fifth areas (see lowercase letters 0 to 4) becomes five, so the moving average value of the low-pass filter (small) 24 is 5/5 = 1, and the moving average value of the low-pass filter (large) 23 is 5/50 = 0.1. That is, the low-pass filter (small) 24 outputs a correct filtering value from the fifth sampling.

  As shown in FIG. 7E, since the data is stored in the entire data area 24a of the low pass filter (small) 24 at the sixth sampling, the data “1” at the sixth sampling is stored in the data area 24a. In the first area (see area number 0). In the low-pass filter (large) 23, data “1” is stored in the sixth area (see area number 5) of the data area 23a. The moving average value of the low-pass filter (small) 24 at this time remains 5/5 = 1, and the moving average value of the low-pass filter (large) 23 is 6/50 = 0.12.

  Next, the previous filtering result of the low-pass filter (small) 24 (moving average value at the first to fifth sampling) and the current filtering result of the low-pass filter (small) 24 (moving average value at the second to sixth sampling) are obtained. It is determined whether or not they are equal (S4).

  When the previous filtering result of the low-pass filter (small) 24 is equal to the current filtering result (S4: YES), the convergence time for detecting whether or not the fluctuations of the fundamental frequency and the n-th harmonic have converged Measurement is started or continued (S5).

  That is, as shown in FIG. 7E, when “1” is stored in the first area (see area number 0) of the data area 24a of the low-pass filter (small) 24 at the time of data input at the sixth sampling, In the low-pass filter (small) 24, since the previous filtering result and the current filtering result are equal, measurement of the convergence time is started.

  On the other hand, when the previous filtering result of the low-pass filter (small) 24 and the current filtering result are not equal (S4: NO), the measurement value of the convergence time is reset to “0” (S6). In this case, it indicates that the input data is not continuously the same data, that is, that the fundamental frequency and the nth harmonic have changed.

  As shown in FIG. 7 (f), “1” continues to the second to fourth areas (refer to area numbers 1 to 3) of the data area 24 a of the low-pass filter (small) 24 until the data is input at the ninth sampling. Is stored, the previous filtering result and the current filtering result in the low-pass filter (small) 24 are kept equal, and the convergence time measurement is continued.

  Thereafter, it is determined whether or not the measured value of the convergence time is equal to the response time constant of the low-pass filter (small) 24 (S7), and the measured value of the convergence time is equal to the response time constant of the low-pass filter (small) 24. If this is the case (S7: YES), the entire data area 23a of the low-pass filter (large) 23 is changed to the moving average value of the low-pass filter (small) 24 (S8).

  That is, as shown in FIG. 7G, when the data input at the 10th sampling is “1”, the convergence time is equal to the response time constant of the low-pass filter (small) 24. The entire data area 23 a is replaced with “1” which is the moving average value of the low-pass filter (small) 24.

  When the data area 23a of the low-pass filter (large) 23 is all changed to the moving average value of the low-pass filter (small) 24 at step S8, the convergence time measurement value is reset to “0” at step S6, or step S7 When the convergence time is not equal to the response time constant of the low-pass filter (small) 24 (S7: NO), the result of filtering by the low-pass filter (large) 23, that is, the moving average value of the low-pass filter (large) 23 is output. (S9).

FIG. 9 is a diagram illustrating a simulation result of the q-axis output when the moving average value of the low-pass filter (small) 24 is replaced with the moving average value of the low-pass filter (large) 23. In FIG. 9, for convenience of explanation, only the signal relating to the q-axis is shown, the two-dot chain line is the output value of the low-pass filter (small), the dotted line is the output value of the low-pass filter ( large ) (when the output value is not switched), The solid line indicates the output value of the mth-order reversed-phase sub-conversion circuit 18, the alternate long and short dash line indicates the output value of the fundamental frequency conversion circuit 2 (for the positive phase of the fundamental frequency), and the lower solid line indicates the output value of the cancellation circuit 5.

  According to FIG. 9, fluctuation occurs at time “0 msec”, and the moving average value of the low-pass filter (small) 24 continues at a constant value during the period “20 to 40 msec” (see FIG. 9A). Assuming that the fluctuation has converged, the moving average value of the low-pass filter (small) 24 is replaced with the moving average value of the low-pass filter (large) 23 after the time “40 msec” (see a in FIG. 9). In this way, the output of the cancellation circuit 5 (see the lower solid line) was oscillated in the period “0 to 40 msec” (AC component not filtered), but the oscillation was suppressed at the time “40 msec”. Only the output “−1” (DC component of the dq conversion value) is output.

  As described above, when the measurement value of the convergence time becomes equal to the response time constant of the low-pass filter (small) 24, that is, when it is detected that the fluctuation of the fundamental frequency and the n-th harmonic has converged, the low-pass filter (small). The moving average value of 24 is replaced with the output of the low-pass filter (large) 23. Thereby, the detection of the dq conversion value of only the positive phase component and the negative phase component of the nth order harmonic in the nth order positive phase component generation circuit 3 and the mth order negative phase generation circuit 4 is performed. It can be performed at an appropriate speed according to the period of variation.

  10 and 11 are diagrams showing the configuration of a power conversion system when the signal extraction device 1 according to the present invention is applied to a reactive power compensation device. The reactive power compensator includes, for example, a type that detects a load current and a type that detects a system voltage. FIG. 10 shows a type that detects a load current in the reactive power compensator. This power conversion system is roughly configured by a system power supply 31, a power distribution system 32, and a reactive power compensator 33.

  The system power supply 31 is composed of, for example, a three-phase AC power supply. A wiring system 32 is connected to the system power supply 31, and a resistance component 34 and an impedance component 35 are provided in the wiring system 32. Further, the reactive power compensator 33 for improving the power factor of the system power is connected to the wiring system 32. The reactive power compensator 33 is a device in which a compensation current is given to the wiring system 32 by the inverter 36 in order to suppress the fluctuation of the reactive current generated in the wiring system 32.

  The wiring system 32 is provided with a load current extraction circuit 38 for extracting a reactive current component of a load current flowing through a load (not shown) via a current detector 37. The load current extraction circuit 38 employs the signal extraction device 1 of the present invention. Since the load current extraction circuit 38 detects only the direct current component of the q axis as the reactive current, it has only a circuit configuration relating to the q axis.

A current detector 39 is provided between the wiring system 32 and the inverter 36, and a compensation current extraction circuit 40 for extracting a current flowing through the inverter 36 through the current detector 39 is provided. The compensation current extraction circuit 40 also employs the signal extraction device 1 of the present invention.

The load current extraction circuit 38 and the compensation current extraction circuit 40 are respectively provided with the phase (fundamental frequency) θ of the system power supply 31. That is, the PLL circuit 42 is connected to the wiring system 32 via the transformer 41. PLL circuit 42 is for detecting the phase theta, the value of the detected phase theta is output to the load current extraction circuit 38 and the compensation current extraction circuit 40.

  A difference between the q-axis output of the load current extraction circuit 38 and the q-axis output of the compensation current extraction circuit 40 is calculated by the calculator 43, and an inverse dq conversion is performed via an I (integral) control circuit 44 for performing integration processing. Input to the circuit 45.

  The d-axis output of the compensation current extraction circuit 40 is input to the calculator 46, and the difference from the output of the DC voltage output circuit 47 is calculated. More specifically, the DC voltage output circuit 47 outputs a constant voltage as a target value (for example, 700 V) and is PI-controlled by a PI (proportional-integral) control circuit 49 via a calculator 48 (described later). 46, and the difference from the d-axis output of the compensation current extraction circuit 40 is calculated. The output of the arithmetic unit 46 is input to the inverse dq conversion circuit 45 via the I control circuit 50 for performing integration processing. Note that in the computing unit 48, the output of the capacitor 36 a of the inverter 36 is input via the LPF unit 51.

  In the inverse dq conversion circuit 45, the output of the I control circuit 44 and the output of the I control circuit 50 are subjected to inverse dq conversion, and then subjected to two-phase / three-phase conversion and output to a PWM (Pulse Width Modulation) circuit 52. The inverter 36 is controlled by the output of the PWM circuit 52.

  The reactive power compensator 33 extracts the q-axis component (invalid component) included in the load current and also extracts the q-axis component (invalid component) included in the compensation current to cancel the q-axis components. After the inverse dq conversion, the output of the inverter 36 is controlled by the signal. That is, since the output of the inverter 36 is controlled so that the compensation current becomes zero, a stable load current can be obtained. In this case, since the load current extraction circuit 38 and the compensation current extraction circuit 40 employ the signal extraction device 1 of the present embodiment, the q-axis output of the load current extraction circuit 38 and the d-axis of the compensation current extraction circuit 40 are used. The output and the q-axis output are output without impairing the signal responsiveness.

  FIG. 11 is a diagram showing a configuration when the signal extraction device 1 according to the present invention is applied to a reactive power compensator of a type that detects a system voltage. When the difference in configuration from FIG. 10 is mainly described, in this reactive power compensator 33 ′, the system voltage is detected via the transformer 41, and the system voltage extraction in which the signal extraction apparatus 1 of the present embodiment is employed. Input to the circuit 53.

  The system voltage extraction circuit 53 extracts the d-axis and q-axis components for the basic frequency positive phase based on the detected system voltage. These d-axis and q-axis components are output to the effective value calculation circuit 54, and the effective value calculation circuit 54 calculates the effective value of the system voltage. The effective value of the system voltage is obtained, for example, by calculating the square root of the sum of the square of the d-axis component and the square of the q-axis component.

  The effective value of the system voltage is input to the calculator 55, and the difference from the system voltage value as the target value from the system voltage output circuit 56 is calculated. The difference between the effective value of the system voltage from the effective value calculation circuit 54 and the target value from the system voltage output circuit 56 is PI-controlled by the PI control circuit 57, and the q-axis from the compensation current extraction circuit 40 is calculated by the computing unit 43. The difference from the output is calculated. As a result, the system voltage is controlled to match the target value.

  Of course, the scope of the present invention is not limited to the embodiment described above. For example, the configuration of each circuit in the signal extraction device 1 can be arbitrarily configured without departing from the function of each circuit.

It is a figure which shows the structure of the signal extraction apparatus which concerns on this invention. It is a figure for demonstrating the extraction method of a fundamental frequency component. It is a figure which shows the structure of a fundamental frequency converter circuit. It is a figure which shows the simulation input waveform of the three-phase alternating current signal in a signal extraction device. It is a figure which shows the simulation output waveform in a signal extraction apparatus. It is a figure which shows the internal structure of a 1st thru | or 4th low-pass filter. It is the figure which showed the transition state of the data in the data area | region of a low-pass filter (large) and a low-pass filter (small), and the moving average value accompanying it. It is a flowchart which shows operation | movement of a low-pass filter (large) and a low-pass filter (small). It is a figure which shows the simulation result of q-axis output when replacing the moving average value of a low-pass filter (small) with the moving average value of a low-pass filter (large). It is a figure which shows the structure of the power conversion system when the signal extraction apparatus which concerns on this invention is applied to a reactive power compensation apparatus. It is a figure which shows the other structure of the power conversion system at the time of the signal extracting device which concerns on this invention being applied to the reactive power compensation apparatus. It is the figure which showed the structure of the conventional reactive power compensation apparatus.

DESCRIPTION OF SYMBOLS 1 Signal extraction device 2 Fundamental frequency rotation coordinate conversion circuit 3 Nth-order harmonic positive phase generation circuit 4 m-order harmonic antiphase generation circuit 5 Cancellation circuit 5 Filter unit 6 Three-phase / two-phase conversion unit 7 dq conversion unit 11 nth-order harmonic positive phase rotation coordinate conversion circuit 12 first low-pass filter 13 second low-pass filter 14 n-order positive phase sub-conversion circuit 15 m-order harmonic reverse phase rotation coordinate conversion circuit 16 third low-pass filter 17 fourth Low-pass filter 18 m-order negative phase sub-conversion circuit 19 First arithmetic circuit 20 Second arithmetic circuit 21 Third arithmetic circuit 22 Fourth arithmetic circuit 23 Low-pass filter (large)
24 Low pass filter (small)
25 Fluctuation Detection Unit 31 System Power Supply 32 Distribution System 33 Reactive Power Compensation Device 36 Inverter 38 Load Current Extraction Circuit 40 Compensation Current Extraction Circuit 42 PLL Circuit 44 I Control Circuit 45 Reverse dq Conversion Circuit 47 DC Voltage Output Circuit 49 PI Control Circuit 52 PWM circuit

Claims (7)

A signal extraction device for extracting the fundamental frequency from a three-phase AC signal in which a harmonic of a predetermined order is superimposed on the fundamental frequency,
The three-phase alternating current signal is converted into a two-phase signal in a first orthogonal coordinate system that rotates at an angular frequency having the same frequency as the fundamental frequency by the first three-phase / two-phase conversion calculation process. First three-phase / two-phase conversion means for converting a signal into a two-phase signal of the first orthogonal coordinate system;
The predetermined two-order harmonics converted from the three-phase AC signal into the two-phase signal of the first orthogonal coordinate system by the first three-phase / two-phase conversion means by a predetermined arithmetic process. Harmonic generation means for generating a phase signal;
The first three-phase / two-phase conversion is performed by calculating a difference between the two-phase signal output from the first three-phase / two-phase conversion means and the two-phase signal output from the harmonic generation means. Harmonic cancellation means for canceling the harmonics of the predetermined order included in the output of the means;
A signal extraction device comprising: The harmonic generation means includes
By a second three-phase / two-phase conversion calculation process for converting the three-phase alternating current signal into a two-phase signal in a second orthogonal coordinate system that rotates at an angular frequency having the same frequency as the harmonic of the predetermined order, Second three-phase / two-phase conversion means for converting a three-phase AC signal into a two-phase signal in the second orthogonal coordinate system;
Filter means for removing an AC signal included in the two-phase signal of the second orthogonal coordinate system converted by the second three-phase / two-phase conversion means;
The second orthogonal coordinate system output from the filter means by an arithmetic process of rotating the second orthogonal coordinate system at a relative angular frequency of the second orthogonal coordinate system with respect to the first orthogonal coordinate system. Coordinate conversion means for converting the two-phase signal of the first to a two-phase signal of the first orthogonal coordinate system;
The signal extraction device according to claim 1, comprising: The harmonic generation means includes
A positive-phase component of a seventh harmonic that rotates at least in the same direction as the rotation direction of the three-phase AC signal of the fundamental frequency, or the fundamental frequency that rotates in a direction opposite to the rotation direction of the three-phase AC signal of the fundamental frequency; The signal extraction device according to claim 1, wherein a two-phase signal corresponding to a reverse phase of a fifth harmonic is generated. The filter means includes
4. The signal extraction device according to claim 2, comprising a first low-pass filter having a predetermined response time constant of the fundamental frequency. The filter means includes
A second low-pass filter connected in parallel to the first low-pass filter and having a response time constant shorter than the response time constant of the first low-pass filter;
Detecting means for detecting that the output value of the second low-pass filter becomes a constant value and the constant value continues for a predetermined time;
An output changing means for changing the output value of the first low-pass filter to the output value of the second low-pass filter when the detecting means detects that the constant value has continued for a predetermined time or more;
The signal extraction device according to claim 4, further comprising: A reactive power compensator that is provided between an AC power supply and a power system and supplies a compensation current to a load current flowing in the power system in order to improve the power factor of the AC power supplied from the AC power supply. And
A load current detection circuit for detecting the load current;
A compensation current detection circuit for detecting the compensation current,
6. The reactive power compensator according to claim 1, wherein the load current detection circuit and the compensation current detection circuit use the signal extraction device according to claim 1. A reactive power compensator that is provided between an AC power supply and a power system and supplies a compensation current to the power system in order to stabilize a system voltage,
A system voltage detection circuit for detecting the system voltage;
A compensation current detection circuit for detecting the compensation current,
6. The reactive power compensator according to claim 1, wherein the system voltage detection circuit and the compensation current detection circuit use the signal extraction device according to claim 1.