JP2009033782A - Power transmission control device, power transmission device, electronic equipment, and non-contact power transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power transmission control device having an improved detection accuracy of detecting foreign substances, and to provide a power transmission device. <P>SOLUTION: The power transmission control device provided on the power transmission device of a non-contact power transmission system includes: a drive clock generating circuit 25 for generating a drive clock DRCK defining the drive frequency of a primary coil L1; a driver control circuit 26 for generating a driver control signal on the basis of the drive clock DRCK and outputting the generated driver clock signal to the power transmission driver; a waveform detecting circuit 30 for detecting a change in waveform of an induction voltage signal PHIN of the primary coil L1; and a control circuit 20 for detecting foreign substances on the basis of a result of detection in the waveform detection circuit 30. In detecting foreign substances, the drive clock generating circuit 25 outputs the drive clock signal DRCK set in a foreign substance detecting frequency F2 being a frequency different from a usual power transmission frequency. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power transmission control device, a power transmission device, an electronic device, and a contactless power transmission system.

  In recent years, contactless power transmission (contactless power transmission) that uses electromagnetic induction and enables power transmission even without a metal part contact has been highlighted. Charging of telephones and household equipment (for example, a handset of a telephone) has been proposed.

  There exists patent document 1 as a prior art of non-contact electric power transmission. In Patent Document 1, the power transmission device (primary side) detects the load state on the power receiving side by monitoring the peak value of the induced voltage signal of the primary coil and comparing it with a predetermined threshold voltage. , Metal foreign object detection is realized.

However, in the prior art of Patent Document 1, the drive frequency of the coil is always constant, and the drive frequency is not changed. For this reason, there was a problem that the accuracy of foreign object detection could not be improved.
JP 2006-60909 A

  The present invention has been made in view of the technical problems as described above. The object of the present invention is to provide a power transmission control device, a power transmission device, an electronic device, and a contactless power transmission system capable of improving the accuracy of foreign object detection. It is to provide.

  The present invention relates to the non-contact power transmission system in which a primary coil and a secondary coil are electromagnetically coupled to transmit power from a power transmission device to a power reception device and supply power to a load of the power reception device. A power transmission control device provided in a power transmission device, a drive clock generation circuit that generates and outputs a drive clock that defines a drive frequency of the primary coil, a driver control signal is generated based on the drive clock, and A driver control circuit that outputs to a power transmission driver that drives the primary coil, a waveform detection circuit that detects a change in the waveform of the induced voltage signal of the primary coil, and a foreign object based on the detection result of the waveform detection circuit A control circuit that performs detection, and the drive clock generation circuit is configured to detect a foreign object before setting the foreign object detection frequency to a frequency different from a normal power transmission frequency. It related to power transmission control device for outputting a drive clock.

  According to the present invention, the drive clock generation circuit generates and outputs a drive clock that defines the drive frequency, and the driver control circuit generates a driver control signal based on the drive clock and outputs it to the power transmission driver. Output. In this case, according to the present invention, when a foreign object is detected, a drive clock set at a foreign object detection frequency different from the normal power transmission frequency is output. In this way, with the drive clock set to the foreign object detection frequency, the waveform detection circuit detects the change in the waveform of the induced voltage signal of the primary coil, and the control circuit detects the foreign object based on the detection result. Perform detection. In this way, foreign object detection is performed at a driving frequency different from that during normal power transmission, and the foreign object detection accuracy can be improved.

  In the present invention, the drive clock generation circuit may output the drive clock set to a foreign object detection frequency that is a frequency between the normal power transmission frequency and the coil resonance frequency when the foreign object is detected.

  In this way, at the time of foreign object detection, the drive frequency comes closer to the coil resonance frequency than during normal power transmission. As a result, the waveform of the induced voltage signal is distorted, and the waveform can be greatly varied with a small load variation, and the foreign object detection accuracy can be improved.

  In the present invention, the waveform detection circuit may include a pulse width detection circuit that detects pulse width information of the induced voltage signal, and the control circuit may perform foreign object detection based on the pulse width information.

  In this way, stable foreign object detection can be realized with a simple configuration without adopting a method of individually detecting the voltage and current and determining based on the phase difference.

  In the present invention, the waveform detection circuit may be configured such that the first timing is a timing at which the first induced voltage signal of the primary coil changes from the low potential power supply side and exceeds the first threshold voltage. , A first pulse width detection circuit for detecting a first pulse width information by measuring a first pulse width period which is a period between the first edge timing of the drive clock and the first timing The control circuit may perform foreign object detection based on the first pulse width information.

  According to the present invention, the first pulse width period, which is the period between the first edge timing (for example, falling edge or rising edge timing) of the drive clock and the first timing, is measured, and the first Is detected as pulse width information. Then, foreign object detection is performed based on the detected first pulse width information. In this way, stable foreign object detection can be realized without adopting a method in which voltage and current are individually detected and determined based on the phase difference. In the present invention, the first timing is a timing at which the first induced voltage signal changes from the low-potential power supply side and exceeds the first threshold voltage. However, pulse width detection with little variation can be realized.

  In the present invention, the waveform detection circuit includes a first waveform shaping circuit that shapes the first induced voltage signal and outputs a first waveform shaping signal, the first pulse width detection circuit. May measure the first pulse width period based on the first waveform shaping signal and the drive clock.

  In this way, it is possible to measure the first pulse width period by digital processing using the signal waveform-shaped by the first waveform shaping circuit and the drive clock.

  In the present invention, the first pulse width detection circuit increments or decrements a count value in the first pulse width period, and the length of the first pulse width period is based on the obtained count value. A first counter that counts may be included.

  In this way, the first pulse width period can be accurately measured by digital processing using the first counter.

  In the present invention, the first pulse width detection circuit receives the first waveform shaping signal and the drive clock, and generates a first enable signal that is active during the first pulse width period. The first counter may increment or decrement a count value when the first enable signal is active.

  In this way, the count process for counting the pulse width period can be controlled only by generating the first enable signal, and the process can be simplified.

  In the present invention, the first enable signal generation circuit has the drive clock input to the clock terminal, the high potential power supply voltage or the low potential power supply voltage input to the data terminal, and the reset terminal or the set terminal. A first flip-flop circuit to which the first waveform shaping signal is input may be included.

  In this way, the generation of the enable signal can be realized with a simple configuration in which only the first flip-flop circuit is provided.

  In the present invention, the control circuit may perform primary foreign object detection, which is foreign object detection before the start of normal power transmission, based on the first pulse width information.

  In this way, primary foreign object detection can be realized, for example, in a no-load state before the start of normal power transmission.

  In the present invention, the waveform detection circuit may be configured such that the second timing is a timing at which the second induced voltage signal of the primary coil changes from the high potential power supply side and falls below the second threshold voltage. , A second pulse width detection circuit that detects a second pulse width information by measuring a second pulse width period that is a period between the second edge timing of the drive clock and the second timing The control circuit may perform secondary foreign object detection, which is foreign object detection after the start of normal power transmission, based on the second pulse width information.

  In this way, foreign objects can be detected with different standards before the start of normal power transmission and after the start of normal power transmission, and the accuracy and stability of foreign object detection can be improved.

  According to the present invention, the waveform detection circuit includes a second waveform shaping circuit that shapes the second induced voltage signal and outputs a second waveform shaping signal, and the second pulse width detection circuit. May measure the second pulse width period based on the second waveform shaping signal and the drive clock.

  In this way, it is possible to measure the second pulse width period by digital processing using the signal waveform-shaped by the second waveform shaping circuit and the drive clock.

  In the present invention, the second pulse width detection circuit increments or decrements a count value in the second pulse width period, and the length of the second pulse width period is based on the obtained count value. A second counter may be included for measuring.

  In this way, the second pulse width period can be accurately measured digitally using the second counter.

  In the present invention, the waveform detection circuit includes a first waveform shaping circuit that shapes the first induced voltage signal and outputs the first waveform shaping signal to the first pulse width detection circuit. The second waveform shaping circuit shapes the second induced voltage signal different from the first induced voltage signal, and the second waveform shaped signal is supplied to the second pulse width detection circuit. It may be output.

  In this manner, the first method using the first waveform shaping circuit and the first pulse width detection circuit and the second method using the second waveform shaping circuit and the second pulse width detection circuit. The pulse width detection can be realized by using the first and second induced voltage signals having different signal states, and the accuracy and stability of the pulse width detection can be improved.

  The present invention also relates to a power transmission device including any of the power transmission control devices described above and a power transmission unit that generates an alternating voltage and supplies the alternating voltage to the primary coil.

  Moreover, this invention relates to the electronic device containing the power transmission apparatus as described above.

  In addition, the present invention includes a power transmission device and a power reception device, and electromagnetically couples a primary coil and a secondary coil to transmit power from the power transmission device to the power reception device, and to a load of the power reception device. A contactless power transmission system for supplying power, wherein the power receiving device includes a power receiving unit that converts an induced voltage of the secondary coil into a DC voltage, and the power transmitting device defines a driving frequency of the primary coil A drive clock generation circuit that generates and outputs a drive clock, a driver control circuit that generates a driver control signal based on the drive clock and outputs the driver control signal to a power transmission driver that drives the primary coil, and the primary A waveform detection circuit for detecting a change in the waveform of the induced voltage signal of the coil; and a control circuit for detecting a foreign substance based on a detection result of the waveform detection circuit. , Upon foreign object detection is related to the non-contact power transmission system for outputting the driving clock set to foreign object detection frequency is a frequency different from the normal power transmission frequency.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Electronic Device FIG. 1A shows an example of an electronic device to which the contactless power transmission method of this embodiment is applied. A charger 500 (cradle) which is one of electronic devices has a power transmission device 10. A mobile phone 510 that is one of the electronic devices includes a power receiving device 40. The mobile phone 510 includes a display unit 512 such as an LCD, an operation unit 514 including buttons and the like, a microphone 516 (sound input unit), a speaker 518 (sound output unit), and an antenna 520.

  Electric power is supplied to the charger 500 via the AC adapter 502, and this electric power is transmitted from the power transmitting device 10 to the power receiving device 40 by contactless power transmission. Thereby, the battery of the mobile phone 510 can be charged or the device in the mobile phone 510 can be operated.

  Note that the electronic apparatus to which this embodiment is applied is not limited to the mobile phone 510. For example, the present invention can be applied to various electronic devices such as wristwatches, cordless telephones, shavers, electric toothbrushes, wrist computers, handy terminals, portable information terminals, electric bicycles, and IC cards.

  As schematically shown in FIG. 1B, power transmission from the power transmission device 10 to the power reception device 40 is performed on the primary coil L1 (power transmission coil) provided on the power transmission device 10 side and on the power reception device 40 side. This is realized by electromagnetically coupling the secondary coil L2 (power receiving coil) formed to form a power transmission transformer. Thereby, non-contact power transmission becomes possible.

2. FIG. 2 shows a configuration example of the power transmission device 10, the power transmission control device 20, the power reception device 40, and the power reception control device 50 according to the present embodiment. A power transmission-side electronic device such as the charger 500 of FIG. 1A includes the power transmission device 10 of FIG. In addition, a power receiving-side electronic device such as the mobile phone 510 can include the power receiving device 40 and a load 90 (main load). 2, for example, the primary coil L1 and the secondary coil L2, which are planar coils, are electromagnetically coupled to transmit power from the power transmitting apparatus 10 to the power receiving apparatus 40, and the voltage output node of the power receiving apparatus 40 A non-contact power transmission (non-contact power transmission) system that supplies power (voltage VOUT) from the NB 7 to the load 90 is realized.

  The power transmission device 10 (power transmission module, primary module) can include a primary coil L1, a power transmission unit 12, a waveform monitor circuit 14, a display unit 16, and a power transmission control device 20. Note that the power transmission device 10 and the power transmission control device 20 are not limited to the configuration in FIG. 2, and some of the components (for example, the display unit and the waveform monitor circuit) are omitted, other components are added, and the connection relationship Various modifications such as changing the above are possible.

  The power transmission unit 12 generates an AC voltage having a predetermined frequency during power transmission, and generates an AC voltage having a different frequency according to data during data transfer, and supplies the AC voltage to the primary coil L1. Specifically, as shown in FIG. 3A, for example, when data “1” is transmitted to the power receiving device 40, an AC voltage of frequency f1 is generated and data “0” is transmitted. Generates an alternating voltage of frequency f2. The power transmission unit 12 includes at least a first power transmission driver that drives one end of the primary coil L1, a second power transmission driver that drives the other end of the primary coil L1, and a resonance circuit together with the primary coil L1. One capacitor can be included.

  Each of the first and second power transmission drivers included in the power transmission unit 12 is an inverter circuit (buffer circuit) configured by, for example, a power MOS transistor, and is controlled by the driver control circuit 26 of the power transmission control device 20.

  The primary coil L1 (power transmission side coil) is electromagnetically coupled to the secondary coil L2 (power reception side coil) to form a power transmission transformer. For example, when power transmission is necessary, as shown in FIGS. 1A and 1B, a mobile phone 510 is placed on the charger 500 so that the magnetic flux of the primary coil L1 passes through the secondary coil L2. To make sure On the other hand, when power transmission is unnecessary, the charger 500 and the mobile phone 510 are physically separated so that the magnetic flux of the primary coil L1 does not pass through the secondary coil L2.

  The waveform monitor circuit 14 (rectifier circuit, waveform shaping circuit) generates an induced voltage signal PHIN for waveform monitoring based on the coil end signal CSG of the primary coil L1. For example, the coil end signal CSG which is an induced voltage signal of the primary coil L1 exceeds the maximum rated voltage of the IC of the power transmission control device 20, or becomes a negative voltage. The waveform monitor circuit 14 receives such a coil end signal CSG, generates an induced voltage signal PHIN for waveform monitoring, which is a signal that can be detected by the waveform detection circuit 30 of the power transmission control device 20, and generates the power transmission control device. For example, output to 20 waveform monitor terminals. Specifically, the waveform monitor circuit 14 performs a limit operation for clamping the voltage so as not to exceed the maximum rated voltage, or performs half-wave rectification so that a negative voltage is not applied to the power transmission control device 20. For this purpose, the waveform monitor circuit 14 can include a resistor, a diode, and the like necessary for limit operation, half-wave rectification, and current limitation. For example, the coil end signal CSG is voltage-divided by a voltage dividing circuit composed of a plurality of resistors, or half-wave rectified by a diode and output to the power transmission control device 20 as an induced voltage signal PHIN.

  The display unit 16 displays various states of the contactless power transmission system (during power transmission, ID authentication, etc.) using colors, images, and the like, and is realized by, for example, an LED or an LCD.

  The power transmission control device 20 is a device that performs various controls of the power transmission device 10, and can be realized by an integrated circuit device (IC) or the like. The power transmission control device 20 can include a control circuit 22 (power transmission side), an oscillation circuit 24, a drive clock generation circuit 25, a driver control circuit 26, and a waveform detection circuit 30. In addition, some implementations, such as abbreviate | omitting some of these components and adding another component, are possible.

  The control circuit 22 (control unit) on the power transmission side controls the power transmission device 10 and the power transmission control device 20, and can be realized by, for example, a gate array or a microcomputer. Specifically, the control circuit 22 performs various sequence control and determination processes necessary for power transmission, load state detection (data detection, foreign object detection, removal detection, etc.), frequency modulation, and the like.

  The oscillation circuit 24 is constituted by a crystal oscillation circuit, for example, and generates a primary side clock. The drive clock generation circuit 25 generates a drive clock that defines the drive frequency. The driver control circuit 26 generates a control signal having a desired frequency based on the drive clock, the frequency setting signal from the control circuit 22, and the like, and outputs the control signal to the first and second power transmission drivers of the power transmission unit 12. Then, the first and second power transmission drivers are controlled.

  The waveform detection circuit 30 detects a change in the waveform of the induced voltage signal PHIN of the primary coil L1. For example, when the load state (load current) on the power receiving side (secondary side) changes, the waveform of the induced voltage signal PHIN changes. The waveform detection circuit 30 detects such a change in waveform and outputs a detection result (detection result information) to the control circuit 22.

  Specifically, the waveform detection circuit 30 shapes the induced voltage signal PHIN, for example, and generates a waveform shaped signal. For example, a square wave (rectangular wave) waveform shaping signal (pulse signal) that becomes active (eg, H level) when the signal PHIN exceeds a given threshold voltage is generated. The waveform detection circuit 30 detects pulse width information (pulse width period) of the waveform shaping signal based on the waveform shaping signal and the drive clock. Specifically, the pulse width information of the induced voltage signal PHIN is detected by receiving the waveform shaping signal and the drive clock from the drive clock generation circuit 25 and detecting the pulse width information of the waveform shaping signal.

  Based on the detection result of the waveform detection circuit 30, the control circuit 22 detects the load state (load fluctuation, load level) on the power receiving side (power receiving device 40 side). Specifically, based on the pulse width information detected by the waveform detection circuit 30 (pulse width detection circuit), the load state on the power receiving side is detected, for example, data (load) detection, foreign object (metal) detection, removal (detachment) ) Perform detection. That is, the pulse width period, which is the pulse width information of the induced voltage signal, changes according to the change in the load state on the power receiving side. The control circuit 22 detects a load fluctuation on the power receiving side based on the pulse width period (a count value obtained by measuring the pulse width period). Thereby, when the load modulation unit 46 of the power receiving device 40 transmits data by load modulation as shown in FIG. 3B, this transmission data can be detected.

  The power reception device 40 (power reception module, secondary module) can include a secondary coil L2, a power reception unit 42, a load modulation unit 46, a power supply control unit 48, and a power reception control device 50. The power reception device 40 and the power reception control device 50 are not limited to the configuration in FIG. 2, and various modifications such as omitting some of the components, adding other components, and changing the connection relationship. Is possible.

  The power receiving unit 42 converts the AC induced voltage of the secondary coil L2 into a DC voltage. This conversion is performed by a rectifier circuit 43 included in the power receiving unit 42. The rectifier circuit 43 includes diodes DB1 to DB4. The diode DB1 is provided between the node NB1 at one end of the secondary coil L2 and the generation node NB3 of the DC voltage VDC, and DB2 is provided between the node NB3 and the node NB2 at the other end of the secondary coil L2. , DB3 is provided between the node NB2 and the VSS node NB4, and DB4 is provided between the nodes NB4 and NB1.

  The resistors RB1 and RB2 of the power receiving unit 42 are provided between the nodes NB1 and NB4. A signal CCMPI obtained by dividing the voltage between the nodes NB1 and NB4 by the resistors RB1 and RB2 is input to the frequency detection circuit 60 of the power reception control device 50.

  The capacitor CB1 and the resistors RB4 and RB5 of the power receiving unit 42 are provided between the node NB3 of the DC voltage VDC and the node NB4 of VSS. A signal ADIN obtained by dividing the voltage between the nodes NB3 and NB4 by the resistors RB4 and RB5 is input to the position detection circuit 56 of the power reception control device 50.

  The load modulation unit 46 performs load modulation processing. Specifically, when desired data is transmitted from the power receiving device 40 to the power transmitting device 10, the load at the load modulation unit 46 (secondary side) is variably changed in accordance with the transmission data, and FIG. As shown, the signal waveform of the induced voltage of the primary coil L1 is changed. For this purpose, the load modulation unit 46 includes a resistor RB3 and a transistor TB3 (N-type CMOS transistor) provided in series between the nodes NB3 and NB4. The transistor TB3 is on / off controlled by a signal P3Q from the control circuit 52 of the power reception control device 50. When performing load modulation by controlling on / off of the transistor TB3, the transistor TB2 of the power supply control unit 48 is turned off, and the load 90 is not electrically connected to the power receiving device 40.

  For example, as shown in FIG. 3B, when the secondary side is set to a low load (impedance is large) in order to transmit data “0”, the signal P3Q becomes L level and the transistor TB3 is turned off. As a result, the load of the load modulator 46 becomes almost infinite (no load). On the other hand, when the secondary side is set to a high load (low impedance) in order to transmit data “1”, the signal P3Q becomes H level and the transistor TB3 is turned on. As a result, the load of the load modulation unit 46 becomes the resistance RB3 (high load).

  The power supply control unit 48 controls power supply to the load 90. The regulator 49 adjusts the voltage level of the DC voltage VDC obtained by the conversion in the rectifier circuit 43 to generate the power supply voltage VD5 (for example, 5V). The power reception control device 50 operates by being supplied with the power supply voltage VD5, for example.

  The transistor TB2 (P-type CMOS transistor) is controlled by a signal P1Q from the control circuit 52 of the power reception control device 50. Specifically, the transistor TB2 is turned on when ID authentication is completed (established) and normal power transmission is performed, and turned off when load modulation is performed.

  The power reception control device 50 is a device that performs various controls of the power reception device 40 and can be realized by an integrated circuit device (IC) or the like. The power reception control device 50 can be operated by a power supply voltage VD5 generated from the induced voltage of the secondary coil L2. The power reception control device 50 can include a control circuit 52 (power reception side), a position detection circuit 56, an oscillation circuit 58, a frequency detection circuit 60, and a full charge detection circuit 62.

  The control circuit 52 (control unit) controls the power receiving device 40 and the power receiving control device 50, and can be realized by, for example, a gate array or a microcomputer. Specifically, the control circuit 52 performs various sequence control and determination processes necessary for ID authentication, position detection, frequency detection, load modulation, full charge detection, and the like.

  The position detection circuit 56 monitors the waveform of the signal ADIN corresponding to the waveform of the induced voltage of the secondary coil L2, and determines whether the positional relationship between the primary coil L1 and the secondary coil L2 is appropriate. Specifically, the signal ADIN is converted into a binary value by a comparator or a level is determined by A / D conversion to determine whether or not the positional relationship is appropriate.

  The oscillation circuit 58 is constituted by a CR oscillation circuit, for example, and generates a secondary clock. The frequency detection circuit 60 detects the frequency (f1, f2) of the signal CCMPI and determines whether the transmission data from the power transmission device 10 is “1” or “0” as shown in FIG. To do.

  The full charge detection circuit 62 (charge detection circuit) is a circuit that detects whether or not the battery 94 (secondary battery) of the load 90 is in a fully charged state (charged state).

  The load 90 can include a charge control device 92 that performs charge control of the battery 94 and the like. The charge control device 92 (charge control IC) can be realized by an integrated circuit device or the like. Note that, like a smart battery, the battery 94 itself may have the function of the charging control device 92.

  Next, an outline of the operation on the power transmission side and the power reception side will be described using the flowchart of FIG. When the power transmission side is powered on and powered on (step S1), the power transmission side performs temporary power transmission for position detection (step S2). By this power transmission, the power supply voltage on the power receiving side rises and the reset of the power reception control device 50 is released (step S11). Then, the power receiving side sets the signal P1Q to H level (step S12). As a result, the transistor TB2 is turned off, and the electrical connection with the load 90 is interrupted.

  Next, the power receiving side uses the position detection circuit 56 to determine whether or not the positional relationship between the primary coil L1 and the secondary coil L2 is appropriate (step S13). If the positional relationship is appropriate, the power receiving side starts an ID authentication process and transmits an authentication frame to the power transmission side (step S14). Specifically, authentication frame data is transmitted by the load modulation described with reference to FIG.

  When the power transmission side receives the authentication frame, the power transmission side performs determination processing such as whether or not the IDs match (step S3). When the ID authentication is permitted, a permission frame is transmitted to the power receiving side (step S4). Specifically, data is transmitted by the frequency modulation described with reference to FIG.

  The power receiving side receives the permission frame and, if the content is OK, transmits a start frame for starting contactless power transmission to the power transmitting side (steps S15 and S16). On the other hand, the power transmission side receives the start frame and starts normal power transmission when the content is OK (steps S5 and S6). Then, the power receiving side sets the signal P1Q to the L level (step S17). As a result, both transistors TB2 are turned on, so that power transmission to the load 90 becomes possible, and power supply to the load (output of VOUT) starts (step S18).

3. Foreign object detection frequency FIG. 5 shows a configuration example of the power transmission control device 20 of the present embodiment. Note that the power transmission control device 20 of the present embodiment is not limited to the configuration of FIG. 5, and various modifications such as omitting some of the components (for example, a waveform monitor circuit) or adding other components are possible. Is possible.

  In FIG. 5, the drive clock generation circuit 25 generates a drive clock DRCK that defines the drive frequency of the primary coil L1. Specifically, the reference clock CLK generated by the oscillation circuit 24 is divided to generate the drive clock DRCK. The primary coil L1 is supplied with an AC voltage having a driving frequency of the driving clock DRCK.

  The driver control circuit 26 generates a driver control signal based on the drive clock DRCK and outputs the driver control signal to the power transmission drivers (first and second power transmission drivers) of the power transmission unit 12 that drives the primary coil L1. In this case, the signal input to the gate of the P-type transistor of the inverter circuit and the signal input to the gate of the N-type transistor are non-overlapping so that no through current flows through the inverter circuit constituting the power transmission driver. A driver control signal is generated so as to become a signal.

  The waveform detection circuit 30 detects a change in the waveform of the induced voltage signal PHIN of the primary coil L1. Then, the control circuit 22 performs foreign object detection based on the detection result in the waveform detection circuit 30.

  For example, the waveform detection circuit 30 detects pulse width information of the induced voltage signal PHIN. Then, the control circuit 22 performs foreign object detection based on the detected pulse width information. Specifically, the waveform detection circuit 30 detects pulse width information by a first method of pulse width detection described later, and foreign object detection is performed based on the pulse width information. For example, the foreign matter is detected by measuring the pulse width period from the edge timing of the drive clock to the timing when the induced voltage signal PHIN (coil end signal CSG) rises and exceeds a given threshold voltage.

  Further, the waveform detection circuit 30 may detect the foreign matter by detecting the pulse width information by a second method of detecting the pulse width described later. For example, the foreign matter is detected by measuring the pulse width period from the edge timing of the drive clock to the timing when the induced voltage signal PHIN (coil end signal CSG) falls and falls below a given threshold voltage.

  Further, the waveform detection circuit 30 may detect the foreign matter by performing the pulse width detection of both the first method and the second method. For example, primary foreign matter detection may be performed by the first method before the start of normal power transmission, and secondary foreign matter detection may be performed by the second method after the start of normal power transmission.

  Further, the waveform detection circuit 30 may detect the foreign matter by a method of determining the phase characteristic due to the load. For example, a foreign object may be detected by detecting a voltage / current phase difference. Alternatively, the foreign substance may be detected by monitoring the peak value of the induced voltage signal PHIN and detecting a change in the peak value.

  In this embodiment, when such foreign matter is detected (foreign matter detection period, foreign matter detection mode), the drive clock DRCK (including a signal equivalent to the drive clock) is set to a frequency that is different from the normal power transmission frequency F1. The detection frequency is set to F2. Specifically, the control circuit 22 outputs a drive frequency change instruction signal to the drive clock generation circuit 25 when a foreign object is detected (for example, when a primary foreign object is detected). Then, the drive clock generation circuit 25 generates and outputs the drive clock DRCK set to the foreign object detection frequency F2 when the foreign object is detected. For example, by changing the frequency division ratio with respect to the reference clock CLK, the drive frequency is changed from the normal power transmission frequency F1 to the foreign object detection frequency F2, and the drive clock DRCK having the frequency F2 is output to the driver control circuit 26. Then, the driver control circuit 26 generates a driver control signal having a frequency F2, and controls the power transmission driver. In this case, the foreign object detection frequency F2 can be set to a frequency between the normal power transmission frequency F1 and the coil resonance frequency F0, for example.

  For example, FIG. 6A shows a signal waveform example of the coil end signal CSG when the load on the power receiving side (secondary side) is low (when the load current is small), and FIG. 6B shows the load on the power receiving side. Shows a signal waveform example of the coil end signal CSG in a case where the current is high (when the load current is large). As shown in FIGS. 6A and 6B, the waveform of the coil end signal CSG is distorted as the load on the power receiving side increases.

  Specifically, as described later, at the time of low load in FIG. 6A, the square wave that is the drive waveform (DRCK waveform) is more dominant than the sine wave that is the coil resonance waveform. On the other hand, when the load is high as shown in FIG. 6B, the sine wave that is the resonance waveform becomes more dominant than the square wave that is the drive waveform, and the waveform is distorted.

  In the first method of detecting the pulse width, which will be described later, as shown in FIG. 6B, the pulse width period XTPW1 at the rising edge of the coil end signal CSG is detected to detect the load fluctuation accompanying the foreign object insertion. . In the second method of detecting the pulse width, the pulse width period XTPW2 at the fall of the coil end signal CSG is detected to detect the load fluctuation accompanying the insertion of the foreign matter. That is, in FIG. 6 (B), the coil end signal CSG detects a change in load accompanying the insertion of a foreign object by detecting a change from a signal waveform in which a square wave is dominant to a signal waveform in which a sine wave is dominant. ing.

  In the present embodiment, when such foreign matter is detected, the drive frequency is set to a foreign matter detection frequency F2 different from the normal power transmission frequency F1, as shown in FIG. 6C. Specifically, it is set to a frequency F2 between the normal power transmission frequency F1 and the coil resonance frequency F0 (resonance frequency of a resonance circuit constituted by a coil or the like).

  As described above, when detecting a foreign object, the waveform of the coil end signal CSG (induced voltage signal) can be increased by changing the drive frequency from F1 to F2 and bringing it closer to the coil resonance frequency F0.

  Specifically, as will be described later with reference to FIG. 9C, when the drive frequency approaches the resonance frequency, the sine wave that is the resonance waveform becomes dominant. Therefore, by setting the drive frequency to the foreign object detection frequency F2 close to the resonance frequency F0, the sine wave becomes dominant and the waveform becomes more distorted than when the normal transmission power frequency F1 is set. That is, foreign object detection can be performed in a frequency band in which pulse width fluctuation (phase fluctuation) is likely to occur. As a result, the foreign object detection sensitivity is increased and the foreign object detection accuracy is improved. That is, the waveform greatly fluctuates with a small load variation, and the pulse width periods XTPW1 and XTPW2 greatly fluctuate, so that it is easy to detect a metal foreign object having a small size.

  For example, from the viewpoint of power transmission efficiency and current consumption, the drive frequency F1 during normal power transmission is generally set to a frequency away from the resonance frequency F0, and the frequency F2 close to the resonance frequency F0 is generally not used during normal power transmission. It is.

  However, when a foreign object is detected before the start of normal power transmission (primary foreign object detection), the transistor TB2 in FIG. 2 is turned off and power transmission to the load 90 is stopped. become. Therefore, at the time of foreign object detection, it is not necessary to consider power transmission efficiency and power consumption, and there is no problem even if the foreign object detection frequency F2 is set to a frequency close to the resonance frequency F0. In this embodiment, the frequency F2 between the frequencies F0 and F1 is set from such a viewpoint.

  Further, as will be described later, the pulse width detection method of the first method has a problem that the sensitivity to the load variation is low, although the variation of the pulse width detection with respect to the power supply voltage variation or the like is less than the second method. In this regard, when detecting the foreign matter by the first method, if the foreign matter detection frequency F2 is brought close to the resonance frequency F0, the distortion of the waveform with respect to the load change increases, so that there is an advantage that the sensitivity to the load change can be improved.

  As described above, various methods such as a phase detection method and a peak voltage detection method can be adopted as the waveform detection circuit 30 in addition to the pulse width detection method. When such a method is adopted, the foreign object detection frequency F2 may be set to the most appropriate frequency in the method. For example, the foreign object detection frequency F2 is set to a frequency higher than the normal power transmission frequency F1. It may be set.

4). First Modification FIG. 7 shows a first modification of this embodiment. In FIG. 7, for example, when the inductance of the primary coil L1 or the capacitance value of the capacitor constituting the resonance circuit varies, the power supply voltage varies, or the distance and positional relationship between the primary coil L1 and the secondary coil L2 vary. The peak voltage (amplitude) of the induced voltage signal PHIN1 also varies. Therefore, there is a possibility that accurate detection of the load variation cannot be realized only by the method of detecting the peak voltage of the signal PHIN1. Therefore, in FIG. 7, the load fluctuation due to the insertion of foreign matter or the like is detected by detecting the pulse width information of the induced voltage signal PHIN1.

  In FIG. 7, the waveform detection circuit 30 includes a first waveform detection circuit 31 that detects a change in the waveform of the first induced voltage signal PHIN1 of the primary coil L1. The first waveform detection circuit 31 includes a first waveform shaping circuit 32 and a first pulse width detection circuit 33. The waveform shaping circuit 32 (pulse signal generation circuit) shapes the induced voltage signal PHIN1 of the primary coil L1 and outputs a waveform shaping signal WFQ1. Specifically, for example, a square wave (rectangular wave) waveform shaping signal WFQ1 (pulse signal) that becomes active (eg, H level) when the signal PHIN1 exceeds a given threshold voltage is output.

  The pulse width detection circuit 33 detects the pulse width information of the induced voltage signal PHIN1 of the primary coil L1. Specifically, the waveform shaping signal WFQ1 from the waveform shaping circuit 32 and the drive clock DRCK (driver control signal) from the drive clock generation circuit 25 are received, and the pulse width information of the waveform shaping signal WFQ1 is detected to induce the waveform shaping signal WFQ1. The pulse width information of the voltage signal PHIN1 is detected.

  For example, it is assumed that the timing when the induced voltage signal PHIN1 changes from the GND side (low potential power supply side) and exceeds the first threshold voltage VT1 is the first timing. In this case, the pulse width detection circuit 33 measures a first pulse width period, which is a period between the first edge timing (for example, the falling timing) of the drive clock DRCK and the first timing, The pulse width information is detected. For example, the first pulse width period in which the voltage signal PHIN1 induced by the voltage change of the drive clock DRCK is equal to or lower than a given threshold voltage VT1 is measured. Then, the magnitude of the pulse width of the waveform shaping signal WFQ1 (induced voltage signal) with respect to the pulse width of the drive clock DRCK is measured. In this case, the first pulse width period is measured using, for example, the reference clock CLK. Data PWQ1 as a result of measurement by the pulse width detection circuit 33 is latched by, for example, a latch circuit (not shown). Specifically, the pulse width detection circuit 33 measures the first pulse width period using a counter that increments (or decrements) the count value using the reference clock CLK, and the measurement result data PWQ1 is stored in the latch circuit. Latched.

  Based on the pulse width information detected by the pulse width detection circuit 33, the control circuit 22 detects the load state (load fluctuation, load level) on the power receiving side (secondary side). Specifically, the control circuit 22 performs foreign object detection (primary foreign object detection) based on the pulse width information detected by the pulse width detection circuit 33. Alternatively, the data transmitted by the power receiving device 40 by load modulation may be detected.

  8A to 8C show measurement results of signal waveforms of the drive clock DRCK, the coil end signal CSG, the induced voltage signal PHIN1, and the pulse signal PLS1. 8A, 8B, and 8C are respectively a low load (for example, secondary side load current = 0 mA), a medium load (load current = 70 mA), and a high load (load current = 150 mA) is a signal waveform (voltage waveform). The pulse signal PLS1 used for pulse width detection becomes H level at the first timing TM1 when the induced voltage signal PHIN1 exceeds the first threshold voltage VT1, and L level at the rising edge timing TR of the drive clock DRCK. Is a signal. Note that as the threshold voltage VT1 for measuring the pulse width period (for example, the threshold voltage of the N-type transistor), a voltage that optimizes the load state detection accuracy may be appropriately selected and set.

  As shown in FIGS. 8A to 8C, the pulse width period XTPW1 of the pulse signal PLS1 becomes longer as the load on the power receiving side becomes higher (as the load current becomes larger). Therefore, by measuring the pulse width period XTPW1, it is possible to detect the load state (load level) on the power receiving side. For example, if a foreign object such as metal is inserted on the primary coil L1 (between L1 and L2), the primary power is supplied to the foreign object, and the load state on the power receiving side is an overload state. become. Even in such a case, this overload state can be detected by measuring the length of the pulse width period XTPW1, and so-called foreign matter detection (primary foreign matter detection) can be realized. In addition, by measuring the pulse width period XTPW1, it is possible to determine whether the load of the load modulation unit 46 of the power receiving device 40 is high or low and to detect whether the transmission data from the power receiving side is “0” or “1”. become.

  In FIGS. 8A to 8C, a period from the timing TM1 to the rising edge timing TR of the drive clock DRCK is defined as a pulse width period XTPW1. That is, in this case, the first waveform detection circuit 31 detects the pulse width period XTPW1 of the pulse signal PLS1 as the first pulse width information. However, as shown in FIG. 11 described later, the period from the falling edge timing TF to the timing TM1 of the drive clock DRCK is defined as the pulse width period TPW1, and the first waveform detection circuit 31 sets the pulse width period TPW1 to the first time. It is desirable to detect it as pulse width information. In this way, it is possible to prevent a situation in which the noise signal is regarded as a pulse signal and the pulse width period is measured when the load on the power receiving side is low. In this case, the pulse width period TPW1 becomes shorter as the load on the power receiving side becomes higher. Therefore, when the pulse width period TPW1 (pulse width count number) becomes shorter than a given period (given count number), it can be determined that foreign matter has been inserted on the primary coil L1, and foreign matter detection is realized. it can.

  FIG. 9A shows an equivalent circuit on the primary side when there is no load, and FIG. 9B shows an equivalent circuit when there is a load. As shown in FIG. 9A, when there is no load, a series resonance circuit is formed by the capacitance C, the primary side leakage inductance L11, and the coupling inductance M. Accordingly, as indicated by B1 in FIG. 9C, the coil resonance characteristic at no load becomes a sharp characteristic having a high Q value. On the other hand, in the case of a load, a secondary side leakage inductance Ll2 and a secondary side load resistance RL are added. Therefore, as shown in FIG. 9C, the resonance frequencies fr2 and fr3 in the case of load are larger than the resonance frequency fr1 in the case of no load. Further, due to the influence of the resistance RL, the resonance characteristic under load is a gentle characteristic with a low Q value. Further, as the load becomes low (large RL) and high load (RL small), the resonance frequency increases and the resonance frequency approaches the coil drive frequency (DRCK frequency).

  As the resonance frequency approaches the drive frequency in this way, the portion of the sine wave that is the resonance waveform gradually appears. That is, in the voltage waveform at the time of low load as shown in FIG. 8A, the square wave as the drive waveform is more dominant than the sine wave as the resonance waveform. On the other hand, in the voltage waveform at the time of high load as shown in FIG. 8C, the sine wave that is the resonance waveform is more dominant than the square wave that is the drive waveform. As a result, as the load becomes higher, the pulse width period XTPW1 becomes longer (TPW1 becomes shorter). Therefore, by measuring the pulse width period XTPW1 (TPW1), it is possible to determine the load fluctuation (high or low) on the power receiving side with a simple configuration.

  For example, a method is conceivable in which load variation on the power receiving side due to insertion of a metal foreign object or the like is detected by detecting only a change in peak voltage of a coil end signal. However, according to this method, the peak voltage changes depending not only on the load fluctuation but also on the distance and the positional relationship between the primary coil L1 and the secondary coil L2. Therefore, there is a problem that variation in load variation detection becomes large.

  On the other hand, in the pulse width detection method of the present embodiment, the load fluctuation is detected by measuring, by digital processing, the pulse width period that changes depending on the load state on the power receiving side instead of the peak voltage. Therefore, there is an advantage that load variation detection with little variation can be realized.

  In addition, a method for determining the load fluctuation on the power receiving side based on the phase characteristics due to the load is also conceivable. Here, the phase characteristic due to the load indicates a voltage / current phase difference. However, this method has a problem that the circuit configuration is complicated and the cost is increased.

  On the other hand, the pulse width detection method of the present embodiment has an advantage that the circuit configuration can be simplified because a voltage waveform can be used and processed as digital data by a simple waveform shaping circuit and a counting circuit (counter). Further, there is an advantage that it is easy to realize a combination with an amplitude detection method for detecting a load fluctuation by detecting a peak voltage.

  Furthermore, in the pulse width detection method of this embodiment, as shown in FIGS. 8A to 8C, the timing TM1 when the induced voltage signal PHIN1 changes from 0 V (GND side) and exceeds the threshold voltage VT1. The pulse width period XTPW1 defined by is measured. Therefore, by setting the threshold voltage VT1 close to 0V, adverse effects due to power supply voltage fluctuations and coil distance / position relation fluctuations can be reduced, and load fluctuation detection with less variation can be realized.

  FIG. 10 shows a specific configuration example of the power transmission control device 20 and the waveform monitor circuit 14 of the first modification. The waveform monitor circuit 14 includes a first rectifier circuit 17 with a limiter function. This rectifier circuit 17 has a current provided between a coil end node NA2 where a coil end signal CSG of the primary coil L1 is generated and a first monitor node NA11 where an induced voltage signal PHIN1 for waveform monitoring is generated. It has a limiting resistor RA1. The rectifier circuit 17 performs a limiter operation for clamping the induced voltage signal PHIN1 to the voltage of VDD (high potential power supply voltage) and performs half-wave rectification on the induced voltage signal PHIN1.

  By providing such a current limiting resistor RA1, it is possible to prevent an excessive current from the coil end node NA2 from flowing into the IC terminal of the power transmission control device 20. Further, the rectifier circuit 17 clamps the induced voltage signal PHIN1 to the voltage of VDD, so that a situation where a voltage equal to or higher than the maximum rated voltage is applied to the IC terminal of the power transmission control device 20 is prevented. Moreover, the situation where the negative voltage is applied to the IC terminal of the power transmission control device 20 is prevented by the rectifier circuit 17 performing half-wave rectification.

  Specifically, the rectifier circuit 17 is provided between the monitor node NA11 and a VDD (high potential power supply in a broad sense) node, and a first diode DA1 whose forward direction is from the monitor node NA11 to the VDD node. including. Further, it includes a second diode DA2 provided between the monitor node NA11 and a GND (low potential power supply in a broad sense) node and having a forward direction from the GND node to the monitor node NA11. A limit operation to VDD is realized by the diode DA1, and half-wave rectification is realized by the diode DA2.

  Instead of providing the diode DA1, a Zener diode may be provided. That is, a Zener diode provided between the monitor node NA11 and a GND (low potential power supply) node and having a forward direction from the GND node to the monitor node NA11 may be provided.

  The waveform shaping circuit 32 (first waveform shaping circuit) includes a resistor RC1 and an N-type transistor TC1 connected in series between VDD (high potential power supply) and GND (low potential power supply), and an inverter circuit INVC1. . The induced voltage signal PHIN1 from the waveform monitor circuit 14 is input to the gate of the transistor TC1. When the signal PHIN1 becomes higher than the threshold voltage of the transistor TC1, the TC1 is turned on and the voltage of the node NC1 becomes L level, so that the waveform shaping signal WFQ1 becomes H level. On the other hand, when the signal PHIN1 becomes lower than the threshold voltage, the waveform shaping signal WFQ1 becomes L level.

  The pulse width detection circuit 33 includes a first counter 122. The counter 122 increments (or decrements) the count value in the pulse width period, and measures the length of the pulse width period (first pulse width period) based on the obtained count value. In this case, the counter 122 performs a count value counting process based on the reference clock CLK, for example.

  More specifically, the pulse width detection circuit 33 includes a first enable signal generation circuit 120. The enable signal generation circuit 120 receives the first waveform shaping signal WFQ1 and the drive clock DRCK, and generates the first enable signal ENQ1 that becomes active in the first pulse width period. The counter 122 increments (or decrements) the count value when the enable signal ENQ1 is active (eg, H level).

  In the enable signal generation circuit 120, a drive clock DRCK (including a signal equivalent to DRCK) is input to its clock terminal (inverted clock terminal), and a voltage of VDD (high potential power supply) is input to its data terminal. It can be configured by a flip-flop circuit FFC1 in which a waveform shaping signal WFQ1 (including a signal equivalent to WFQ1) is input to a reset terminal (non-inverting reset terminal). According to the flip-flop circuit FFC1, when the drive clock DRCK becomes L level after the waveform shaping signal WFQ1 becomes L level, the output signal enable signal ENQ1 becomes H level (active). Thereafter, when the waveform shaping signal WFQ1 becomes H level, the flip-flop circuit FFC1 is reset, and the enable signal ENQ1 that is an output signal thereof becomes L level (inactive). Therefore, the counter 122 can measure the pulse width period by counting the period in which the enable signal ENQ1 is at the H level (active) with the reference clock CLK.

  The enable signal generation circuit 120 is configured by a flip-flop circuit in which the drive clock DRCK is input to its clock terminal, GND (low potential power supply) is connected to its data terminal, and the waveform shaping signal WFQ1 is input to its set terminal. May be. In this case, an inverted signal of the output signal of the flip-flop circuit may be input to the counter 122 as the enable signal ENQ1.

  The count value holding circuit 124 holds the count value CNT1 (pulse width information) from the counter 122. The held count value data LTQ 1 is output to the output circuit 126.

  The output circuit 126 (filter circuit, noise removal circuit) receives the count value data LTQ1 held in the count value holding circuit 124 and outputs data PWQ1 (first pulse width information). The output circuit 126 can include, for example, a comparison circuit 130 that compares the count value held this time in the count value holding circuit 124 with the count value held last time and outputs the larger count value. As a result, the maximum count value is held and output from the output circuit 126. This makes it possible to suppress fluctuations in the pulse width period due to noise or the like, and to realize stable pulse width detection. Further, the combination with the amplitude detection method can be facilitated.

  FIG. 11 shows a signal waveform example for explaining the operation of the circuit of FIG. When the waveform shaping signal WFQ1 becomes L level at the timing of D1 in FIG. 11, the reset of the flip-flop circuit FFC1 is released. Then, at the falling edge timing TF of the drive clock DRCK, the VDD voltage is taken into the flip-flop circuit FFC1, and the enable signal ENQ1 changes from L level to H level. As a result, the counter 122 starts the counting process, and measures the pulse width period TPW1 using the reference clock CLK.

  Next, when the waveform shaping signal WFQ1 becomes H level at the first timing TM1, the flip-flop circuit FFC1 is reset and the enable signal ENQ1 changes from H level to L level. Thereby, the count process of the counter 122 is completed. Then, the count value obtained by this counting process becomes a measurement result representing the pulse width period TPW1.

  As shown in FIG. 11, the sum of the pulse width periods TPW1 and XTPW1 is a half cycle period of the drive clock DRCK. The pulse width period XTPW1 in FIGS. 8A to 8C becomes longer as the load on the power receiving side becomes higher. Therefore, the pulse width period TPW1 in FIG. 11 becomes shorter as the load on the power receiving side becomes higher. In the pulse width period XTPW1 in FIGS. 8A to 8C, there is a problem that it is difficult to distinguish between the noise signal and the pulse signal when the load on the power receiving side is low, but the pulse width period TPW1 in FIG. Then, such a problem can be prevented.

  In the first method of the pulse width detection method of the present embodiment, as indicated by D3 in FIG. 11, the coil end signal CSG changes from 0V and exceeds the threshold voltage VTL on the low potential side, based on the timing TM1. A pulse width period TPW1 is defined. That is, the pulse width period TPW1 is a period between the falling edge timing TF and the timing TM1 of the drive clock CLK, and the pulse width period TPW1 is changed by changing the timing TM1 due to load fluctuation on the power receiving side. Since the threshold voltage VTL for determining the timing TM1 is a low voltage, there is little variation in the timing TM1 even when the power supply voltage or the like fluctuates. Even when the distance and the positional relationship between the coils L1 and L2 vary, there is little variation in the timing TM1. Therefore, according to the first method of this embodiment, it is possible to realize a pulse width detection method in which the adverse effect of fluctuations in the power supply voltage and the like is small.

  In the rectifier circuit 17 of FIG. 10, unlike the rectifier circuit 18 for the second method of the present embodiment shown in FIG. 16 described later, the waveform shaping circuit is generated as the induced voltage signal PHIN1 without dividing the coil end signal CSG. 32. Therefore, the threshold voltage VTL of FIG. 11 is substantially equal to the threshold voltage of the N-type transistor TC1 of the waveform shaping circuit 32 of FIG. 10, and the threshold voltages of FIGS. 8A to 8C. It becomes almost equal to VT1.

  The configuration of the waveform shaping circuit 32 is not limited to the configuration of FIG. 10, and may be configured by a comparator, for example. Further, the configuration of the enable signal generation circuit 120 is not limited to the configuration of FIG. 10, and may be configured by a logic circuit such as a NOR circuit or a NAND circuit. Further, the configuration of the output circuit 126 is not limited to the configuration of FIG. 10. For example, the output circuit 126 may be configured by an averaging circuit that calculates an average value (moving average) of count values (for example, the current count value and the previous count value). Good.

5). Second Modification FIG. 12 shows a second modification of the present embodiment. In the second modification, the waveform detection circuit 30 detects the waveform change of the second induced voltage signal PHIN2 of the primary coil L1 in addition to the first waveform detection circuit 31 described with reference to FIGS. The second waveform detection circuit 34 is included. Here, the first waveform detection circuit 31 performs the pulse width detection of the first method described in FIG. 8A to FIG. 8C and the like. On the other hand, the second waveform detection circuit 34 performs pulse width detection of the second method, which will be described later with reference to FIGS. 13 (A) to 13 (C).

  The second waveform detection circuit 34 includes a second waveform shaping circuit 35 and a second pulse width detection circuit 36. The waveform shaping circuit 35 shapes the induced voltage signal PHIN2 of the primary coil L1, and outputs a waveform shaping signal WFQ2. Specifically, for example, a square wave (rectangular wave) waveform shaping signal WFQ2 that is active (eg, H level) when the signal PHIN2 exceeds a given threshold voltage is output.

  The pulse width detection circuit 36 detects the pulse width information of the induced voltage signal PHIN2 of the primary coil L1. Specifically, the pulse of the induced voltage signal PHIN2 is received by receiving the waveform shaping signal WFQ2 from the waveform shaping circuit 35 and the drive clock DRCK from the drive clock generation circuit 25 and detecting the pulse width information of the waveform shaping signal WFQ2. Detect width information.

  For example, it is assumed that the timing when the induced voltage signal PHIN2 changes from the high potential power supply (VDD) side and falls below the second threshold voltage VT2 is the second timing. In this case, the pulse width detection circuit 36 measures a second pulse width period, which is a period between the second edge timing (for example, rising edge timing) of the drive clock DRCK and the second timing, The pulse width information is detected. For example, the second pulse width period in which the voltage signal PHIN2 induced by the voltage change of the drive clock DRCK is equal to or higher than a given threshold voltage VT2 is measured. Then, the magnitude of the pulse width of the waveform shaping signal WFQ2 (induced voltage signal) with respect to the pulse width of the drive clock DRCK is measured. In this case, the pulse width period is measured using, for example, the reference clock CLK. Then, data PWQ2 as a result of measurement by the pulse width detection circuit 36 is latched by, for example, a latch circuit (not shown). Specifically, the pulse width detection circuit 36 measures the pulse width period using a counter that increments (or decrements) the count value by the reference clock CLK, and the measurement result data PWQ2 is latched by the latch circuit. .

  Then, the control circuit 22 performs foreign matter detection (secondary foreign matter detection) based on the pulse width information detected by the pulse width detection circuit 36. Alternatively, the data transmitted by the power receiving device 40 by load modulation is detected.

  FIGS. 13A to 13C show measurement results of signal waveforms of the drive clock DRCK, the coil end signal CSG, the induced voltage signal PHIN2, and the pulse signal PLS2. FIG. 13A, FIG. 13B, and FIG. 13C are signal waveforms in the case of low load, medium load, and high load, respectively. The pulse signal PLS2 used for pulse width detection becomes H level at the second timing TM2 when the induced voltage signal PHIN2 falls below the second threshold voltage VT2, and becomes L at the falling edge timing TF of the drive clock DRCK. It is a signal that becomes a level. Note that as the threshold voltage VT2 (for example, the threshold voltage of an N-type transistor) for measuring the pulse width period, a voltage that optimizes the load state detection accuracy may be appropriately selected and set.

  As shown in FIGS. 13A to 13C, the pulse width period XTPW2 of the pulse signal PLS2 becomes longer as the load on the power receiving side becomes higher. Therefore, the load state on the power receiving side can be detected by measuring the pulse width period XTPW2. Specifically, it is possible to detect a foreign object (secondary foreign object detection) or whether transmission data (save frame) from the power receiving side is “0” or “1”.

  In FIGS. 13A to 13C, a period from the timing TM2 to the falling edge timing TF of the drive clock DRCK is defined as a pulse width period XTPW2. That is, in this case, the second waveform detection circuit 34 detects the pulse width period XTPW2 of the pulse signal PLS2 as the second pulse width information. However, as shown in FIG. 17 described later, the period from the rising edge timing TR of DRCK to the timing TM2 is defined as the pulse width period TPW2, and the second waveform detection circuit 34 sets the pulse width period TPW2 to the second pulse width. It is desirable to detect as information. In this way, it is possible to prevent a situation in which the noise signal is regarded as a pulse signal and the pulse width period is measured when the load on the power receiving side is low. In this case, the pulse width period TPW2 becomes shorter as the load on the power receiving side becomes higher.

  The second method (falling detection method) in FIGS. 13A to 13C has a smaller load fluctuation than the first method (rising detection method) in FIGS. 8A to 8C. However, there is an advantage that the pulse width (count value) changes greatly and the sensitivity is high. On the other hand, the first method shown in FIGS. 8A to 8C is different from the second method shown in FIGS. 13A to 13C in that the power supply voltage fluctuation, the distance between the coils L1 and L2, There is an advantage that the variation in the detection of the pulse width is small with respect to the fluctuation of the positional relationship.

  For example, FIG. 14A is a diagram showing the detection variation of the pulse width with respect to the power supply voltage variation in the first method, and FIG. 14B is the diagram showing the detection variation of the pulse width with respect to the power supply voltage variation in the second method. FIG.

  As shown in FIG. 14A, in the first method, the load current-pulse width characteristic curve does not vary so much even when the power supply voltage increases or decreases. On the other hand, as shown in FIG. 14B, in the second method, when the power supply voltage becomes higher or lower, the load current-pulse width characteristic curve also fluctuates, and the detection variation of the pulse width with respect to the power supply voltage fluctuation is large. .

  Therefore, in the second modified example of FIG. 12, in the primary foreign object detection that is the foreign object detection before the start of normal power transmission, the first waveform detection circuit 31 performs the waveform detection by the first method, and the first obtained thereby. The pulse width information (PWQ1) is used. On the other hand, in secondary foreign object detection that is foreign object detection after the start of normal power transmission, the second waveform detection circuit 34 performs waveform detection by the second method, and uses the second pulse width information (PWQ2) obtained thereby. . Further, data transmitted from the power receiving side (data notifying full charge detection or the like) is also detected using, for example, second pulse width information.

  FIG. 15 shows a flowchart for explaining these primary foreign object detection and secondary foreign object detection.

  First, the primary side (power transmission device side) is activated (step S21), and the activated primary side transmits power for activating the secondary side (position detection power) (step S22), and is in a communication standby state. (Step S23). Then, the secondary side (power receiving apparatus side) is activated (step S31), and an authentication frame (synchronization ID) is transmitted to the primary side by the load modulation described with reference to FIG. 3B (step S32).

  When the primary side receives the authentication frame, it performs ID authentication (step S24). Then, the drive frequency (DRCK frequency) is set to the foreign object detection frequency F2, which is a frequency different from the normal power transmission frequency F1. Specifically, the foreign object detection frequency F2 which is a frequency between the normal power transmission frequency F1 and the coil resonance frequency F0 is set.

  Then, the primary side performs primary foreign object detection in a state where the drive frequency is set to the foreign object detection frequency F2 in this way (step S26). Specifically, primary foreign matter detection is performed by the first waveform detection circuit 31 performing waveform detection using the first method described with reference to FIGS.

  Next, the primary side sets the drive frequency to the normal power transmission frequency F1 and starts normal power transmission (step S27), whereby the secondary side receives power (step S33).

  After the normal power transmission starts in this way, the secondary side performs secondary foreign object detection (step S28). Specifically, secondary foreign matter detection is performed by the second waveform detection circuit 34 performing waveform detection using the second method described with reference to FIGS. 13 (A) to 13 (C). In this case, it is desirable to perform secondary foreign object detection periodically after normal power transmission starts.

  When the secondary side detects the full charge of the load, it notifies the end of normal power transmission (step S34), and thereby the primary side ends normal power transmission (step S29).

  In FIG. 15, primary foreign matter detection is performed, for example, in a no-load state before the start of normal power transmission. The primary foreign matter detection is performed by the first method with little variation with respect to power supply voltage fluctuation or the like as shown in FIG. Accordingly, even when there is a power supply voltage fluctuation or the like, stable foreign object detection is possible, and the pulse width count obtained in the primary foreign object detection can be set as a reference value. Based on the reference value in the no-load state, secondary foreign matter detection after normal power transmission can be performed, and “0” and “1” of data transmitted from the power receiving side can be detected. Load variation can be detected.

  FIG. 16 shows a specific configuration example of the second modification of the present embodiment. In FIG. 16, the waveform shaping circuit 35 of the second waveform detection circuit 34 has the same configuration as the waveform shaping circuit 32 of the first waveform detection circuit 31. In the enable signal generation circuit 140 of the second waveform detection circuit 34, the drive clock DRCK is input to the non-inverted clock terminal of the flip-flop circuit FFC2, and the waveform shaping signal WFQ2 is input to the inverted reset terminal. The other configurations of the counter 142, count value holding circuit 144, and output circuit 146 of the second waveform detection circuit 34 are the same as those of the counter 122, count value holding circuit 124, and output circuit 126 of the first waveform detection circuit 31. It is.

  In FIG. 16, the waveform monitor circuit 14 includes a second rectifier circuit 18 in addition to the first rectifier circuit 17. The second rectifier circuit 18 outputs a second induced voltage signal PHIN2 for waveform monitoring to the second waveform detection circuit 34 via the second monitor node NA21. Specifically, the rectifier circuit 18 includes a first resistor RA2 provided between the coil end node NA2 and the monitor node NA21, and a first resistor RA2 provided between the monitor node NA21 and the GND (low potential power supply) node. 2 resistor RA3. Further, it includes a third diode DA3 provided between the monitor node NA21 and the GND node. Then, the voltage of the coil end signal CSG is divided by the resistors RA2 and RA3, and is input to the second waveform detection circuit 34 as the induced voltage signal PHIN2. Further, the diode DA3 performs half-wave rectification of the coil end signal CSG so that a negative voltage is not applied to the second waveform detection circuit 34.

  FIG. 17 shows an example of a signal waveform for explaining the operation of the circuit of FIG. When the waveform shaping signal WFQ2 becomes H level at the timing D2 in FIG. 17, the reset of the flip-flop circuit FFC2 is released. Then, at the rising edge timing TR of the drive clock DRCK, the VDD voltage is taken into the flip-flop circuit FFC2, and the enable signal ENQ2 changes from L level to H level. As a result, the counter 142 starts the counting process, and measures the pulse width period TPW2 using the reference clock CLK.

  Next, when the waveform shaping signal WFQ2 becomes L level at the second timing TM2, the flip-flop circuit FFC2 is reset, and the enable signal ENQ2 changes from H level to L level. Thereby, the count process of the counter 142 is completed. And the count value obtained by this count process becomes a measurement result representing the pulse width period TPW2.

  As shown in FIG. 17, the sum of the pulse width periods TPW2 and XTPW2 is a half-cycle period of the drive clock DRCK. The pulse width period XTPW2 in FIGS. 13A to 13C becomes longer as the load on the power receiving side becomes higher. Therefore, the pulse width period TPW2 of FIG. 17 becomes shorter as the power receiving side load increases. In the pulse width period XTPW2 in FIGS. 13A to 13C, there is a problem that it is difficult to distinguish between the noise signal and the pulse signal when the load on the power receiving side is low, but the pulse width period TPW2 in FIG. Then, such a problem can be prevented.

  As shown in D3 of FIG. 17, in the first method, the timing TM1 is determined using the threshold voltage VTL on the low potential side, and as shown in D4, the threshold voltage VTH on the high potential side is used in the second method. Is used to determine the timing TM2.

  Then, in the first method for determining the timing TM1 using the threshold voltage VTL on the low potential side as indicated by D3 in FIG. 17, if the rectifier circuit 18 for the second method as shown in FIG. 16 is used, the resistor RA2 As a result of voltage division by RA3, the waveform may be crushed and the detection accuracy may be degraded.

  In this regard, in the rectifier circuit 17 for the first method shown in FIG. 16, the signal PHIN1 obtained by clamping and half-wave rectifying the coil end signal CSG without performing voltage division using a resistor, Can be input to the waveform monitor circuit 31. Therefore, the pulse width can be detected based on a clean waveform signal PHIN1 that is not subjected to voltage division using a resistor, so that the detection accuracy can be improved. Further, by providing the diodes DA1 and DA2, it is possible to prevent a situation in which the signal PHIN1 exceeds the maximum rated voltage or a negative voltage is input to the first waveform detection circuit 31.

  On the other hand, in the rectifier circuit 18 for the second system, the signal PHIN2 that is voltage-divided by the resistors RA2 and RA3 is input to the N-type transistor TC2 of the waveform shaping circuit 35. By performing voltage division in this way, a situation where the signal PHIN2 exceeds the maximum rated voltage can be prevented, and the threshold voltage VTH can be set to the high potential side as indicated by D4 in FIG. That is, the signals PHIN1 and PHIN2 are input to the gates of the N-type transistors TC1 and TC2 having the same threshold voltage, respectively. However, since the signal PHIN2 is a signal that is voltage-divided by the resistors RA2 and RA3, when viewed from the coil end signal CSG, the threshold voltage indicated by D4 is larger than the threshold voltage VTL indicated by D3. VTH becomes a high voltage. When the threshold voltage VTH is set to a high voltage as described above, the change in the pulse width with respect to the load change becomes large, and the load change detection with high sensitivity can be realized. Therefore, secondary foreign object detection after the start of normal power transmission and determination of “1” and “0” of data transmitted from the secondary side can be properly realized.

6). Third Modification Example FIG. 18 shows a third modification example of the present embodiment. In the third modification, the waveform detection circuit 30 includes an amplitude detection circuit 200, an A / D conversion circuit 208, and a latch circuit 230. Then, load fluctuation on the power receiving side is detected by detecting amplitude information (peak voltage, amplitude voltage, AC voltage) of the induced voltage signal PHIN3. And in the case of the foreign material detection by such amplitude detection, you may set a drive frequency to the foreign material detection frequency F2. In addition to the first and second waveform detection circuits 31 and 34 in FIG. 12, a third waveform detection circuit including the amplitude detection circuit 200, the A / D conversion circuit 208, and the latch circuit 230 in FIG. 18 is provided. It is good.

  The amplitude detection circuit 200 includes operational amplifiers OPA1 and OPA2, a holding capacitor CA1, and a reset N-type transistor TA1. In the operational amplifier OPA1, the signal PHIN3 is input to its non-inverting input terminal, and the output node NA5 of the operational amplifier OPA2 is connected to its inverting input terminal. The holding capacitor CA1 and the reset transistor TA1 are provided between the GND and the holding node NA4 of the peak voltage which is the output node of the operational amplifier OPA1. The operational amplifier OPA2 has a holding node NA4 connected to its non-inverting input terminal and an output node NA5 of OPA2 connected to its inverting input terminal, thereby constituting a voltage follower-connected operational amplifier. Note that a voltage follower-connected operational amplifier may be further provided after the operational amplifier OPA2.

  The peak hold circuit (peak detection circuit) is configured by the operational amplifiers OPA1 and OPA2, the holding capacitor CA1, and the reset transistor TA1 in FIG. That is, the peak voltage of the signal PHIN2 from the waveform monitor circuit 14 is held in the holding node NA4, and the held peak voltage signal is impedance-converted by the voltage follower-connected operational amplifier OPA2 and output to the node NA5. Note that the reset transistor TA1 is turned on during the reset period, and discharges the charge of the holding node NA4 to the GND side.

  The A / D conversion circuit 208 includes a sample hold circuit 210, a comparator CPA1, a successive approximation register 212, and a D / A conversion circuit 214. The sample hold circuit 210 samples and holds the signal PHQ. The comparator CPA1 compares the analog signal DAQ after D / A conversion from the D / A conversion circuit 214 with the sample hold signal SHQ from the sample hold circuit 210. The successive approximation register 212 (successive comparison control circuit) stores the data of the output signal CQ1 of the comparator CPA1. The D / A conversion circuit 214 D / A converts, for example, 8-bit digital data SAQ from the successive approximation register 212 and outputs an analog signal DAQ.

  In the successive approximation type A / D conversion circuit 208, the comparator CPA1 compares the signal DAQ after D / A conversion when only the MSB (most significant bit) is set to “1” and the input signal SHQ (PHQ). To do. If the voltage of the signal SHQ is larger, the MSB is kept at “1”, and if smaller, the MSB is set to “0”. The A / D conversion circuit 208 sequentially performs comparison processing for subsequent lower bits in the same manner. The finally obtained digital data ADQ is output to the latch circuit 230. The A / D conversion circuit 208 is not limited to the configuration shown in FIG. 18, and may be, for example, a successive approximation A / D conversion circuit having a different circuit configuration, a tracking comparison type, a parallel comparison type, or a double integration type. An A / D conversion circuit such as

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (GND, VDD, mobile phone / charger, etc.) described together with different terms (low-potential power supply, high-potential power supply, electronic device, etc.) in a broader sense or the same meaning at least once The different terms can be used anywhere in the specification or drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Further, the configuration and operation of the power transmission control device, the power transmission device, the power reception control device, the power reception device, the foreign object detection method, and the pulse width detection method are not limited to those described in this embodiment, and various modifications can be made. .

1A and 1B are explanatory diagrams of contactless power transmission. 1 is a configuration example of a power transmission device, a power transmission control device, a power reception device, and a power reception control device of the present embodiment. 3A and 3B are explanatory diagrams of data transfer by frequency modulation and load modulation. The flowchart for demonstrating the outline | summary of operation | movement of the power transmission side and the power receiving side. The structural example of the power transmission control apparatus of this embodiment. 6A to 6C are explanatory diagrams of the frequency setting method of the present embodiment. The structural example of the 1st modification of this embodiment. 8A to 8C show signal waveform measurement results for explaining the pulse width detection of the first method. FIG. 9A to FIG. 9C are equivalent circuits and resonance characteristic diagrams when there is no load and when there is a load. The specific structural example of a 1st modification. The signal waveform example for demonstrating the operation | movement of a 1st modification. The structural example of the 2nd modification of this embodiment. FIG. 13A to FIG. 13C show signal waveform measurement results for explaining the second method of pulse width detection. FIGS. 14A and 14B are diagrams for explaining variations in pulse width detection due to power supply voltage fluctuations. The flowchart for demonstrating a primary foreign material detection and a secondary foreign material detection. The specific structural example of a 2nd modification. The signal waveform example for demonstrating operation | movement of a 2nd modification. The structural example of the 3rd modification of this embodiment.

Explanation of symbols

L1 primary coil, L2 secondary coil,
DESCRIPTION OF SYMBOLS 10 Power transmission apparatus, 12 Power transmission part, 14 Waveform monitor circuit, 16 Display part,
17, 18 Rectifier circuit, 20 power transmission control device, 22 control circuit (power transmission side),
24 oscillation circuit, 25 drive clock generation circuit, 26 driver control circuit,
30 waveform detection circuit,
31 first waveform detection circuit, 32 waveform shaping circuit, 33 pulse width detection circuit,
34 second waveform detection circuit, 35 waveform shaping circuit, 36 pulse width detection circuit,
40 power receiving device, 42 power receiving unit, 43 rectifier circuit, 46 load modulation unit,
48 power supply control unit, 50 power reception control device, 52 control circuit (power reception side),
56 position detection circuit, 58 oscillation circuit, 60 frequency detection circuit, 62 full charge detection circuit,
90 load, 92 charge control device, 94 battery,
120 enable signal generation circuit, 122 counter, 124 count value holding circuit,
126 output circuit, 130 comparison circuit 140 enable signal generation circuit, 142 counter, 144 count value holding circuit,
146 output circuit, 150 comparison circuit, 200 amplitude detection circuit,
208 A / D conversion circuit, 210 Sample hold circuit, 212 Successive approximation register, 214 D / A conversion circuit

Claims (16)

Provided in the power transmission device of the non-contact power transmission system that electromagnetically couples the primary coil and the secondary coil to transmit power from the power transmission device to the power reception device and supplies power to the load of the power reception device. A power transmission control device,
A drive clock generation circuit that generates and outputs a drive clock that defines the drive frequency of the primary coil;
A driver control circuit that generates a driver control signal based on the drive clock and outputs the driver control signal to a power transmission driver that drives the primary coil;
A waveform detection circuit for detecting a change in waveform of the induced voltage signal of the primary coil;
And a control circuit that performs foreign object detection based on the detection result in the waveform detection circuit,
The drive clock generation circuit includes:
A power transmission control device that outputs the drive clock set to a foreign object detection frequency that is different from a normal power transmission frequency when detecting a foreign object. In claim 1,
The drive clock generation circuit includes:
A power transmission control device that outputs the drive clock set to a foreign object detection frequency that is a frequency between the normal power transmission frequency and a coil resonance frequency when detecting a foreign object. In claim 1 or 2,
The waveform detection circuit includes:
Including a pulse width detection circuit for detecting pulse width information of the induced voltage signal;
The control circuit includes:
A power transmission control device that performs foreign object detection based on the pulse width information. In claim 1 or 2,
The waveform detection circuit includes:
When the timing at which the first induced voltage signal of the primary coil changes from the low potential power supply side and exceeds the first threshold voltage is set as the first timing, A first pulse width detection circuit that measures a first pulse width period that is a period between the first timing and detects first pulse width information;
The control circuit includes:
A power transmission control device, wherein foreign matter detection is performed based on the first pulse width information. In claim 4,
The waveform detection circuit includes:
Including a first waveform shaping circuit that shapes the first induced voltage signal and outputs a first waveform shaping signal;
The first pulse width detection circuit includes:
The power transmission control device characterized in that the first pulse width period is measured based on the first waveform shaping signal and the drive clock. In claim 5,
The first pulse width detection circuit includes:
And a first counter that increments or decrements a count value in the first pulse width period and measures a length of the first pulse width period based on the obtained count value. Control device. In claim 6,
The first pulse width detection circuit includes:
A first enable signal generation circuit that receives the first waveform shaping signal and the drive clock and generates a first enable signal that becomes active in the first pulse width period;
The first counter is
A power transmission control device that increments or decrements a count value when the first enable signal is active. In claim 7,
The first enable signal generation circuit includes:
The first flip-flop in which the drive clock is input to the clock terminal, the high potential power supply voltage or the low potential power supply voltage is input to the data terminal, and the first waveform shaping signal is input to the reset terminal or the set terminal. A power transmission control device including a power circuit. In any of claims 4 to 8,
The control circuit includes:
A power transmission control device that performs primary foreign object detection, which is foreign object detection before starting normal power transmission, based on the first pulse width information. In claim 9,
The waveform detection circuit includes:
When the timing at which the second induced voltage signal of the primary coil changes from the high potential power supply side and falls below the second threshold voltage is set as the second timing, A second pulse width detection circuit that measures a second pulse width period that is a period between the second timing and detects second pulse width information;
The control circuit includes:
A power transmission control device that performs secondary foreign object detection, which is foreign object detection after starting normal power transmission, based on the second pulse width information. In claim 10,
The waveform detection circuit includes:
A second waveform shaping circuit for shaping the second induced voltage signal and outputting a second waveform shaping signal;
The second pulse width detection circuit includes:
The power transmission control device, wherein the second pulse width period is measured based on the second waveform shaping signal and the drive clock. In claim 11,
The second pulse width detection circuit includes:
And a second counter for incrementing or decrementing a count value in the second pulse width period and measuring a length of the second pulse width period based on the obtained count value. Control device. In claim 11 or 12,
The waveform detection circuit includes:
Including a first waveform shaping circuit for shaping the waveform of the first induced voltage signal and outputting the first waveform shaping signal to the first pulse width detection circuit;
The second waveform shaping circuit includes:
Waveform shaping of the second induced voltage signal different from the first induced voltage signal, and outputting the second waveform shaped signal to the second pulse width detection circuit . A power transmission control device according to any one of claims 1 to 13,
And a power transmission unit that generates an AC voltage and supplies the AC voltage to the primary coil.   An electronic device comprising the power transmission device according to claim 14. A power transmission device and a power reception device are included, and a primary coil and a secondary coil are electromagnetically coupled to transmit power from the power transmission device to the power reception device, and supply power to a load of the power reception device. A contact power transmission system,
The power receiving device is:
A power receiving unit that converts an induced voltage of the secondary coil into a DC voltage;
The power transmission device is:
A drive clock generation circuit that generates and outputs a drive clock that defines the drive frequency of the primary coil;
A driver control circuit that generates a driver control signal based on the drive clock and outputs the driver control signal to a power transmission driver that drives the primary coil;
A waveform detection circuit for detecting a change in waveform of the induced voltage signal of the primary coil;
And a control circuit that performs foreign object detection based on the detection result in the waveform detection circuit,
The drive clock generation circuit includes:
A contactless power transmission system that outputs the drive clock set to a foreign object detection frequency that is different from a normal power transmission frequency when detecting a foreign object.

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