JP2009033492A - Clock signal control circuit and ofdm receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which appropriately controls the frequency of a clock signal used in an OFDM receiver. <P>SOLUTION: A calculation circuit 90 calculates the power values of each of a plural of pilot signals during the same symbol term, based on an I channel demodulation data IR and a Q-channel demodulation data QR. A phase shift amount calculating circuit 70 calculates the phase shift amount between the pilot signal of the minimum frequency and the pilot signal of the maximum frequency as an accumulation addition value PS1 in the pilot signals whose power values are in a prescribed range, among the plural pilot signals. A control circuit 80 controls the frequency of the clock signal used in the OFDM receiver, on the basis of the accumulation addition value PS1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an OFDM receiver that receives a radio signal (hereinafter referred to as an “OFDM signal”) modulated based on an orthogonal frequency division multiplexing (hereinafter referred to as “OFDM”), and the OFDM receiver. The present invention relates to a clock signal control circuit in a receiver.

  As a method for transmitting a digital signal, an OFDM transmission method has been proposed in which a number of orthogonal subcarriers are provided in a transmission band and data is allocated to the amplitude and phase of each subcarrier. In this transmission method, digital modulation is performed using techniques such as PSK (Phase Shift Keying) and QAM (Quadrature Amplitude Modulation).

  In the OFDM transmission system, the transmission band is divided by a large number of subcarriers transmitted in parallel. Therefore, although the transmission band allocated to one subcarrier wave is narrowed and the data transmission rate for one subcarrier wave is slow, the number of subcarriers is large, so the total data transmission rate is the same as the conventional modulation method. There is no inferiority.

  Further, in the OFDM transmission scheme, since a large number of subcarriers are transmitted in parallel, the signal amount of one symbol (one OFDM symbol) is reduced, so that the symbol transmission rate is reduced. Therefore, in a transmission path in which so-called multipath interference exists, the time length of the multipath relative to the time length of the symbol can be shortened, and the OFDM transmission system is a system that is strong against multipath interference. I can expect.

  Because of the features described above, the OFDM transmission system is advantageous when digitally transmitting terrestrial waves that are strongly affected by multipath interference due to topography, buildings, etc., and is also adopted in Japanese terrestrial digital broadcasting systems. Yes.

  By the way, in an OFDM transmission system receiver, in order to correctly demodulate an OFDM signal, it is necessary to establish various types of synchronization in the demodulation circuit, and a clock signal that serves as a reference for all processing in the demodulation process is also included. It must be synchronized with the clock signal on the transmitting side. Accordingly, various methods for generating a clock signal synchronized with a clock signal on the transmission side on the reception side have been proposed. For example, in Patent Document 1, the phase variation amount of a pilot signal within one symbol is calculated, and the clock signal is controlled based on the phase variation amount to synchronize the clock signal with the transmission side clock signal. Thus, a technique for reproducing the clock signal on the transmission side on the reception side is disclosed.

JP 2002-94480 A

  In the technique of Patent Document 1, since the influence of multipath is not taken into consideration, the frequency of the clock signal cannot be appropriately controlled.

  Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of appropriately controlling the frequency of a clock signal used in an OFDM receiver.

  The first clock signal control circuit according to the present invention is used when performing discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM. A clock signal control circuit for controlling a frequency of a clock signal to be generated, each of a plurality of pilot signals in the same symbol period based on a demodulated signal obtained by performing a discrete Fourier transform on the digital signal A calculation circuit for calculating a power value and a phase fluctuation amount between a pilot signal having the lowest frequency and a pilot signal having the highest frequency in the pilot signal having the power value within a predetermined range among the plurality of pilot signals. Phase fluctuation amount calculation circuit and control circuit for controlling the frequency of the clock signal based on the phase fluctuation amount Equipped with a.

  The second clock signal control circuit according to the present invention performs discrete Fourier transform on a digital signal obtained by analog-digital conversion of an analog baseband signal modulated based on OFDM. A clock signal control circuit for controlling a frequency of a clock signal used for the digital signal, based on a demodulated signal obtained by performing a discrete Fourier transform on the digital signal, and a plurality of pilot signals in the same symbol period A phase between a lowest frequency pilot signal and a highest frequency pilot signal in a calculation circuit for calculating each power value and a pilot signal having the power value larger than a predetermined threshold among the plurality of pilot signals A phase fluctuation amount calculating circuit for calculating a fluctuation amount, and a frequency of the clock signal based on the phase fluctuation amount. And a Gosuru control circuit.

  The third clock signal control circuit according to the present invention performs discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM. A clock signal control circuit for controlling a frequency of a clock signal used for the digital signal, based on a demodulated signal obtained by performing a discrete Fourier transform on the digital signal, and a plurality of pilot signals in the same symbol period A calculation circuit for calculating an amplitude value of each of the I component and the Q component; and among the plurality of pilot signals, the amplitude value of the I component is within a first predetermined range, and the amplitude value of the Q component is 2 calculates a phase fluctuation amount between the pilot signal of the lowest frequency and the pilot signal of the highest frequency in the pilot signal within a predetermined range of 2. Comprising a phase variation amount calculating circuit, and a control circuit for controlling the frequency of the clock signal based on the phase variation amount.

  The fourth clock signal control circuit according to the present invention performs discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM. A clock signal control circuit for controlling a frequency of a clock signal used for the digital signal, based on a demodulated signal obtained by performing a discrete Fourier transform on the digital signal, and a plurality of pilot signals in the same symbol period A calculation circuit for calculating an amplitude value of each I component and Q component; and among the plurality of pilot signals, an amplitude value of the I component is greater than a first threshold value, and an amplitude value of the Q component is In the pilot signal larger than the second threshold, the amount of phase fluctuation between the lowest frequency pilot signal and the highest frequency pilot signal is Comprising a phase variation calculating circuit for output, and a control circuit for controlling the frequency of the clock signal based on the phase variation amount.

  The fifth clock signal control circuit according to the present invention performs discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM. A clock signal control circuit for controlling a frequency of a clock signal used for the digital signal, based on a demodulated signal obtained by performing a discrete Fourier transform on the digital signal, and a plurality of pilot signals in the same symbol period Based on a calculation circuit for calculating each power value and a frequency and phase error of a pilot signal having the power value within a predetermined range among the plurality of pilot signals, the pilot signal having the power value within the predetermined range Phase fluctuation rate with respect to frequency change between the plurality of pilot signals is calculated based on the phase fluctuation rate. A phase fluctuation amount calculating circuit for calculating a phase fluctuation amount caused by a frequency error of the clock signal between the lowest frequency and the highest frequency pilot signal, and controlling the frequency of the clock signal based on the phase fluctuation amount A control circuit.

  The sixth clock signal control circuit according to the present invention performs discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM. A clock signal control circuit for controlling a frequency of a clock signal used for the digital signal, based on a demodulated signal obtained by performing a discrete Fourier transform on the digital signal, and a plurality of pilot signals in the same symbol period Based on a calculation circuit for calculating each power value, and a frequency and phase error of a pilot signal in which the power value is greater than a predetermined threshold value among the plurality of pilot signals, the power value is a predetermined threshold value. Calculating a phase variation rate with respect to a frequency change between pilot signals larger than that, and based on the phase variation rate, A phase fluctuation amount calculating circuit for calculating a phase fluctuation amount due to a frequency error of the clock signal between the lowest frequency and the highest frequency pilot signal in the pilot signal; and the frequency of the clock signal based on the phase fluctuation amount And a control circuit for controlling.

  The seventh clock signal control circuit according to the present invention performs discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM. A clock signal control circuit for controlling a frequency of a clock signal used for the digital signal, based on a demodulated signal obtained by performing a discrete Fourier transform on the digital signal, and a plurality of pilot signals in the same symbol period A calculation circuit for calculating an amplitude value of each of the I component and the Q component; and among the plurality of pilot signals, the amplitude value of the I component is within a first predetermined range, and the amplitude value of the Q component is 2 based on the frequency and phase error of the pilot signal within a predetermined range of 2, the amplitude value of the I component is within the first predetermined range, and the Q component of A phase fluctuation rate with respect to a frequency change between pilot signals having a width value within the second predetermined range is calculated, and based on the phase fluctuation rate, the lowest frequency and the highest frequency pilot signal in the plurality of pilot signals are calculated. And a control circuit for controlling the frequency of the clock signal based on the phase fluctuation amount.

  The eighth clock signal control circuit according to the present invention performs discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM. A clock signal control circuit for controlling a frequency of a clock signal used for the digital signal, based on a demodulated signal obtained by performing a discrete Fourier transform on the digital signal, and a plurality of pilot signals in the same symbol period A calculation circuit for calculating an amplitude value of each I component and Q component; and among the plurality of pilot signals, an amplitude value of the I component is greater than a first threshold value, and an amplitude value of the Q component is Based on the pilot signal frequency and phase error greater than the second threshold, the amplitude value of the I component is greater than the first threshold, and Calculating a phase variation rate with respect to a frequency change between pilot signals in which the amplitude value of the Q component is larger than the second threshold, and based on the phase variation rate, the lowest frequency and the highest frequency in the plurality of pilot signals A phase fluctuation amount calculating circuit for calculating a phase fluctuation amount caused by a frequency error of the clock signal between pilot signals of a frequency, and a control circuit for controlling the frequency of the clock signal based on the phase fluctuation amount. Prepare.

  An OFDM receiver according to the present invention includes any one of the first to eighth clock signal control circuits described above, a clock signal oscillator that generates the clock signal, and a receiving antenna that receives an OFDM signal that is a radio signal. A multiplication circuit that multiplies the OFDM signal by a main carrier frequency signal to generate the baseband signal, an analog / digital conversion circuit that converts the baseband signal into the digital signal, and the clock signal. A fast Fourier transform circuit that performs discrete Fourier transform on the digital signal to generate the demodulated signal.

  According to the first clock signal control circuit of the present invention and the OFDM receiver including the first clock signal control circuit, the lowest of pilot signals having a power value within a predetermined range among pilot signals in the same symbol period. Since the frequency of the clock signal is controlled based on the amount of phase fluctuation between the pilot signal of the frequency and the pilot signal of the highest frequency, the frequency of the clock signal can be controlled without the influence of multipath.

  Further, according to the second clock signal control circuit and the OFDM receiver including the second clock signal control circuit of the present invention, the power value of a plurality of pilot signals in the same symbol period exceeds a predetermined threshold value. Since the phase fluctuation amount between the pilot signal of the lowest frequency and the pilot signal of the highest frequency is calculated in the pilot signal that is larger, the frequency of the clock signal can be controlled by eliminating the influence of multipath to some extent. .

  In addition, according to the third clock signal control circuit and the OFDM receiver including the third clock signal control circuit of the present invention, the amplitude value of the I component of the pilot signal in the same symbol period is the first predetermined value. The frequency of the clock signal is determined based on the amount of phase fluctuation between the pilot signal with the lowest frequency and the pilot signal with the highest frequency in the pilot signal with the amplitude value of the Q component within the second predetermined range. Therefore, the frequency of the clock signal can be controlled without the influence of multipath.

  Further, according to the fourth clock signal control circuit and the OFDM receiver including the fourth clock signal control circuit of the present invention, the amplitude value of the I component of the pilot signal in the same symbol period is the first value. Based on the amount of phase variation between the pilot signal of the lowest frequency and the pilot signal of the highest frequency in the pilot signal that is larger than the threshold value and the amplitude value of the Q component is larger than the second threshold value, Since the frequency is controlled, the frequency of the clock signal can be controlled by eliminating the influence of multipath to some extent.

  Further, according to the fifth clock signal control circuit of the present invention and the OFDM receiver having the fifth clock signal control circuit, when controlling the frequency of the clock signal, the pilot signal in the same symbol period Since the phase error of the pilot signal whose power value is within the predetermined range is used, the frequency of the clock signal can be controlled without the influence of multipath.

  Further, according to the sixth clock signal control circuit and the OFDM receiver including the sixth clock signal control circuit of the present invention, when controlling the frequency of the clock signal, the pilot signal in the same symbol period Since the phase error of the pilot signal whose power value is larger than a predetermined threshold is used, the frequency of the clock signal can be controlled without the influence of multipath.

  Further, according to the seventh clock signal control circuit of the present invention and the OFDM receiver including the seventh clock signal control circuit, when controlling the frequency of the clock signal, the pilot signal in the same symbol period Since the phase error of the pilot signal with the amplitude value of the I component being in the first predetermined range and the amplitude value of the Q component being in the second predetermined range is used, the influence of multipath is eliminated. Thus, the frequency of the clock signal can be controlled.

  Further, according to the eighth clock signal control circuit of the present invention and the OFDM receiver including the eighth clock signal control circuit, when controlling the frequency of the clock signal, the pilot signal in the same symbol period Since the phase error of the pilot signal in which the amplitude value of the I component is larger than the first threshold value and the amplitude value of the Q component is larger than the second threshold value is used, the influence of multipath is reduced. The frequency of the clock signal can be controlled by eliminating it.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of an OFDM receiver according to Embodiment 1 of the present invention. As shown in FIG. 1, the OFDM receiver according to the first embodiment includes a reception antenna 101, a multiplication circuit 102, a main carrier oscillation circuit 103, a band pass filter (BPF) 104, analog / digital ( A / D) conversion circuit 105, subcarrier frequency signal demodulation circuit 120, clock signal oscillator 116, and clock signal control circuit 130 are provided.

  The subcarrier frequency signal demodulation circuit 120 includes a demultiplexer 106, low-pass filters (LPF) 107 and 108, a complex multiplication circuit 109, a numerically controlled oscillation circuit (NCO) 110, an addition circuit 111, and a fast Fourier transform circuit ( FFT) 112, a correlation value calculation circuit 113, and a carrier frequency error calculation circuit 114.

  The clock signal oscillator 116 has, for example, a VCXO (Voltage Controlled Xtal Oscillator), and the clock signal CLK generated by the clock signal oscillator 116 is used to regenerate the clock signal used when the subcarrier is modulated on the transmission side. Signal. The frequency of the clock signal CLK generated by the clock signal oscillator 116 is controlled by the control signal CS output from the clock signal control circuit 130.

  The receiving antenna 101 receives an OFDM signal that is a radio signal. The multiplication circuit 102 multiplies the main carrier frequency signal output from the main carrier oscillation circuit 103 and the OFDM signal received by the receiving antenna 101 and outputs the result. The main carrier oscillation circuit 103 outputs, as a main carrier frequency signal, a sine wave signal having the same frequency as the main carrier used when generating the OFDM signal on the transmission side. An output signal from the multiplication circuit 102 is input to the analog / digital conversion circuit 105 through the band pass filter 104. As a result, a baseband signal having a frequency band occupied by a plurality of subcarriers is extracted from the output signal of the multiplication circuit 102 and input to the analog / digital conversion circuit 105. The baseband signal is configured by adding a plurality of subcarriers modulated by PSK modulation or the like.

  The analog / digital conversion circuit 105 samples the baseband signal of the analog signal using the clock signal CLK output from the clock signal oscillator 116, and converts the baseband signal of the analog signal into the baseband signal BS of the digital signal. And output. The demultiplexer 106 separates the baseband signal BS into I channel data XI and Q channel data XQ and outputs the separated data. The low-pass filter 107 outputs the I channel data XI after removing unnecessary high frequency components included therein, and the low pass filter 108 outputs the Q channel data XQ after removing unnecessary high frequency components included therein. To do.

  The complex multiplication circuit 109 performs complex multiplication on the I channel data CI and Q channel data CQ output from the numerical control oscillation circuit 110 and the I channel data XI and Q channel data XQ processed by the low-pass filters 107 and 108. The data obtained thereby is separated into I channel data TIR and Q channel data TQR and output.

  The numerically controlled oscillation circuit 110 separates and outputs a correction sine wave signal for removing a frequency error common to each subcarrier included in the baseband signal BS into I channel data CI and Q channel data CQ. The numerically controlled oscillation circuit 110 controls the frequency of the correction sine wave signal based on the output signal of the adder circuit 111. Thereby, in the complex multiplication circuit 109, the frequency error of each subcarrier included in the baseband signal BS is removed, and from the complex multiplication circuit 109, the I component and the Q component of the baseband signal BS after frequency correction are respectively set to I. Output as channel data TIR and Q channel data TQR.

  Correlation value calculation circuit 113 receives I channel data TIR and Q channel data TQR and uses them as they are and data delayed by an effective symbol period, and is separated from each other by an effective symbol period. The correlation value COR between the baseband signals BS is calculated and output.

  The fast Fourier transform circuit 112 operates in synchronization with the clock signal CLK, and based on the I channel data TIR and Q channel data TQR output from the complex multiplication circuit 109, the baseband signal of the digital signal after frequency correction A discrete Fourier transform is performed on the BS, and the demodulated signal obtained thereby is separated into I channel demodulated data IR and Q channel demodulated data QR and output. The fast Fourier transform circuit 112 sets a time window for executing discrete Fourier transform using the clock signal CLK.

  Here, the time window that defines the range of transform when performing discrete Fourier transform will deviate from the original position if there is a frequency error in the clock signal CLK. When there is a frequency error in the clock signal CLK, a position shift that differs for each OFDM symbol occurs in the time window. Therefore, in this case, a phase rotation that varies with time is given to the phase of each subcarrier. When the time window is shifted from the original position by a certain time, a phase error proportional to the frequency is generated in each subcarrier during the same symbol period.

  In the first embodiment, as will be described later, the frequency of the clock signal CLK is appropriately controlled by the clock signal control circuit 130, thereby eliminating the frequency error included in the clock signal CLK. As a result, the time window in the fast Fourier transform circuit 112 can be set appropriately, and an accurate demodulated signal can be obtained.

  The carrier frequency error calculation circuit 114 detects the phase error of the pilot signal included in the baseband signal BS based on the I channel demodulated data IR and the Q channel demodulated data QR, and based on the phase error, the baseband signal The subcarrier frequency error DF included in the BS is obtained and output to the adder circuit 111. Since the phase of the pilot signal is known, the frequency error DF of the subcarrier included in the baseband signal BS can be calculated by detecting the phase error.

  The addition circuit 111 adds the correlation value COR output from the correlation value calculation circuit 113 and the frequency error DF output from the carrier frequency error calculation circuit 114, and supplies the result to the numerically controlled oscillation circuit 110.

  Here, in the OFDM symbol, a signal having the same content as that of a part near the end of the effective symbol is added to the head of the effective symbol, and the time length of the added signal is called a guard interval period. Therefore, the guard interval period appears in the period of the symbol period.

  Thus, since the signal in the guard interval period has the same content as a part near the end of the effective symbol, if the subcarrier of the baseband signal BS does not include a frequency error, the baseband signal BS and The correlation value COR with the baseband signal BS delayed by the effective symbol period takes a peak value every symbol period. On the other hand, when a frequency error is included in the subcarrier of the baseband signal BS, the correlation value COR does not show a peak value and is always a small value.

  Therefore, in the first embodiment, the frequency of the correction sine wave signal of the numerically controlled oscillation circuit 110 is controlled based on the correlation value COR and the frequency error DF so that the correlation value COR takes a peak value. Thereby, the frequency error of each subcarrier of baseband signal BS can be removed appropriately. For example, assuming that the frequency error of each subcarrier of the baseband signal BS is Δf, the numerically controlled oscillation circuit 110 calculates a correction sine wave signal as COS (2π (−Δf) t) + jsin (2π (−Δf) t). The frequency is controlled so that

  Further, the correlation value calculation circuit 113 according to the first embodiment makes the fast Fourier transform circuit 112 start the discrete Fourier transform at the timing when the correlation value COR reaches the peak value, so that the frequency error of the demodulated signal is minimized. can do.

  FIG. 2 is a block diagram showing a configuration of the clock signal control circuit 130. As shown in FIG. 2, the clock signal control circuit 130 determines the power value of each of a plurality of pilot signals in the same symbol period for each symbol period based on the I channel demodulated data IR and the Q channel demodulated data QR. And a calculation circuit 90 for calculating the minimum frequency pilot signal and the maximum frequency pilot signal in a pilot signal having a power value within a predetermined range among a plurality of pilot signals in the same symbol period for each symbol period. And a control circuit 80 for controlling the frequency of the clock signal CLK based on the phase fluctuation amount calculated by the phase fluctuation amount calculation circuit 70.

  The calculation circuit 90 includes selectors 30 and 40 and a signal level calculation circuit 17. The phase variation calculation circuit 70 includes switch circuits 18 and 19, RAMs 6 and 7, a sign inversion circuit 10, a complex multiplication circuit 11, a ROM 12, and a cumulative addition circuit 15. The control circuit 80 includes an offset addition circuit 16, a loop filter 50, and a clock oscillation control circuit 60.

  Selector 30 selects only data corresponding to a pilot signal (pilot symbol) from I-channel demodulated data IR, and outputs it as data PIR, and transmits to data PIR output from switch circuit 31. A phase correction circuit 32 that performs correction according to the phase defined on the side and outputs corrected data PIR. Similarly, the selector 40 selects only data corresponding to the pilot signal from the Q channel demodulated data QR and outputs it as data PQR, and the transmission side for the data PQR output from the switch circuit 41 And a phase correction circuit 42 that performs correction in accordance with the phase defined in (1) and outputs corrected data PQR.

  The phase defined on the transmission side is, for example, a phase defined in the Japanese digital terrestrial broadcasting standard. In the Japanese digital terrestrial broadcasting standard, the amplitude and phase of the pilot signal (the amplitude and phase on the IQ plane) are specified in advance on the transmission side, and the specified values are known on the reception side. . As a specific example, when the phase of the pilot signal is defined as 0 or π on the transmission side, the reception side recognizes in advance whether the phase of the received pilot signal is 0 or π. When the phase of the pilot signal is π, the phase correction circuits 32 and 42 correct the data PIR and PQR, respectively, so that the phase of the pilot signal is subtracted by π as a result. Thereby, the phase of each pilot signal becomes zero if the phase error is not taken into consideration.

  The signal level calculation circuit 17 calculates the power value of each pilot signal based on the corrected data PIR and PQR.

  Based on the calculation result of the signal level calculation circuit 17, the switch circuit 18 selects only the data corresponding to the pilot signal whose power value is within the predetermined range from the corrected data PIR and uses it as the data IRP. Output. From the switch circuit 18, a plurality of data IRPs within the same symbol period are output in series in order from the lowest pilot signal frequency for each symbol period.

  Similarly, the switch circuit 19 selects only the data corresponding to the pilot signal whose power value is within the predetermined range from the corrected data PQR based on the calculation result in the signal level calculation circuit 17, and selects the data as the data Output as QRP. From the switch circuit 19, a plurality of data PIRs within the same symbol period are output in series in order from the lowest pilot signal frequency for each symbol period.

  The RAM 6 stores data IRP input from the switch circuit 18. When the next data IRP is input, the RAM 6 stores it, and outputs the already stored data IRP as delay data dIRP. Therefore, the delay data dIRP is data IRP corresponding to the pilot signal having a frequency lower than the frequency of the pilot signal corresponding to the data IRP currently output from the switch circuit 18 and having the frequency closest thereto. The RAM 6 performs this operation every time data IRP is input.

  Similarly, the RAM 7 stores data QRP input from the switch circuit 19. When the next data QRP is input, the RAM 7 stores it and outputs the already stored data QRP as delay data dQRP. Therefore, the delay data dQRP is data QRP corresponding to the pilot signal having a frequency lower than the frequency of the pilot signal corresponding to the data QRP currently output from the switch circuit 19 and having the frequency closest thereto. The RAM 7 performs this operation every time data QRP is input. The sign inversion circuit 10 inverts the sign of the delay data dQRP and outputs it as delay data -dQRP.

  The complex multiplication circuit 11 calculates (IRP + jQRP) · (dIRP−jdQRP) from the data IRP, QRP and the delay data dIRP, −dQRP, and the real number component and the imaginary number component of the calculation result are the real number component data RN and the imaginary number component, respectively. Output as data JN.

  The ROM 12 stores arctangent data. The ROM 12 uses the arc tangent data stored therein and the real number component data RN and the imaginary number component data JN output from the complex multiplication circuit 11 to use a plurality of pilots whose power values are within a predetermined range during the same symbol period. In the signal, a difference in phase error between two pilot signals having adjacent frequencies, that is, a phase fluctuation amount PS is obtained and output.

  The cumulative addition circuit 15 accumulates and adds the phase fluctuation amount PS output from the ROM 12 over one symbol period in the same symbol period, and outputs the addition result as a cumulative addition value PS1. As a result, the cumulative addition circuit 15 cumulatively adds the phase fluctuation amount between the pilot signal with the lowest frequency and the pilot signal with the highest frequency among the plurality of pilot signals having the power value within the predetermined range in the same symbol period. It is determined as the value PS1. The cumulative addition circuit 15 performs this process for each symbol period.

  The offset addition circuit 16 adds the offset value to the cumulative addition value PS1, and outputs the result as an error value PS2. The loop filter 50 removes a noise component from the error value PS2, and outputs the filtered error value PS2 as an error value PS3. The clock oscillation control circuit 60 generates a control signal CS corresponding to the error value PS3 and outputs it to the clock signal oscillator 116.

  As described above, the analog / digital conversion circuit 105, the subcarrier frequency signal demodulation circuit 120, the clock signal control circuit 130, and the clock signal oscillator 116 constitute a PLL circuit that controls the frequency of the clock signal CLK. The PLL circuit operates so that the error value PS3 becomes zero. As a result, the frequency of the clock signal CLK can be appropriately controlled without the influence of multipath. Hereinafter, the reason why the frequency of the clock signal CLK is appropriately controlled by the control method according to the first embodiment will be described in detail.

  In the technique of Patent Document 1 described above, when controlling the frequency of the clock signal CLK, all pilot signals within the same symbol period are used. Normally, an OFDM signal received by an OFDM receiver is affected by multipath, and therefore, when the clock signal CLK has a frequency error, unlike the state shown in FIG. However, the phase error of the pilot signal does not always change linearly according to the frequency. Therefore, when all pilot signals within the same symbol period are used, the influence of multipath cannot be eliminated and the frequency of the clock signal CLK cannot be controlled appropriately.

For example, when the clock signal is shifted by Δt with respect to the main signal in time and a signal with a gain α that is delayed from the main signal by time t _m exists as a multipath, the amplitude of the main signal is normalized to 1. The transmission characteristic h _d (2πf) (f is the frequency of the main signal) can be expressed by the following equation.

  However, ω = 2πf.

Therefore, the phase error θ _m given by the multipath to the received OFDM signal can be expressed by the following equation.

FIG. 3 is a diagram showing the relationship between the phase error θ _m caused by multipath and the frequency f of the main signal. As shown in FIG. 3, a phase distortion that repeats periodically according to the frequency f is added to the received OFDM signal. Therefore, the phase of each received subcarrier includes a phase error θ _m caused by multipath. Therefore, when a frequency error occurs in the clock signal CLK, the phase error of the pilot signal does not change linearly in accordance with the frequency within the same symbol period, and all pilot signals within the same symbol period are changed. If it is used, the influence of the phase error θ _m caused by multipath cannot be eliminated, and an error remains in the frequency of the clock signal CLK.

Here, when the phase error θ _m is n × π (n is an integer), it can be considered that there is no multipath effect. The condition for the phase error θ _m = nπ is α sin (2πft _m ) = 0. In this case, t _m = n / (2f). When the multipath delay time t _m satisfies this condition, the multipath effect becomes zero.

The midpoint of the frequency at which the multipath effect becomes zero, that is, the midpoint of f = 0 / (2t _m ), 1 / (2t _m ), 2 / (2t _m ), 3 / (2t _m ) is f _{= 1 / (4t m),} 3 / (4t m), a 5 / (4t _m).

When f = 1 / (4t _m ), the phase error θ _m is as follows.

When f = 3 / (4t _m ), the phase error θ _m is as follows.

When f = 5 / (4t _m ), the phase error θ _m is as follows.

From the above, the phase error θ _m is a periodic function with a period of 1 / t _m .

On the other hand, the amplitude component | h _d (2πf) | shown in the above equation (1) is also a periodic function with a period 1 / t _m taking a value within (1 ± α). Therefore, it can be said that the influence of the phases on the pilot signals having the same power value is almost the same.

In the phase fluctuation amount calculation circuit 70 according to the first embodiment, as described above, among the plurality of pilot signals in the same symbol period, the pilot signal whose power value is within the predetermined range, that is, the influence from the multipath. Since the amount of phase fluctuation between pilot signals received almost equally is calculated, it is possible to control the frequency of the clock signal CLK by removing the influence of the phase error θ _m caused by multipath. Hereinafter, the operation of the phase variation calculation circuit 70 will be described in more detail.

  FIG. 4 is a diagram for explaining the operation of the phase variation calculation circuit 70 when the clock signal CLK includes a frequency error. FIG. 4A is a diagram showing a plurality of pilot signals SP0 to SP4 included in the same symbol period, with the horizontal axis indicating the frequency and the vertical axis indicating the power value. FIG. 4B is a diagram illustrating the phase error included in each of the pilot signals SP0 to SP4, where the horizontal axis indicates the frequency and the vertical axis indicates the phase error.

  As shown in FIG. 4 (a), in a plurality of pilot signals within the same symbol period, the power value should be essentially constant, but the power value is changed due to the influence of multipath. . Further, as shown in FIG. 4B, the phase error of the pilot signal is also affected by the multipath and does not change linearly according to the frequency.

In the first embodiment, in the phase fluctuation amount calculation circuit 70, the power value of the plurality of pilot signals SP0 to SP4 in the same symbol period is equal to or higher than the first threshold value TH1 and the second threshold value. The amount of phase fluctuation between pilot signals SP0, SP1, and SP4 that is equal to or less than TH2 is calculated. Specifically, among the pilot signals SP0, SP1, and SP4 whose power values are within a predetermined range within the same symbol period, first, the difference between the phase error θ1 of the pilot signal SP1 and the phase error θ0 of the pilot signal SP0. (Θ1-θ0) is calculated as the phase fluctuation amount 81 (phase fluctuation amount PS). At this time, since the phase error θ _m caused by the multipath is substantially equal between the pilot signals SP0 and SP1, the influence of the phase error θ _m is removed from the phase fluctuation amount 81 by obtaining (θ1−θ0). be able to. Then, the difference (θ4−θ1) between the phase error θ4 of the pilot signal SP4 and the phase error θ1 of the pilot signal SP1 is calculated as the phase fluctuation amount 84 (phase fluctuation amount PS). Also at this time, the phase error θ _m caused by the multipath is substantially equal between the pilot signals SP1 and SP4, so that the influence of the phase error θ _m is removed from the phase fluctuation amount 84 by obtaining (θ4−θ1). can do. Then, in the cumulative addition circuit 15, the phase fluctuation amount 81 and the phase fluctuation amount 84 are added, and the result becomes the cumulative addition value PS1.

  In the first embodiment, the phase fluctuation amount 81 and the phase fluctuation amount 84 are added. This is the lowest of the pilot signals SP0, SP1, SP4 whose power values are within a predetermined range in the same symbol period. This is equivalent to obtaining the phase fluctuation amount 85 between the pilot signal SP0 having the frequency and the pilot signal SP4 having the highest frequency. Therefore, the cumulative addition value PS1 indicates the phase fluctuation amount 85 between the pilot signal SP0 having the lowest frequency and the pilot signal SP4 having the highest frequency.

Thus, the phase fluctuation amount 85 between the pilot signal SP0 having the lowest frequency and the pilot signal SP4 having the highest frequency among the pilot signals SP0, SP1 and SP4 having the power value within the predetermined range in the same symbol period is obtained. Thus, the influence of the phase error θ _m caused by the multipath can be removed from the phase fluctuation amount 85. Therefore, by controlling the frequency of the clock signal CLK based on the phase fluctuation amount 85, the frequency of the clock signal CLK can be appropriately controlled by eliminating the influence of multipath.

  Further, when the S / N ratio of the pilot signal deteriorates, the power value thereof decreases. Therefore, by not using a pilot signal whose power value is smaller than the first threshold value TH1, a pilot signal having a poor S / N ratio is eliminated. Thus, the phase fluctuation amount 85 can be obtained. Therefore, the detection accuracy of the phase fluctuation amount 85 is improved, and the frequency of the clock signal CLK can be controlled appropriately.

  FIG. 5 is a flowchart showing the operation of the OFDM receiver according to the first embodiment. As shown in FIG. 5, in step s 1, data PIR and PQR corresponding to the pilot signal are selected by selectors 30 and 40 from I channel demodulated data IR and Q channel demodulated data QR.

  Next, in step s2, the signal level calculation circuit 17 calculates the power value of each pilot signal based on the data PIR and PQR selected by the selectors 30 and 40.

  Next, in step s3, the data IRP, QRP corresponding to the pilot signal whose power value is within a predetermined range is selected by the switch circuits 18, 19 from the data PIR, PQR.

  In step s4, data IRP and QRP are stored in RAMs 6 and 7, respectively. When the data IRP and data QRP corresponding to the next pilot signal are respectively input, the RAMs 6 and 7 output the stored data IRP and QRP, respectively. That is, the RAM 6 delays the stored data IRP by a time corresponding to the generation interval of the pilot signal whose power value is within the predetermined range and outputs it as the delayed data dIRP, and the RAM 7 outputs the stored data QRP to the power value Are delayed by a time corresponding to the generation interval of pilot signals within a predetermined range, and output as delayed data dQRP. The delay data dQRP output from the RAM 7 is inverted in sign by the sign inversion circuit 10 and input to the complex multiplication circuit 11 as delay data -dQRP.

  Next, in step s5, the complex multiplication circuit 11 performs complex multiplication based on the data IRP, QRP and the delay data dIRP, -dQRP. The calculation result of the complex multiplication circuit 11 is separated into real number component data RN and imaginary number component data JN and output from the complex multiplication circuit 11. In the ROM 12, based on the real number component data RN and the imaginary number component data JN, the phase variation PS between the pilot signals whose frequencies are adjacent to each other in a plurality of pilot signals having the power value within a predetermined range within the same symbol period. Is required.

  Next, in step s6, in the cumulative addition circuit 15, the phase fluctuation amount PS output from the ROM 12 is cumulatively added over one symbol period within the same symbol period. When the cumulative addition over one symbol period is completed, the cumulative addition circuit 15 outputs the cumulative addition value PS1 and initializes the internal cumulative addition value PS1. The cumulative addition circuit 15 outputs a cumulative addition value PS1 for each symbol period.

  Next, in step s7, the offset addition circuit 16 adds the offset value to the cumulative addition value PS1, and the result is output from the offset addition circuit 16 as an error value PS2.

  Here, the position and width of the time window in the fast Fourier transform circuit 112 are ideally set so that only effective symbols are included in the OFDM symbols. When the position of the time window is shifted backward on the time axis, the data of the first half of the effective symbol protrudes from the time window, and the data of the guard interval period in the next adjacent OFDM symbol is included in the time window. Will end up.

  In this case, in the fast Fourier transform circuit 112, the data of the next adjacent OFDM symbol is processed in place of the original data, resulting in intersymbol interference in the demodulated signal obtained by the discrete Fourier transform. Thus, the bit error rate of the demodulated signal is greatly affected.

  Therefore, in the first embodiment, the offset addition circuit 16 adds the offset value to the cumulative addition value PS1, so that the time window is shifted backward even when the frequency error remains in the clock signal CLK. The position of the time window is set in advance ahead of the original position so as not to be present.

  Next, in step s8, the error value PS2 is supplied to the loop filter 50, and is output from the loop filter 50 as an error value PS3 from which unnecessary noise components are removed.

  In step s9, the clock oscillation control circuit 60 generates and outputs a control signal CS corresponding to the error value PS3.

  As described above, in the first embodiment, among the pilot signals in the same symbol period, the phase between the lowest frequency pilot signal and the highest frequency pilot signal in the pilot signal having a power value within a predetermined range. Since the frequency of the clock signal CLK is controlled based on the fluctuation amount, the frequency of the clock signal CLK can be controlled without the influence of multipath. Further, since the phase fluctuation amount can be calculated by eliminating the pilot signal having a poor S / N ratio, the detection accuracy of the phase fluctuation amount is improved. Therefore, the frequency of the clock signal CLK can be appropriately controlled. As a result, the pull-in performance of the clock signal CLK can be improved.

Embodiment 2. FIG.
In Embodiment 1 described above, a pilot signal having a power value within a predetermined range is used among a plurality of pilot signals in the same symbol period. However, a pilot signal having a power value larger than a predetermined threshold value is used. May be used. Specifically, the switch circuit 18 selects only data corresponding to a pilot signal whose power value is larger than a predetermined threshold value from the corrected data PIR, and sets this as data IRP. Further, the switch circuit 19 selects only data corresponding to a pilot signal whose power value is larger than a predetermined threshold value from the corrected data PQR, and sets this as data QRP. The subsequent processing is the same as in the first embodiment.

  Thereby, in the phase fluctuation amount calculation circuit 70, the pilot signal having the lowest frequency and the pilot signal having the highest frequency among the pilot signals having a power value larger than a predetermined threshold among the plurality of pilot signals in the same symbol period. Is calculated as the cumulative addition value PS1, and the control circuit 80 controls the frequency of the clock signal CLK based on the cumulative addition value PS1.

  As described above, among pilot signals in the same symbol period, when a pilot signal having a power value larger than a predetermined threshold is used, it is compared with a case where all pilot signals are used as in the prior art. Thus, the frequency of the clock signal CLK can be controlled by eliminating the influence of multipath to some extent.

  Further, as described above, when the S / N ratio of the pilot signal deteriorates, the power value thereof decreases, so that a demodulated signal having a poor S / N ratio is used by using a pilot signal having a power value larger than a predetermined threshold value. The amount of phase fluctuation can be obtained by eliminating. Therefore, the detection accuracy of the phase fluctuation amount is improved, and the frequency of the clock signal CLK can be controlled appropriately.

Embodiment 3 FIG.
In Embodiment 1 described above, among the pilot signals in the same symbol period, the pilot signal whose power value is within the predetermined range is used. However, the amplitude values of the I component and the Q component are within the predetermined range, respectively. A certain pilot signal may be used. Specifically, the signal level calculation circuit 17 obtains the amplitude value of the I component of each pilot signal based on the corrected data PIR, and the amplitude value of the Q component of each pilot signal based on the corrected data PQR. Ask for. Then, the switch circuit 18 selects only the data corresponding to the pilot signal whose amplitude value of the I component is within the first predetermined range from the corrected data PIR, and sets this as data IRP. Further, the switch circuit 19 selects only data corresponding to a pilot signal having an amplitude value of the Q component within the second predetermined range from the corrected data PQR, and sets this as data QRP. The subsequent processing is the same as in the first embodiment.

  Thereby, in the phase fluctuation amount calculation circuit 70, the amplitude value of the I component is within the first predetermined range and the amplitude value of the Q component is the second predetermined value among the plurality of pilot signals in the same symbol period. In the pilot signal within the range, the phase fluctuation amount between the pilot signal with the lowest frequency and the pilot signal with the highest frequency is calculated as the cumulative addition value PS1. Then, the control circuit 80 controls the frequency of the clock signal CLK based on the cumulative addition value PS1.

  As described above, among the plurality of pilot signals in the same symbol period, the pilot signal having the I component amplitude value within the first predetermined range and the Q component amplitude value within the second predetermined range is used. Even if it is a case, the effect similar to Embodiment 1 can be acquired. Note that the first and second predetermined ranges may be the same range or different ranges.

Embodiment 4 FIG.
In Embodiment 2 described above, a pilot signal having a power value greater than a predetermined threshold value among the plurality of pilot signals in the same symbol period is used, but the amplitude value of the I component is the first threshold value. A pilot signal that is larger than the value and whose Q component amplitude value is larger than the second threshold value may be used. Specifically, the signal level calculation circuit 17 obtains the amplitude value of the I component of each pilot signal based on the corrected data PIR, and the amplitude value of the Q component of each pilot signal based on the corrected data PQR. Ask for. Then, the switch circuit 18 selects only data corresponding to the pilot signal whose amplitude value of the I component is larger than the first threshold value from the corrected data PIR, and sets this as data IRP. Further, the switch circuit 19 selects only data corresponding to a pilot signal whose amplitude value of the Q component is larger than the second threshold value from the corrected data PQR, and sets this as data QRP. The subsequent processing is the same as in the first embodiment.

  Thereby, in the phase fluctuation amount calculation circuit 70, the amplitude value of the I component is larger than the first threshold value and the amplitude value of the Q component is the second value among the plurality of pilot signals in the same symbol period. For a pilot signal larger than the threshold value, the amount of phase fluctuation between the lowest frequency pilot signal and the highest frequency pilot signal is calculated as the cumulative addition value PS1. Then, the control circuit 80 controls the frequency of the clock signal CLK based on the cumulative addition value PS1.

  As described above, among the plurality of pilot signals in the same symbol period, a pilot signal in which the amplitude value of the I component is larger than the first threshold value and the amplitude value of the Q component is larger than the second threshold value. Even if it is used, the same effect as in the second embodiment can be obtained. The first and second threshold values may be the same value or different values.

Embodiment 5 FIG.
In Embodiment 1 described above, a pilot signal having a power value within a predetermined range is selected from a plurality of pilot signals in the same symbol period. When the selected pilot signal includes a pilot signal in the high frequency range and a pilot signal in the low frequency range, the cumulative addition value PS1 obtained by the cumulative addition circuit 15 is within the same symbol period. The maximum phase fluctuation amount due to the frequency error of the clock signal CLK between the plurality of pilot signals, that is, the phase fluctuation amount due to the frequency error of the clock signal CLK between the pilot signals of the lowest frequency and the highest frequency. Match or close to it. By controlling the frequency of the clock signal CLK based on the cumulative addition value PS1, the frequency can be accurately controlled.

For example, when the selected pilot signal includes pilot signals SP0 and SP4 having the lowest frequency and the highest frequency in the symbol period as in the example of FIG. accumulated value PS1 is between pilot signals SP0, SP4, the phase variation amount due to the frequency error of the clock signal CLK, and that is the effect of the phase error theta _m due to multipath is removed, the pilot signals SP0, By controlling the frequency of the clock signal CLK based on the cumulative addition value PS1, the frequency can be accurately controlled.

  On the other hand, if the selected pilot signal generally does not include a high frequency region pilot signal or a low frequency region pilot signal generally, The cumulative addition value PS1 obtained by the cumulative addition circuit 15 is smaller than the maximum phase fluctuation amount caused by the frequency error of the clock signal CLK between a plurality of pilot signals within the same symbol period. When the frequency of the clock signal CLK is controlled based on the value PS1, the frequency cannot be controlled with high accuracy.

  Therefore, the fifth embodiment provides a clock signal control circuit 130 that can control the frequency of the clock signal CLK with higher accuracy.

  FIG. 6 is a block diagram showing a configuration of the clock signal control circuit 130 according to the fifth embodiment. As shown in FIG. 6, the clock signal control circuit 130 according to the fifth embodiment includes a phase fluctuation rate calculation circuit 200 and a fluctuation amount calculation circuit 201 in the clock signal control circuit 130 according to the first embodiment described above. Furthermore, it is provided.

  The phase fluctuation rate calculation circuit 200 is based on the cumulative addition value PS1 obtained by the cumulative addition circuit 15, and in the same symbol period, the phase fluctuation rate α with respect to the frequency change between pilot signals whose power values are within a predetermined range. Is calculated. The fluctuation amount calculation circuit 201 is based on the phase fluctuation rate α, and the phase fluctuation caused by the frequency error of the clock signal CLK between the lowest frequency pilot signal and the highest frequency pilot signal in the plurality of pilot signals within the same symbol period. The amount PS4 is calculated. The offset addition circuit 16 of the control circuit 80 adds the offset value to the phase fluctuation amount PS4 and outputs it as an error value PS2. The subsequent processing in the clock signal control circuit 130 is the same as that in the first embodiment.

  FIG. 7 is a diagram for explaining the operation of the phase variation calculation circuit 70 according to the fifth embodiment. FIG. 7A shows a plurality of pilot signals SP0 to SP4 included in the same symbol period, with the horizontal axis indicating the frequency and the vertical axis indicating the power value. FIG. 7B is a diagram illustrating phase errors included in each of the pilot signals SP0 to SP4, where the horizontal axis indicates the frequency and the vertical axis indicates the phase error.

  As shown in FIG. 7A, among the plurality of pilot signals SP0 to SP4 in the same symbol period, the power values of the pilot signals SP1 to SP3 are equal to or higher than the first threshold value TH1, and the second signal is output. When the threshold value TH2 is equal to or smaller than the threshold value TH2, in the phase fluctuation amount calculation circuit 70, first, the difference (θ2-θ1) between the phase error θ2 of the pilot signal SP2 and the phase error θ1 of the pilot signal SP1 is the phase fluctuation amount. Calculated as 210 (phase fluctuation amount PS). Thereafter, the difference (θ3−θ2) between the phase error θ3 of the pilot signal SP3 and the phase error θ2 of the pilot signal SP2 is calculated as the phase fluctuation amount 211 (phase fluctuation amount PS). Then, in the cumulative addition circuit 15, the phase fluctuation amount 210 and the phase fluctuation amount 211 are added, and the result becomes the cumulative addition value PS1. In the fifth embodiment, the phase fluctuation amount 210 and the phase fluctuation amount 211 are added. This is the lowest of the pilot signals SP1, SP2, and SP3 whose power values are within a predetermined range in the same symbol period. This is equivalent to obtaining the phase fluctuation amount 212 between the pilot signal SP1 having the highest frequency and the pilot signal SP3 having the highest frequency. Therefore, the cumulative addition value PS1 indicates the phase fluctuation amount 212.

  The phase fluctuation rate calculation circuit 200 divides the cumulative addition value PS1 (phase fluctuation amount 212) by a value obtained by subtracting the frequency f1 of the pilot signal SP1 from the frequency f3 of the pilot signal SP3, and the result is set as the phase fluctuation rate α. . That is, the inclination of the straight line 220 in FIG. Here, the straight line 220 is a straight line connecting the coordinates of the pilot signals SP1 to SP3 in a two-dimensional orthogonal coordinate system in which the horizontal axis indicates the frequency of the pilot signal and the vertical axis indicates the phase error of the pilot signal.

The fluctuation amount calculation circuit 201 obtains a phase error θ00 caused by the frequency error of the clock signal CLK in the pilot signal SP0 having the lowest frequency among the pilot signals SP0 to SP4 using the phase fluctuation rate α. As shown in FIG. 7 (b), in the pilot signal SP0, the phase error θ00 due to frequency error of the clock signal CLK, the words phase error θ00 in which the influence of phase error theta _m due to multipath linear Since the frequency f0 of the pilot signal SP0 is known, the phase error θ00 can be easily obtained from the phase fluctuation rate α indicating the slope of the straight line 220.

  Similarly, the fluctuation amount calculation circuit 201 obtains the phase error θ40 resulting from the frequency error of the clock signal CLK in the pilot signal SP4 having the highest frequency among the pilot signals SP0 to SP4 using the phase fluctuation rate α. Thereafter, the fluctuation amount calculation circuit 201 obtains a difference (θ40−θ00) between the phase error θ40 and the phase error θ00 and sets this as the phase fluctuation amount PS4.

  As described above, in the phase variation calculation circuit 70 according to the fifth embodiment, among the plurality of pilot signals in the same symbol period, based on the frequency and phase error of the pilot signal whose power value is within the predetermined range, A phase variation rate α with respect to a frequency change between pilot signals in which the power value is within a predetermined range is calculated. Based on the phase fluctuation rate α, the phase fluctuation amount PS4 caused by the frequency error of the clock signal CLK between the pilot signals of the lowest frequency and the highest frequency in the plurality of pilot signals in the same symbol period is calculated. . The control circuit 80 controls the frequency of the clock signal CLK based on the phase fluctuation amount PS4.

  As described above, in the fifth embodiment, when the frequency of the clock signal CLK is controlled, the phase of the pilot signal whose power value is within the predetermined range in the same symbol period as in the first embodiment described above. Since the error is used, the frequency of the clock signal CLK can be controlled without the influence of multipath. Furthermore, by using the phase error of the pilot signal whose power value is within the predetermined range, it is possible to eliminate the pilot signal having a poor S / N ratio. Therefore, the frequency of the clock signal CLK can be appropriately controlled.

  In addition, based on the phase fluctuation rate α calculated based on the frequency and phase error of the pilot signal whose power value is within the predetermined range, the pilot signal of the lowest frequency and the highest frequency in the plurality of pilot signals within the same symbol period 7 is calculated, and the frequency of the clock signal CLK is controlled based on the phase variation PS4, so that the power value is as shown in the example of FIG. The frequency of the clock signal CLK is accurately controlled even when the pilot signal having a frequency within the predetermined range does not include the lowest frequency and the highest frequency pilot signals in the plurality of pilot signals within the same symbol period. be able to.

  Similarly, in clock signal control circuit 130 according to the second embodiment described above, among the pilot signals in the same symbol period, the frequency of the pilot signal having a power value greater than a predetermined threshold value and Based on the phase error, the phase variation rate α with respect to the frequency change between pilot signals whose power value is larger than a predetermined threshold value may be calculated. Then, based on the obtained phase fluctuation rate α, the phase fluctuation amount PS4 due to the frequency error of the clock signal CLK between the lowest frequency pilot signal and the highest frequency pilot signal in a plurality of pilot signals within the same symbol period is calculated. Then, the frequency of the clock signal CLK may be controlled based on the phase fluctuation amount PS4.

  Similarly, in clock signal control circuit 130 according to Embodiment 3 described above, the amplitude value of the I component is within the first predetermined range among the plurality of pilot signals in the same symbol period, and Based on the frequency and phase error of the pilot signal whose Q component amplitude value is within the second predetermined range, the phase variation rate α for the frequency change between the pilot signals may be calculated. Then, based on the obtained phase fluctuation rate α, the phase fluctuation amount PS4 due to the frequency error of the clock signal CLK between the lowest frequency pilot signal and the highest frequency pilot signal in a plurality of pilot signals within the same symbol period is calculated. Then, the frequency of the clock signal CLK may be controlled based on the phase fluctuation amount PS4.

  Similarly, in the clock signal control circuit 130 according to the above-described fourth embodiment, the amplitude value of the I component among the plurality of pilot signals in the same symbol period is larger than the first threshold value. Further, based on the frequency and phase error of the pilot signal whose Q component amplitude value is larger than the second threshold value, the phase variation rate α with respect to the frequency change between the pilot signals may be calculated. Then, based on the obtained phase fluctuation rate α, the phase fluctuation amount PS4 due to the frequency error of the clock signal CLK between the lowest frequency pilot signal and the highest frequency pilot signal in a plurality of pilot signals within the same symbol period is calculated. Then, the frequency of the clock signal CLK may be controlled based on the phase fluctuation amount PS4.

It is a block diagram which shows the structure of the OFDM receiver which concerns on Embodiment 1 of this invention. 1 is a block diagram illustrating a configuration of a clock signal control circuit according to a first embodiment of the present invention. It is a figure which shows the characteristic of the phase error resulting from a multipath. It is a figure for demonstrating operation | movement of the phase variation calculation circuit which concerns on Embodiment 1 of this invention. 3 is a flowchart showing an operation of the OFDM receiver according to the first embodiment of the present invention. It is a block diagram which shows the structure of the clock signal control circuit which concerns on Embodiment 5 of this invention. It is a figure for demonstrating operation | movement of the phase variation calculation circuit which concerns on Embodiment 5 of this invention.

Explanation of symbols

  70 Phase fluctuation calculation circuit, 80 control circuit, 90 calculation circuit, 101 reception antenna, 102 multiplication circuit, 105 analog-digital conversion circuit, 112 fast Fourier transform circuit, 130 clock signal control circuit, CLK clock signal, PS1 cumulative addition value , PS4 Phase fluctuation amount, SP0 to SP4 pilot signal.

Claims (9)

Clock signal control circuit for controlling the frequency of a clock signal used when performing discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM Because
A calculation circuit that calculates a power value of each of a plurality of pilot signals in the same symbol period based on a demodulated signal obtained by performing discrete Fourier transform on the digital signal;
A phase fluctuation amount calculating circuit for calculating a phase fluctuation amount between a pilot signal having the lowest frequency and a pilot signal having the highest frequency in the pilot signal having the power value within a predetermined range among the plurality of pilot signals;
A clock signal control circuit comprising: a control circuit that controls a frequency of the clock signal based on the phase variation amount. Clock signal control circuit for controlling the frequency of a clock signal used when performing discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM Because
A calculation circuit that calculates a power value of each of a plurality of pilot signals in the same symbol period based on a demodulated signal obtained by performing discrete Fourier transform on the digital signal;
A phase fluctuation amount calculating circuit for calculating a phase fluctuation amount between a pilot signal having the lowest frequency and a pilot signal having the highest frequency in the pilot signal having the power value larger than a predetermined threshold value among the plurality of pilot signals; ,
A clock signal control circuit comprising: a control circuit that controls a frequency of the clock signal based on the phase variation amount. Clock signal control circuit for controlling the frequency of a clock signal used when performing discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM Because
A calculation circuit for calculating the amplitude values of the I component and Q component of each of a plurality of pilot signals in the same symbol period based on a demodulated signal obtained by performing discrete Fourier transform on the digital signal;
Among the pilot signals, the pilot signal having the lowest frequency in the pilot signal in which the amplitude value of the I component is in a first predetermined range and the amplitude value of the Q component is in a second predetermined range is A phase fluctuation amount calculation circuit for calculating a phase fluctuation amount between the pilot signal of the highest frequency and
A clock signal control circuit comprising: a control circuit that controls a frequency of the clock signal based on the phase variation amount. Clock signal control circuit for controlling the frequency of a clock signal used when performing discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM Because
A calculation circuit for calculating the amplitude values of the I component and Q component of each of a plurality of pilot signals in the same symbol period based on a demodulated signal obtained by performing discrete Fourier transform on the digital signal;
Among the plurality of pilot signals, a pilot signal having the lowest frequency in a pilot signal having an amplitude value of the I component larger than a first threshold value and an amplitude value of the Q component larger than a second threshold value. A phase fluctuation amount calculation circuit for calculating a phase fluctuation amount between the signal and the pilot signal of the highest frequency;
A clock signal control circuit comprising: a control circuit that controls a frequency of the clock signal based on the phase variation amount. Clock signal control circuit for controlling the frequency of a clock signal used when performing discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM Because
A calculation circuit that calculates a power value of each of a plurality of pilot signals in the same symbol period based on a demodulated signal obtained by performing discrete Fourier transform on the digital signal;
Based on the frequency and phase error of the pilot signal having the power value within the predetermined range among the plurality of pilot signals, the phase variation rate with respect to the frequency change between the pilot signals having the power value within the predetermined range is calculated. A phase fluctuation amount calculation circuit for calculating a phase fluctuation amount caused by a frequency error of the clock signal between the lowest frequency pilot signal and the highest frequency pilot signal in the plurality of pilot signals based on the phase fluctuation rate; ,
A clock signal control circuit comprising: a control circuit that controls a frequency of the clock signal based on the phase variation amount. Clock signal control circuit for controlling the frequency of a clock signal used when performing discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM Because
A calculation circuit that calculates a power value of each of a plurality of pilot signals in the same symbol period based on a demodulated signal obtained by performing discrete Fourier transform on the digital signal;
Frequency change between pilot signals having the power value greater than the predetermined threshold based on the frequency and phase error of the pilot signal having the power value greater than the predetermined threshold among the plurality of pilot signals And a phase fluctuation amount caused by a frequency error of the clock signal between the lowest frequency pilot signal and the highest frequency pilot signal in the plurality of pilot signals is calculated based on the phase fluctuation rate. A phase variation calculation circuit;
A clock signal control circuit comprising: a control circuit that controls a frequency of the clock signal based on the phase variation amount. Clock signal control circuit for controlling the frequency of a clock signal used when performing discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM Because
A calculation circuit for calculating the amplitude values of the I component and Q component of each of a plurality of pilot signals in the same symbol period based on a demodulated signal obtained by performing discrete Fourier transform on the digital signal;
Of the plurality of pilot signals, the amplitude value of the I component is within a first predetermined range, and the amplitude value of the Q component is within a second predetermined range, based on the frequency and phase error of the pilot signal Calculating a phase variation rate with respect to a frequency change between pilot signals in which the amplitude value of the I component is in a first predetermined range and the amplitude value of the Q component is in a second predetermined range; A phase fluctuation amount calculation circuit for calculating a phase fluctuation amount caused by a frequency error of the clock signal between the pilot signals of the lowest frequency and the highest frequency in the plurality of pilot signals based on the phase fluctuation rate;
A clock signal control circuit comprising: a control circuit that controls a frequency of the clock signal based on the phase variation amount. Clock signal control circuit for controlling the frequency of a clock signal used when performing discrete Fourier transform on a digital signal obtained by analog-to-digital conversion of an analog baseband signal modulated based on OFDM Because
A calculation circuit for calculating the amplitude values of the I component and Q component of each of a plurality of pilot signals in the same symbol period based on a demodulated signal obtained by performing discrete Fourier transform on the digital signal;
Among the plurality of pilot signals, the frequency and phase error of the pilot signal in which the amplitude value of the I component is larger than a first threshold value and the amplitude value of the Q component is larger than a second threshold value. On the basis of a phase variation rate with respect to a frequency change between pilot signals in which the amplitude value of the I component is larger than a first threshold value and the amplitude value of the Q component is larger than a second threshold value A phase fluctuation amount calculating circuit that calculates a phase fluctuation amount caused by a frequency error of the clock signal between the pilot signals of the lowest frequency and the highest frequency in the plurality of pilot signals based on the phase fluctuation rate. When,
A clock signal control circuit comprising: a control circuit that controls a frequency of the clock signal based on the phase variation amount. A clock signal control circuit according to any one of claims 1 to 8,
A clock signal oscillator for generating the clock signal;
A receiving antenna for receiving an OFDM signal as a radio signal;
A multiplier for multiplying the OFDM signal by a main carrier frequency signal to generate the baseband signal;
An analog-to-digital conversion circuit that converts the baseband signal into the digital signal;
An OFDM receiver comprising: a fast Fourier transform circuit that performs discrete Fourier transform on the digital signal using the clock signal to generate the demodulated signal.

Images