JP2009025505A - Image signal processor, image signal processing method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct the response speed of a display part, while reducing access to a memory. <P>SOLUTION: A writing circuit 132 writes an input image signal into a storage device 134, a reading circuit 135 reads out the image signal written into the storage device 134, and a reading circuit 137 reads out the image signal of an image more time-serially previous than the image signal read out by the reading circuit 135 and written into the storage device 134. A liquid crystal response speed correcting circuit 139 generates a correction signal for correcting a response speed of an LCD 96, based on the image signals read out by the reading circuit 135 and the reading circuit 137, and generates an image signal for correcting the response speed of the LCD 96, from the image signal read out by the reading circuit 135, based on the correction signal, to be output to LCD 96. The present invention is applicable, for example, to a TV receiver. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a video signal processing device, a video signal processing method, and a program, and in particular, a video signal that can correct a response speed of a display unit that displays an image while reducing access to a memory, for example. The present invention relates to a processing device, a video signal processing method, and a program.

  For example, in a television receiver having an LCD (Liquid Crystal Display), liquid crystal response speed correction processing for correcting the response speed of the LCD is performed in order to improve the response delay of the LCD.

  FIG. 1 is a block diagram showing a configuration example of a conventional television receiver 11 that performs liquid crystal response speed correction processing.

  The television receiver 11 of FIG. 1 includes a tuner 31, a resolution conversion circuit 32, a writing circuit 33, a storage device control circuit 34, a storage device 35, a reading circuit 36, an image quality improving circuit 37, a writing circuit 38, a reading circuit 39, A liquid crystal response speed correction circuit 40 and an LCD 41 are included.

  A broadcast signal is supplied to the tuner 31 of the television receiver 11 from an antenna or the like (not shown).

  The tuner 31 receives a broadcast signal supplied from an antenna (not shown) and the like, demodulates a video signal from a broadcast signal of a channel (frequency band) designated by the user, and outputs a resolution conversion circuit. 32.

  The resolution conversion circuit 32 converts the image resolution of the video signal supplied from the tuner 31 to the resolution of the LCD 41. In addition, when the video signal supplied from the tuner 31 is an interlace signal, the resolution conversion circuit 32 converts the video signal from the interlace signal to a progressive signal. The resolution conversion circuit 32 supplies the converted video signal to the writing circuit 33.

  The writing circuit 33 supplies the video signal to the storage device control circuit 34 in order to replace the synchronization signal of the converted video signal supplied from the resolution conversion circuit 32 with a synchronization signal for driving the LCD 41, and also stores it. By controlling the device control circuit 34, it is stored in a storage device 35 constituted by DRAM (Dynamic Random Access Memory) or the like.

Reading circuit 36, by controlling the storage control circuit 34, from the storage device 35, a video signal of the image F _t of the current frame, read in synchronism with the synchronizing signals of the LCD 41, supplied to the high image quality circuit 37 To do.

High image quality circuit 37, a video signal supplied from the read circuit 36, for example, if it is configured of a luminance signal Y and chrominance signals C _b, and C _r, converting the video signal into an RGB signal.

Further, high image quality circuit 37, an image F _t of the video signal supplied from the read circuit 36, as image quality improvement processing for converting a high-quality high-quality image F _t ^'than its image F _t, for example, Perform gamma correction.

Further, the image quality enhancement circuit 37 supplies the video signal of the high quality image F _t ′ obtained by the image quality enhancement processing to the writing circuit 38 and the liquid crystal response speed correction circuit 40.

The writing circuit 38 supplies the video signal of the high-quality image F _t ′ supplied from the image quality improving circuit 37 to the storage device control circuit 34, and controls the storage device control circuit 34 to thereby store the video signal in the storage device 35. Remember.

The reading circuit 39 controls the storage device control circuit 34 to thereby control the video signal of the high _- quality image F _t-1 ′ written by the writing circuit 38 last time, that is, the height of the frame output from the high-quality circuit 37. the video signal quality image F _t 'from the previous frame quality images F _t-1', and supplies the liquid crystal response speed correction circuit 40 reads out from the storage device 35. In other words, at this time, the storage device 35 functions as a frame memory for delaying the video signal by one frame.

The liquid crystal response speed correction circuit 40 is based on the video signal of the high-quality image F _t ′ from the image quality improvement circuit 37 and the video signal of the high-quality image F _t−1 ′ one frame before from the readout circuit 39. Then, liquid crystal response speed correction processing for generating a video signal for correcting the response speed of the LCD 41 is performed. The liquid crystal response speed correction circuit 40 outputs the corrected video signal to the LCD 41 and displays a corresponding image on the LCD 41.

  A technique for increasing the display response speed by overdriving the liquid crystal panel is also described in Patent Document 1 (particularly, refer to paragraph [0001] of Patent Document 1).

  FIG. 2 is a block diagram showing another configuration of the conventional television receiver 11.

  In the figure, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  That is, the television receiver 11 of FIG. 2 has the same configuration as that of FIG. 1 except that a resolution conversion circuit 61 is provided instead of the resolution conversion circuit 32 of FIG.

  The writing circuit 33 writes the video signal supplied from the tuner 31 to the storage device 35 via the storage device control circuit 34.

  The readout circuit 36 reads out the video signal written in the storage device 35 via the storage device control circuit 34 and supplies it to the resolution conversion circuit 61.

  The resolution conversion circuit 61 converts the image resolution of the video signal supplied from the readout circuit 36 into the resolution of the LCD 41. In addition, when the video signal supplied from the readout circuit 36 is an interlace signal, the resolution conversion circuit 61 converts the video signal from the interlace signal to a progressive signal. The resolution conversion circuit 61 supplies the converted video signal to the image quality improvement circuit 37.

  That is, the television receiver 11 of FIG. 2 is obtained by changing the position of the resolution conversion circuit 32 of the television receiver 11 of FIG. 1 to a position between the readout circuit 36 and the image quality improving circuit 37. The operation is basically the same as in FIG.

JP 2006-195231 A

  By the way, in the television receiver 11 of FIGS. 1 and 2, in order to output and display the image of the video signal for correcting the response speed of the LCD 41 on the LCD 41, the writing circuit 33 writes to the storage device 35. One access, one read by the read circuit 36, one write by the write circuit 38, and one read by the read circuit 39 required a total of four accesses.

  However, the access amount that represents the sum of the transfer amount of data read from the memory and the transfer amount of data written to the memory within a certain time is limited to an access amount that is not more than a predetermined threshold defined by the memory specifications. ing.

  Therefore, in order to perform the liquid crystal response speed correction process within a certain time, the access amount accessible within a certain time in the storage device 35 is configured to be equal to or greater than a predetermined access amount corresponding to a total of four accesses. In other words, the television receiver 11 shown in FIGS. 1 and 2 is expensive.

  The present invention has been made in view of such a situation, and it is possible to correct the response speed of a display unit while reducing access to a memory.

  The video signal processing apparatus according to one aspect of the present invention includes a storage unit that stores an input video signal, and a write that writes the input video signal to the storage unit in order to synchronize with the synchronization signal of the output video signal. Means, a first reading means for reading out the video signal written in the storage means by the writing means in synchronization with a synchronizing signal of an output video signal, and a video read by the first reading means Second readout means for reading out the video signal written in the storage means by the writing means in synchronization with a synchronization signal of the output video signal, which is a video signal temporally prior to the image of the signal And a video output based on the video signal read by the first reading means and the video signal read by the second reading means Generation means for generating a correction signal for correcting the response speed of the display unit for displaying the image of the signal, and the first readout from the video signal read out by the first readout means based on the correction signal Correction means for generating a video signal for correcting a response speed of the display unit for displaying an image of the video signal read by the unit and outputting the video signal to the display unit.

  Image quality improvement means for converting an image of the video signal read by the first readout means into a high quality image having higher image quality than the image can be further provided, and the generation means can include the high quality image. The correction signal is generated on the basis of the video signal read out by the second reading means, and the correction means generates the correction signal from the video signal of the high-quality image based on the correction signal. The video signal for correcting the response speed of the display unit that displays the high-quality image can be generated.

  The image quality improving means can improve the image quality by at least one of gamma correction, color correction, sharpness correction, enhancement correction, and contrast correction.

  Other image quality improving means for converting the image of the video signal read by the second reading means into another high quality image having a higher image quality than that image can be further provided. The correction signal can be generated based on the video signal of the high-quality image and the video signal of the other high-quality image.

  The other image quality improving means can improve the image quality by at least one of gamma correction, color correction, sharpness correction, enhancement correction, and contrast correction.

  First differential video signal generation for generating a first differential video signal by subtracting the video signal read by the second readout means from the video signal read by the first readout means And a second differential video signal generating unit that generates a second differential video signal by subtracting the first differential video signal from the video signal of the high-quality image, The generation unit can generate the correction signal based on the video signal of the high quality image and the second difference video signal.

  A differential video signal correction unit that corrects the first differential video signal and converts it into a corrected differential video signal can be further provided. In the second differential video signal generation unit, from the video signal of the high-quality image, The second differential video signal can be generated by subtracting the corrected differential video signal.

  The image quality enhancement means may further comprise a correction coefficient generation means for gamma correcting at least the video signal and generating a correction coefficient corresponding to the gamma correction, and the difference video signal correction means may include the first difference. The video signal can be converted into the corrected difference video signal using the correction coefficient.

  A video signal processing method or program according to one aspect of the present invention includes a writing step of writing an input video signal in a storage unit that stores the input video signal in order to synchronize the input video signal with a synchronization signal of the output video signal. A first readout step of reading out the video signal written in the storage unit by the writing step in synchronization with a synchronization signal of an output video signal, and a video signal read out by the first readout step A second readout step of reading out the video signal of the image temporally prior to the image of the image in synchronization with a synchronization signal of the video signal to be output; , The video signal read by the first read step and the video signal read by the second read step. And a generation step of generating a correction signal for correcting the response speed of the display unit that displays the image of the output video signal, and the first readout step based on the correction signal. A correction step of generating a video signal for correcting a response speed of the display unit that displays an image of the video signal read out in the first reading step from the video signal, and outputting the video signal to the display unit.

  In one aspect of the present invention, the input video signal is written in the storage unit that stores the input video signal and is written in the storage unit in order to synchronize with the synchronization signal of the output video signal. The video signal is read out in synchronization with a synchronization signal of the video signal to be output, and is a video signal of an image temporally previous to the image of the read video signal, and the video signal written in the storage unit The video signal is read out in synchronization with the synchronization signal of the video signal to be output. The response speed of the display unit that displays the image of the output video signal based on the read video signal and the read video signal of the image temporally prior to the image of the video signal A correction signal for correcting the image is generated, and based on the correction signal, a video signal for correcting the response speed of the display unit that displays the image of the read video signal is generated from the read video signal. Are output to the display unit.

  According to the present invention, it is possible to correct the response speed of the display unit while reducing access to the memory.

  Embodiments of the present invention will be described below. Correspondences between the constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment which is described in the specification or the drawings but is not described here as an embodiment corresponding to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described herein as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

The video signal processing apparatus according to one aspect of the present invention (for example, the television receiver 81 in FIG. 3)
Storage means for storing the input video signal (for example, the storage device 134 in FIG. 4);
Writing means (for example, the writing circuit 132 in FIG. 4) for writing the input video signal into the storage means in order to synchronize with the synchronizing signal of the output video signal;
First reading means (for example, the reading circuit 135 in FIG. 4) that reads the video signal written in the storage means by the writing means in synchronization with a synchronizing signal of the video signal to be output;
A video signal of an image temporally prior to the image of the video signal read by the first reading means, wherein the video signal written to the storage means by the writing means Second reading means (for example, the reading circuit 137 in FIG. 4) for reading in synchronization with the synchronization signal;
Based on the video signal read by the first reading means and the video signal read by the second reading means, a display unit that displays an image of the output video signal (for example, FIG. 3). Generating means (for example, the correction signal generation circuit 181 in FIG. 5) for generating a correction signal for correcting the response speed of the LCD 96);
A video for correcting the response speed of the display unit that displays an image of the video signal read by the first reading means from the video signal read by the first reading means based on the correction signal. Correction means (for example, an adder 182 in FIG. 5) that generates a signal and outputs the signal to the display unit.

In the video signal processing apparatus according to one aspect of the present invention,
Further provided is an image quality improving means (for example, an image quality improving circuit 191 in FIG. 10) for converting the image of the video signal read by the first reading means into a high quality image having a higher image quality than that image. Can
The generation means generates the correction signal based on the video signal of the high-quality image and the video signal read by the second reading means,
The correction means can generate a video signal for correcting a response speed of the display unit that displays the high-quality image from the video signal of the high-quality image based on the correction signal.

In the video signal processing apparatus according to one aspect of the present invention,
Other image quality improving means (for example, the image quality improving circuit 201 in FIG. 12) for converting the image of the video signal read by the second reading means into another high quality image having a higher image quality than that image. Can be further provided,
The generation unit can generate the correction signal based on the video signal of the high-quality image and the video signal of the other high-quality image.

In the video signal processing apparatus according to one aspect of the present invention,
First differential video signal generation for generating a first differential video signal by subtracting the video signal read by the second readout means from the video signal read by the first readout means Means (eg, subtracter 283 in FIG. 16);
Second difference video signal generating means (for example, a subtractor 321 in FIG. 17) that generates a second difference video signal by subtracting the first difference video signal from the video signal of the high-quality image; Can be further provided,
The generation unit can generate the correction signal based on the video signal of the high quality image and the second difference video signal.

In the video signal processing apparatus according to one aspect of the present invention,
Difference video signal correction means (for example, a multiplier 362 in FIG. 21) for correcting the first difference video signal and converting it into a corrected difference video signal can be further provided.
The second differential video signal generation means can generate the second differential video signal by subtracting the corrected differential video signal from the video signal of the high-quality image.

In the video signal processing apparatus according to one aspect of the present invention,
In the image quality improving means, at least the video signal is gamma corrected,
Correction coefficient generation means (for example, a correction coefficient generation circuit 361 in FIG. 21) for generating a correction coefficient corresponding to the gamma correction can be further provided.
The differential video signal correcting means can convert the first differential video signal into the corrected differential video signal using the correction coefficient.

A video signal processing method or program according to one aspect of the present invention includes:
In order to synchronize the input video signal with the synchronization signal of the output video signal, a writing step (for example, FIG. 8) writes the input video signal in a storage unit (for example, the storage device 134 in FIG. 4). Step S32),
A first reading step (for example, step S33 in FIG. 8) for reading the video signal written in the storage unit by the writing step in synchronization with a synchronization signal of the video signal to be output;
An image signal of an image temporally prior to the image of the image signal read by the first reading step, wherein the image signal written to the storage unit by the writing step A second reading step (for example, step S35 in FIG. 8) for reading in synchronization with the synchronization signal;
Based on the video signal read in the first read step and the video signal read in the second read step, the response speed of the display unit that displays the image of the output video signal is corrected. A generation step for generating a correction signal to be performed (for example, step S71 in FIG. 9);
A video for correcting a response speed of the display unit that displays an image of the video signal read by the first reading step from the video signal read by the first reading step based on the correction signal. And a correction step (for example, step S72 in FIG. 9) for generating a signal and outputting the signal to the display unit.

  Next, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 is a block diagram showing a configuration of an embodiment of a television receiver as a video signal processing apparatus to which the present invention is applied.

  3 is connected to a network 82, and includes an external input terminal 91, a tuner 92, a decoder 93, a switch 94, a video signal processing unit 95, and an LCD 96.

  The network 82 to which the television receiver 81 is connected is constituted by, for example, the Internet or a LAN (Local Area Network), and a transmission signal output from a server (not shown) is sent to the decoder 93 of the television receiver 81. Supply.

  The external input terminal 91 supplies a video signal supplied from a playback device (not shown) to the switch 94.

  The tuner 92 receives a broadcast signal supplied from an antenna (not shown), demodulates the video signal from the broadcast signal of the channel (frequency band) designated by the user, and sends it to the switch 94. Supply.

  The decoder 93 decodes the video signal of the channel specified by the user from the transmission signal transmitted via the network 82 and supplies the decoded video signal to the switch 94.

  The switch 94 selects one video signal from the video signals supplied from the external input terminal 91, the tuner 92, or the decoder 93 based on a user instruction and supplies the selected video signal to the video signal processing unit 95.

  The video signal processing unit 95 is a synchronization signal of the video signal selected by the switch 94 so that the image displayed on the LCD 96 is suppressed from being disturbed when any video signal is selected by the switch 94. In order to improve the response delay of the LCD 96, a liquid crystal response for generating a video signal for correcting the response speed of the LCD 96 from the video signal supplied to the LCD 96 is improved. Perform speed correction processing.

  The video signal processing unit 95 outputs the processed video signal to the LCD 96. The LCD 96 displays an image corresponding to the video signal supplied from the video signal processing unit 95.

  FIG. 4 is a block diagram showing the configuration of the embodiment of the video signal processing unit 95 of FIG.

  The video signal processing unit 95 includes a resolution conversion circuit 131, a writing circuit 132, a storage device control circuit 133, a storage device 134, a reading circuit 135, an RGB (Red Green Blue) conversion circuit 136, a reading circuit 137, an RGB conversion circuit 138, and The liquid crystal response speed correction circuit 139 is configured. Although not shown, each circuit is supplied with a timing signal for synchronizing timing.

  A video signal is supplied from the switch 94 of FIG. 3 to the resolution conversion circuit 131 of the video signal processing unit 95.

  The resolution conversion circuit 131 converts the resolution of the video signal supplied from the switch 94 into the resolution of the LCD 96 so that the size of the image of the video signal supplied from the switch 94 matches the size of the screen of the LCD 96.

  In addition, when the video signal supplied from the switch 94 is an interlace signal, the resolution conversion circuit 131 converts the video signal from the interlace signal to a progressive signal. The resolution conversion circuit 131 supplies the converted video signal to the writing circuit 132.

  The writing circuit 132 controls the storage device control circuit 133 to synchronize the converted video signal supplied from the resolution conversion circuit 131 with the synchronization signal of the video signal output from the video signal processing unit 95 to the LCD 96. Are written (stored) in the storage device 134. This writing is performed in synchronization with the synchronizing signal of the video signal written into the storage device 134 by the writing circuit 132.

  The storage device 134 is constituted by a memory such as a DRAM, for example, and stores the video signal supplied from the writing circuit 132 via the storage device control circuit 133.

  The readout circuit 135 controls the storage device control circuit 133 to read out the video signal written in the storage device 134 by the writing circuit 132 in synchronization with the synchronization signal of the LCD 96 and supply it to the RGB conversion circuit 136.

  When the format of the video signal supplied from the readout circuit 135 is a signal format different from the RGB signal, the RGB conversion circuit 136 converts the video signal into an RGB signal. The RGB conversion circuit 136 supplies the RGB signal to the liquid crystal response speed correction circuit 139.

Read circuit 137, by controlling the storage control circuit 133, the read circuit 135 reads the video signal image F _t than temporally previous as an image (in the past), for example, one frame preceding image F The video signal that is the video signal of _t−1 and written to the storage device 134 by the writing circuit 132 is read out in synchronization with the synchronizing signal of the LCD 96 and supplied to the RGB conversion circuit 138.

  Similar to the RGB conversion circuit 136, the RGB conversion circuit 138 converts the video signal into an RGB signal when the format of the video signal supplied from the readout circuit 137 is a signal format different from the RGB signal. The RGB conversion circuit 138 supplies the RGB signal to the liquid crystal response speed correction circuit 139.

  The liquid crystal response speed correction circuit 139 corrects the response speed of the LCD 96 based on the video signal of the current frame supplied from the RGB conversion circuit 136 and the video signal of the past frame supplied from the RGB conversion circuit 138. Liquid crystal response speed correction processing for generating a video signal is performed.

  FIG. 5 is a block diagram showing a configuration of an embodiment of the liquid crystal response speed correction circuit 139 of FIG.

  The liquid crystal response speed correction circuit 139 includes a correction signal generation circuit 181 and an adder 182.

  The correction signal generation circuit 181 is supplied with the video signal of the current frame from the RGB conversion circuit 136 and the video signal of the past frame from the RGB conversion circuit 138.

  The correction signal generation circuit 181 includes a lookup table 181a. The lookup table 181a stores a set of pixel values of the current frame and the past frame in association with a correction signal for correcting the video signal from the RGB conversion circuit 136 in order to correct the response speed of the LCD 96. It is a table.

  The correction signal generation circuit 181 includes the pixel value of the pixel of the current frame video signal supplied from the RGB conversion circuit 136 and the pixel value of the corresponding pixel of the video signal of the past frame supplied from the RGB conversion circuit 138. Based on the above, a built-in lookup table 181a is referred to generate a correction signal for correcting the response speed of the LCD 96 and supplied to the adder 182.

  In addition to the correction signal supplied from the correction signal generation circuit 181, the adder 182 is supplied with the video signal of the current frame from the RGB conversion circuit 136.

  Based on the correction signal supplied from the correction signal generation circuit 181, the adder 182 generates a video signal for correcting the response speed of the LCD 96 from the video signal of the current frame supplied from the RGB conversion circuit 136. Output to.

  Specifically, the adder 182 adds the video signal of the current frame supplied from the RGB conversion circuit 136 and the correction signal supplied from the correction signal generation circuit 181, and the corrected video obtained by the addition. The signal is output to the LCD 96.

  FIG. 6 is a diagram for explaining a lookup table 181a built in the correction signal generation circuit 181 of FIG.

In the figure, the horizontal axis represents the pixel value of the pixel of the video signal of the image F _t of the current frame supplied from the RGB converter 136 to the correction signal generating circuit 181, the vertical axis, the correction signal from the RGB conversion circuit 138 The pixel value of the pixel of the video signal of the image F _t-1 of the frame one frame before the image F _t of the current frame supplied to the generation circuit 181 is represented. _{V 00, V 01, V 02} , ··· is a value representing a correction signal, and the pixel value of the pixel of the video signal of the image F _t of the current frame shown on the horizontal axis, 1 frame shown on the vertical axis This is associated with a set of pixel values of pixels of the video signal of the image F _t-1 of the previous frame.

That is, for example, a predetermined pixel of the video signal of the image F _t of the current frame takes the value 0 as the pixel value, and the pixel of the video signal of the image F _t-1 of the frame one frame before corresponding to that pixel is When taking the value 1 as the pixel value, the value V ₁₀ is determined as the corresponding correction signal.

The adder 182 adds the pixel value of each pixel of the video signal of the image F _t of the current frame supplied from the RGB converter 136, corresponding to each pixel, the correction signal supplied from the correction signal generation circuit 181 Add the value to represent. The adder 182 outputs the video signal corrected by the addition to the LCD 96.

  Next, video processing performed by the television receiver 81 of FIG. 3 will be described with reference to the flowchart of FIG.

  In step S11, the video signal processing unit 95 of the television receiver 81 performs video signal processing on the video signal supplied thereto, and the video signal obtained by the video signal processing is displayed on the LCD 96 of the television receiver 81. Output to. That is, the video signal processing unit 95 processes one video signal selected by the switch 94 based on a user instruction from among the video signals supplied from the external input terminal 91, the tuner 92, or the decoder 93.

  Next, in step S <b> 12, the LCD 96 displays an image corresponding to the video signal supplied from the video signal processing unit 95.

  Next, the video signal processing in step S11 of FIG. 7 will be described in detail with reference to the flowchart of FIG.

  In step S31, the resolution conversion circuit 131 sets the resolution of the video signal supplied from the switch 94 to the resolution of the LCD 96 so that the size of the image of the video signal supplied from the switch 94 matches the size of the screen of the LCD 96. Convert to

  In step S31, when the video signal supplied from the switch 94 is an interlace signal, the resolution conversion circuit 131 converts the video signal from the interlace signal to a progressive signal.

  In step S <b> 32, the writing circuit 132 writes the video signal supplied from the resolution conversion circuit 131 in the storage device 134.

  That is, the writing circuit 132 controls the storage device control circuit 133 so that the video signal after resolution conversion supplied from the resolution conversion circuit 131 is converted into a synchronizing signal of the video signal output from the video signal processing unit 95 to the LCD 96. Write to storage device 134 for synchronization.

  In step S <b> 33, the reading circuit 135 reads the video signal of the current frame written in the storage device 134 by the writing circuit 132 by controlling the storage device control circuit 133. This reading is performed in synchronization with the synchronization signal of the LCD 96. In other words, the synchronization signal is replaced, so that even if the synchronization signal of the video signal selected by the switch 94 is not synchronized with the synchronization signal that drives the LCD 96, the LCD 96 has no synchronization disturbance and is stable. Can be displayed.

Next, in step S34, when the format of the video signal supplied from the readout circuit 135 is different from the RGB signal, the RGB conversion circuit 136 is, for example, the luminance signal Y and the color difference signals C _r and C _b . In this case, the video signal is converted into an RGB signal.

  In step S <b> 35, the reading circuit 137 controls the storage device control circuit 133 to control the storage device control circuit 133 so that the video signal written to the storage device 134 by the writing circuit 132 is temporal in comparison with the current frame read by the reading circuit 135. For example, the video signal of the previous frame as the previous frame is read out in synchronization with the synchronization signal of the LCD 96. Thereby, similarly to the reading by the reading circuit 135, synchronization disturbance is suppressed, and the video signal read by the reading circuit 135 and the video signal read by the reading circuit 137 are synchronized.

  In step S36, when the format of the video signal supplied from the readout circuit 137 is different from the RGB signal, the RGB conversion circuit 138 converts the video signal into an RGB signal. That is, a conversion process similar to the conversion process by the RGB conversion circuit 136 is performed.

  In step S <b> 37, the liquid crystal response speed correction circuit 139 calculates the LCD 96 based on the video signal of the current frame supplied from the RGB conversion circuit 136 and the video signal of the previous frame supplied from the RGB conversion circuit 138. Liquid crystal response speed correction processing for generating a video signal for correcting the response speed is performed.

  Thereafter, the process returns to step S11 in FIG.

  Next, the liquid crystal response speed correction process in step S37 of FIG. 8 will be described in detail with reference to the flowchart of FIG.

  In step S71, the correction signal generation circuit 181 generates a correction signal. Specifically, based on the video signal of the current frame supplied from the RGB conversion circuit 136 and the video signal one frame before the current frame supplied from the RGB conversion circuit 138, a built-in lookup table 181a. By referring to the above, a correction signal for correcting the response speed of the LCD 96 is generated.

  In step S <b> 72, the adder 182 generates a video signal for correcting the response speed of the LCD 96 based on the correction signal supplied from the correction signal generation circuit 181. Specifically, the correction signal supplied from the correction signal generation circuit 181 is added to the video signal of the current frame supplied from the RGB conversion circuit 136, so that the correction as the video signal for correcting the response speed of the LCD 96 is performed. The generated video signal is generated and output to the LCD 96. As a result, even a fast moving image is clearly displayed on the LCD 96.

  Thereafter, the process returns to step S37 in FIG.

  As described above, in the video signal processing of FIG. 8, the video signal written for replacement of the synchronization signal is read by the read circuit 135 by the write circuit 132. Then, the video signal of the frame one frame before the frame read by the read circuit 135 is further read by the read circuit 137 using writing for replacing the synchronization signal.

  Then, the liquid crystal response speed correction circuit 139 performs a liquid crystal response speed correction process for correcting the response speed of the LCD 96 based on the video signal read by the read circuit 135 and the video signal read by the read circuit 137. Done.

  Therefore, in the video signal processing of FIG. 8 that performs the liquid crystal response speed correction process of FIG. 9, in order to perform the liquid crystal response speed correction process of FIG. It is only necessary to perform a total of three accesses, one read by the circuit 135 and one read by the read circuit 137, and there is no need to perform a special write for generating a video signal delayed by one frame. Compared with the television receiver 11 of FIG. 1 and FIG. 2 that performs access once, access to the storage device 134 can be reduced by one time.

  As a result, compared with the conventional television receiver 11, a memory that operates at a lower speed can be adopted as the memory constituting the storage device 134, and the cost of the storage device 134, and further, the television receiver can be adopted. The cost of 81 can be reduced.

  4 corrects the video signal read by the read circuit 135 and outputs it to the LCD 96 as it is, but the image displayed on the LCD 96 has a high image quality. It is desirable that the image has a high quality.

10 converts the image F _t of the read video signal by the read circuit 135, on the image F _t quality quality image than F _t ', of FIG. 3 to be displayed and outputs the LCD96 video It is a block diagram which shows the structural example of 2nd Embodiment of the signal processing part.

  In the figure, portions corresponding to those in the case of FIG. 4 are denoted by the same reference numerals and repeated, and therefore, the description thereof will be omitted as appropriate. The same applies to the other embodiments.

  That is, the video signal processing unit 95 in FIG. 10 has the same configuration as that in FIG. 4 except that an image quality improving circuit 191 is provided instead of the RGB conversion circuit 136 in FIG.

The image quality circuit 191, the read circuit 135, the video signal of the image F _t of the current frame is supplied. The image quality enhancement circuit 191 has a conversion function similar to that of the RGB conversion circuit 136 of FIG. 4, and the image signal F _t supplied from the readout circuit 135 is converted into a high image quality image with higher image quality than the image F _t. For example, gamma correction is performed as an image quality enhancement process for conversion to F _t ′. The image quality improving circuit 191 supplies the video signal of the high image quality image F _t ′ obtained by the image quality improving process to the liquid crystal response speed correcting circuit 139.

  That is, the video signal processor 95 generally includes a CRT (Cathode Ray Tube) having a gamma characteristic in which the brightness of the screen changes exponentially with respect to the pixel value of the image pixel displayed on the screen. Considering this, a video signal subjected to inverse gamma correction on the broadcast station side is supplied. However, unlike the CRT, the LCD 96 is a display having no gamma characteristic. Therefore, if the video signal subjected to inverse gamma correction is displayed on the LCD 96 as it is, a high-quality image cannot be displayed.

  Therefore, the image quality enhancement circuit 191 performs gamma correction corresponding to the inverse gamma correction performed on the broadcast station side on the video signal supplied from the readout circuit 135, so that the brightness of the screen is displayed on the screen. It is corrected to a video signal suitable for display on the LCD 96 that is proportional to the pixel value of the pixel of the image to be displayed.

  Next, the video signal processing performed by the video signal processing unit 95 in FIG. 10 will be described with reference to the flowchart in FIG.

  In steps S81 to S83, processing similar to that in steps S31 to S33 in FIG. 8 is performed, and then the processing proceeds to step S84.

  In step S84, as in the case of the RGB conversion circuit 136 in FIG. 4, when the format of the video signal supplied from the readout circuit 135 is different from the RGB signal, the image quality improving circuit 191 converts the video signal to RGB. Convert to signal.

  In step S84, the image quality improving circuit 191 performs, for example, gamma correction as an image quality improving process for converting the image of the video signal supplied from the readout circuit 135 into a high image quality image. The image quality improving circuit 191 supplies a video signal of a high quality image obtained by the image quality improving process to the liquid crystal response speed correcting circuit 139.

  Thereafter, the process proceeds from step S84 to step S85. In steps S85 to S87, the same processes as steps S35 to S37 in FIG. 8 are performed, and then the process ends.

  As described above, in the video signal processing of FIG. 11, the video signal written by the writing circuit 132 is read by the reading circuit 135 and converted into a video signal of a high quality image by the image quality improving circuit 191. In addition, the same processing as the video signal processing of FIG. 8 is performed.

  Therefore, the video signal processing of FIG. 11 can realize the same effect as the video signal processing of FIG. 8 and outputs the video signal of the high quality image output from the image quality improving circuit 191 to the LCD 96. Therefore, it is possible to display a higher quality image on the LCD 96 than in the embodiment of FIG.

  By the way, the correction signal generation circuit 181 (FIG. 5) in the liquid crystal response speed correction circuit 139 (FIG. 10) is a circuit that generates an optimal correction signal based on the same type of video signal of the image before and after one frame. . Accordingly, it is desirable that the video signals of the images before and after one frame are the same type of video signals.

  12 shows an implementation of the video signal processing unit 95 of FIG. 3 having a liquid crystal response speed correction circuit 139 (correction signal generation circuit 181) that generates a correction signal based on the same type of video signal of the image before and after one frame. It is a block diagram which shows the structure of this form.

  The video signal processing unit 95 in FIG. 12 has the same configuration as that in FIG. 10 except that an image quality improving circuit 201 is provided instead of the RGB conversion circuit 138 in FIG.

  The image quality improvement circuit 201 is supplied from the readout circuit 137 with a video signal of a frame one frame before the current frame. Similar to the RGB conversion circuit 138 in FIG. 10, the image quality improvement circuit 201 has a function of converting the video signal into an RGB signal when the format of the video signal supplied from the readout circuit 137 is different from the RGB signal. The video signal supplied from the readout circuit 137 is subjected to gamma correction. In other words, the image quality improving circuit 201 executes the same processing as the image quality improving circuit 191.

  Then, the image quality improvement circuit 201 supplies the video signal obtained by the image quality improvement processing to the liquid crystal response speed correction circuit 139.

  Next, the video signal processing performed by the video signal processing unit 95 in FIG. 12 will be described with reference to the flowchart in FIG.

  In steps S91 to S95, processing similar to that in steps S81 to S85 in FIG. 11 is performed, and then the processing proceeds to step S96.

  In step S96, the image quality improvement circuit 201 performs the same image quality improvement processing as the image quality improvement processing on the video signal output from the readout circuit 135 by the image quality improvement circuit 191 in step S94. To do. That is, a process for converting to an RGB signal and a gamma correction process are performed. The video signal obtained by the image quality enhancement processing is supplied to the liquid crystal response speed correction circuit 139.

  Thereafter, the process proceeds from step S96 to step S97. After the same process as step S87 in FIG. 11 is performed, the process ends.

  As described above, in the video signal processing of FIG. 13, the same effect as the video signal processing of FIG. 11 can be realized, and the video signal subjected to the same kind of high image quality processing by the correction signal generation circuit 181. Since the correction signal is generated based on the above, the data of the lookup table 181a can be easily generated.

  FIG. 14 is a block diagram showing a configuration of still another embodiment of the video signal processing unit 95 of FIG.

  The video signal processing unit 95 in FIG. 14 is configured in the same manner as in FIG. 12 except that resolution conversion circuits 221 and 222 are provided instead of the resolution conversion circuit 131 in FIG.

  Since the resolution conversion circuit 131 is omitted, the video signal is directly supplied from the switch 94 in FIG.

  The resolution conversion circuit 221 is supplied with the video signal of the current frame read from the storage device 134 by the reading circuit 135.

  The resolution conversion circuit 221 converts the resolution of the video signal to the resolution of the LCD 96 so that the size of the image of the video signal supplied from the readout circuit 135 matches the size of the screen of the LCD 96. In addition, when the video signal supplied from the readout circuit 135 is an interlace signal, the resolution conversion circuit 221 converts the video signal from the interlace signal to a progressive signal. The resolution conversion circuit 221 supplies the converted video signal to the image quality enhancement circuit 191.

  The resolution conversion circuit 222 is supplied with the video signal of the frame one frame before the current frame read from the storage device 134 by the reading circuit 137.

  The resolution conversion circuit 222 converts the resolution of the video signal to the resolution of the LCD 96 so that the size of the image of the video signal supplied from the readout circuit 137 matches the size of the screen of the LCD 96. In addition, when the video signal supplied from the readout circuit 137 is an interlace signal, the resolution conversion circuit 222 converts the video signal from the interlace signal to a progressive signal. The resolution conversion circuit 222 supplies the converted video signal to the image quality improvement circuit 201.

  In other words, the resolution conversion circuits 221 and 222 perform the same processing as the resolution conversion circuit 131, except that the video signals to be processed are different. Therefore, the same effect as the embodiment of FIG. 12 can be realized.

  FIG. 15 is a block diagram showing a configuration of another embodiment of the video signal processing unit 95 of FIG.

  The video signal processing unit 95 in FIG. 15 is different from the RGB conversion circuit 138 and the liquid crystal response speed correction circuit 139 in FIG. 10 except that a frame difference calculation unit 231 and a liquid crystal response speed correction circuit 232 are provided. The configuration is the same as in the case of.

  The frame difference calculation unit 231 is supplied with the video signal of the current frame from the readout circuit 135 and the video signal of the frame one frame before the current frame from the readout circuit 137.

  The frame difference calculation unit 231 is different from the RGB signal in the format of the video signal of the current frame supplied from the readout circuit 135 and the video signal of the frame one frame before the current frame supplied from the readout circuit 137. In the case of a format, a video signal of a different format is converted into an RGB signal.

  Further, the frame difference calculation unit 231 subtracts the video signal of the previous frame supplied from the read circuit 137 from the video signal of the current frame supplied from the read circuit 135, and performs the subtraction. The obtained difference video signal is supplied to the liquid crystal response speed correction circuit 232.

  The liquid crystal response speed correction circuit 232 is supplied not only with the differential video signal from the frame difference calculation unit 231 but also with the video signal that has been converted into a high-quality image from the image quality improving circuit 191.

  The liquid crystal response speed correction circuit 232 generates a video signal for correcting the response speed of the LCD 96 based on the video signal supplied from the image quality improving circuit 191 and the difference video signal supplied from the frame difference calculation unit 231. Liquid crystal response speed correction processing is performed.

  FIG. 16 is a block diagram showing a configuration of an embodiment of the frame difference calculation unit 231 of FIG.

  16 includes RGB conversion circuits 281 and 282, a subtracter 283, and a delay adjustment circuit 284.

  The RGB conversion circuit 281 is supplied with the video signal of the current frame from the readout circuit 135.

  When the format of the video signal of the current frame supplied from the readout circuit 135 is different from the RGB signal, the RGB conversion circuit 281 converts the video signal into an RGB signal. The RGB conversion circuit 281 supplies the RGB signal to the subtracter 283.

  The RGB conversion circuit 282 is supplied with the video signal of the frame one frame before the current frame from the readout circuit 137. The RGB conversion circuit 282 converts the video signal into an RGB signal when the format of the video signal of the frame one frame before the current frame supplied from the readout circuit 137 is different from the RGB signal. The RGB conversion circuit 282 supplies the RGB signal to the subtracter 283.

  The subtractor 283 subtracts the video signal of the previous frame supplied from the RGB conversion circuit 282 from the video signal of the current frame supplied from the RGB conversion circuit 281 and obtains the difference obtained by the subtraction. The video signal is supplied to the delay adjustment circuit 284.

  The delay adjustment circuit 284 delays the differential video signal supplied from the subtractor 283 by a predetermined time, so that the video signal having a high-quality image is transferred from the high-quality image improvement circuit 191 in FIG. 15 to the liquid crystal response speed correction circuit. The liquid crystal response speed correction circuit 232 is supplied so as to coincide with the timing supplied to the H.232.

  FIG. 17 is a block diagram showing a configuration of an embodiment of the liquid crystal response speed correction circuit 232 of FIG.

  The liquid crystal response speed correction circuit 232 in FIG. 17 has the same configuration as that in FIG. 5 except that a subtracter 321 is newly provided.

  The subtracter 321 is supplied with a video signal of a high-quality image from the image quality enhancement circuit 191 and a differential video signal from the frame difference calculation unit 231. The subtractor 321 subtracts the difference video signal (first difference video signal) supplied from the frame difference calculation unit 231 from the video signal of the high quality image supplied from the image quality enhancement circuit 191 and obtains the result by the subtraction. The obtained difference video signal (second difference video signal) is supplied to the correction signal generation circuit 181.

  Next, the video signal processing performed by the video signal processing unit 95 in FIG. 15 will be described with reference to the flowchart in FIG.

  In steps S111 to S115, processing similar to that in steps S91 to S95 in FIG. 13 is performed, and the processing proceeds to step S116.

  In step S <b> 116, the frame difference calculation unit 231 calculates a difference video signal based on the video signal of the current frame supplied from the readout circuit 135 and the video signal of the previous frame supplied from the readout circuit 137. Generate frame difference calculation processing.

  In step S117, the liquid crystal response speed correction circuit 232 determines the response speed of the LCD 96 based on the video signal of the high quality image supplied from the image quality improving circuit 191 and the difference video signal supplied from the frame difference calculation unit 231. A liquid crystal response speed correction process for generating a video signal for correcting the image is performed.

  Thereafter, the process returns to step S11 in FIG.

  Next, the frame difference calculation process in step S116 of FIG. 18 will be described in detail with reference to the flowchart of FIG.

  In step S141, when the format of the video signal of the current frame supplied from the readout circuit 135 is different from the RGB signal, the RGB conversion circuit 281 converts the video signal into an RGB signal. The converted RGB signal is supplied to the subtracter 283.

  In step S142, the RGB conversion circuit 282 converts the video signal into an RGB signal when the format of the video signal of the frame one frame before the current frame supplied from the readout circuit 137 is different from the RGB signal. To do.

  In step S143, the subtracter 283 subtracts the video signal of the frame one frame before the current frame supplied from the RGB conversion circuit 282 from the video signal of the current frame supplied from the RGB conversion circuit 281. The difference video signal obtained by the subtraction is supplied to the delay adjustment circuit 284.

  In step S144, the delay adjustment circuit 284 adjusts the output timing of the difference video signal supplied from the subtracter 283. That is, by delaying the differential video signal by a predetermined time, the liquid crystal response speed correction is performed so that the video signal of the high quality image coincides with the timing supplied from the image quality improvement circuit 191 to the liquid crystal response speed correction circuit 232. The difference video signal is output to the circuit 232.

  Thereafter, the process returns to step S116 in FIG.

  Next, the liquid crystal response speed correction process in step S117 of FIG. 18 will be described in detail with reference to the flowchart of FIG.

  In step S181, the subtractor 321 subtracts the difference video signal (first difference video signal) supplied from the frame difference calculation unit 231 from the video signal of the high quality image supplied from the image quality improvement circuit 191. The differential video signal (second differential video signal) thus generated substantially corresponds to the video signal of the frame one frame before the current frame. The second difference video signal is supplied to the correction signal generation circuit 181.

  Next, in steps S182 and S183, processing similar to that in steps S71 and S72 of FIG. 9 is performed.

  Thereafter, the process returns to step S117 in FIG.

  As a result of the processing as described above, in the video signal processing of FIG. 18, the access amount to the storage device 134 can be reduced by one time, and the cost can be reduced. Further, a higher quality image can be displayed on the LCD 96.

  Note that the same effect can be realized by directly supplying the video signal one frame before output from the RGB conversion circuit 282 of FIG. 16 to the correction signal generation circuit 181 instead of the output of the subtractor 321. However, in this case, the data content of the lookup table 181a is different from that in FIG.

  Incidentally, the correction signal generation circuit 181 (FIG. 17) in the liquid crystal response speed correction circuit 232 (FIG. 15) is a circuit that generates an optimal correction signal based on the video signals before and after one frame. Therefore, it is easier to generate the data of the lookup table 181a if the video signal input thereto is the same type of video signal.

  FIG. 21 is a block diagram showing a configuration of an embodiment of a liquid crystal response speed correction circuit 232 that generates an optimal correction signal based on the same type of video signal before and after one frame.

  The liquid crystal response speed correction circuit 232 in FIG. 21 has the same configuration as that in FIG. 17 except that a correction coefficient generation circuit 361 and a multiplier 362 are newly provided.

  The correction coefficient generation circuit 361 is supplied with the video signal that has been gamma corrected by the image quality enhancement circuit 191. The correction coefficient generation circuit 361 generates a correction coefficient corresponding to the gamma correction performed by the image quality improvement circuit 191 based on the gamma-corrected video signal supplied from the image quality improvement circuit 191 and supplies the correction coefficient to the multiplier 362. Supply.

  In addition to the correction coefficient supplied from the correction coefficient generation circuit 361, the multiplier 362 is supplied with a difference video signal (first difference video signal) from the frame difference calculation unit 231. The multiplier 362 performs a correction process for correcting the first difference video signal.

  That is, the multiplier 362 generates a corrected difference video signal by multiplying the first difference video signal from the frame difference calculation unit 231 by the correction coefficient from the correction coefficient generation circuit 361 and supplies the corrected difference video signal to the subtractor 321. .

  Next, with reference to FIGS. 22 and 23, the gamma correction performed by the image quality enhancement circuit 191 in FIG. 15 as the image quality enhancement processing and the correction processing performed by the multiplier 362 in FIG. 21 will be described.

  FIG. 22 is a diagram showing a curve f (x) of a gamma curve used for gamma correction performed by the image quality improving circuit 191 of FIG. In FIG. 22, the horizontal axis represents the pixel value of the pixel of the image of the video signal before gamma correction, and the vertical axis represents the pixel value of the pixel of the image of the video signal after gamma correction.

  The image quality improving circuit 191 in FIG. 15 performs gamma correction on the pixel value x of the pixel of the image of the video signal from the readout circuit 135 using the gamma curve shown in FIG.

  FIG. 23 is a diagram showing a curve g (x) representing the slope of the curve f (x) in FIG. In FIG. 23, the horizontal axis indicates the pixel value of the pixel, and the vertical axis indicates the slope of the curve f (x). In FIG. 23, the slope when the pixel value is x is A.

  The difference video signal output by the frame difference calculation unit 231 is the difference between the video signal before and after one frame that has not been gamma corrected. As the pixel value before gamma correction increases, the pixel value after gamma correction increases exponentially, as is apparent from the curve f (x) in FIG. The difference between the video signals is larger when the pixel value of the video signal before and after the frame is larger than when the pixel value is smaller.

For example, the difference in pixel value between the current frame of the video signal before gamma correction and the frame before 1 frame is d _1b , and the current frame of the corresponding video signal after gamma correction and the frame before 1 frame are Assume that the difference in pixel values is d _1a . Then, the pixel value of the pixel of the current frame at that time is assumed to be v _1. Similarly, it is assumed that the difference between the pixel values before and after the gamma correction when the pixel values of other pixels of the current frame are v ₂ is d _2b and d _2a , respectively. In this case, when the pixel value v ₂ is greater than the pixel value v _1, even if the difference d _1b and difference d _2b were the same size, the difference d _2a is larger than the difference d _1a. The rate of change of the difference is substantially proportional to the slope of the curve f (x), that is, the curve g (x) in FIG.

  Therefore, the multiplier 362 multiplies the difference video signal generated from the video signal not subjected to gamma correction output from the frame difference calculation unit 231 by a multiplier 362 having characteristics substantially corresponding to the curve g (x). The corrected differential video signal output from the device 362 can correspond to the differential video signal generated from the video signal subjected to gamma correction.

  The correction coefficient generation circuit 361 generates a correction coefficient corresponding to the pixel value of the pixel of the current frame supplied from the image quality enhancement circuit 191 each time or generates a correction coefficient by referring to a built-in lookup table, This is supplied to the multiplier 362.

  The multiplier 362 multiplies the difference video signal supplied from the frame difference calculation unit 231 by the correction coefficient supplied from the correction coefficient generation circuit 361, and uses the difference video signal generated from the video signal not subjected to gamma correction. And a value corresponding to the difference video signal generated from the video signal subjected to gamma correction.

  The multiplier 362 supplies the corrected difference video signal to the subtracter 321.

  Next, the liquid crystal response speed correction process performed by the liquid crystal response speed correction circuit 232 of FIG. 21 will be described in detail with reference to the flowchart of FIG.

  In step S <b> 211, the correction coefficient generation circuit 361 generates a correction coefficient corresponding to the pixel value of the pixel of the current frame supplied from the image quality improvement circuit 191 and supplies the correction coefficient to the multiplier 362.

  In step S212, the multiplier 362 corrects the difference video signal (first difference video signal) from the frame difference calculation unit 231. That is, the corrected differential video signal is generated by multiplying the first differential video signal by the correction coefficient from the correction coefficient generation circuit 361. The generated corrected difference video signal is supplied to the subtractor 321.

  In step S <b> 213, the subtractor 321 subtracts the corrected difference video signal supplied from the multiplier 362 from the video signal of the high quality image supplied from the image quality improving circuit 191. As a result, a second differential video signal corresponding to the video signal of the previous frame is generated. The second difference video signal is supplied to the correction signal generation circuit 181.

  After the process of step S213 is completed, the process proceeds to step S214. In steps S214 and S215, processes similar to steps S182 and S183 of FIG. 20 are performed.

  Thereafter, the process returns to step S117 in FIG.

  Note that the correction coefficient generation circuit 361 and the multiplier 362 can be configured integrally.

  As described above, in the liquid crystal response speed correction process of FIG. 24, the difference video signal is corrected based on the correction coefficient. Therefore, for example, as compared with the case where the difference video signal is not corrected as shown in FIG. The video signal before and after one frame input to the correction signal generation circuit 181 can be the same type of video signal, and the data of the lookup table 181a can be generated more easily.

  FIG. 25 is a block diagram showing a configuration of another embodiment of the video signal processing unit 95 of FIG.

  The video signal processing unit 95 in FIG. 25 is configured in the same manner as in FIG. 15 except that resolution conversion circuits 401 and 402 are provided instead of the resolution conversion circuit 131 in FIG.

  In this case, the video signal selected by the switch 94 is supplied to the writing circuit 132. The writing circuit 132 writes the video signal supplied from the switch 94 to the storage device 134 via the storage device control circuit 133.

  The resolution conversion circuit 401 is supplied with the video signal of the current frame read by the reading circuit 135 from the storage device 134. The resolution conversion circuit 401 converts the resolution of the video signal to the resolution of the LCD 96 so that the size of the image of the video signal supplied from the readout circuit 135 matches the size of the screen of the LCD 96.

  Further, when the video signal supplied from the readout circuit 135 is an interlace signal, the resolution conversion circuit 401 converts the video signal from an interlace signal to a progressive signal. The converted video signal is supplied to the image quality enhancement circuit 191 and the frame difference calculation unit 231.

  The resolution conversion circuit 402 is supplied with a video signal of a frame one frame before the current frame read by the reading circuit 137 from the storage device 134.

  The resolution conversion circuit 402 converts the resolution of the video signal to the resolution of the LCD 96 so that the size of the image of the video signal supplied from the readout circuit 137 matches the size of the screen of the LCD 96.

  Also, when the video signal supplied from the readout circuit 137 is an interlace signal, the resolution conversion circuit 402 converts the video signal from an interlace signal to a progressive signal. The converted video signal is supplied to the frame difference calculation unit 231.

  That is, the resolution conversion circuits 401 and 402 perform the same processing only with different video signals to be processed. Therefore, in this embodiment, since only the position of the resolution conversion circuit is different from that of the embodiment of FIG. 15, the same effect as that of the embodiment of FIG. 15 can be realized.

  In the above embodiment, the image quality improvement processing performed by the image quality improvement circuits 191 and 208 is to improve the image quality by performing gamma correction. However, in addition to the gamma correction, the color is corrected. At least one of a color correction to be performed, a sharpness correction to correct the image to a sharpened (sharp) image, an enhancement correction to correct an image with a blurred image, a contrast correction to correct a contrast, and the like. Thus, the image quality may be improved.

  In the above embodiment, the correction signal generation circuit 181 in FIG. 5 generates the correction signal based on the current frame and the frame one frame before that frame. It is also possible to generate a correction signal based on this frame and a frame n frames before that frame.

  Further, the case where the response speed of the LCD is corrected has been described above, but the present invention can also be applied to the case where the response speed of another display is corrected. Further, in addition to the television receiver, the present invention can be applied to a personal computer or other video signal processing apparatus having a display unit for displaying images.

  The series of processing performed by the video signal processing unit 95 of FIG. 3 described above can be executed by dedicated hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software can execute various functions by installing a so-called embedded computer or various programs. For example, it is installed from a program storage medium in a general-purpose personal computer or the like.

  FIG. 26 is a block diagram illustrating a configuration example of a computer that executes the above-described series of processing by a program.

  A CPU (Central Processing Unit) 901 executes various processes according to a program stored in a ROM (Read Only Memory) 902 or a storage unit 908. A RAM (Random Access Memory) 903 appropriately stores programs executed by the CPU 901, data, and the like. The CPU 901, ROM 902, and RAM 903 are connected to each other by a bus 904.

  An input / output interface 905 is also connected to the CPU 901 via the bus 904. Connected to the input / output interface 905 are an input unit 906 made up of a keyboard, mouse, microphone, and the like, and an output unit 907 made up of a monitor, a speaker, and the like. The CPU 901 executes various processes in response to a command input from the input unit 906. Then, the CPU 901 outputs the processing result to the output unit 907.

  The storage unit 908 connected to the input / output interface 905 includes, for example, a hard disk, and stores programs executed by the CPU 901 and various data. A communication unit 909 communicates with an external device via a network such as the Internet or a local area network.

  The drive 910 connected to the input / output interface 905 drives a removable medium 911 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, and drives the program or data recorded therein. Etc. The acquired program and data are transferred to and stored in the storage unit 908 as necessary.

  As shown in FIG. 26, a program recording medium that stores a program that is installed in a computer and is ready to be executed by the computer includes a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only). Memory, DVD (Digital Versatile Disc)), magneto-optical disk, removable medium 911 which is a package medium made of semiconductor memory, or ROM 902 in which a program is temporarily or permanently stored, or a storage unit 908 It is comprised by the hard disk etc. which comprise. The program is stored in the program recording medium using a wired or wireless communication medium such as a local area network, the Internet, or digital satellite broadcasting via a communication unit 909 that is an interface such as a router or a modem as necessary. Done.

  In the present specification, the step of describing the program stored in the program recording medium is not limited to the processing performed in time series in the order described, but is not necessarily performed in time series. Or the process performed separately is also included.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows the structure of the conventional television receiver. It is a block diagram which shows the other structure of the conventional television receiver. It is a block diagram which shows the structure of one Embodiment of the television receiver to which this invention is applied. It is a figure which shows the structure of one Embodiment of a video signal processing part. It is a block diagram which shows the structure of one Embodiment of a liquid-crystal response speed correction circuit. It is a figure explaining a lookup table. It is a flowchart explaining the video processing which a television receiver performs. It is a flowchart explaining the video signal process in step S11 of FIG. It is a flowchart explaining the liquid-crystal response speed correction process in step S37 of FIG. It is a block diagram which shows the structure of one Embodiment of a video signal processing part. It is a flowchart explaining the video signal processing which a video signal processing part performs. It is a block diagram which shows the structure of one Embodiment of a video signal processing part. It is a flowchart explaining the video signal processing which a video signal processing part performs. It is a block diagram which shows the structure of one Embodiment of a video signal processing part. It is a block diagram which shows the structure of one Embodiment of a video signal processing part. It is a block diagram which shows the structure of one Embodiment of a frame difference calculating part. It is a block diagram which shows the structure of one Embodiment of a liquid-crystal response speed correction circuit. It is a flowchart explaining the video signal processing which a video signal processing part performs. It is a flowchart explaining the frame difference calculation process in step S116 of FIG. It is a flowchart explaining the liquid-crystal response speed correction process in step S117 of FIG. It is a block diagram which shows the structure of one Embodiment of a liquid-crystal response speed correction circuit. It is a figure which shows the gamma curve used for the gamma correction which an image quality improvement circuit performs. It is a figure which shows the inclination of a gamma curve. It is a flowchart explaining the liquid crystal response speed correction process which a liquid crystal response speed correction circuit performs. It is a block diagram which shows the structure of one Embodiment of a video signal processing part. It is a block diagram which shows the structure of one Embodiment of a personal computer.

Explanation of symbols

  81 television receiver, 95 video signal processing unit, 96 LCD, 132 writing circuit, 133 storage device control circuit, 134 storage device, 135, 137 reading circuit, 139 liquid crystal response speed correction circuit, 181 correction signal generation circuit, 181a look Up table, 182 adder, 191, 201 high image quality circuit, 231 frame difference calculation unit, 232 liquid crystal response speed correction circuit, 283 subtractor, 284 delay adjustment circuit, 321 subtractor, 361 correction coefficient generation circuit, 362 multiplier

Claims (10)

Storage means for storing the input video signal;
Writing means for writing the input video signal to the storage means in order to synchronize with the synchronizing signal of the output video signal;
First reading means for reading out the video signal written in the storage means by the writing means in synchronization with a synchronization signal of an output video signal;
A video signal of an image temporally prior to the image of the video signal read by the first reading means, wherein the video signal written to the storage means by the writing means A second reading means for reading in synchronization with the synchronization signal;
Based on the video signal read by the first reading unit and the video signal read by the second reading unit, the response speed of the display unit that displays the image of the output video signal is corrected. Generating means for generating a correction signal to be
A video for correcting the response speed of the display unit that displays an image of the video signal read by the first reading means from the video signal read by the first reading means based on the correction signal. A video signal processing apparatus comprising: correction means for generating a signal and outputting the signal to the display unit. Further comprising high image quality conversion means for converting an image of the video signal read by the first reading means into a high quality image having a higher image quality than the image;
The generation means generates the correction signal based on the video signal of the high quality image and the video signal read by the second reading means,
The video signal according to claim 1, wherein the correction unit generates a video signal for correcting a response speed of the display unit that displays the high-quality image, from the video signal of the high-quality image, based on the correction signal. Processing equipment. The video signal processing apparatus according to claim 2, wherein the image quality improving unit increases the image quality of the image by at least one of gamma correction, color correction, sharpness correction, enhancement correction, and contrast correction. And further comprising other image quality improving means for converting the image of the video signal read by the second reading means into another high quality image having a higher image quality than the image,
The video signal processing apparatus according to claim 2, wherein the generation unit generates the correction signal based on a video signal of the high quality image and a video signal of the other high quality image. The video signal processing apparatus according to claim 4, wherein the other image quality improving means improves the image quality by at least one of gamma correction, color correction, sharpness correction, enhancement correction, and contrast correction. First differential video signal generation for generating a first differential video signal by subtracting the video signal read by the second readout means from the video signal read by the first readout means Means,
A second differential video signal generating means for generating a second differential video signal by subtracting the first differential video signal from the video signal of the high-quality image;
The video signal processing apparatus according to claim 2, wherein the generation unit generates the correction signal based on a video signal of the high-quality image and the second differential video signal. A differential video signal correcting unit that corrects the first differential video signal and converts the first differential video signal into a corrected differential video signal;
The video signal processing according to claim 6, wherein the second differential video signal generation unit generates the second differential video signal by subtracting the corrected differential video signal from the video signal of the high-quality image. apparatus. The image quality enhancement means performs gamma correction on at least the video signal,
A correction coefficient generating means for generating a correction coefficient corresponding to the gamma correction;
The video signal processing device according to claim 7, wherein the differential video signal correcting unit converts the first differential video signal into the corrected differential video signal using the correction coefficient. In order to synchronize the input video signal with the synchronization signal of the video signal to be output, a writing step of writing in the storage unit that stores the input video signal;
A first reading step of reading out the video signal written in the storage unit by the writing step in synchronization with a synchronization signal of an output video signal;
An image signal of an image temporally prior to the image of the image signal read by the first reading step, wherein the image signal written to the storage unit by the writing step A second reading step for reading in synchronization with the synchronization signal;
Based on the video signal read in the first read step and the video signal read in the second read step, the response speed of the display unit that displays the image of the output video signal is corrected. Generating a correction signal to generate,
A video for correcting a response speed of the display unit that displays an image of the video signal read by the first reading step from the video signal read by the first reading step based on the correction signal. A video signal processing method comprising: a correction step of generating a signal and outputting the signal to the display unit. In order to synchronize the input video signal with the synchronization signal of the video signal to be output, a writing step of writing in the storage unit that stores the input video signal;
A first reading step of reading out the video signal written in the storage unit by the writing step in synchronization with a synchronization signal of an output video signal;
An image signal of an image temporally prior to the image of the image signal read by the first reading step, wherein the image signal written to the storage unit by the writing step A second reading step for reading in synchronization with the synchronization signal;
Based on the video signal read in the first read step and the video signal read in the second read step, the response speed of the display unit that displays the image of the output video signal is corrected. Generating a correction signal to generate,
A video for correcting a response speed of the display unit that displays an image of the video signal read by the first reading step from the video signal read by the first reading step based on the correction signal. A program that causes a computer to execute processing including a correction step of generating a signal and outputting the signal to the display unit.

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