JP2009016518A - Multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simple manufacturing method of a multilayer wiring board, for improving a yield, reducing the number of processes and inhibiting the generation of useless materials. <P>SOLUTION: The manufacturing method includes: (1) a process of half-etching a first conductor plate and forming a first conductive layer provided with a wiring part and a via part arranged in an island shape; (2) a process of arranging an insulating material around the first conductive layer and forming a first conductive pattern layer provided with the first conductive layer and a first insulation part; (3) a process of arranging a second conductor plate on the surface of the first conductive pattern layer; (4) a process of half-etching the second conductor plate and forming a second conductive layer provided with a wiring part and a via part arranged in an island shape; and (5) a process of arranging the insulating material around the second conductive layer and forming a second conductive pattern layer provided with the second conductive layer and a second insulation part on the first conductive pattern layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention provides a conductive pattern layer comprising a conductive layer having a wiring portion and at least one via portion disposed in an island shape on the wiring portion, and an insulating portion disposed around the conductive layer. The present invention relates to a method for manufacturing a laminated multilayer wiring board and a multilayer wiring board obtained by the method.

With recent downsizing and weight reduction of electronic devices, wiring boards constituting the electronic devices are also required to be smaller and lighter. As a measure for reducing the size and weight of the wiring board, there is a method of increasing the density by multilayering the wiring board.
Here, in a multilayer wiring board in which wiring boards are multilayered, a wiring portion is usually arranged on a base material, an insulating material is further arranged thereon, and another wiring pattern is further arranged on the insulating material. Is laminated by repeating. In this multilayer wiring board, in order to electrically couple the lower wiring pattern and the upper wiring pattern, a part of the insulator is replaced with a conductor called a via. Various methods have been developed to create this via.
For example, in Patent Document 1, a wiring part (conductive pattern 13) is arranged on a base material (insulating base material 11), a resist pattern (14) including a via hole (via hole 15) is formed thereon, A metal to be a via (copper pattern 16) is embedded in the via hole (via hole 15) (FIGS. 1A to 1D). Next, the resist pattern (14) is removed to form a via (copper pattern 16) (FIG. 1 (e)). However, this method requires the formation and removal of separate resist patterns for forming the wiring portion and the via, and the process is complicated. Also, the metal filling in the via hole tends to be incomplete, and the formation of the via may be incomplete. Furthermore, since this resist pattern is not included in the final multilayer wiring board, wasteful materials are generated.
Moreover, in patent document 2, the wiring part (wiring layer 2) on a base material (21) is protected with a conductor (23) having resistance at the time of etching, and metal plating (24) is applied on the conductor (23). Disclosed is a method of forming a via (columnar metal body 24) by removing unnecessary metal plating after applying a mask layer (25) to a portion where the (columnar metal body 24) is to be formed (FIGS. 1 to 1). 3). However, in this method, it is necessary to protect the wiring pattern (wiring layer 22) with a conductor (23) having resistance during etching, and the process is complicated.

JP-A-6-314878 International Publication WO00 / 30420 Pamphlet JP 2004-95757 A

A first object of the present invention is to provide a simple method for manufacturing a multilayer wiring board.
A second object of the present invention is to provide a method for manufacturing a multilayer wiring board that has a good yield, reduces the number of steps, and does not generate wasteful materials.

The present inventor reduces the manufacturing process of the multilayer wiring board and generates useless material by simultaneously creating the wiring part and the via part by using the half etching technique capable of etching only a part of the conductor. Thus, the present inventors have found that a multilayer wiring board having a target structure can be manufactured without arriving at the present invention.
Specifically, the present invention
1. Multilayer wiring in which a conductive layer having a wiring portion and at least one via portion arranged in an island shape on the wiring portion, and a conductive pattern layer including an insulating portion arranged around the conductive layer is laminated A method for manufacturing a substrate, comprising:
(1) Half-etching the first conductor plate from the surface so as to leave a via part and a wiring part, and forming a first conductive layer having a wiring part and a via part arranged in an island shape on the wiring part Forming step;
(2) An insulating material is disposed around the first conductive layer to form a first insulating portion, and a first conductive pattern layer including the first conductive layer and the first insulating portion is formed. The step of:
(3) a step of disposing a second conductor plate on the surface of the first conductive pattern layer;
(4) A second conductive layer having a wiring portion and a via portion disposed in an island shape on the wiring portion by half-etching the second conductive plate from the surface so as to leave a via portion and a wiring portion. And (5) a second insulating portion is formed around the second conductive layer to form a second insulating portion, and a second conductive layer and a second insulating portion are provided. Forming a conductive pattern layer on the first conductive pattern layer,
The present invention relates to a method for manufacturing a multilayer wiring board.
2. The second conductor plate in the step (3) comprises a metal plating layer disposed on the surface of the first conductive pattern layer and a conductor layer disposed on the surface of the metal plating layer, The manufacturing method according to 1.
3. The manufacturing method according to 2 above, wherein the metal plating layer is disposed on a part of the surface of the first conductive pattern layer.
4). A conductive layer that is manufactured by the manufacturing method according to any one of 1 to 3 above and includes a wiring portion and at least one via portion arranged in an island shape on the wiring portion, and the periphery of the conductive layer The present invention relates to a multilayer wiring board in which a conductive pattern layer including an insulating portion disposed on the substrate is laminated.

The present invention can provide a simple method for manufacturing a multilayer wiring board.
The present invention can provide a method for manufacturing a multilayer wiring board that has a good yield, reduces the number of steps, and does not generate wasteful materials.

(A) Manufacturing method of multilayer wiring board As described above, the present invention includes a wiring portion and at least one via portion arranged in an island shape on the wiring portion, including the steps (1) to (5). A method of manufacturing a multilayer wiring board in which a conductive pattern layer including a conductive layer having an insulating portion disposed around the conductive layer is laminated. Hereinafter, each process will be described with reference to FIG.

(A-1) First Mode of Manufacturing Method of Multilayer Wiring Substrate (1) Half etching is performed on the first conductor plate so as to leave a via portion and a wiring portion from the surface, and an island shape is formed on the wiring portion and the wiring portion. Step of Forming First Conductive Layer Having Via Part Arranged in Firstly, a first conductor plate (1) is prepared. The first conductor plate (1) may be disposed on the substrate (2). The first conductor plate (1) is made of a plate-like conductive material having a substantially uniform thickness. The first conductor plate (1) may have a flat plate shape or a necessary wiring circuit shape in advance.
Such a first conductor plate (1) is half-etched so as to leave the via portion (4) and the wiring portion (5) from the upper surface of the first conductor plate (1).
The portion to be the via portion (4) is slightly etched or not etched, and the thickness of the first conductor plate (1) remains as it is. The wiring portion (5) is formed by etching (half etching) a part of the first conductor plate (1) in the thickness direction of the first conductor plate (1). The wiring portion may have a flat plate shape or a circuit shape. When the wiring portion is flat, the first conductor plate (1) does not etch the portion that becomes the via portion (4), and all other portions are in the thickness direction of the first conductor plate (1). On the other hand, only a part is etched to form a wiring part (5). When the wiring portion has a circuit shape, the portion that becomes the via portion (4) is not etched, and the portion that becomes the wiring portion (5) is only a part in the thickness direction of the first conductor plate (1). Etching is performed, and all other portions are removed by etching in the thickness direction of the first conductor plate (1). The wiring portion may have a thickness such that the side opposite to the side where the via portion (4) is formed can be further half-etched. Such a wiring part can be a wiring part having a necessary circuit shape by performing etching or the like later, and further half-etching the surface opposite to the via part (4) in a later step, Another via part can be formed on the side opposite to the via part (4), and a wiring part having a required circuit shape can be formed.

Here, half-etching means a method of etching while leaving a part of the material to be etched in the thickness direction of the material to be etched. In the term of half-etching, a portion that is not etched, a portion that is etched while leaving a portion of the etching material, and a portion that etches all of the etching material are formed in the thickness direction of the material to be etched. Partially etching. Specifically, when the via portion and the wiring portion are formed from the first conductor plate, a resist is formed on the portion of the first conductor plate to be the via and protected from etching, thereby forming the via. The portion of the first conductor plate to be the wiring portion is 30 to 98%, preferably 40 to 98%, more preferably 50 to 95% of the thickness of the first conductor plate. Preferably, the wiring portion is formed by etching 60 to 95% without etching the rest. Such control of the etching amount can be achieved, for example, by adjusting the etching time. In particular, the etching amount can be controlled more accurately by slowing the etching rate and adjusting the etching time. As an etching method, a known etching method can be used, and examples thereof include chemical etching and mechanical processing methods. Examples of chemical etching include photo etching, wet etching, and dry etching, and examples of mechanical processing include laser processing, end milling, milling, and the like.
In particular, as a chemical etching method that can be used for half-etching, for example, when the material of the first conductor plate is copper, an alkaline etching solution such as a copper ammonium complex salt, ammonium persulfate, a mixture of hydrogen peroxide and sulfuric acid, chloride There is a method in which copper, which is the material of the first conductor plate, is partially dissolved using cupric, ferric chloride or the like as an etching solution. Here, as a method of partially dissolving, a mask material is previously coated on a portion not to be etched, such as a via portion, and then exposed to an etching solution, and after partial etching progresses, a thickness that becomes a wiring portion is increased. There is a method of stopping the etching in the state of being left.

  As a resist forming method for protecting a portion of the conductor plate to be the via portion, a generally known resist forming method can be adopted. For example, a method of covering a portion to be protected from etching with a mask material and a photoresist method can be mentioned. In the photoresist method, for example, a resist material is applied to the surface of a conductor plate by screen printing, and a portion to be protected from etching is exposed by irradiating with UV light. And a portion to be a via portion by using an appropriate combination to coat the portion with a photocured resist material. As the resist material, for example, an epoxy-based or acrylic-based photocurable resin or thermosetting resin can be used alone or in combination. Note that, after etching, the resist material is also peeled off by appropriately combining removers described later.

(2) An insulating material is disposed around the first conductive layer to form a first insulating portion, and a first conductive pattern layer including the first conductive layer and the first insulating portion is formed. The first insulating portion (7) is formed by disposing an insulating material around the first conductive layer (3) formed in the step (1) (aside from the top and bottom surfaces and around the side). Accordingly, the surface of the via portion (4) of the first conductive layer (3) and the surface of the first insulating portion (7) form a flat or substantially flat surface. When the wiring portion (5) has a circuit shape instead of a flat plate type, the bottom surface of the wiring portion (5) of the first conductive layer (3) and the bottom surface of the first insulating portion (7) are flat or substantially. A flat surface is formed. When the wiring part (5) is a flat plate type, only the wiring part (5) is exposed on the bottom surface, and the bottom surface of the wiring part (5) forms a flat or substantially flat surface.
That is, as one aspect, the portion of the first conductor plate (1) removed by half etching is replaced with an insulating material. When the first conductor plate (1) having a necessary wiring circuit shape is used in advance, in addition to the portion removed by the half etching, the lower surface of the wiring portion (5) of the first conductive layer (3) Then, an insulating material is applied to the height of the upper surface of the via portion (4), and the first insulating portion (7) is formed so that both surfaces of the obtained first conductive pattern layer (6) are flat.
Thus, the first conductive pattern layer (6) including the first conductive layer (3) and the first insulating portion (7) is formed. The first conductive pattern layer (6) is a flat plate type having the same or substantially the same thickness as the first conductive layer. The surface of the first conductive pattern layer (6) is flat or substantially flat. On the upper surface of the first conductive pattern layer (6), the upper surface of the via portion (4) of the first conductive layer (3) and the upper surface of the first insulating portion (7) are exposed. Only the bottom surface of the wiring part (5) or the bottom surface of the wiring part (5) and the bottom surface of the first insulating part (7) are exposed on the lower surface of the first conductive pattern layer (6). In order to make the surface of the first conductive pattern layer (6) flat or substantially flat, the surface of the first conductive pattern layer (6) may be appropriately ground and polished. Examples of the grinding method include a method using a grinding device having a hard rotary blade in which a plurality of hard blades made of diamond or the like are arranged in the radial direction of the rotary plate. By moving the hard rotary blade while rotating along the surface of the first conductive pattern layer fixedly supported, the surface can be flattened. Examples of the polishing method include a method of polishing by belt sander, buff polishing or the like. Furthermore, when the upper surface of the first insulating portion (7) is higher than the upper surface of the via portion (4), the insulating material of the insulating portion may be heated and pressed to be approximately the same height as the upper surface of the via portion. The remaining insulating material pieces may be removed by plasma treatment, grinding / polishing, or the like.
In addition, by the manufacturing method including the steps (1) and (2), a conductive layer having a wiring portion and at least one via portion arranged in an island shape on the wiring portion is disposed around the conductive layer. It is also possible to manufacture a single-layer wiring board having a conductive pattern layer having the same thickness as the conductive layer.

(3) A step of disposing a second conductor plate on the surface of the first conductive pattern layer. Further, a second conductive plate is formed on the surface of the first conductive pattern layer (6) obtained in the step (2). A conductor plate (8) is disposed. The second conductor plate (8) may be disposed by a method such as adhesion or pressure bonding.
For example, in the case of adhesion, a curable resin as an adhesive is applied to the surface of the first conductive pattern layer (6), and after the second conductive plate is further disposed, the curable resin is cured by heating or the like. The method of letting it be mentioned. At this time, after placing the conductor plate after semi-curing the curable resin, the curable resin may be finally cured.

(4) A second conductive layer having a wiring portion and a via portion disposed in an island shape on the wiring portion by half-etching the second conductive plate from the surface so as to leave a via portion and a wiring portion. As in the step (1), the second conductor plate (8) is half-etched from the surface so as to leave the via part (10) and the wiring part (11), and the wiring part (11) and A second conductive layer (9) having a via portion (10) is formed. The definition and method of half-etching are the same as in step (1).
At this time, the wiring part (11) of the second conductive layer (9) may be arranged independently of the position of the wiring part (5) of the first conductive layer (3). For example, the wiring part (11) of the second conductive layer (9) may be disposed on the surface of the first insulating part (7). Further, the via part (4) of the second conductive layer (9) may be arranged independently of the position of the via part (4) of the first conductive layer (3).
In the half etching of the second conductor plate (8), it is preferable not to etch the first conductive pattern layer (6). The via portion (4) and the first insulating portion (7) are exposed on the surface of the first conductive pattern layer (6). These via portion (4) and the first insulating portion (7) It is preferable not to remove by etching. In order not to etch the via part (4) and the first insulating part (7), for example, there is a method of laminating a protective film having etching resistance on the surface of the first conductive pattern layer (6). Examples of the protective film include a film obtained by subjecting a film made of a polyester resin typified by polyethylene terephthalate, polypropylene, and a polyolefin resin typified by polyethylene to adhesion processing. Further, as the second conductor plate, there is a method in which a material different from that of the first conductor plate is used and only the second conductor plate is etched without etching the first conductive pattern layer (6). . In addition, there are a method for controlling the etching time and a method for processing only the second conductor plate by a mechanical processing method.

(5) An insulating material is disposed around the second conductive layer to form a second insulating portion, and the second conductive pattern layer including the second conductive layer and the second insulating portion is formed as the second conductive pattern layer. Step of forming on the first conductive pattern layer As in the step (2), around the second conductive layer (9) formed in the step (4) (sideways except for the vertical direction). A second insulating part (13) is formed by disposing an insulating material, and a second conductive pattern layer (12) having a second conductive layer (9) and a second insulating part (13) is obtained. .
That is, as one embodiment, the portion of the second conductor plate (8) removed by half etching is replaced with an insulating material. When the second conductor plate (8) having the necessary wiring circuit shape is used in advance, in addition to the portion removed by the half etching, the lower surface of the wiring portion (11) of the second conductive layer (9) Then, an insulating material is applied to the height of the upper surface of the via portion (10), and the second insulating portion (13) is formed so that both surfaces of the obtained second conductive pattern layer (12) are flat.
The second conductive pattern layer (12) is a flat plate type having the same or substantially the same thickness as the second conductive layer. The second conductive pattern layer (12) is disposed on the first conductive pattern layer (6). The surface of the second conductive pattern layer (12) is flat or substantially flat. On the upper surface of the second conductive pattern layer (12), the upper surface of the via portion (10) and the upper surface of the second insulating portion (13) of the second conductive layer (9) are exposed. Only the bottom surface of the wiring portion (11) or the bottom surface of the wiring portion (11) and the bottom surface of the second insulating portion (13) are exposed on the lower surface of the second conductive pattern layer (12). In order to make the surface of the second conductive pattern layer (12) flat or substantially flat, the surface of the second conductive pattern layer (12) may be ground and polished as appropriate. Same as layer (6). In addition, the method for forming the second insulating portion and the method for forming the second conductive pattern layer are the same as in step (2).

(6) Arbitrary Additional Laminating Step The multilayer wiring board of the present invention having two conductive pattern layers is formed by the above steps (1) to (5). In the multilayer wiring board of the present invention, it is possible to laminate two or more conductive pattern layers, for example, 2 to 8 layers. When three or more conductive pattern layers are laminated in this way, the above steps (3) to (5) or the steps (3) ′ to (5) ′ described below are further repeated after the step (5). May be. However, for example, when applying the third conductive pattern layer, in the description of the steps (3) to (5) or (3) ′ to (5) ′, “first” is “second”, “Second” is read as “third”. The same applies to the third and subsequent layers.

(A-2) Second Aspect of Manufacturing Method of Multilayer Wiring Substrate The manufacturing method of the multilayer wiring substrate of the present invention includes the second conductor plate in the step (3) during the steps (1) to (5). You may consist of the metal plating layer arrange | positioned on the surface of the said 1st conductive pattern layer, and the conductor arrange | positioned on the surface of this metal plating layer. That is, the multilayer wiring board of the present invention may be manufactured as follows.
-First, a 1st conductive pattern layer is formed according to the said (1)-(2) process.
-Then, after disposing a metal plating layer on the surface of the first conductive pattern layer, a conductor is disposed on the metal plating layer, and a second conductor plate including the metal plating layer and the conductor layer is provided. Form (step (3) ′).
-Further, a second conductive pattern layer is formed in the same manner as in the above steps (4) and (5) (steps (4) 'and (5)').
Hereinafter, these steps (3) ′ to (5) ′ will be described with reference to FIG. 2 as appropriate.

(3) 'A second conductor plate including a metal plating layer disposed on the surface of the first conductive pattern layer, a conductor disposed on the metal plating layer, and the metal plating layer and the conductor layer. The metal plating layer (14) includes a via portion (4) of the first conductive pattern layer (6) having conductivity and a first portion of the first conductive pattern layer (6) having no conductivity. It can be applied on both surfaces of the insulation (7). Therefore, the metal plating layer is preferably applied by an electroless plating method. Alternatively, a metal foil may be used as the metal plating layer, and the metal foil may be disposed on the surface of the first conductive pattern layer by a method such as pressure bonding.

As a third aspect of the method for manufacturing a multilayer wiring board of the present invention, the metal plating layer may be disposed on a part of the surface of the first conductive pattern layer. For example, as shown in FIGS. 3 (a) and 3 (b), the metal plating layer (14) is disposed only in a portion where the second conductive layer (9) is to be applied. After that, if a conductive material is applied using an electrolytic plating method, the conductor layer is applied only on the metal plating layer (14), and is applied to other parts such as the first insulating portion (7). Not. Thereby, since the second conductor plate (8) can be applied only to a necessary portion, the amount of the second conductor plate removed by etching after that can be suppressed.
As a method of arranging the metal plating layer only on a part of the surface of the first conductive pattern layer, a method of press-bonding a metal foil of a predetermined shape onto the first conductive pattern layer, or a general resist forming method is used. Can be used. As the resist forming method, the photoresist method described in the step (1) can be used. For example, first, a metal plating layer is applied to the entire surface of the first conductive pattern layer by a method such as electroless plating. After that, a resist material is applied to the surface of the metal plating layer, and only the portion to which the second conductive layer (9) is to be applied is irradiated with UV light and exposed, and the unexposed portion of the resist material is used with a solvent. Remove. Thereafter, by removing the portion of the metal plating layer not covered with the resist material by etching, the metal plating layer can be disposed only on a part of the surface of the first conductive pattern layer.

  Thus, after arrange | positioning a metal plating layer (14) on the whole surface or a part of 1st conductive pattern layer (6), a conductor is arrange | positioned on a metal plating layer (14) and a metal plating layer (14 ) And a conductor layer (15), a second conductor plate (8) is formed. As a conductor to be disposed, the same or different material as the first conductor plate and the metal plating layer can be used. The conductor can be arranged using a method such as electrolytic plating, electroless plating, adhesion, or pressure bonding. In particular, when the metal plating layer (14) is disposed only on a part of the surface of the first conductive pattern layer (6), the conductor is disposed only on the upper portion of the metal plating layer (14) by using the electrolytic plating method. This is preferable.

(4) 'The second conductor plate including the metal plating layer and the conductor layer is half-etched so as to leave a via part and a wiring part from the surface, and arranged in an island shape on the wiring part and the wiring part. Step of Forming Second Conductive Layer Having Via Portion (4) ′ Step is performed in the same manner as the above step (4). The method and conditions for half-etching are the same as in the above steps (1) and (4). However, since the metal plating layer forms a part of the second conductor plate, it can be etched in the same manner as the conductor plate by half etching.

(5) 'An insulating material is disposed around the second conductive layer to form a second insulating portion, and has the same thickness as the second conductive layer and the second conductive layer and the second conductive layer. The step (5) ′ of forming the second conductive pattern layer having the insulating portion on the first conductive pattern layer is performed in the same manner as the step (5).
When the metal plating layer is arranged on a part of the surface of the first conductive pattern layer and the second conductor plate having the necessary wiring circuit shape is used in advance, the portion removed by the half etching In addition, an insulating material is applied from the lower surface of the wiring portion of the second conductive layer to the height of the upper surface of the via portion, and the second insulating portion is formed so that both surfaces of the obtained first conductive pattern layer are flat.
In addition, as in the step (6), as the step (6) ′, a further multilayering step may be added to manufacture a multilayer wiring board in which three or more layers are laminated.

(A-3) Fourth Aspect of Manufacturing Method of Multilayer Wiring Substrate In the first and second embodiments, an example in which a via portion and a wiring portion are formed on one side of a conductor plate has been shown. Separate and independent via portions may be simultaneously formed on both sides of the material, the conductive pattern layer and the like. For example, the conductor plate may be half-etched from the upper and lower surfaces to form separate independent via portions on both sides of the wiring portion. Alternatively, the first conductor plate may be applied to both surfaces of the base material (2), and a conductive pattern layer may be sequentially formed to form the multilayer wiring board of the present invention on both surfaces of the base material (2). Further, after applying the second conductor plate on the first conductive pattern layer, the wiring portion of the first conductive pattern layer and the second conductor plate are simultaneously half-etched to form separate independent via portions. It may be formed.
In this way, the process can be shortened by simultaneously forming separate and independent via portions on both sides simultaneously. Specifically, as shown in FIG. 4, first, the first conductor plate (1) (FIG. 4 (a)) is connected to the via portion (4) from the upper and lower surfaces of the first conductor plate (1). ) And (4 ′), and half-etched to leave the wiring part (5), and the via part (4) and (4) arranged in an island shape on both sides of the wiring part (5) and the wiring part (5). 1) is formed (FIG. 4B). Next, an insulating material is disposed around the first conductive layer (3) to form a first insulating portion (7), and the first conductive layer (3), the first insulating portion (7), A first conductive pattern layer (6) provided with is formed (FIG. 4 (c)). At this time, the insulating material is applied with the same thickness as the thickness of the first conductive layer (3) from the upper surface of the via part (4) to the via part (4 ′). The first conductive pattern layer (6) thus obtained has a flat or substantially flat plate shape with the upper surfaces of the via portions (4) and (4 ') and the surface of the first insulating portion (3) exposed. is doing.
Although the case where the first conductor substrate is half-etched from the upper and lower surfaces has been described above, other conductor substrates such as second and third conductors may be half-etched from the upper and lower surfaces in the same manner. The multilayer wiring board can also be manufactured by forming a wiring circuit by providing a conductor such as metal foil on at least one surface of the first conductive pattern layer.

(A-4) Circuitization step A circuit may be formed on the surface of the multilayer wiring board obtained as described above. First, a conductor is appropriately disposed on the upper surface of the multilayer wiring board obtained as described above. Protect the portion of the circuit where the circuit is formed by the resist formation method described in step (1), remove the unnecessary conductor by etching, etc., and then remove the resist material to form the circuit. To do. Such a circuitization step may be performed simultaneously with the circuitization of the lower surface of the multilayer wiring board. That is, the wiring part (5) formed from the conductor plate (1) in the step (1) may have a flat plate shape that does not have a circuit shape. In such a case, a resist material is applied along the circuit pattern to the surface of the wiring portion as well as the surface of the conductor applied to the upper surface of the multilayer wiring board, and the circuit is subjected to etching and resist material peeling. Can be formed. For example, the circuitization process is performed as shown in FIG. First, a first conductive pattern layer (6) formed in the step (2) is prepared (FIG. 5 (a)). The conductive pattern layer (6) has a flat wiring portion (5) which is not a circuit shape at the bottom. Next, a metal plating layer (14) is applied to the surface of the first conductive pattern layer (6) (FIG. 5 (b)). The metal plating layer (14) may be applied by an electroless plating method, a method of performing an electroplating method after the electroless plating method, or the like, or by pressing a metal foil. Next, a portion where a circuit is to be formed is covered with a resist (20) (20) 'using the above-described photoresist method or the like (FIGS. 5 (c)-(d)), and then an unnecessary conductor is formed by etching. Then, the wiring portion is removed (FIG. 5 (e)), and the resists (20) and (20) ′ are further removed (FIG. 5 (f)), and a desired circuit is formed. Here, the method of circuitizing the upper and lower surfaces of the first conductive pattern layer (6) is shown. However, the multilayer wiring board of the present invention is used instead of the first conductive pattern layer (6). The upper and lower surfaces of the substrate may be circuitized.

(B) Specific Aspect of Manufacturing Method of Multilayer Wiring Substrate Hereinafter, the first aspect of the manufacturing method of the multilayer wiring substrate of the present invention will be described more specifically with reference to FIG.
First, a first conductor plate (1) is prepared (FIG. 6 (a)). Next, a resist (20) is applied to the portion of the first conductor plate (1) that becomes the via portion (4) (FIG. 6 (b)), and the resist (20) is exposed and cured, but not cured. Then, the resist (20) is removed to cover the portion to be the via portion (4) (FIG. 6C). Next, the first conductor plate (1) is half-etched to form a via portion (4) which is a portion not etched and a wiring portion (5) which is a portion where a part of the thickness is etched (FIG. 6). (d)) The resist material is peeled to obtain the first conductive layer (3) (FIG. 6 (e)) (step (1)).
A first insulating portion (7) is formed by applying an insulating material to the half-etched portion of the first conductive plate (1), and the first conductive layer (3) and the first insulating portion (7) are formed. A flat-plate-type first conductive pattern layer (6) having the following structure is formed (FIG. 6 (f)) (step (2)). Here, a flat surface having no step is formed at the boundary between the upper surface of the via part (4) and the upper surface of the first insulating part (7).
A second conductor plate (8) is further arranged on the surface of the first conductive pattern layer (6) (FIG. 6 (g)) (step (3)).
A resist (20) is applied to the second conductor plate (8) (FIG. 6 (i)), the resist (20) is exposed and cured, and the uncured resist (20) is removed to remove the via portion. The portion to be (10) is covered (FIG. 6 (i)). The second conductor plate (8) is half-etched to form a via portion (10) which is a portion not etched and a wiring portion (11) which is a portion where a part of the thickness is etched (FIG. 6 (j )), The resist (20) is removed to obtain the second conductive layer (9) (FIG. 6 (k)) (step (4)).
The second insulating layer (13) is applied from the bottom surface of the wiring portion (11) of the second conductive layer (9) to the height of the top surface of the via portion (10), and the second conductive layer (9) and the second conductive layer (9) The second conductive pattern layer (12) having the insulating portion (13) is formed (FIG. 6 (l)) (step (5)). Here, a flat surface without a step is formed at the boundary between the upper surface of the via part (10) and the upper surface of the second insulating part (13).

  Further, as shown in the second aspect of the method for manufacturing a multilayer wiring board of the present invention, the second conductor plate (8) may be formed by disposing a metal plating layer by electroless plating. . Specifically, as shown in FIGS. 6 (g) 'and (g) ", a metal plating layer (14) is disposed on the surface of the first conductive pattern layer (6) by electroless plating, and then electrolysis is performed. A conductor layer (15) is disposed on the metal plating layer (14) by plating to form a second conductor plate (8) including the metal plating layer (14) and the conductor layer (15). (Step (3) ′).

Furthermore, as shown in the third aspect of the method for manufacturing a multilayer wiring board of the present invention, the metal plating layer may be disposed only on a part of the surface of the first conductive pattern layer.
Specifically, a metal plating layer (14) is disposed on the surface of the first conductive pattern layer (6) (FIG. 6 (o)). Next, a resist (20) is applied to the portion of the second conductor plate (8) that will become the wiring portion (11) (FIG. 6 (p)), and the resist (20) is exposed and cured, but not cured. The resist (20) is removed to cover the portion to be the wiring portion (11) (FIG. 6 (q)). The metal plating layer (14) is etched to the surface of the first conductive pattern layer (6) (FIG. 6 (r)), and then the resist (20) is peeled off to form the wiring portion (11). ) Is formed (FIG. 6 (s)). Further, a conductor layer (15) is disposed on the metal plating layer (14) by electrolytic plating, and a second conductor plate (8) including the metal plating layer (14) and the conductor layer (15) is provided. Form (FIG. 6 (t)) (step (3) ′).
Resist (20) is applied to the portion of the second conductor plate (8) that becomes the via portion (10) (FIG. 6 (u)), and the resist (20) is exposed and cured, and the resist that has not been cured. (20) is removed to cover the portion to be the via portion (10) (FIG. 6 (v)). The conductor layer (15) is half-etched to form a via portion (10) which is a portion not etched and a wiring portion (11) which is a portion where a part of the thickness is etched (FIG. 6 (w)), The resist (20) is peeled off to obtain the second conductive layer (9) (FIG. 6 (x)) (step (4) ′).
The second insulating portion (13) is applied from the bottom surface of the wiring portion (11) of the second conductive layer (9) to the height of the upper surface of the via portion (10), and the second conductive layer (9) and the second conductive layer (9) The second conductive pattern layer (12) having the insulating portion (13) is formed (FIG. 6 (y)) (step (5) ′). Here, a flat surface without a step is formed at the boundary between the upper surface of the via part (10) and the upper surface of the second insulating part (13).

Furthermore, as one of the fourth aspects of the method for manufacturing a multilayer wiring board according to the present invention, a specific example in which the conductor plate is half-etched from the upper and lower surfaces to form separate via portions on both sides of the wiring portion. Will be described with reference to FIG.
First, similarly to FIGS. 6 (a) to 6 (g), a laminate of the first conductive pattern layer (6) and the second conductive plate (8) disposed thereon is prepared (FIG. 6). 7 (a)). However, the wiring part (5) of the first conductive pattern layer (6) is a flat wiring part having a thickness that allows half-etching later. A resist (20) is further applied to the lower surface of the first conductive pattern layer (6) and the upper surface of the second conductive plate (8) of the laminate (FIG. 7 (b)), and the resist (20) is applied. The resist (20) that has been cured by exposure is removed, and the uncured resist (20) is removed to cover the portions to be the via portions (10) and (16) (FIG. 7 (c)). The wiring part (5) and the second conductor plate (8) are half-etched at the same time, and the via parts (10) and (16) which are not etched parts, and the wiring part which is a part where a part of the thickness is etched. (5) is formed (FIG. 7 (d)), and the resist (20) is peeled off to obtain the second conductive layer (9) and the via part (16) (FIG. 7 (e)).
The second insulating portion (13) is applied from the bottom surface of the wiring portion (11) of the second conductive layer (9) to the height of the upper surface of the via portion (10), and the second conductive layer (9) and the second conductive layer (9) A second conductive pattern layer (12) having the insulating portion (13) is formed (FIG. 7 (f)). At the same time, the third insulating portion (17) is applied from the wiring portion (5) to the height of the via portion (16), and the wiring portion (19) is applied thereon to form the third conductive pattern layer (18). ) Is formed (FIGS. 7 (f) (g)).

(C) Material constituting multilayer wiring board (1) Conductive material The conductive material is a conductor plate of the present invention, a conductor plate such as a first conductor plate or a second conductor plate, a conductor layer, Used for substrates and metal foils. The first and second conductive layers, the via portion and the wiring portion constituting the conductive layer are also formed by etching the conductor plate, and thus are made of the same material.
The conductive material may be any material having conductivity, and examples thereof include aluminum, copper, silver, nickel, tin, and alloys of these metals. In addition, the electroconductive material used for each conductor plate may be the same or different.
The metal used as the metal substrate and metal foil of the present invention may be aluminum, iron, copper, or an alloy of the above metals, but aluminum, copper, or an alloy thereof is preferable in consideration of heat dissipation. Further, if necessary, surface treatment such as sandblasting, etching, various plating treatments, coupling agent treatment, etc. can be appropriately selected on the adhesion surface side with the insulation layer in order to improve adhesion with the insulation layer. .
The thickness of the metal substrate is preferably 13 to 4000 μm. If it is 13 μm or more, wrinkles will not occur during handling. The upper limit is not technically limited, but is practical as a metal base circuit board if the thickness of the metal board is 4000 μm or less.
The thickness of each conductive pattern layer is preferably 13 to 200 μm, more preferably 20 to 150 μm.

(2) Conductive layer The conductive layer is obtained by half-etching a conductive plate as described above. Therefore, the conductive layer is the same material as the conductor plate.
The conductive layer has a wiring portion and at least one via portion arranged in an island shape on the wiring portion. Here, the wiring portion is a portion having a circuit shape having a substantially uniform thickness.
The thickness of the wiring part included in the conductive layer is, for example, 13 to 200 μm, preferably 20 to 150 μm.
The via portion is arranged in an island shape on the wiring portion. Here, the “island shape” is a protruding portion having a convex shape that is scattered on the upper surface of the wiring portion.
The thickness of the via portion included in the conductive layer is, for example, 50 to 400 μm, preferably 60 to 300 μm, and more preferably 80 to 200 μm.

(3) Base material The same material as the following insulating material can be used as the base material. The thickness of the base material is, for example, 50 to 400 μm, preferably 60 to 300 μm, more preferably 80 to 200 μm. If it is 50 μm or more, electrical insulation can be secured, and if it is 400 μm or less, heat dissipation can be sufficiently achieved, and it can contribute to miniaturization and thickness reduction.

(4) Insulating material As the insulating material, a resin used for a circuit board such as a phenol resin, an imide resin, a silicone resin, or an epoxy resin can be selected. These resins can be used in combination with glass cloth or inorganic filler. In particular, those containing an inorganic filler and an epoxy resin are preferred for thermal conductivity and withstand voltage characteristics.
<Epoxy resin>
Examples of the epoxy resin include known epoxy resins such as naphthalene type, phenylmethane type, tetrakisphenolmethane type, biphenyl type, and bisphenol A alkylene oxide adduct type epoxy resins, among which the stress relaxation property is mentioned. For this reason, an epoxy resin in which the main chain has a polyether skeleton and is linear is preferable. The epoxy resin whose main chain has a polyether skeleton and has a main chain shape includes bisphenol A type, bisphenol F type epoxy resin, bisphenol A type hydrogenated epoxy resin, polypropylene glycol type epoxy resin, polytetramethylene glycol type epoxy. Examples thereof include aliphatic epoxy resins typified by resins, polysulfide-modified epoxy resins, and the like, and a plurality of these can be used in combination.
<Filler type>
As the inorganic filler contained in the epoxy resin, any inorganic filler may be used as long as it is electrically insulating and excellent in thermal conductivity. Examples of such substances include silicon oxide, aluminum oxide, aluminum nitride, boron nitride, magnesium oxide, and silicon nitride. These fillers may be used alone or in combination.
As a method for forming the insulating portion, various coaters can be used when applying an uncured liquid resin, and a hot press can be used when using a sheet-shaped resin. It is. Examples of the sheet-like resin include a prepreg obtained by impregnating a glass cloth with an epoxy resin, or a sheet obtained by making the curable resin into a sheet shape with a coater or the like, and the like.

(5) Conductive pattern layer A conductive pattern layer is a layer provided with the said conductive layer and the insulation part arrange | positioned around the said conductive layer.
Therefore, the thickness of the conductive pattern layer is the same as or substantially the same as that of the conductive layer, and is preferably, for example, 13 to 200 μm, and more preferably 20 to 150 μm.

(6) Metal plating layer Examples of the metal plating layer include copper, silver, nickel, tin, and alloys of these metals. The material used for the metal plating layer may be the same as or different from the material used for the conductor plate. However, it is not necessary to exhibit etching resistance during the half etching of the conductor plate. Preferably, the same material as the material used for the conductor plate that does not exhibit etching resistance during the half-etching of the conductor plate is ensured, and the uniformity of the material is ensured. It is appropriate from the viewpoint of
The thickness of the metal plating layer is, for example, 5 to 200 μm, preferably 5 to 150 μm, and more preferably 13 to 150 μm.
The thickness of the conductor layer used in combination with the metal plating layer is, for example, 5 to 500 μm, preferably 18 to 300 μm.
Examples of the arrangement method of the metal plating layer include an electroless plating method, a method of applying a conductive paste (conductive paint) containing a metal to be plated, solder coating using solder, and the like.
Specifically, in the electroless plating method, the first conductive pattern layer is immersed in a plating solution, and a predetermined temperature (for example, 15 to 150 ° C., preferably 25 to 100 ° C.) for a predetermined time (for example, 1 minute to 60 minutes, preferably 3 minutes to 30 minutes). The plating solution contains a metal / alloy material to be plated, an alkali source, a reducing agent, a chelating agent, and the like.
Examples of electroless plating include copper, nickel, gold, silver, zinc, and cobalt.
Electroless plating methods include displacement plating, contact plating, non-catalytic chemical plating, and autocatalytic chemical plating. A particularly preferable plating method is autocatalytic chemical plating.
A method of applying a conductive paste (conductive paint) containing a metal to be plated is performed by applying the conductive paste along the pattern of the wiring layer and then curing it. Here, the conductive paste includes a metal / alloy material to be plated, an alcohol solvent having a low viscosity and a low boiling point, an organic vehicle having a low viscosity and thermosetting properties, and a high heat resistance.
When the metal plating layer is disposed on a part of the surface of the first conductive pattern layer in the form of a wiring circuit, the conductive paste may be applied by screen printing.
Solder coating is a technique for coating a conductive pattern layer with solder. For example, when using a tin-lead solder alloy, the conductive pattern layer is treated with a flux.

(7) Mask material The mask material is a resist or a resist material used in the case of half-etching the conductor plate. As a mask material, a dry film resist, an organic compound resist, a metal resist, or the like can be used. Using such mask material, printing method, photolithography method, spin coating method, roll coating method, spray coating method, laminating method, electrolytic plating coating method, dispenser method, curtain coater method, dip coater method, etc. are utilized. Then, a mask is applied to a portion that is not etched.
In removing the mask material, methods such as removal of chemicals and peeling removal can be used. Examples of agents that can be used for removal include main agents such as hydroquinone, metol and phenidone, accelerators such as sodium hydroxide, borax, boric acid and sodium metaborate, and antioxidants such as sodium sulfite. And auxiliary solvents such as methylene chloride, ethyl acetate, isopropyl acetate and butyl acetate.

(8) Adhesive Examples of the adhesive used for adhesion between the first conductive pattern layer and the second conductive plate include, for example, epoxy-based, urethane-based, and acrylic-based adhesives.

It is the schematic of the 1st aspect of the manufacturing method of the multilayer wiring board of this invention. It is the schematic of the 2nd aspect of the manufacturing method of the multilayer wiring board of this invention. It is the schematic of the 3rd aspect of the manufacturing method of the multilayer wiring board of this invention. It is the schematic of the manufacturing method of the multilayer wiring board of this invention. It is the schematic of the manufacturing method of the multilayer wiring board of this invention. It is the schematic of the specific manufacturing method of the multilayer wiring board of this invention. It is the schematic of the specific manufacturing method of the multilayer wiring board of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st conductor board 2 Base material 3 1st conductive layer 4 Via part 5 Wiring part 6 1st conductive pattern layer 7 1st insulating part 8 2nd conductor board 9 2nd conductive layer 10 Via Part 11 wiring part 12 second conductive pattern layer 13 second conductor plate 14 metal plating layer 15 conductor layer 16 via part 17 third insulating part 18 third conductive pattern layer 19 wiring part 20 resist

Claims (4)

Multilayer wiring in which a conductive layer having a wiring portion and at least one via portion arranged in an island shape on the wiring portion, and a conductive pattern layer including an insulating portion arranged around the conductive layer is laminated A method for manufacturing a substrate, comprising:
(1) Half-etching the first conductor plate from the surface so as to leave a via part and a wiring part, and forming a first conductive layer having a wiring part and a via part arranged in an island shape on the wiring part Forming step;
(2) An insulating material is disposed around the first conductive layer to form a first insulating portion, and a first conductive pattern layer including the first conductive layer and the first insulating portion is formed. The step of:
(3) a step of disposing a second conductor plate on the surface of the first conductive pattern layer;
(4) A second conductive layer having a wiring portion and a via portion disposed in an island shape on the wiring portion by half-etching the second conductive plate from the surface so as to leave a via portion and a wiring portion. Forming; and
(5) An insulating material is disposed around the second conductive layer to form a second insulating portion, and the second conductive pattern layer including the second conductive layer and the second insulating portion is formed as the second conductive pattern layer. Forming on the first conductive pattern layer;
A method for producing a multilayer wiring board, comprising:   The second conductor plate in the step (3) comprises a metal plating layer disposed on the surface of the first conductive pattern layer and a conductor layer disposed on the surface of the metal plating layer. Item 2. The production method according to Item 1.   The manufacturing method according to claim 2, wherein the metal plating layer is disposed on a part of the surface of the first conductive pattern layer.   A conductive layer manufactured by the manufacturing method according to claim 1, having a wiring portion and at least one via portion arranged in an island shape on the wiring portion, and the conductive layer A multilayer wiring board in which a conductive pattern layer including an insulating portion disposed around is laminated.

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