JP2009016418A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for sufficient heat radiation for a fin FET. <P>SOLUTION: A semiconductor device has a P<SP>+</SP>common source semiconductor layer 2 of power supply level extended in an X axis direction and an N<SP>+</SP>common source semiconductor layer 3 of ground level extended in the X axis direction. A fin layer 4 has the source region 21, the channel region 22, and the drain region 23 of a P type fin FET 20, and the drain region 24, the channel region 25, and the source region 26 of an N type fin FET 30. The fin layer 4 is formed to connect the P<SP>+</SP>common source semiconductor layer 2 and N<SP>+</SP>common source semiconductor layer 3 to each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a three-dimensional structure MISFET (hereinafter referred to as “three-dimensional FET”).

  One technique for miniaturizing the MISFET (for example, suppressing the short channel effect) is a so-called three-dimensional FET having a structure for improving the channel charge control capability of the gate electrode, instead of a normal planar MISFET. A three-dimensional FET is a kind of SOI (silicon on insulator) device, and a fin MISFET (FinFET, finFET), a double gate FET (DG-FET), and the like are typical three-dimensional FETs.

  For example, Zheng Guo et al., "FinFET-Based SRAM Design", International Symposium on Low Power Electronics and Design, pp. 2-7, 2005 (ISLPED'05) is a three-dimensional FET, specifically a fin FET. An SRAM (static random access memory) composed of By adopting a fin FET as the SRAM FET, an SRAM with a small cell size can be realized.

  Such a three-dimensional FET such as a fin FET is also considered to be applied to a logic circuit, but one of the problems when the three-dimensional FET is applied to a logic circuit is heat generation during operation. . Since SRAM generates a small amount of heat during operation, heat generation is unlikely to be a problem. First, the on-current of the FET of the SRAM cell is originally small. In addition, it is extremely rare that the same SRAM cell is continuously accessed, and sufficient heat dissipation can be performed from one access to the next. On the other hand, when the three-dimensional FET is applied to a logic circuit, the three-dimensional FET can operate continuously, and thus heat generation can increase.

  In general, heat generation can be a problem in three-dimensional FETs including planar FETs and planar SOI devices, and various techniques for heat dissipation have been studied. However, most of the conventional studies are directed to planar SOI devices, and it cannot be said that three-dimensional FETs are sufficiently studied. Since the three-dimensional FET has a structure different from that of the planar SOI device, the heat radiation of the three-dimensional FET needs to be examined from a viewpoint different from that of the planar SOI device. More specifically, a planar SOI device performs element isolation by partially oxidizing a semiconductor layer (SOI layer) formed on the entire wafer surface, while a three-dimensional FET is separately formed on an insulating film. Element isolation is performed by forming a semiconductor layer. In general, for a three-dimensional FET, a heat dissipation measure is more important than a planar SOI device.

  More specifically, Japanese Patent Application Laid-Open No. 2004-72017 discloses that, for a planar SOI device, the metal wiring in the upper layer is used as a radiator. Japanese Laid-Open Patent Publication No. 2004-363136 discloses a structure of a planar SOI device in which a gate electrode of a MOSFET used as an ESD protection element is formed in a ring shape and the outside of a source region is separated by a shield plate electrode. is doing. According to such a structure, since the SOI layer is continuous, the heat dissipation efficiency is improved. Japanese Patent Laid-Open No. 2005-197462 discloses a structure in which a gate electrode and a channel region (referred to as “well” in the publication) are short-circuited although heat dissipation is not mentioned. In the structure disclosed in this publication, the wells of a P-type FET and an N-type FET are joined via a pn junction.

  Japanese Laid-Open Patent Publication No. 2006-19578 discloses heat dissipation of the fin FET. This publication discloses a structure in which the gate electrode and the channel region are short-circuited in order to reduce the power consumption of the fin FET and suppress the short channel effect. According to this structure, heat generated at the source and drain is dissipated through the gate electrode.

As a prior art in which a logic circuit is configured by a three-dimensional FET, there is an inverter circuit chain disclosed in Japanese Patent Laid-Open No. 2005-116969. Although the layout diagram is shown in FIG. 1 of the publication, each source (104, 105 in the figure) of the inverter circuit is not connected in the semiconductor layer (there is no common semiconductor layer), and metal wiring. (106 and 107 in the figure are electrically connected by source electrode wiring). Normally, when a functional circuit is formed by combining a logic gate circuit with a three-dimensional FET, the sources of the FETs constituting each logic gate circuit are connected by a metal wiring as in the same publication. Accordingly, in such a structure, the heat radiation from the metal wiring is performed from the semiconductor layer through the contact plug, and thus is limited by the heat dissipation resistance of the contact plug. As a result, the heat dissipation of the semiconductor layer is limited by the heat dissipation resistance of the contact plug.
JP 2004-72017 A JP 2004-363136 A JP 2005-197462 A JP 2006-19578 A JP 2005-116969 A Zheng Guo et al., "FinFET-Based SRAM Design", International Symposium on Low Power Electronics and Design, pp. 2-7,2005 (ISLPED'05)

  However, according to the inventor's study, in the fin FET disclosed in Japanese Patent Laid-Open No. 2006-19578 and Japanese Patent Laid-Open No. 2005-116969, the fin layer in which the source, channel, and drain are formed is formed in isolation. Therefore, it is difficult to release heat generated when the fin FET is operating.

  Since the drain is usually connected to a metal wiring, a method of providing a large number of contacts to the drain for heat dissipation or adopting a structure in which a metal wiring of a large area is connected may be considered. However, this method is not preferable because it increases the drain capacitance.

  Accordingly, an object of the present invention is to provide a technique for performing sufficient heat dissipation particularly in a three-dimensional FET.

  In order to solve the above problems, the present invention employs the means described below. In the description of technical matters constituting the means, in order to clarify the correspondence between the description of [Claims] and the description of [Best Mode for Carrying Out the Invention] No./symbol used in [Best Mode for Doing]. However, the appended numbers and symbols should not be used to limit the technical scope of the invention described in [Claims].

  The semiconductor device of the present invention includes a first common source semiconductor layer (2) extending in a first direction, a second common source semiconductor layer (3) extending in the first direction, and at least one 3 A first logic gate circuit composed of a three-dimensional P-type FET (20, 20A, 20B) and one three-dimensional N-type FET (30, 30A, 30B); and at least one three-dimensional P-type FET (20, 20A) 20B) and a second logic gate circuit composed of one three-dimensional N-type FET (30, 30A, 30B). The source side of the semiconductor layers (4, 4A to 4D) of the three-dimensional P-type FETs (20, 20A, 20B) constituting the first logic gate circuit and the second logic gate circuit is the first common source. The source side of the semiconductor layer (4) of the three-dimensional N-type FET (30, 30A, 30B) connected to the semiconductor layer (2) and constituting the first logic gate circuit and the second logic gate circuit is , And connected to the second common source semiconductor layer (3). At least one location where the drain-side semiconductor layers of the three-dimensional P-type FETs (20, 20A, 20B) and the three-dimensional N-type FETs (30, 30A, 30B) constituting the first logic gate circuit are connected to each other is connected. Further, there are at least one place where the drain side semiconductor layers of the three-dimensional P-type FET and the three-dimensional N-type fin FET constituting the second logic gate circuit are connected to each other.

  In the semiconductor device of the present invention, the semiconductor layers (4, 4A to 4D) are formed so as to connect the first and second common source semiconductor layers (2) and (3). The heat generated in 4A to 4D) can be dissipated through the first and second common source semiconductor layers (2) and (3). Therefore, the semiconductor device of the present invention can dissipate heat efficiently.

  According to the present invention, the heat generated in the three-dimensional FET can be efficiently radiated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the accompanying drawings, the same or similar components are referred to by the same or similar reference numerals.

(First embodiment)
Hereinafter, a fin FET, which is a typical three-dimensional FET, will be described as an example. FIG. 1 is a plan view showing a layout of the semiconductor device 1 according to the first embodiment of the present invention. The semiconductor device 1 shown in FIG. 1 includes three stages of inverter circuits 10 connected in series. Each inverter circuit 10 includes a P-type fin FET 20 and an N-type fin FET 30. In the semiconductor device 1 of FIG. 1, the inverter circuits 10 are arranged side by side in the X-axis direction, and the signal is transmitted in the + X direction. Hereinafter, the structure of the semiconductor device 1 will be described in detail.

The semiconductor device 1 includes a P ⁺ common source semiconductor layer 2 and an N ⁺ common source semiconductor layer 3, all extending in the X-axis direction. The P ⁺ common source semiconductor layer 2 is a semiconductor layer doped with P-type impurities at a high concentration, and is connected to a power supply level wiring (not shown). Here, the power supply level wiring is a metal wiring having a power supply level V _DD . On the other hand, the N ⁺ common source semiconductor layer 3 is a semiconductor layer doped with an N-type impurity at a high concentration, and is connected to a ground level wiring (not shown). The ground-level interconnect is a metal wire with a ground level V _SS.

A fin layer 4 is connected to the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3. Here, the fin layer 4 is a semiconductor layer in which the source, channel, and drain of the P-type fin FET 20 and the N-type fin FET 30 are formed. As shown in FIG. 2, the P ⁺ common source semiconductor layer 2, the N ⁺ common source semiconductor layer 3, and the fin layer 4 are formed on the insulating film 6 formed on the substrate 5. . In FIG. 2, the P ⁺ common source semiconductor layer 2, the N ⁺ common source semiconductor layer 3, and the fin layer 4 are illustrated separately, but actually, the P ⁺ common source semiconductor layer 2 and the fin layer 4 are separated from each other. There is no physically clear boundary between the N ⁺ common source semiconductor layer 3 and the fin layer 4.

In the fin layer 4, the source region 21, the channel region 22, and the drain region 23 of the P-type fin FET 20 are formed, and further, the drain region 24, the channel region 25, and the source region 26 of the N-type fin FET 30 are formed. The source region 21 and the drain region 23 are semiconductor regions doped with P-type impurities at a high concentration, and the channel region 22 is a semiconductor region doped with N-type impurities at a low concentration. On the other hand, the drain region 24 and the source region 26 are semiconductor regions doped with N-type impurities at a high concentration, and the channel region 25 is a semiconductor region doped with P-type impurities at a low concentration. The source region 21 of the P-type fin FET 20 is joined to the P ⁺ common source semiconductor layer 2, and the source region 26 of the N-type fin FET 30 is joined to the N ⁺ common source semiconductor layer 3. The source region 21, the channel region 22, the drain region 23 of the P-type fin FET 20, and the drain region 24, the channel region 25, and the source region 26 of the N-type fin FET 30 are arranged in the Y-axis direction (perpendicular to the X-axis direction). Is arranged in.

  In the structure shown in FIG. 2, it is noted that the drain region 23 of the P-type fin FET 20 and the drain region 24 of the N-type fin FET 30 are joined (connected) not only electrically but also physically. I want. In the present embodiment, the fin layer in which the P-type fin FET 20 is formed and the fin layer in which the N-type fin FET 30 is formed are physically integrated. As will be described later, such a structure is effective for improving heat dissipation.

  As shown in FIG. 3, the gate insulating film 7 is formed so as to cover the side surface and the upper surface of the fin layer 4, and the gate electrode 8 is formed on the gate insulating film 7. The gate electrode 8 is formed so as to cover the channel regions 22 and 25 of the P-type fin FET 20 and the N-type fin FET 30. As shown in FIG. 2, side walls 9 are formed on the side surfaces of the gate electrode 8.

  As shown in FIG. 1, the semiconductor device 1 further includes a contact 11 connected to the fin layer 4, a contact 12 connected to the gate electrode 8, and a metal wiring 13 connecting the contacts 11 and 12. Has been. As shown in FIG. 2, the contact 11 is formed so as to be connected to both the drain region 23 of the P-type fin FET 20 and the drain region 24 of the N-type fin FET 30. The metal wiring 13 is used for transmitting a signal between adjacent inverter circuits 10.

One feature of the semiconductor device 1 of this embodiment is that the fin layer 4 is formed so as to connect the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3. In the semiconductor device 1 of FIG. 1, the drain regions of the P-type fin FET 20 and the N-type fin FET 30 are electrically and physically joined. According to such a configuration, heat generated in the fin layer 4 can be dissipated through the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3, so that the heat dissipation effect is great. Also, P ⁺ common source semiconductor layer 2 and the N ⁺ common fin layer 3, without affecting the layout area, by increasing the width (i.e., by having a larger surface area), to obtain a high heat radiation effect be able to. For better heat radiation, P ⁺ width of the common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3 is desirably wider than the width of the fin layer 4, P ⁺ common source semiconductor layer 2 and the N ⁺ common source The sum of the pattern areas of the semiconductor layer 3 is preferably larger than the sum of the pattern areas of the fin layer 4.

In this embodiment, the fin layer 4 Fin-FET constituting each of the inverter circuit 10 is formed is bonded to the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3, P ⁺ common source semiconductor layer 2 Note that a square ring is formed by the N ⁺ common source semiconductor layer 3 and the fin layer 4. In the semiconductor device of FIG. 1, three inverter circuits 10 are connected in series, so that two square rings are formed by the P ⁺ common source semiconductor layer 2, the N ⁺ common source semiconductor layer 3, and the fin layer 4. Has been. In general, in k inverter circuits 10, k-1 square rings are formed. The P ⁺ common source semiconductor layer 2, the N ⁺ common source semiconductor layer 3, and the fin layer 4 are preferably formed to form as many angular rings as possible for heat dissipation. When k is large, the P ⁺ common source semiconductor layer 2, the N ⁺ common source semiconductor layer 3, and the fin layer 4 may be laid out so that about k / 2 square rings are formed.

  It should be noted that in the structure of the semiconductor device 1 of this embodiment, it is not necessary to increase the drain capacitance of the P-type fin FET 20 and the N-type fin FET 30 for heat dissipation. As described above, a structure in which a large number of contacts are connected to the drain or a metal wiring having a large area is connected is effective in improving the heat dissipation characteristics from the drain, but the drain capacitance increases. On the other hand, in the structure of the semiconductor device 1 of the present embodiment, the drain capacitance does not increase.

  In addition, according to the configuration of the semiconductor device 1 of the present embodiment, since the drain regions of the P-type fin FET 20 and the N-type fin FET 30 are directly joined (connected), the layout area can be reduced.

  The configuration of the semiconductor device 1 in FIG. 1 is also preferable in that the width of each inverter circuit 10 in the X-axis direction can be reduced. In the configuration of FIG. 1, the source region 21, the channel region 22, the drain region 23 of the P-type fin FET 20, and the drain region 24, the channel region 25, and the source region 26 of the N-type fin FET 30 are aligned in the Y-axis direction. They are arranged side by side. Such an arrangement makes it possible to reduce the width of each inverter circuit 10 in the X-axis direction.

  In the structure shown in FIG. 2, the drain region 23 of the P-type fin FET 20 and the drain region 24 of the N-type fin FET 30 are joined to each other. However, in such a configuration, interdiffusion of impurities can be a problem. . The interdiffusion can adversely affect the characteristics of the P-type fin FET 20 and the N-type fin FET 30.

  One method for avoiding such a problem is that the channel region 22 of the P-type fin FET 20 is separated from the drain region 24 of the N-type fin FET 30 by a sufficient distance, and the channel region 25 of the N-type fin FET 30 is separated from the P-type fin FET 20. It is to be separated from the drain region 23 by a sufficient distance. If necessary, a region 27 not doped with impurities by ion implantation may be provided between the drain regions 23 and 24 as shown in FIG. In this case, contacts 11a and 11b connected to the drain regions 23 and 24, respectively, are formed, and the metal wiring 13 is formed so as to be connected to both the contacts 11a and 11b.

Although not shown, a metal silicide structure may be adopted for the source region and the drain region excluding the channel region of the P ⁺ common source semiconductor layer 2, the N ⁺ common source semiconductor layer 3, and the fin layer 4. That is, part or all of the surfaces of the source region and the drain region of the P ⁺ common source semiconductor layer 2, the N ⁺ common source semiconductor layer 3, and the fin layer 4 may be silicided. A heat radiation effect can be obtained by silicidation.

The P ⁺ common source semiconductor layer 2 is preferably connected to the power supply level wiring through a plurality of contacts, and the N ⁺ common source semiconductor layer 3 is preferably connected to the ground level wiring through a plurality of contacts. The connection of the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3 to the metal wiring through many contacts is effective for enhancing the heat dissipation effect.

  In order to clarify the characteristics of the semiconductor device 1 of the present embodiment, the configuration of the fin FET in the SRAM cell part of Non-Patent Document 1 is schematically shown in FIG. As shown in FIG. 15, when viewed together with adjacent cells, the fin layer is continuous by two inverter circuits, and the drain fins of the P-type fin FET (Load) and the N-type fin FET (NPD) are connected to each other. Looks like you are. On the other hand, the source region fin layers of both fin FETs are shared with adjacent cells, but do not extend. There is no extended common source potential fin layer as in the present invention, and a heat dissipation effect cannot be obtained. Originally, an SRAM cell generates little heat, and such an arrangement in Non-Patent Document 1 is not made in consideration of heat dissipation, but is provided with a fin layer shared portion for reduction. A feature of the semiconductor device 1 of this embodiment is that it has a wide common source potential fin layer, that is, a large area, and the fin layers of the drains of the P-type fin FET and the N-type fin FET are connected and connected. The layers are continuous. For this reason, more heat dissipation effect can be obtained.

(Second Embodiment)
FIG. 5 is a plan view showing a configuration of a semiconductor device 1A according to the second embodiment of the present invention. Similar to the semiconductor device 1 of the first embodiment, the semiconductor device 1A of the second embodiment includes a three-stage inverter circuit 10A connected in series. However, in the semiconductor device 1A of the second embodiment, the shapes of the fin layer and the gate electrode are different from those of the semiconductor device 1 of the first embodiment. In the first embodiment, the fin layer 4 is formed in a straight line in the Y-axis direction, whereas in the second embodiment, a bent fin layer 4A is formed.

  FIG. 6 is a plan view showing the configuration of the fin layer 4A. In the second embodiment, a part of the source region 21 of the P-type finFET 20, a part of the channel region 22 and the drain region 23 are arranged side by side in the X-axis direction, and the drain region 24 of the N-type finFET 30. , A channel region 25, and a part of the source region 26 are arranged side by side in the X-axis direction. In addition, the channel region 22 of the P-type fin FET 20 and the channel region 25 of the N-type fin FET 30 are They are arranged side by side in the axial direction. As shown in FIG. 5, the gate electrode 8 </ b> A is formed so as to cover the channel region 22 of the P-type fin FET 20 and the channel region 25 of the N-type fin FET 30.

Also in the structure of the second embodiment, the fin layer 4A is formed so as to connect the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3 as in the first embodiment. Therefore, the heat generated in the fin layer 4A can be radiated through the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3, and the heat radiation effect is great. In addition, the structure of the second embodiment is also preferable in that the width of each inverter circuit 10A in the Y-axis direction can be reduced. Although the size of a suitable logic gate circuit varies depending on the layout of the entire chip, the integration degree of the logic circuit can be improved by properly using the structures of the first embodiment and the second embodiment.

(Third embodiment)
FIG. 7 is a plan view showing the configuration of the semiconductor device 1B of the third embodiment. The semiconductor device 1B according to the third embodiment functions as a NAND circuit including P-type fin FETs 20A and 20B and N-type fin FETs 30A and 30B.

More specifically, the semiconductor device 1B includes a fin layer 4B formed so as to connect the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3. The fin layer 4B has a branched shape. Specifically, the fin layer 4B includes a portion where the P-type fin FET 20A is formed, a portion where the P-type fin FET 20B is formed, and a portion where the N-type fin FETs 30A and 30B are formed in series. Configured. Each of the portions where the P-type fin FETs 20A and 20B are formed has one end joined to the P ⁺ common source semiconductor layer 2 and the other end joined to one end of the portion where the N-type fin FETs 30A and 30B are formed. The other ends of the portions where the N-type fin FETs 30 </ b> A and 30 </ b> B are formed are joined to the N ⁺ common source semiconductor layer 3.

FIG. 8A is a plan view showing the configuration of the fin layer 4B in detail. The following regions are formed in the fin layer 4B:
(1) Source region 31 and channel region 32 of the P-type fin FET 20A
(2) Source region 33 and channel region 34 of P-type fin FET 20B
(3) A common drain region 35 functioning as a common drain of the P-type fin FETs 20A and 20B

The source region 31 and the channel region 32 of the P-type fin FET 20A are formed between the common drain region 35 and the P ⁺ common source semiconductor layer 2 and aligned in the Y-axis direction. Similarly, the source region of the P-type fin FET 20B The region 33 and the channel region 34 are formed side by side in the Y-axis direction between the common drain region 35 and the P ⁺ common source semiconductor layer 2. As shown in FIG. 7, the channel region 32 of the P-type fin FET 20A is covered with the gate electrode 14A, and the channel region 34 of the P-type fin FET 20B is covered with the gate electrode 14B.

The following regions are further formed in the fin layer 4B:
(4) Drain region 36 and channel region 37 of the N-type fin FET 30A
(5) Source / drain region 38 that functions as the drain of the N-type fin FET 30A and also functions as the source of the N-type fin FET 30B
(6) Channel region 39, source region 40 of N-type fin FET 30B

The drain region 36, the channel region 37, the source / drain region 38, the channel region 39, and the source region 40 constituting the N-type fin FETs 30A and 30B are the same as the common drain region 35 of the P-type fin FETs 20A and 20B and the N ⁺ common source semiconductor. Between the layers 3, they are formed side by side in the Y-axis direction. The drain region 36 of the N-type fin FET 30A is formed so as to be joined to the common drain region 35 of the P-type fin FETs 20A and 20B. As shown in FIG. 7, the channel region 37 of the N-type fin FET 30A is covered with the gate electrode 15A, and the channel region 39 of the N-type fin FET 30B is covered with the gate electrode 15B.

  As shown in FIG. 7, contacts 16A and 17A are formed on the gate electrode 14A of the P-type fin FET 20A and the gate electrode 15A of the N-type fin FET 30A, respectively. The first input wiring 18A used as the first input of the NAND circuit is connected to the gate electrodes 14A and 15A via the contacts 16A and 17A.

  Similarly, contacts 16B and 17B are formed on the gate electrode 14B of the P-type fin FET 20B and the gate electrode 15B of the N-type fin FET 30B, respectively. The second input wiring 18B used as the second input of the NAND circuit is connected to the gate electrodes 14B and 15B via the contacts 16B and 17B.

  As shown in FIG. 8A, the contact 19 is formed so as to be joined to both the common drain region 35 of the P-type fin FETs 20A and 20B and the drain region 36 of the N-type fin FET 30A. The contact 19 is connected to an output wiring 18C that functions as an output of the NAND circuit. In the present embodiment, the output wiring 18C is formed in the first wiring layer (the metal wiring layer located at the lowest position), and the first input wiring 18A and the second input wiring 18B are formed in the second wiring layer (second from the bottom). Metal wiring layer located on

Similarly to the first and second embodiments, the semiconductor device 1B of the third embodiment also exhibits high heat dissipation capability. Even in the structure of the third embodiment, since the fin layer 4B is formed so as to connect the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3, the heat generated in the fin layer 4B is P. Heat can be radiated through the ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3. Therefore, a great heat dissipation effect can be obtained.

In the present embodiment, the configuration of the connection portion between the drains of the P-type fin FETs 20A and 20B and the drain of the N-type fin FET 30A can be variously changed. For example, as shown in FIG. 8B, the drain region 35A of the P-type fin FET 20A and the drain region 35B of the P-type fin FET 20B are formed separately, and the drain regions 35A and 35B are formed as the drain region 36 of the N-type fin FET 30A. It is also possible to have a configuration that is joined to each other. 8B, contacts 19A and 19C are formed in the drain regions 35A and 35B, contacts 19B are formed in the drain region 36, and these contacts 19A to 19C are commonly connected to the output wiring 18C. . 8A and 8B, the P-type fin FETs 20A and 20B are formed between the drain region 36 of the N-type fin FET 30A and the P ⁺ common source semiconductor layer 2, and either of the structures shown in FIGS. 8A and 8B. The configuration is also electrically equivalent.

A NOR circuit can be realized by a structure similar to that of the semiconductor device 1B of the third embodiment. In this case, specifically, the fin layer 4B includes a portion where the P-type fin FETs 20A and 20B are formed in series, a portion where the N-type fin FET 30A is formed, and a portion where the N-type fin FET 30B is formed. And is configured. One end of the portion where the P-type fin FETs 20A and 20B are formed in series is joined to the P ⁺ common source semiconductor layer 2, and the other end is joined to one end of the portion where the N-type fin FETs 30A and 30B are formed. The The other end of the portion where the N-type fin FETs 30 </ b> A and 30 </ b> B are formed is joined to the N ⁺ common source semiconductor layer 3.

(Fourth embodiment)
FIG. 9 is a plan view showing a configuration of a semiconductor device 1C according to the fourth embodiment. The semiconductor device 1C according to the fourth embodiment functions as a clocked inverter circuit including P-type fin FETs 20A and 20B and N-type fin FETs 30A and 30B.

More specifically, the semiconductor device 1 ^</ b ^> C includes a fin layer 4 ^</ b ^> C formed so as to connect the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3. In the present embodiment, the fin layer 4C is provided so as to extend in a straight line in the Y-axis direction. Specifically, as shown in FIG. 10, the following regions are formed in the fin layer 4C:
(1) The source region 41 and the channel region 42 of the P-type fin FET 20B
(2) Source / drain region 43 that functions as the drain of the P-type fin FET 20B and the source of the P-type fin FET 20A
(3) The channel region 44 and the drain region 45 of the P-type fin FET 20A
(4) Drain region 46 and channel region 47 of N-type fin FET 30A
(5) Source / drain region 48 that functions as the sole of the N-type fin FET 30A and the drain of the N-type fin FET 30B
(6) Channel region 49 and source region 50 of N-type fin FET 30B

  In the present embodiment, the source region 41, the channel region 42, the source / drain region 43, the channel region 44, the drain region 45, the drain region 46, and the channel region constituting the P-type fin FETs 20A and 20B and the N-type fin FETs 30A and 30B. 47, the source / drain region 48, the channel region 49, and the source region 50 are arranged side by side in the Y-axis direction.

  Referring to FIG. 9 again, the gate electrode 14A of the P-type fin FET 20A is formed so as to cover the channel region 44 formed in the fin layer 4C, and the gate electrode 14B of the P-type fin FET 20B is formed of the channel region 42. It is formed so as to cover. Similarly, the gate electrode 15A of the N-type fin FET 30A is formed so as to cover the channel region 44 formed in the fin layer 4C, and the gate electrode 15B of the N-type fin FET 30B is formed so as to cover the channel region 49. Has been.

  Contacts 16A and 17A are formed on the gate electrode 14A of the P-type fin FET 20A and the gate electrode 15A of the N-type fin FET 30A, respectively. The first input wiring 18A used as the data input of the clocked inverter circuit is connected to the gate electrodes 14A and 15A via the contacts 16A and 17A, respectively.

  Similarly, contacts 16B and 17B are formed on the gate electrode 14B of the P-type fin FET 20B and the gate electrode 15B of the N-type fin FET 30B, respectively. The second input wiring 18B used as the enable input of the clocked inverter circuit is connected to the gate electrodes 14B and 15B via the contacts 16B and 17B.

  As shown in FIG. 10, the contact 19 is formed to be joined to both the drain region 45 of the P-type fin FET 20A and the drain region 46 of the N-type fin FET 30A. The contact 19 is connected to an output wiring 18C that functions as an output of the clocked inverter circuit. In the present embodiment, the output wiring 18C is formed in the first wiring layer (the metal wiring layer located at the lowest position), and the first input wiring 18A and the second input wiring 18B are formed in the second wiring layer (second from the bottom). Metal wiring layer located on

The semiconductor device 1C having such a structure, the second input line 18B becomes the ground level V _SS, a first input line 18A and the input, functions as an inverter for the output of the output wires 18C. On the other hand, when the second input wiring 18B reaches the power supply level V _DD , the output wiring 18C enters a high impedance state.

Similarly to the first to third embodiments, the semiconductor device 1 </ b> C of the fourth embodiment also exhibits high heat dissipation capability. Even in the structure of the fourth embodiment, since the fin layer 4C is formed so as to connect the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3, the heat generated in the fin layer 4C is P. Heat can be radiated through the ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3, and the heat radiation effect is great.

  In addition, the configuration of FIG. 9 in which the fin layer 4C is provided so as to extend in a straight line in the Y-axis direction is suitable for reducing the width of the clocked inverter circuit in the X-axis direction.

(Fifth embodiment)
FIG. 11 is a plan view showing a configuration of a semiconductor device 1D of the fifth embodiment. Similar to the fourth embodiment, the semiconductor device 1D of the fifth embodiment functions as a clocked inverter circuit including P-type fin FETs 20A and 20B and N-type fin FETs 30A and 30B. However, the semiconductor device 1D of the fifth embodiment is formed in a shape in which the fin layer 4D is bent as in the second embodiment in order to reduce the width in the Y-axis direction of the clocked inverter circuit. .

More specifically with reference to FIG. 12, the fin layer 4 </ b> D has the following regions as in the semiconductor device 1 </ b> C of the fourth embodiment:
(1) The source region 41 and the channel region 42 of the P-type fin FET 20B
(2) Source / drain region 43 that functions as the drain of the P-type fin FET 20B and the source of the P-type fin FET 20A
(3) The channel region 44 and the drain region 45 of the P-type fin FET 20A
(4) Drain region 46 and channel region 47 of N-type fin FET 30A
(5) Source / drain region 48 that functions as the sole of the N-type fin FET 30A and the drain of the N-type fin FET 30B
(6) Channel region 49 and source region 50 of N-type fin FET 30B
However, the arrangement of these regions is different.

In the fifth semiconductor device 1D, in order to reduce the width in the Y-axis direction of the clocked inverter circuit, (a) the source region 41, the channel region 42, and the source / drain region 43 of the P-type fin FET 20B are arranged in the X-axis direction. Arranged side by side,
(B) The source / drain region 43, the channel region 44, and the drain region 45 of the P-type fin FET 20A are arranged side by side in the X-axis direction,
(C) The drain region 46, the channel region 47, and the source / drain region 48 of the N-type fin FET 30A are arranged side by side in the X-axis direction,
(D) The source / drain region 48, the channel region 49, and the source region 50 of the N-type fin FET 30B are arranged side by side in the X-axis direction.
In addition, the channel regions 42, 44, 47, and 49 of the P-type fin FETs 20A and 20B and the N-type fin FETs 30A and 30B are arranged side by side in the Y-axis direction.

  Returning to FIG. 11, in the present embodiment, the P-type fin FET 20 </ b> A and the N-type fin FET 30 </ b> A share the common gate electrode 51. The common gate electrode 51 is formed so as to cover the channel regions 44 and 47 formed in the fin layer 4D. On the other hand, the gate electrode 52 of the P-type fin FET 20B is formed so as to cover the channel region 42 formed in the fin layer 4D, and the gate electrode 53 of the N-type fin FET 30B is formed so as to cover the channel region 49. ing.

  A contact 54 is formed on the common gate electrode 51 of the P-type fin FET 20A and the N-type fin FET 30A. The first input wiring 18 </ b> A used as data input of the clocked inverter circuit is connected to the common gate electrode 51 through the contact 54. On the other hand, contacts 55 and 56 are formed on the gate electrode 52 of the P-type fin FET 20B and the gate electrode 53 of the N-type fin FET 30B, respectively. The second input wiring 18B used as an enable input of the clocked inverter circuit is connected to the gate electrodes 52 and 53 via contacts 55 and 56, respectively.

The semiconductor device 1D having such a structure, the second input line 18B becomes the ground level V _SS, a first input line 18A and the input, functions as an inverter to output the output wiring 18C. On the other hand, when the second input wiring 18B reaches the power supply level V _DD , the output wiring 18C enters a high impedance state.

Similarly to the first to fourth embodiments, the semiconductor device 1D of the fifth embodiment also exhibits high heat dissipation capability. Also in the structure of the fifth embodiment, since the fin layer 4D is formed so as to connect the P ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3, the heat generated in the fin layer 4D is P Heat can be dissipated through the ⁺ common source semiconductor layer 2 and the N ⁺ common source semiconductor layer 3, and the heat dissipation effect is large. In addition, the structure of the fifth embodiment is preferable in that the width of the clocked inverter circuit in the Y-axis direction can be reduced. Although the size of a suitable functional circuit differs depending on the layout of the entire chip, the degree of integration of the functional circuit can be improved by properly using the structures of the fourth embodiment and the fifth embodiment.

  Although various embodiments of the present invention have been described above, the present invention should not be construed as being limited to the above-described embodiments.

  For example, in the above-described embodiment, a configuration in which the gate electrode straddles the fin layer is disclosed, but a configuration in which the fin layer 4 straddles the gate electrode 8 as shown in FIG. 13 can also be adopted. It is. In this case, the gate insulating film 7 is formed on the surface of the gate electrode 8. In addition, the present invention can be applied to many three-dimensional MISFETs (DG-FET: Double Gate-FET, etc.).

  Further, the present invention may be implemented as a logic circuit in which a plurality of logic gate circuits such as inverter circuits and NAND circuits described in the above embodiments are combined. In this case, the fin layers of the fin FETs constituting each logic gate circuit are joined to the common source semiconductor layer, and a square ring is formed by the fin layer and the common source semiconductor layer of the preceding logic gate circuit, the succeeding logic gate circuit, and so on. You may comprise as follows. That is, the logic circuit having k logic gate circuits is preferably configured so that k-1 square rings are formed. Even if k-1 square rings are not formed, the layout of the fin layer and the common source semiconductor layer so as to form as many square rings as possible has an effect on heat dissipation. It does not deviate. If k is large, the fin layer and the common source semiconductor layer may be laid out so that about k / 2 square rings are formed.

  In the above-described embodiments, the fin layers are illustrated as having the same width, but it is preferable that the portion of the fin layer where the channel region of the fin FET is formed is formed thin. FIG. 14 is a bird's-eye view showing the configuration of the fin layer 4 for forming the channel region of the fin FET to be thin. In the configuration of FIG. 14, the fin layer 4 includes a wide source pad 61 and drain pad 62 and a gap between them. And a thin line portion 63 formed in the structure. The source pad 61 functions as the source of the fin FET, and the drain pad 62 functions as the drain of the fin FET. In addition, in the thin line portion 63, a portion covered with the gate electrode functions as a channel region, and a portion not covered with the thin line portion 63 functions as a part of the source region or the drain region. The source pad 61 is desirably extended as it is to obtain a heat dissipation effect. The drain pad 62 is preferably a common drain electrode contact portion for the P-type fin FET and the N-type fin FET.

FIG. 1 is a plan view showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing the configuration of the semiconductor device in the B-B ′ cross section of FIG. 1. FIG. 3 is a cross-sectional view showing a configuration of the semiconductor device in the A-A ′ cross section of FIG. 1. FIG. 4 is a cross-sectional view showing another structure of the junction of the drains of the three-dimensional P-type FET (P-type fin FET) and the three-dimensional N-type FET (N-type fin FET). FIG. 5 is a plan view showing the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 6 is a plan view showing the configuration of the fin layer in the second embodiment. FIG. 7 is a plan view showing the configuration of the semiconductor device according to the third embodiment of the present invention. FIG. 8A is a plan view showing a configuration of a fin layer in the third embodiment. FIG. 8B is a plan view illustrating another configuration of the fin layer according to the third embodiment. FIG. 9 is a plan view showing the configuration of the semiconductor device according to the fourth embodiment of the present invention. FIG. 10 is a plan view showing the configuration of the fin layer in the fourth embodiment. FIG. 11 is a plan view showing the configuration of the semiconductor device according to the fifth embodiment of the present invention. FIG. 12 is a plan view showing the configuration of the fin layer in the fifth embodiment. FIG. 13 is a bird's-eye view showing another configuration of a three-dimensional FET (fin FET). FIG. 14 is a bird's-eye view showing a preferred structure of the fin layer. FIG. 15 is a conceptual diagram showing a conventional configuration of an SRAM composed of fin FETs.

Explanation of symbols

1, 1A, 1B, 1C, 1D: Semiconductor device 2: P ⁺ common source semiconductor layer 3: N ⁺ common source semiconductor layer 4, 4A, 4B, 4C, 4D: fin layer 5: substrate 6: insulating film 7: gate Insulating film 8, 8A: Gate electrode 9: Side wall 11, 11a, 11b, 12: Contact 13: Metal wiring 14A, 14B, 15A, 15B: Gate electrode 16A, 16B, 17A, 17B, 19, 19A, 19B, 19C : Contact 18A: first input wiring 18B: second input wiring 18C: output wiring 10, 10A: inverter circuit 20, 20A, 20B: P-type fin FET
30, 30A, 30B: N-type fin FET
21, 26: Source region 22, 25: Channel region 23, 24: Drain region 27: Intrinsic region 31, 33: Source region 32, 34: Channel region 35: Common drain region 35A, 35B: Drain region 36: Drain region 37: Channel region 38: Source / drain region 39: Channel region 40: Source region 41: Source region 42: Channel region 43: Source / drain region 44: Channel region 45: Drain region 46: Drain region 47: Channel region 48: Source / drain region 49: Channel region 50: Source region 51: Common gate electrode 52, 53: Gate electrode 54, 55, 56: Contact 61: Source pad 62: Drain pad 63: Fine line portion

Claims (17)

A first common source semiconductor layer extending in a first direction;
A second common source semiconductor layer extending in the first direction;
A first logic gate circuit composed of at least one three-dimensional P-type FET and one three-dimensional N-type FET; a second composed of at least one three-dimensional P-type FET and one three-dimensional N-type FET; A logic gate circuit,
The source side of the semiconductor layer of the three-dimensional P-type FET constituting the first logic gate circuit and the second logic gate circuit is connected to the first common source semiconductor layer,
The source side of the semiconductor layer of the three-dimensional N-type FET constituting the first logic gate circuit and the second logic gate circuit is connected to the second common source semiconductor layer,
There is at least one place where the drain side semiconductor layers of the three-dimensional P-type FET and the three-dimensional N-type FET constituting the first logic gate circuit are connected to each other;
A semiconductor device having at least one location where the drain side semiconductor layers of the three-dimensional P-type FET and the three-dimensional N-type fin FET constituting the second logic gate circuit are connected to each other. The semiconductor device according to claim 1,
The three-dimensional P-type FET and the three-dimensional N-type FET are a fin FET or a double gate FET. The semiconductor device according to claim 1 or 2,
A direction in which a signal is transmitted from the first logic gate circuit to the second logic gate circuit is the first direction. A semiconductor device according to claim 1,
Channel regions of the respective semiconductor layers of the three-dimensional P-type FET and the three-dimensional N-type FET constituting the first logic gate circuit are arranged side by side in a second direction perpendicular to the first direction,
A semiconductor device in which channel regions of the respective semiconductor layers of the three-dimensional P-type FET and the three-dimensional N-type FET constituting the second logic gate circuit are arranged side by side in a second direction perpendicular to the first direction . A semiconductor device according to claim 1,
Channel regions of the semiconductor layers of the three-dimensional P-type FET and the three-dimensional N-type FET constituting the first logic gate circuit are arranged in the first direction, and a part of the source region is the channel. Arranged in a second direction perpendicular to the first direction with respect to the region,
Channel regions of the respective semiconductor layers of the three-dimensional P-type FET and the three-dimensional N-type FET constituting the second logic gate circuit are arranged side by side in the first direction, and a part of the source region is the channel region The semiconductor device is disposed so as to be positioned in a second direction perpendicular to the first direction. A semiconductor device according to claim 1,
The drain regions of the three-dimensional P-type FET and the three-dimensional N-type FET are connected and connected so as to form a PN junction. The semiconductor device according to claim 6,
A semiconductor device in which a common drain electrode contact is provided at a position where the drain regions of the three-dimensional P-type FET and the three-dimensional type FET are connected to each other. A semiconductor device according to claim 1,
A drain region of the three-dimensional P-type FET and the three-dimensional N-type FET is connected and connected via a region not doped with impurities. A semiconductor device according to claim 1,
Of the semiconductor layers of the three-dimensional P-type FET and the three-dimensional N-type FET, part or all of the source region and drain region excluding the channel region have a metal silicide structure. A semiconductor device according to claim 1,
The first common source potential semiconductor layer, the second common source semiconductor layer, the three-dimensional P-type FET semiconductor layer and the three-dimensional N-type FET semiconductor layer constituting the first logic gate circuit; A semiconductor device in which the semiconductor layer of the three-dimensional P-type FET and the semiconductor layer of the three-dimensional N-type FET constituting the logic gate circuit of 2 are arranged so as to form a square ring as a whole. A semiconductor device according to claim 1,
The first logic gate circuit and the second logic gate circuit are any of an inverter circuit, a NAND circuit, a NOR circuit, and a clocked inverter circuit. A semiconductor device according to claim 1,
The width of the first common source semiconductor layer and the second common source semiconductor layer is wider than the width of the semiconductor layer of the three-dimensional P-type FET and the semiconductor layer of the three-dimensional N-type FET. A semiconductor device according to claim 1,
The sum of the pattern areas of the first common source semiconductor layer and the second common source semiconductor layer is larger than the sum of the pattern areas of the semiconductor layer of the three-dimensional P-type FET and the semiconductor layer of the three-dimensional N-type FET. . A semiconductor device according to claim 1,
The first common source semiconductor layer is connected to a power level wiring,
The second common source semiconductor layer is connected to a ground level wiring semiconductor device. The semiconductor device according to claim 14,
The first common source semiconductor layer and the power level wiring are connected via a plurality of contacts,
The second common source semiconductor layer and the ground level wiring are connected via a plurality of contacts. A first common source semiconductor layer extending in a first direction;
A second common source semiconductor layer extending in the first direction;
Comprising at least one set of a three-dimensional P-type FET and a first to k-th logic gate circuit each composed of a three-dimensional N-type FET;
The source side of the semiconductor layer of at least one three-dimensional P-type FET among the three-dimensional P-type FETs constituting the k logic gate circuits is connected to the first common source semiconductor layer,
The source side of the semiconductor layer of at least one three-dimensional N-type FET among the three-dimensional N-type FETs constituting the k logic gate circuits is connected to the second common source semiconductor layer,
The drain side semiconductor layers of at least one set of the three-dimensional P-type FET and the three-dimensional N-type FET among the three-dimensional P-type FET and the three-dimensional N-type FET constituting the k logic gate circuits are connected to each other. In addition, there are at least k places where the drain side semiconductor layers of the at least one set of the three-dimensional P-type FET and the three-dimensional N-type FET are connected to each other. The semiconductor device according to claim 16,
The first common source semiconductor layer, the second common source semiconductor layer, the three-dimensional P-type FET semiconductor layer and the three-dimensional N-type FET semiconductor layer constituting the first to k-th logic gate circuits are provided. , A semiconductor device formed so as to form k−1 square rings.

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